Communication system, communication device, and communication method

Abstract

To inhibit the decline in data transfer capacity.SOLUTION: A communication system includes a host controller, multiple communication devices, and a communication path. The communication path connects the host controller and the multiple communication devices in a ring shape and is capable of transmitting serial communication frames. The host controller and each of the multiple communication devices perform error correction and detection and includes an ECC circuit with variable error correction capability. The host controller sets the error correction capability of the ECC circuit according to the error occurrence status in the communication path.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a communication system, a communication device, and a communication method. [Background technology]

[0002] There is a communication system having a host controller and a plurality of communication devices. As one of the connection methods in such a communication system, a connection method in which the host controller and the plurality of communication devices are connected in a ring shape is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-150878 A Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a communication system, a communication device, and a communication method that suppresses degradation of data transfer capacity. [Means for solving the problem]

[0005] A communication system according to an embodiment includes a host controller, a plurality of communication devices, and a communication path. The communication path connects the host controller and the plurality of communication devices in a ring shape and is capable of transmitting communication frames for serial communication. Each of the host controller and the plurality of communication devices includes an ECC circuit that performs error correction and detection and has a variable error correction capability. The host controller sets the error correction capability of the ECC circuit according to the occurrence status of errors in the communication path. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing the overall configuration of a communication system according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram of a host controller included in the communication system according to the first embodiment. [Diagram 3] FIG. 2 is a block diagram of a communication device included in the communication system according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of a communication frame handled in the communication system according to the first embodiment. [Diagram 5] 4 is a flowchart showing the operation of the communication system according to the first embodiment. [Figure 6] 3 is a diagram showing an example of communication frame transmission in a ring connection of the communication system according to the first embodiment. [Figure 7] 5 is a flowchart showing an initial setting operation of the communication system according to the first embodiment. [Figure 8] FIG. 11 is a diagram showing an example of the configuration of a container payload in a communication system according to a second embodiment. [Figure 9] FIG. 13 is a diagram showing an example of the configuration of a container payload in a communication system according to the third embodiment. [Figure 10] 13 is a flowchart showing a resetting operation of the communication system according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the description, components having substantially the same functions and configurations are given the same reference numerals. The embodiments described below are merely examples of technical ideas. The materials, shapes, structures, arrangements, etc. of the components are not specified in the embodiments. Various modifications can be made to the embodiments.

[0008] <1> First embodiment A communication system according to a first embodiment will be described.

[0009] <1-1> Configuration <1-1-1>Communication system configuration First, an example of the configuration of a communication system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of a communication system according to a first embodiment.

[0010] As shown in Fig. 1, the communication system 1 includes a system board 2, a connector 3, a host controller 4, multiple device boards 5, and multiple communication paths 8. In the example of Fig. 1, the communication system 1 includes n (n is an integer equal to or greater than 1) device boards 5-1 to 5-n. The communication system 1 also includes n communication paths 8-1 to 8-n corresponding to the n device boards 5-1 to 5-n, respectively.

[0011] The system board 2 is, for example, an accelerator board that supports ultra-wideband (for example, 200 GB / s or more) and large capacity.

[0012] The connector 3 is provided on the system board 2. The connector 3 is used for wired connection between the system board 2 and an external device (such as a computer). The connector 3 is connected to a host controller 4. Note that, in addition to the connector 3, the system board 2 may have a communication circuit used for wireless connection between the system board 2 and the external device.

[0013] The host controller 4 controls the entire communication system 1. The host controller 4 controls each communication device 6 mounted on the device board 5. For example, if the communication device 6 is a memory device, the host controller 4 requests (commands) the communication device 6 to perform a data write operation or a data read operation. In other words, if the communication device 6 is a memory device, the communication system 1 can also be referred to as a memory system. The host controller 4 transmits and receives information to and from an external device via the connector 3. The host controller 4 transmits and receives information to and from the device board 5 via a communication path 8. For example, the host controller 4 is configured to be capable of transmitting and receiving differential serial signals.

[0014] Each device board 5 includes a substrate and a plurality of communication devices 6. In the example of Fig. 1, each device board 5 includes four communication devices 6-1 to 6-4. The communication devices 6-1 to 6-4 are mounted on the substrate by soldering, sockets, or the like. For example, the communication devices 6-1 to 6-4 may be arranged side by side along the longitudinal direction of the substrate.

[0015] The communication device 6 is a device that operates based on communication with the host controller 4. In the following, a case where the communication device 6 is a memory device equipped with a NAND type flash memory will be described. For example, the communication device 6 may be a memory system such as an SSD (Solid State Drive) equipped with a NAND type flash memory. In addition, when the communication device 6 is a memory device, the device board 5 may also be referred to as a memory board. The communication device 6 is communicatively connected to the host controller 4 via a communication path 8.

[0016] The communication paths 8-1 to 8-n correspond to the device boards 5-1 to 5-n, respectively. Each communication path 8 connects the host controller 4 to the communication devices 6-1 to 6-4 included in the corresponding device board 5 in a ring shape. More specifically, the data output terminal of the host controller 4, the input terminals and output terminals of the communication devices 6-1, 6-2, 6-3, and 6-4, and the data input terminal of the host controller 4 are connected in a ring shape via the communication path 8. Each communication path 8 can transmit a differential serial signal. In addition, each communication path 8 may have different characteristics in each part between the host controller 4 and the communication device 6-1, between the communication device 6-1 and the communication device 6-2, between the communication device 6-2 and the communication device 6-3, between the communication device 6-3 and the communication device 6-4, and between the communication device 6-4 and the host controller 4. Specifically, the BER (Bit Error Rate) when a signal is transmitted may be different. Each part of these communication paths 8 can be said to be a part of the communication path 8. That is, the communication path 8 can be divided into a portion between the host controller 4 and communication device 6-1, a portion between communication device 6-1 and communication device 6-2, a portion between communication device 6-2 and communication device 6-3, a portion between communication device 6-3 and communication device 6-4, and a portion between communication device 6-4 and the host controller 4.

[0017] A plurality of communication devices 6 of one device board 5 transmit and receive communication frames of differential serial signals via a communication path 8. A communication frame is a unit of data transmitted via the communication path 8. In the case of a ring connection, a communication frame output from the host controller 4 is input to the host controller 4 via the communication device 6-1, the communication device 6-2, the communication device 6-3, and the communication device 6-4. A communication frame includes a plurality of containers. A container length indicating the length (or size) of each container included in the communication frame is a fixed length. In other words, a data length indicating the length (or size) of data (information) included in one container is a fixed length. Each communication device 6 performs insertion and removal of data to and from a container of a communication frame according to a predetermined condition. Insertion and removal of data includes inserting (writing) data into a container and extracting (reading) data from a container. For example, a communication frame may include a number of containers according to a bandwidth required for the communication system 1 and a bandwidth of each communication device 6.

[0018] The communication system 1 may be configured without the system board 2. The system board 2 and the substrate of the device board 5 may be formed integrally.

[0019] <1-1-2> Host controller configuration Next, the configuration of the host controller 4 will be described with reference to Fig. 2. Fig. 2 is a block diagram of the host controller included in the communication system according to the first embodiment. As shown in Fig. 2, the host controller 4 includes a SoC (System on Chip) 40 and a DRAM (Dynamic Random Access Memory) 401.

[0020] The SoC 40 is a device that realizes various functions of the host controller 4. The SoC 40 controls the DRAM 401. The SoC 40 includes a plurality of receiving units (hereinafter also referred to as Rx) 41, a plurality of transmitting units (hereinafter also referred to as Tx) 42, a plurality of protocol conversion units (hereinafter also referred to as "PCS") 43, a plurality of error correction and detection circuits (hereinafter also referred to as "ECC (Error Correction Code)") 44, a plurality of communication control circuits (hereinafter also referred to as "CONT") 45, an internal bus IB1, a CPU (Central Processing Unit) 46, a DRAM controller 47, a PCIe (Peripheral Component Interconnect Express) controller 48, and an SRAM (Static Random Access Memory) 49. The SoC 40 is configured as a circuit device including these configurations.

[0021] The configuration including the receiving unit 41, the transmitting unit 42, the protocol conversion unit 43, the ECC circuit 44, and the communication control circuit 45 functions as an interface circuit that controls transmission and reception of data between the host controller 4 and the communication device 6. That is, the SoC 40 includes a plurality of interface circuits corresponding to a plurality of communication paths 8. The communication control circuit 45, the CPU 46, the DRAM controller 47, the PCIe controller 48, and the SRAM 49 are connected to each other by an internal bus IB1.

[0022] The receiving unit 41 is a receiving circuit. The receiving unit 41 corresponds to a physical layer. The receiving unit 41 is connected to the communication path 8 and the protocol conversion unit 43. The receiving unit 41 receives a communication frame from the preceding communication device 6 via the communication path 8. The receiving unit 41 performs physical processing such as waveform equalization on the received communication frame and supplies the frame to the protocol conversion unit 43. The receiving unit 41 also supports communication in PAM4 (Pulse Amplitude Modulation 4) and PAM2 (Pulse Amplitude Modulation 2).

[0023] The transmitting unit 42 is a transmission circuit. The transmitting unit 42 corresponds to a physical layer. The transmitting unit 42 is connected to the communication path 8 and the protocol conversion unit 43. The transmitting unit 42 performs physical processing such as waveform equalization on the communication frame supplied from the protocol conversion unit 43. The transmitting unit 42 transmits the processed communication frame to the communication path 8 toward the downstream communication device 6. The transmitting unit 42 also supports communication in PAM4 and PAM2.

[0024] The protocol conversion unit 43 performs protocol conversion of the communication frame. The protocol conversion unit 43 corresponds to a link layer. The protocol conversion unit 43 is connected to the ECC circuit 44. For example, the protocol conversion unit 43 converts the protocol of the processed communication frame received from the receiving unit 41 according to the protocol of the upper layer. In other words, the protocol conversion unit 43 converts the protocol of the processed communication frame received from the receiving unit 41 according to the bus protocol of the internal bus IB1. The upper layer is a layer higher than the link layer when the communication layer structure in the communication between the host controller 4 and the communication device 6 is roughly divided. For example, the internal bus IB1 and each circuit (CPU 46, DRAM controller 47, PCIe controller 48, SRAM 49, and DRAM 401) connected to the communication control circuit 45 via the internal bus IB1 correspond to the upper layer. The protocol conversion unit 43 transmits the communication frame that has been protocol-converted to match the upper layer to the ECC circuit 44.

[0025] Furthermore, the protocol conversion unit 43 converts the protocol of the communication frame received from the ECC circuit 44 in accordance with the protocol of the lower layer. In other words, the protocol conversion unit 43 converts the protocol of the communication frame received from the ECC circuit 44 in accordance with the protocol corresponding to the communication path 8. The lower layer is a layer lower than the physical layer when the communication layer structure is roughly divided. The protocol conversion unit 43 transmits the communication frame, whose protocol has been converted to match the lower layer, to the transmission unit 42.

[0026] The ECC circuit 44 performs error correction and error detection of data included in a communication frame. The data error correction performed by the ECC circuit 44 is called ECC processing. The ECC circuit 44 also performs CRC (Cyclic Redundancy Check). The error detection performed by the ECC circuit 44 is called CRC processing. The ECC circuit 44 receives a communication frame from the protocol conversion unit 43. The ECC circuit 44 performs ECC processing on the received communication frame, and further performs CRC processing to check whether all errors have been corrected. Then, the ECC circuit 44 transmits the communication frame to the communication control circuit 45. Note that, if the ECC circuit 44 finds that an error remains in the communication frame by the CRC processing, it instructs the retransmission of the communication frame. Retransmission is a process of having the source transmit the target communication frame again. The ECC circuit 44 also adds data used for ECC processing and CRC processing to the data received from the communication control circuit 45, and transmits the data to the protocol conversion unit 43. The ECC circuit 44 can change the correction capability of the ECC process, specifically, the data size that can be corrected by the ECC process. In this specification, the correction capability of the ECC circuit 44 is exemplified by a case where one byte can be corrected and a case where three bytes can be corrected.

[0027] The communication control circuit 45 inserts and removes data from a container corresponding to its own device in the communication frame. The communication control circuit 45 corresponds to the link layer. For example, the communication control circuit 45 extracts data (information) from a container corresponding to its own device in the communication frame received from the ECC circuit 44. The communication control circuit 45 also inserts data (information) of a packet from a higher layer into an empty container in the communication frame. A packet is a transmission unit of data transmitted and received between the communication control circuit 45 and the higher layer in response to an operation (such as a write operation or a read operation) executed in the higher layer. The higher layer includes multiple devices connected via an internal bus IB1.

[0028] The CPU 46 is a processor. The CPU 46 controls the operation of the entire host controller 4 based on a request from an external device connected to the connector 3. The CPU 46 controls the DRAM controller 47, the PCIe controller 48, and the SRAM 49 via the internal bus IB1.

[0029] The DRAM controller 47 controls the DRAM 401 based on a request from the CPU 46. The DRAM controller 47 transmits and receives data to and from the DRAM 401 via a signal line IOa.

[0030] The DRAM 401 is a volatile memory. The DRAM 401 may be another volatile memory or a non-volatile memory. The DRAM 401 temporarily stores data that the SoC 40 reads from the communication device 6, write data that the SoC 40 receives from an external device connected to the connector 3, and the like. The DRAM 401 may be implemented inside the SoC 40.

[0031] The PCIe controller 48 controls communication with an external device via the connector 3. The PCIe controller 48 transmits and receives data to and from the external device via the signal line IOb and the connector 3. For example, the PCIe controller 48 transmits data read from the communication device 6 to the external device connected to the connector 3. In addition, the PCIe controller 48 receives data to be written to the communication device 6 from the external device connected to the connector 3.

[0032] The SRAM 49 is a volatile memory. The SRAM 49 may be another memory having a faster access speed than the DRAM 401. The SRAM 49 can be used as a working area for the CPU 46.

[0033] <1-1-3> Communication device configuration Next, the configuration of the communication device 6 will be described with reference to Fig. 3. Fig. 3 is a block diagram of a communication device included in the communication system according to the first embodiment. As shown in Fig. 3, the communication device 6 includes an SoC 60, a DRAM 601, and a plurality of NAND type flash memories 602. Hereinafter, the NAND type flash memory 602 will also be referred to as NAND memory 602.

[0034] The SoC 60 is a device that operates in response to a request from the host controller 4. The SoC 60 controls the DRAM 601 and the NAND memory 602. For example, the SoC 60 commands the NAND memory 602 to perform a read operation, a write operation, and the like. The SoC 60 includes a receiving unit (hereinafter also referred to as "Rx") 61, a transmitting unit (hereinafter also referred to as "Tx") 62, a protocol conversion unit (hereinafter also referred to as "PCS") 63, an ECC circuit (hereinafter also referred to as "ECC") 64, a communication control circuit (hereinafter also referred to as "CONT") 65, an internal bus IB2, a CPU 66, a DRAM controller 67, a NAND controller 68, and an SRAM 69. The SoC 60 is configured as a circuit device including these configurations.

[0035] The configuration including the receiving unit 61, the transmitting unit 62, the protocol conversion unit 63, the ECC circuit 64, and the communication control circuit 65 functions as an interface circuit that controls transmission and reception of data between the host controller 4 and its own device (communication device 6). The communication control circuit 65, the CPU 66, the DRAM controller 67, the NAND controller 68, and the SRAM 69 are connected to each other by an internal bus IB2.

[0036] The receiving unit 61 is a receiving circuit. The receiving unit 61 corresponds to a physical layer. The receiving unit 61 is connected to the communication path 8 and the protocol conversion unit 63. The receiving unit 61 receives a communication frame from the host controller 4 or the preceding communication device 6 via the communication path 8. The receiving unit 61 performs physical processing such as waveform equalization on the received communication frame and supplies the received communication frame to the protocol conversion unit 63. The receiving unit 61 also supports communication in PAM4 and PAM2.

[0037] The transmitting unit 62 is a transmission circuit. The transmitting unit 62 corresponds to a physical layer. The transmitting unit 62 is connected to the communication path 8 and the protocol conversion unit 63. The transmitting unit 62 performs physical processing such as waveform equalization on the communication frame supplied from the protocol conversion unit 63. The transmitting unit 62 transmits the processed communication frame to the communication path 8 toward the downstream communication device 6 or the host controller 4. The transmitting unit 62 also supports communication in PAM4 and PAM2.

[0038] The protocol conversion unit 63 performs protocol conversion of the communication frame. The protocol conversion unit 63 corresponds to the link layer. The protocol conversion unit 63 is connected to the ECC circuit 64. For example, the protocol conversion unit 63 converts the protocol of the processed communication frame received from the receiving unit 61 according to the protocol of the upper layer. In other words, the protocol conversion unit 63 converts the protocol of the processed communication frame received from the receiving unit 61 according to the bus protocol of the internal bus IB2. The upper layer is a layer higher than the link layer when the communication layer structure in the communication between the host controller 4 and the communication device 6 is roughly divided. For example, the internal bus IB2 and each circuit (CPU 66, DRAM controller 67, NAND controller 68, SRAM 69, DRAM 601, and NAND memory 602) connected to the communication control circuit 65 via the internal bus IB2 correspond to the upper layer. The protocol conversion unit 63 transmits the communication frame that has been protocol-converted to match the upper layer to the ECC circuit 64.

[0039] Furthermore, the protocol conversion unit 63 converts the protocol of the communication frame received from the ECC circuit 64 in accordance with the protocol of the lower layer. In other words, the protocol conversion unit 63 converts the protocol of the communication frame received from the ECC circuit 64 in accordance with the protocol corresponding to the communication path 8. The lower layer is a layer lower than the physical layer when the communication layer structure is roughly divided. The protocol conversion unit 63 transmits the communication frame, the protocol of which has been converted in accordance with the lower layer, to the transmission unit 62.

[0040] The ECC circuit 64 performs error correction and error detection of data included in the communication frame. The data error correction performed by the ECC circuit 64 is also called ECC processing, as in the case of the ECC circuit 44. The ECC circuit 64 also performs CRC. The error detection performed by the ECC circuit 64 is also called CRC processing, as in the case of the ECC circuit 44. The ECC circuit 64 receives a communication frame from the protocol conversion unit 63. The ECC circuit 64 performs ECC processing on the received communication frame, and further performs CRC processing to check whether all errors have been corrected. Then, the ECC circuit 64 transmits the communication frame to the communication control circuit 65. Note that, if the ECC circuit 64 finds that an error remains by the CRC processing, it instructs the retransmission of the communication frame. Also, the ECC circuit 64 adds data used for the ECC processing and CRC processing to the data received from the communication control circuit 65, and transmits the data to the protocol conversion unit 63. Note that the ECC circuit 64 can change the correction capability by the ECC processing, specifically, the data size that can be corrected by the ECC processing. In this specification, a case will be exemplified in which the correction capability of the ECC circuit 64 is selectively used between a case in which 1-byte correction is possible and a case in which 3-byte correction is possible.

[0041] The communication control circuit 65 inserts and removes data from a container corresponding to its own device in the communication frame. The communication control circuit 65 corresponds to a link layer. For example, the communication control circuit 65 extracts data (information) from a container corresponding to its own device in the communication frame received from the ECC circuit 64. The communication control circuit 65 also inserts data (information) of a packet from an upper layer into an empty container in the communication frame. The upper layer includes multiple devices connected via the internal bus IB2.

[0042] The CPU 66 is a processor. The CPU 66 controls the operation of the entire communication device 6 based on a request from the host controller 4. The CPU 66 controls the DRAM controller 67, the NAND controller 68, and the SRAM 69 via the internal bus IB2. For example, the CPU 66 commands the NAND controller 68 to perform write operations, read operations, and the like with respect to the NAND memory 602.

[0043] The DRAM controller 67 controls the DRAM 601 based on a request from the CPU 66. The DRAM controller 67 transmits and receives data to and from the DRAM 601 via a signal line IOc.

[0044] The DRAM 601 is a volatile memory. The DRAM 601 may be another volatile memory or a non-volatile memory. The DRAM 601 temporarily stores data read by the SoC 60 from the NAND memory 602, write data received from the host controller 4, and the like. The DRAM 601 may be implemented inside the SoC 60.

[0045] The NAND controller 68 controls the NAND memory 602. One NAND controller 68 can control multiple NAND memories 602. The NAND controller 68 transmits and receives data to and from the NAND memory 602 via a signal line IOd. For example, the NAND controller 68 transmits data (such as a command, an address, and data) corresponding to a write operation, a read operation, or an erase operation to the NAND memory 602. In addition, the NAND controller 68 receives read data from the NAND memory 602 during a read operation.

[0046] The NAND memory 602 is a non-volatile storage medium. The NAND memory 602 may be a non-volatile storage medium other than a NAND flash memory. The NAND memory 602 stores data received from the NAND controller 68 in a non-volatile manner. The NAND memory 602 also reads out the data stored in a non-volatile manner and transmits it to the NAND controller 68.

[0047] The SRAM 69 is a volatile memory. The SRAM 69 may be another memory having a faster access speed than the DRAM 401. The SRAM 69 can be used as a working area for the CPU 66.

[0048] <1-1-3>Communication frame structure Next, an example of the configuration of a communication frame will be described with reference to Fig. 4. Fig. 4 is a diagram showing an example of a communication frame handled in the communication system according to the first embodiment. In the following description, the identification information of the host controller 4, communication device 6-1, communication device 6-2, communication device 6-3, and communication device 6-4 will be represented as ID0, ID1, ID2, ID3, and ID4, respectively.

[0049] As shown in Fig. 4, a plurality of communication frames FR are transmitted in sequence from the host controller 4. For example, each communication frame FR includes a plurality of containers CT of the same fixed length. In the example of Fig. 4, a communication frame FR-1 includes four containers CT (CT1 to CT4) of the same fixed length. Data (information) that can be inserted or removed from the host controller 4 and the communication device 6 is stored in the containers CT. The communication frames FR-2 and onwards have a similar configuration.

[0050] Each container CT may store data corresponding to the host controller 4 or any of the communication devices 6. In the example of FIG. 4, the container CT1 stores identification information ID1, i.e., data corresponding to the communication device 6-1. The container CT2 stores identification information ID2, i.e., data corresponding to the communication device 6-2. The container CT3 stores identification information ID3, i.e., data corresponding to the communication device 6-3. The container CT4 stores identification information ID4, i.e., data corresponding to the communication device 6-4. Note that the data stored in each container CT is arbitrary. The container CT1 may store identification information ID0, i.e., data corresponding to the host controller 4, or data corresponding to any of the identification information ID2 to ID4. Furthermore, the containers CT2 to CT4 may store data for the identification information ID1.

[0051] The container CT includes a container header CH and a container payload CP. The container header CH includes a CP identifier and destination information. The container header CH may also include source information. The CP identifier is an identifier that identifies the start of the container payload CP and the end of the container payload CP when multiple containers CT are transferred together. The destination information includes identification information ID of the destination communication device 6 or host controller 4. For example, when the destination is the communication device 6-1, the destination information includes information indicating identification information ID1.

[0052] The container payload CP includes data transmitted and received (transferred) between a lower layer and a higher layer. The data length of the data included in the container payload CP is fixed. The container payload CP includes a packet header PH, a packet payload PP, and ECC data ED.

[0053] The packet header PH includes a PP identifier, which is an identifier for identifying the start and end of a packet payload PP when multiple packet payloads PP are transferred collectively.

[0054] The packet payload PP includes data (information) corresponding to an operation executed in a higher layer. In other words, the packet payload PP includes data of the packet PK in the higher layer. For example, the packet payload PP may include information (address) indicating a destination, attribute information (command) of an operation (read operation or write operation, etc.) executed in the higher layer, data (write data or read data, etc.), etc. For example, when a write operation is executed in the NAND memory 602, the packet payload PP transmitted from the lower layer to the higher layer includes a write command, an address, and write data. Also, for example, when a read operation is executed in the NAND memory 602, the packet payload PP transmitted from the higher layer to the lower layer includes read data.

[0055] The ECC data ED is data used by the receiving ECC circuit 44 and the ECC circuit 64 to perform error correction and error detection on the packet header PH and the packet payload PP. The ECC data ED is also data for error correction and error detection that is generated by the transmitting ECC circuit 44 and the ECC circuit 64 based on the packet header PH and the packet payload PP.

[0056] <1-2> Operation The operation of the communication system 1 according to the first embodiment will be described.

[0057] <1-2-1> Overview of communication system operation 5 is a flowchart showing the operation of the communication system according to the first embodiment. When the communication system 1 is powered on (START), the communication system 1 executes an initial setting operation (S1). When the initial setting operation is completed, the communication system 1 executes a normal operation (S2). When the normal operation is completed, the communication system 1 ends the operation (END).

[0058] In this way, the communication system 1 according to the first embodiment executes an initial setting operation and a normal operation. In the following, first, as an example of the normal operation, an example of transmission of a communication frame FR in a ring connection will be described. After that, the initial setting operation will be described in detail.

[0059] <1-2-2> Example of sending communication frames in a ring connection An example of transmission of a communication frame FR in a ring connection will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of transmission of a communication frame in a ring connection of the communication system according to the first embodiment. Fig. 6 shows a host controller 4 and one device board 5 connected to the host controller 4. In the example of Fig. 6, for the sake of simplicity, a NAND controller 68 connected to an internal bus IB2 is shown in each communication device 6 (6-1 to 6-4), and other circuits and configurations are omitted.

[0060] As shown in Fig. 6, for example, the host controller 4 transmits a communication frame FR including containers CT1, CT2, CT3, and CT4 to the communication device 6-1. In this communication frame FR, data corresponding to the identification information ID1 (communication device 6-1) is stored in the container CT1, data corresponding to the identification information ID2 (communication device 6-2) is stored in the container CT2, data corresponding to the identification information ID3 (communication device 6-3) is stored in the container CT3, and data corresponding to the identification information ID4 (communication device 6-4) is stored in the container CT4. Note that the container payload CP in each container CT includes a packet header PH, a packet payload PP, and ECC data ED. The ECC data ED is generated by the ECC circuit 44 of the host controller 4 based on the packet header PH and the packet payload PP.

[0061] When the communication device 6-1 receives the communication frame FR, the communication device 6-1 executes ECC processing and CRC processing. Specifically, in the communication device 6-1, the ECC circuit 64 executes error correction and error detection of the packet header PH and the packet payload PP based on the ECC data ED included in each container CT. Then, the ECC circuit 64 checks whether all errors have been corrected by the CRC processing. After that, the communication device 6-1 extracts data from the container CT1. More specifically, the communication control circuit 65 of the communication device 6-1 executes the following operations. The communication control circuit 65 checks the destination information of the container header CH of each container CT. When the communication control circuit 65 checks that the container header CH of the container CT1 includes the identification information ID1 of its own device as the destination information, it extracts data from the container payload CP (packet payload PP) of the container CT1. The communication control circuit 65 transmits the extracted data to a higher layer as a packet PK. For example, if the extracted data (packet PK) includes a command requesting a write operation, an address, and write data, the CPU 66 controls the NAND controller 68 to execute a write operation to the NAND memory 602.

[0062] For example, in the communication device 6-1, when there is data (data of the packet PK) to be transmitted to the host controller 4 that can be inserted into the container CT1, the communication control circuit 65 converts the destination information of the container header CH of the container CT1 from the identification information ID1 of the own device to the identification information ID0 of the host controller 4. Then, the communication control circuit 65 inserts the data to be transmitted to the host controller 4 into the container payload CP (packet payload PP) of the container CT1 to update the communication frame FR. For example, when the data to be transmitted is read data corresponding to a command requesting a read operation that was included in the communication frame FR that has already been received, the communication control circuit 65 inserts the data read from the NAND memory 602 into the container payload CP of the container CT1. That is, data corresponding to the identification information ID0 is inserted into the container CT1. Note that, when there is no data (packet PK) to be inserted into the container CT1, the communication control circuit 65 erases the data of the container header CH and the container payload CP of the container CT1 to make them empty (Null), and updates the communication frame FR. Thereafter, the ECC circuit 64 creates and updates the ECC data ED of each container CT based on the packet header PH and packet payload PP included in each container CT. Then, the communication device 6-1 transmits the updated communication frame FR to the communication device 6-2.

[0063] In the communication device 6-2, similarly to the communication device 6-1, ECC processing, CRC processing, and insertion / removal of data of the container CT2 are performed. As a result, data corresponding to the identification information ID2 is extracted from the container CT2. Then, for example, data corresponding to the identification information ID0 is inserted into the container CT2. Furthermore, the ECC data ED of each container CT is updated. After that, the communication device 6-2 transmits the updated communication frame FR to the communication device 6-3.

[0064] In the communication device 6-3, similarly to the communication device 6-1, ECC processing, CRC processing, and insertion / removal of data of the container CT3 are performed. As a result, data corresponding to the identification information ID3 is extracted from the container CT3. Then, for example, data corresponding to the identification information ID0 is inserted into the container CT3. Furthermore, the ECC data ED of each container CT is updated. After that, the communication device 6-3 transmits the updated communication frame FR to the communication device 6-4.

[0065] In the communication device 6-4, similarly to the communication device 6-1, ECC processing, CRC processing, and insertion / removal of data of the container CT4 are performed. As a result, data corresponding to the identification information ID4 is extracted from the container CT4. Then, for example, data corresponding to the identification information ID0 is inserted into the container CT4. Furthermore, the ECC data ED of each container CT is updated. After that, the communication device 6-4 transmits the updated communication frame FR to the host controller 4.

[0066] <1-2-3> Example of initial setting operation of communication system Next, details of the initial setting operation will be described with reference to Fig. 7. Fig. 7 is a flowchart showing the initial setting operation of the communication system according to the first embodiment.

[0067] When the initial setting operation starts (START), the host controller 4 commands each communication device 6 to output a training pattern, and also outputs a training pattern (S11). The training pattern is a pattern known to the host controller 4 and the communication devices 6.

[0068] Next, the host controller 4 and each communication device 6 measure the BER of the received training pattern to check the required ECC capability (S12). Specifically, the host controller 4 and each communication device 6 compare a known training pattern with the reception result of the training pattern transmitted by the previous stage to measure the BER. Then, based on the BER, the ECC capability required for data correction is determined. The ECC capability is, for example, the data size (e.g., the number of bytes) that can be corrected by ECC processing.

[0069] Next, the host controller 4 issues a command to switch the communication method between the host controller 4 and the communication device 6, and the communication method between the communication devices 6, to a low error method (S13). Specifically, for example, the normal method in which communication is performed using PAM4 is switched to a low error method in which communication is performed using PAM2.

[0070] Next, the host controller 4 commands each communication device 6 to transmit the results of the ECC capability check (S14). Specifically, the host controller 4 commands each communication device 6 to transmit the results of the ECC capability check performed in (S12).

[0071] Next, the host controller 4 receives the investigation results from each communication device 6 (S15).

[0072] Next, the host controller 4 determines the ECC capability based on the received check result (S16). The method of determining the ECC capability will be described in detail later.

[0073] Next, the host controller 4 sets the determined ECC capability in each communication device 6 and in itself (the host controller 4) (S17).

[0074] Next, the host controller 4 issues a command to switch the communication method between the host controller 4 and the communication device 6, and the communication method between the communication devices 6, to the normal method (S18). Specifically, for example, the low error method in which communication is performed using PAM2 is switched to the normal method in which communication is performed using PAM4.

[0075] Then, the host controller 4 ends the initial setting operation (END).

[0076] The method of determining the ECC capability shown in (S16) of FIG. 7 will now be described in further detail.

[0077] The communication system 1 according to the first embodiment uses the ECC capability that can handle the most error-prone part of each part of the communication path 8 that constitutes one ring connection in common to the entire communication path that constitutes one ring connection. Specifically, the ECC capability with the highest correction capability among the ECC capabilities examined in (S12) of FIG. 7 is applied to the entire communication path that constitutes the ring connection. For example, assume that one ring connection is composed of two types of parts, a part that can be handled by 1 byte of ECC processing correction capability and a part that can be handled by 3 bytes of ECC correction capability. In this case, the communication system 1 according to the first embodiment uses 3 bytes as the correction capability of ECC processing in the entire ring connection.

[0078] <1-3> Effects According to the communication system 1 according to the first embodiment described above, it is possible to suppress a decrease in data transfer capacity. The effects of the communication system 1 according to the first embodiment will be described in detail below.

[0079] In a communication system having a ring connection, error correction and detection by an ECC circuit prevents data retransmission and maintains the performance of the communication system. If the correction capability of the ECC circuit is insufficient for the amount of errors, retransmission may occur and performance may decrease. In addition, since an increase in the correction capability of the ECC circuit may increase power consumption and latency, it is not desirable to use a correction capability that is higher than necessary. It is desirable to set the correction capability of the ECC circuit to an appropriate correction capability that is appropriate for the amount of errors that occur in the communication path.

[0080] The communication system 1 according to the first embodiment outputs a training pattern in an initial setting operation to investigate the level of correction capability required. Then, based on the investigation result, the correction capability of the ECC circuit is determined and applied to the entire ring connection. This allows the communication system 1 according to the first embodiment to set the correction capability of the ECC circuit to an appropriate correction capability that is appropriate for the amount of errors that occur in the communication path.

[0081] <2> Second embodiment The communication system 1a according to the second embodiment differs from the communication system 1 according to the first embodiment in the specific configuration of the container payload CP and the operation related to the determination of the ECC capability. The following describes the differences between the communication system 1a according to the second embodiment and the first embodiment.

[0082] <2-1> Configuration <2-1-1> Container payload configuration FIG. 8 is a diagram showing an example of the configuration of a container payload of the communication system according to the second embodiment. As shown in FIG. 8, the container payload CP includes a packet header PH, a packet payload PP, and ECC data ED. The container payload CP includes, for example, a packet header PH and a packet payload PP of fixed length 245 bytes, and ECC data ED of fixed length 10 bytes. The ECC data ED may include valid data END and invalid data DAD. When the error correction capability setting of the ECC circuits 44 and 64 is 1 byte, 6 bytes of the 10-byte ECC data ED are valid data END, and 4 bytes are invalid data DAD. The invalid data DAD is null data. When the error correction capability setting of the ECC circuits 44 and 64 is 3 bytes, the 10-byte ECC data ED does not include invalid data DAD, and all 10 bytes are valid data END.

[0083] In this way, the size of the valid data END differs depending on the strength of the error correction capability. However, in the communication system 1a according to the second embodiment, the ECC data ED has a fixed length. Therefore, when there is little valid data END, invalid data DAD is added until the size of the ECC data ED becomes the same as when there is a lot of valid data END. As a result, in the communication system 1a according to the second embodiment, the size of the ECC data ED is kept constant regardless of the strength of the error correction capability.

[0084] <2-2> Operation The method of determining the ECC capability shown in (S16) of FIG. 7 will be described in detail in the case of the second embodiment.

[0085] The communication system 1a according to the second embodiment sets an appropriate ECC capability for each part of the communication path constituting the ring connection. Specifically, the ECC capability checked in (S12) of FIG. 7 is applied to each part of the communication path. For example, assume that one ring connection includes a part where the ECC correction capability can be handled by 1 byte and a part where the ECC correction capability can be handled by 3 bytes. In this case, the communication system 1a according to the second embodiment applies the ECC capability capable of correcting 1 byte to the former and the ECC capability capable of correcting 3 bytes to the latter.

[0086] <2-3> Effects In the communication system 1a according to the second embodiment, the ECC capability is set for each part of the communication path according to the characteristics of each part. The difference in the size of the valid data END depending on the ECC capability is adjusted to the case where the valid data END is the largest size by inserting the invalid data DAD. This makes it possible to fix the size of the container payload CP and to standardize the time required for communication regardless of the ECC capability.

[0087] Furthermore, the communication system 1a according to the second embodiment can set a correction capability suited to the characteristics of each part of the transmission line, and therefore can suppress increases in power consumption and latency due to excessive error correction capability.

[0088] <3> Third embodiment <3-1> Configuration The communication system 1b according to the third embodiment is different from the communication system 1a according to the second embodiment in the specific configuration of the container payload CP and the details of the communication method of the container payload CP. The following describes the differences between the communication system 1b according to the third embodiment and the second embodiment.

[0089] FIG. 9 is a diagram showing an example of the configuration of a container payload of the communication system according to the third embodiment. As shown in FIG. 9, the container payload CP includes a fixed-length packet header PH and packet payload PP, and variable-length ECC data ED. The container payload CP includes, for example, a packet header PH and packet payload PP of 245 bytes (fixed length), and ECC data ED of 6 bytes or 10 bytes (variable length). When the error correction capability of the ECC circuits 44 and 64 is 1 byte, the container payload CP is 251 bytes in total, consisting of the packet header PH and packet payload PP of 245 bytes and the ECC data ED of 6 bytes. In this case, the 6-byte ECC data ED includes 6 bytes of valid data END. When the error correction capability of the ECC circuits 44 and 64 is 3 bytes, the container payload CP is 255 bytes in total, consisting of the packet header PH and packet payload PP of 245 bytes and the ECC data ED of 10 bytes. In this case, the 10-byte ECC data ED includes 10 bytes of valid data END.

[0090] <3-2> Operation The communication system 1b according to the third embodiment changes the speed of communication through the communication path 8 according to the error correction capability set in the ECC circuit 44 or 64. Specifically, when the error correction capability of the ECC circuit 44 or 64 is 1 byte, communication is performed at a normal speed as a reference. On the other hand, when the error correction capability of the ECC circuit 44 or 64 is 3 bytes, communication is performed faster than normal, for example, 1.6% faster. The number 1.6% comes from the fact that 255 bytes is approximately 1.6% larger than 251 bytes when comparing the container payload of 251 bytes with the container payload of 255 bytes. When the error correction capability of the ECC circuit 44 or 64 is 3 bytes, communication is performed 1.6% faster than normal, so that communication can be performed in approximately the same time as communication at a normal speed when the error correction capability of the ECC circuit 44 or 64 is 1 byte.

[0091] <3-3> Effects In the illustrated example, the size of the container payload CP differs by 4 bytes between when the error correction capability of the ECC circuit 44 or 64 is 1 byte and when it is 3 bytes. However, the communication system 1b according to the third embodiment can make the time required for data transfer consistent between when the error correction capability of the ECC circuit 44 or 64 is 1 byte and when it is 3 bytes by performing high-speed communication.

[0092] Furthermore, the communication system 1b according to the third embodiment can set a correction capability suited to the characteristics of each part of the communication path 8, and therefore can suppress an increase in power consumption and latency due to excessive error correction capability.

[0093] <4> Fourth embodiment The communication system 1c according to the fourth embodiment differs from the communication system 1 according to the first embodiment in that the ECC capability is changed in a manner other than the initial setting operation. The following describes the differences between the communication system 1c according to the fourth embodiment and the first embodiment.

[0094] <4-1>Operation The operation of the communication system 1c in the normal operation shown in (S2) of FIG. 5 will be described. In the normal operation, the host controller 4 and each communication device 6 communicate with each other. Here, in the ECC circuit 64 of the communication device 6, if the correction frequency by the ECC process or the retransmission frequency by the CRC process exceeds a threshold, the communication device 6 notifies the host controller 4 that the correction or retransmission is frequent. Similarly, the ECC circuit 44 of the host controller 4 monitors whether the correction frequency by the ECC process or the retransmission frequency by the CRC process exceeds a threshold. The correction frequency is the cumulative number of errors corrected by the ECC process per a certain period of time. The retransmission frequency is the cumulative number of retransmissions caused by the CRC process per a certain period of time. Under such circumstances, the reconfiguration operation is executed.

[0095] FIG. 10 is a flowchart showing a resetting operation of the communication system according to the fourth embodiment.

[0096] When the resetting operation is started (START), the host controller 4 determines whether it has received or detected a notification that corrections or retransmissions are frequent (S21).

[0097] If it has been received or detected (S21, Yes), the host controller 4 determines new ECC capabilities based on the received or detected notification (S22). A method for determining ECC capabilities will be described in detail later.

[0098] Next, the host controller 4 sets the determined ECC capability in each communication device 6 and in itself (the host controller 4) (S23).

[0099] Then, the host controller 4 ends the reconfiguration operation (END).

[0100] It should be noted that if the host controller 4 does not receive or detect a notification that corrections or retransmissions are frequent in (S21) (S21, No), it ends the resetting operation (End).

[0101] The method of determining the ECC capability shown in (S22) of FIG. 10 will now be described in further detail.

[0102] When an error rate increases in a certain portion of a communication path 8, the communication system 1c according to the fourth embodiment determines a higher ECC capability required in that portion as a new ECC capability to be applied to the entire ring connection. Specifically, for example, assume that the entire ring connection operates with an ECC capability capable of correcting one byte, and an error rate increases in a certain portion. In this case, the communication system 1c according to the fourth embodiment determines an ECC capability capable of correcting three bytes as a new ECC capability for the entire ring connection.

[0103] <4-2> Effects Errors occurring in the communication path 8 may increase due to changes in the environment, for example, changes in temperature. The communication system 1c according to the fourth embodiment resets the ECC capability when errors occurring in the communication path 8 increase. This allows the communication system 1c according to the fourth embodiment to set the correction capability of the ECC circuits 44 and 64 to an appropriate correction capability that corresponds to the change in the environment.

[0104] <5> Fifth embodiment A communication system 1d according to the fifth embodiment differs from the communication system 1c according to the fourth embodiment in the method of determining the ECC capability. The following describes the communication system 1d according to the fifth embodiment and the differences from the fourth embodiment.

[0105] <5-1>Operation The method of determining the ECC capability shown in (S22) of FIG. 10 will be described in detail in the case of the fifth embodiment.

[0106] The communication system 1d according to the fifth embodiment sets an appropriate ECC capability for each part of the communication path in each part of the communication path constituting the ring connection. Therefore, the ECC capability is also reset for each part of the communication path. For example, assume that the characteristics of a certain part of the communication path deteriorate, and errors increase with 1-byte correction, which was initially sufficient. In this case, the communication system 1d according to the fifth embodiment changes the ECC capability used for communication related to that certain part to, for example, 3-byte correction, and does not change the ECC capability for communication related to other parts.

[0107] The method of using different ECC capabilities for each part of the communication path may be the method of using invalid data DAD described in the second embodiment, or the method of increasing the communication speed described in the third embodiment.

[0108] <5-2> Effects When the characteristics of a part of a communication path change, the communication system 1d according to the fifth embodiment can change the ECC capability of the ECC process used for the communication related to the part, without changing the ECC capability of the ECC process used for the communication related to the other part of the communication path. This allows the communication system 1d according to the fifth embodiment to respond to changes in the environment.

[0109] Furthermore, the communication system 1d according to the fifth embodiment can set a correction capability suited to the characteristics of each part of the transmission line, and therefore can suppress increases in power consumption and latency due to excessive error correction capability.

[0110] <6> Modifications etc. In the first embodiment, the low error communication method is described by taking as an example a case where PAM4 is switched to PAM2. The low error communication method is not limited to this. For example, it may be a method of communicating the same data multiple times, or communication may be performed via another interface that does not use the communication path 8. Each of these will be described below.

[0111] In the method of communicating the same data multiple times, the same data is sent and received multiple times to improve error tolerance. By sending the same data multiple times, even if an error occurs in each piece of data, it is possible to obtain the correct data by comparing the multiple received data.

[0112] In the method using another interface, communication is not performed via the communication path 8, but using an interface such as I2C and a communication path different from the communication path 8. It is necessary to connect the host controller 4 and the communication device 6, and the communication device 6 and the communication device 6 in advance using an I2C communication path and interface. By using a different interface and communication path where errors are not a problem (are unlikely to occur), it becomes possible to obtain correct data.

[0113] In the above embodiment, the communication device 6 is a memory device including a NAND flash memory, but the communication device 6 is not limited to a memory device. In addition, the multiple communication devices 6 mounted on one device board 5 may be different communication devices 6.

[0114] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0115] 1, 1a, 1b, 1c, 1d...communication system, 2...system board, 3...connector, 4...host controller, 5...device board, 6...communication device, 8...communication path, 40, 60...SoC, 41, 61...receiving unit, 42, 62...transmitting unit, 43, 63...protocol conversion unit, 44, 64...ECC circuit, 45, 65...communication control circuit, 46, 66...CPU, 47, 67...DRAM controller, 48...PCIe controller, 49, 69...SRAM, 68...NAND controller, 401, 601...DRAM, 602...NAND memory, IB1, IB2...internal bus, IOa, IOb, IOc, IOd...signal line.

Claims

1. A host controller; A plurality of communication devices; a communication path that connects the host controller and the plurality of communication devices in a ring shape and is capable of transmitting a communication frame of serial communication; Equipped with each of the host controller and the plurality of communication devices includes an ECC circuit that performs error correction and detection and has a variable error correction capability; the host controller sets an error correction capability of the ECC circuit in accordance with an error occurrence status in the communication path. Communication systems.

2. when a first amount of errors occurs in a first portion of the communication path and a second amount of errors occurs in a second portion of the communication path, the second amount being greater than the first amount, the host controller applying an error correction capability to the first portion and the second portion that is capable of accommodating the second amount of errors; The communication system according to claim 1 .

3. when a first amount of errors occurs in a first portion of the communication path and a second amount of errors occurs in a second portion of the communication path, the second amount being greater than the first amount, the host controller: applying a first error correction capability to the first portion capable of accommodating the first amount of errors, and applying a second error correction capability to the second portion capable of accommodating the second amount of errors. The communication system according to claim 1 .

4. a size of the first data to which the first error correction capability is applied; and The size of the second data to which the second error correction capability is applied is equal to the size of the second data to which the second error correction capability is applied. The communication system according to claim 3.

5. the first data having the first error correction capability applied thereto has a first size and is communicated at a first rate; the second data to which the second error correction capability has been applied has a second size larger than the first size and is communicated at a second rate faster than the first rate. The communication system according to claim 3.

6. the host controller outputs a training pattern, causes the plurality of communication devices to output the training pattern, and investigates an occurrence state of an error in the communication path based on the output training pattern; The communication system according to claim 1 .

7. after outputting the training pattern, the host controller communicates with the plurality of communication devices by a second communication method different from a first communication method used when outputting the training pattern; 7. The communication system according to claim 6.

8. The first communication method is communication using PAM4, and the second communication method is communication using PAM2.

8. The communication system according to claim 7.

9. the second communication method includes a process of repeatedly transmitting the same data; 8. The communication system according to claim 7.

10. the second communication method uses a sub-communication path that is different from the communication path and connects the host controller and the plurality of communication devices; 8. The communication system according to claim 7.

11. When an error correction frequency in the ECC circuit or a communication frame retransmission frequency exceeds a reference value for the first portion of the communication path, the host controller: changing an error correction capability between the first portion and a second portion different from the first portion; The communication system according to claim 1 .

12. When an error correction frequency in the ECC circuit or a communication frame retransmission frequency exceeds a reference value for the first portion of the communication path, the host controller: changing an error correction capability for the first portion; The communication system according to claim 1 .

13. a receiving circuit that receives a communication frame of serial communication from a communication path that connects the host controller and a plurality of communication devices in a ring shape; a transmission circuit for transmitting a communication frame to the communication path; an ECC circuit that performs error correction and detection and has a variable error correction capability; Including, setting an error correction capability of the ECC circuit based on an instruction from the host controller; Communication devices.

14. A communication method in a communication system including a host controller and a plurality of communication devices, each of which includes an ECC circuit that performs error correction and detection and has a variable error correction capability, and a communication path that connects the host controller and the plurality of communication devices in a ring shape and is capable of transmitting a communication frame of serial communication, the communication method comprising: setting an error correction capability of the ECC circuit according to an error occurrence status in the communication path. Communication methods.

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