Semiconductor device, electric power conversion system and method for manufacturing semiconductor device
The semiconductor device addresses the issue of adhesive contact with the conductor pattern by incorporating a resin case with a stepped portion, enhancing insulation performance and reliability while allowing for a more compact and efficient design.
Patent Information
- Application Number
- JP2023151987
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-20
- Publication Date
- 2025-04-02
AI Technical Summary
The existing semiconductor devices face reliability issues due to adhesive contact with the conductor pattern during bonding, leading to compromised insulation performance. Additionally, attempts to mitigate this by increasing the substrate and resin case size result in heat dissipation, productivity, and circuit layout challenges.
The semiconductor device incorporates a resin case with a stepped portion on the fixed portion side, preventing adhesive contact with the conductor pattern. This configuration enhances the insulation distance and reduces the risk of adhesive contact, while also allowing for improved heat dissipation and circuit layout flexibility.
The stepped portion design effectively prevents adhesive contact with the conductor pattern, thereby enhancing the insulation performance and reliability of the semiconductor device. This configuration also allows for a more compact design, improved heat dissipation, and increased productivity.
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Figure 2025044428000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device. [Background technology]
[0002] Semiconductor devices are mounted on inverters and servo amplifiers installed in FA (Factory Automation) devices, etc. One type of semiconductor device is a case-type semiconductor module (see, for example, Patent Document 1). This semiconductor module is formed by bonding a resin case in which electrode terminals for electrical connection to the outside are embedded and a substrate on which a main circuit including a semiconductor element is provided with an adhesive, connecting the electrode terminals and the main circuit with wire bonds or the like, and sealing them with a sealing resin. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2008-252055 A Summary of the Invention [Problem to be solved by the invention]
[0004] When bonding a substrate and a resin case, if the amount of adhesive applied is small, there is a risk of a gap being formed between the substrate and the resin case, causing the sealing resin to leak, so generally, a larger amount of adhesive is applied. However, as in Patent Document 1, if an amount of adhesive is increased in a configuration in which the inner wall of the resin case has a tapered shape that approaches the conductor pattern as it moves upward, the adhesive that protrudes to the inside of the resin case is guided toward the conductor pattern by the tapered shape. As a result, the adhesive may come into contact with the conductor pattern, which may reduce the reliability of the insulation performance of the semiconductor device.
[0005] In addition, if the circuit area of the board is limited or the outer dimensions of the board and the resin case are enlarged, the distance between the inner wall of the resin case and the conductor pattern of the board can be increased, so that it is possible to prevent the adhesive from coming into contact with the conductor pattern. However, in this case, new problems arise, such as a decrease in heat dissipation, productivity, or freedom of the board circuit layout, and an increase in the size of the semiconductor device.
[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique capable of improving the reliability of the insulating performance of a semiconductor device. [Means for solving the problem]
[0007] The semiconductor device according to the present disclosure comprises an insulating layer provided on a metal plate, a conductor pattern selectively provided on the insulating layer, a semiconductor element mounted on the conductor pattern, an adhesive provided on an edge of the insulating layer, a fixed portion fixed to the edge of the insulating layer by the adhesive, a resin case having an inner wall located above the fixed portion, and a step portion protruding from the inner wall and having one or more stepped portions on the fixed portion side in a cross-sectional view, an external electrode having a first end located outside the resin case and a second end in contact with the step portion, and a metal wire electrically connecting the second end and the semiconductor element. Effect of the Invention
[0008] According to the present disclosure, the step portion of the resin case has a step shape with one step on the fixing portion side in a cross-sectional view. With this configuration, it is possible to improve the reliability of the insulating performance of the semiconductor device. [Brief description of the drawings]
[0009] [Figure 1] 1 is a top view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3]4 is a flowchart showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] 1 is an enlarged top view showing a configuration of a portion of a semiconductor device according to a first embodiment. [Diagram 5] 1 is an enlarged cross-sectional view showing a configuration of a portion of a semiconductor device according to a first embodiment. [Figure 6] FIG. 11 is a top view showing a configuration of a semiconductor device according to a first modified example. [Figure 7] 11 is an enlarged cross-sectional view showing a configuration of a portion of a semiconductor device according to a second modification. FIG. [Figure 8] 11 is an enlarged cross-sectional view showing a configuration of a portion of a semiconductor device according to a second modification. FIG. [Figure 9] FIG. 11 is a top view showing a configuration of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a top view showing a configuration of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a side view showing a configuration of a semiconductor device according to a third embodiment. [Figure 12] FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0010] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are given the same or similar reference numerals, and different components are mainly described. In addition, in the following description, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily correspond to positions and directions in actual implementation.
[0011] <Embodiment 1> FIG. 1 is a top view showing the configuration of a semiconductor device 1 according to the first embodiment, and FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device 1. As shown in FIG.
[0012] 2, the semiconductor device 1 includes a substrate 2, a semiconductor element 3, a bonding material 4, an adhesive 5, a resin case 6, external electrodes 7, metal wires 8, and a sealing resin 9. The substrate 2 includes a metal base plate 2a, an insulating layer 2b, and a conductor pattern 2c.
[0013] The metal base plate 2a is a metal plate for heat dissipation, and is made of metals with high heat dissipation properties, such as copper (Cu) and aluminum (Al). The insulating layer 2b is provided on the metal base plate 2a, and is made of resin containing insulating fillers, such as aluminum nitride (AlN) and boron nitride (BN). The conductor pattern 2c is a conductor circuit pattern selectively provided on the insulating layer 2b, and is made of metals, such as Cu and Al. A solder resist (not shown) may be provided on the surfaces of the insulating layer 2b and the conductor pattern 2c.
[0014] The semiconductor element 3 is mounted on the conductor pattern 2c and electrically connected to the conductor pattern 2c by a conductive bonding material 4. The semiconductor element 3 is, for example, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a reverse conducting IGBT (RC-IGBT), a Schottky barrier diode (SBD), or a PN junction diode (PND). The material of the semiconductor element 3 may be normal silicon (Si), or may be a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the material of the semiconductor element 3 is a wide band gap semiconductor, for example, the power loss in the semiconductor device 1 can be reduced.
[0015] The bonding material 4 connects the conductor pattern 2c and the semiconductor element 3. The bonding material 4 may be, for example, solder, sintered silver paste, or a conductive adhesive.
[0016] The adhesive 5 is provided on the edge of the insulating layer 2b and has insulating properties. The adhesive 5 may be made of a resin such as epoxy or acrylic, or may be made of a ceramic containing silicon dioxide (SiO2) or the like.
[0017] The resin case 6 has insulating properties, and may be made of, for example, a thermoplastic PPS (PolyPhenylene Sulfide) resin, LCP (Liquid Crystal Polymer) resin, or a thermosetting resin. In the present embodiment 1, the resin case 6 is an insert case in which a part of the external electrode 7 is embedded by insert molding or the like.
[0018] The resin case 6 has a fixed portion 6a, an inner wall 6b, and a step portion 6c. The fixed portion 6a is fixed to the edge of the insulating layer 2b with an adhesive 5. In a cross-sectional view, the fixed portion 6a according to the first embodiment includes a step portion that fits with the edge of the insulating layer 2b, and a part of the step portion is located on the insulating layer 2b. Note that the fixed portion 6a may not have a step portion, and the entire fixed portion 6a may be located on the insulating layer 2b.
[0019] The inner wall 6b is located above the fixed portion 6a, and the step portion 6c protrudes from the inner wall 6b. The step portion 6c rises steeply from the inner wall 6b and has a step shape with one step on the fixed portion 6a side in a cross-sectional view. In the example of Fig. 2, the base portion of the step portion 6c protruding from the inner wall 6b is located above the upper portion of the conductor pattern 2c.
[0020] Here, when the semiconductor device 1 is formed, if the fixing portion 6a of the resin case 6 is fitted into the insulating layer 2b, the adhesive 5 applied between the fixing portion 6a and the insulating layer 2b protrudes to the inside of the resin case 6.
[0021] In the conventional semiconductor device, the inner wall of the resin case has a tapered shape that approaches the conductor pattern as it approaches the upper side, so that the adhesive 5 that protrudes to the inside of the resin case is guided toward the conductor pattern 2c by the tapered shape. As a result, the adhesive 5 may come into contact with the conductor pattern 2c, which may reduce the reliability of the insulation performance.
[0022] In contrast, in the first embodiment, the step portion 6c has a step shape with one step on the fixed portion 6a side in a cross-sectional view. With this configuration, the space for retaining the adhesive 5 can be increased on the fixed portion 6a side of the step portion 6c, so that the adhesive 5 can be prevented from contacting the conductor pattern 2c. In addition, since the step portion 6c does not have a tapered shape, it is possible to prevent the adhesive 5 from being guided to the conductor pattern 2c, and as a result, it is possible to prevent the adhesive 5 from contacting the conductor pattern 2c.
[0023] As a result, it is possible to improve the reliability of the insulating performance of the semiconductor device 1. In addition, it is possible to ease the restrictions on the area of the substrate 2 and reduce the outer shape of the resin case 6, which is expected to improve heat dissipation, productivity, or freedom of circuit layout of the substrate 2, or to reduce the size of the semiconductor device 1.
[0024] In Fig. 2, the step portion 6c has a step shape with one step on the fixing portion 6a side in a cross-sectional view, but is not limited thereto and may have a step shape with two or more steps. Although details will be described later with reference to Fig. 5, the step portion 6c of the resin case 6 is provided with a through hole 6e extending in the vertical direction. As shown in Fig. 1, the resin case 6 according to the first embodiment is provided with a screw hole 6d for screwing the semiconductor device 1 to a heat sink or the like.
[0025] 2, the external electrode 7 has an electrode terminal 7a which is a first end located outside the resin case 6, and a wire bond pad 7b which is a second end located inside the resin case 6. The external electrode 7 according to the first embodiment has a bent portion embedded in the resin case 6 between the electrode terminal 7a and the wire bond pad 7b. The electrode terminal 7a protrudes in a substantially vertical direction from the upper surface of the resin case 6, and the wire bond pad 7b protrudes in a substantially horizontal direction from the inner wall of the resin case 6.
[0026] Such external electrodes 7 enable, for example, the exchange of electrical signals between an external substrate electrically connected to the electrode terminals 7a and metal wires 8 electrically connected to the wire bond pads 7b. The external electrodes 7 may be made of metals such as Cu and Al, and the surfaces of these metals may be plated with nickel (Ni) or the like.
[0027] In the first embodiment, the wire bond pad 7b is provided in contact with the upper portion of the step portion 6c in FIG. 2, and protrudes from the step portion 6c to the inside of the resin case 6. This ensures an insulation distance between the wire bond pad 7b and the conductor pattern 2c in the height direction, and the wire bond pad 7b can be brought closer to the conductor pattern 2c as shown in FIG. 1. This allows the size of the semiconductor device 1 to be reduced when viewed from above. In particular, when the conductor pattern 2c partially overlaps the step portion 6c of the resin case 6 when viewed from above (top), the size of the semiconductor device 1 when viewed from above can be further reduced.
[0028] As shown in FIG. 2, the metal wire 8 directly or indirectly connects the wire bond pad 7b to the semiconductor element 3, thereby electrically connecting the wire bond pad 7b to the semiconductor element 3. In the present embodiment 1, a desired circuit is formed by electrically connecting the conductor pattern 2c, the wire bond pad 7b, and the semiconductor element 3 with a plurality of metal wires 8. The metal wire 8 may be, for example, a wire made of pure aluminum, an aluminum alloy wire whose mechanical strength is improved by a trace amount of additive element, or a copper wire. The metal wire 8 may also include a metal ribbon such as a band-shaped aluminum ribbon, or a bus bar made of copper or aluminum.
[0029] In the first embodiment, as shown in FIG. 2, the connection portion 8a between the metal wire 8 and the wire bond pad 7b is located above a part of the fixed portion 6a that is located on the insulating layer 2b. That is, in a top view, the connection portion 8a between the metal wire 8 and the wire bond pad 7b overlaps with a part of the fixed portion 6a that is located on the insulating layer 2b. With this configuration, the insulating layer 2b suppresses the vertical fluctuation of the connection portion 8a. Therefore, when the metal wire 8 is bonded to the wire bond pad 7b, the dissipation of the ultrasonic waves applied to the metal wire 8 can be suppressed, and the bonding quality of the connection portion 8a can be improved.
[0030] The sealing resin 9 is surrounded by the insulating layer 2b and the resin case 6, and seals the semiconductor element 3 and the like inside the resin case 6. The material of the sealing resin 9 is, for example, silicone gel, epoxy resin, or the like.
[0031] <Manufacturing method> FIG. 3 is a flowchart showing the manufacturing process of the semiconductor device 1 according to the first embodiment.
[0032] First, in step S1, a metal frame is placed in a resin molding die. The metal frame is formed by selectively punching out a metal plate to form a pattern on the metal plate in which electrode terminals of multiple external electrodes 7 are connected by tie bars, and then performing a bending process to form bent portions of the external electrodes 7. The metal frame thus configured includes multiple external electrodes 7 and tie bars that are connecting parts that connect the multiple external electrodes 7 together.
[0033] In step S2, insert molding is performed by injecting resin into the space of the resin molding die in which the metal frame is set, thereby forming the resin case 6 integrated with the metal frame. In the first embodiment, the resin molding die is provided with steps and protrusions for forming the step portion 6c and the through hole 6e, respectively, and the formation of the step portion 6c and the through hole 6e is completed at the time when the resin case 6 is removed from the resin molding die. Note that, although the process of molding the resin case 6 in one step has been described here, the present invention is not limited to this. For example, after primary molding in which the portion covering the external electrode 7 is molded as a primary molded product, secondary molding may be performed in which the remaining portion of the resin case 6 is molded so as to embed the primary molded product.
[0034] In step S3, as shown in FIG. 4, the step portion 6c and the portion of the metal frame 17 other than the tie bar 17a are fixed with the clamp 16 from both sides, and the tie bar 17a of the metal frame 17 is cut, that is, the broken line portion in FIG. 4 is cut. This cutting forms a plurality of individualized external electrodes 7. According to this process, the fixing of the step portion 6c by the clamp 16 can suppress the positional deviation of the tie bar 17a when cutting. This can suppress the metal frame 17 from being cut more than necessary, and therefore an improvement in yield can be expected. In the example of FIG. 4, the clamp 16 fixes the step portion 6c and a portion of the metal frame 17, but the step portion 6c may be fixed without fixing the portion of the metal frame 17.
[0035] In parallel with steps S1 to S3, steps S4 to S7 are carried out.
[0036] In step S4, solder printing is performed to print the bonding material 4 on the conductor pattern 2c of the substrate 2. The following describes the case where cream solder made by kneading an organic material containing solder powder and flux is used as the bonding material 4. In step S5, the semiconductor element 3 is mounted on the bonding material 4. In step S6, reflow is performed by heating the bonding material 4 using a reflow furnace to assemble the semiconductor element 3 on the substrate 2. In step S7, cleaning is performed to remove residues such as flux contained in the bonding material 4.
[0037] In the above, a case where cream solder is used as the bonding material 4 has been described, but the present invention is not limited to this. For example, a sintered silver paste, a sintered bonding material using nanoparticles made of silver or the like, or a conductive adhesive may be used as the bonding material 4, or the semiconductor element 3 may be assembled under reducing gas using sheet solder as the bonding material 4. In these cases, the cleaning process in step S7 can be omitted.
[0038] In step S8, adhesive 5 is applied to either or both of insulating layer 2b of substrate 2 on which semiconductor element 3 is assembled and fixed portion 6a of resin case 6, and the two are fitted together. At this time, adhesive 5 spreads in the horizontal and vertical directions. In contrast, according to the configuration of present embodiment 1, as described above, the space for retaining adhesive 5 can be made larger on the fixed portion 6a side of step portion 6c, so that adhesive 5 can be prevented from contacting conductor pattern 2c. After fitting, adhesive 5 is cured by heat from a heating furnace.
[0039] In step S9, wire bonding is performed using the metal wire 8 to electrically connect the conductor pattern 2c, the wire bond pad 7b of the external electrode 7, and the semiconductor element 3. In wire bonding, an ultrasonic tool applies a load and ultrasonic vibration to the metal wire 8 pressed against the conductor pattern 2c, the wire bond pad 7b of the external electrode 7, or the surface of the semiconductor element 3.
[0040] In step S10, uncured sealing resin 9 is injected into the space surrounded by the insulating layer 2b and the resin case 6 to seal the semiconductor element 3 and the like. For example, the uncured sealing resin 9 is injected from a nozzle provided near the center of the space so as to completely cover the internal wiring such as the metal wires 8. Thereafter, the sealing resin 9 is cured to form the semiconductor device 1.
[0041] Note that, by performing a vacuum degassing process such as evacuation before the sealing resin 9 hardens, it is possible to remove fine air bubbles inside the sealing resin 9 and improve the insulating performance of the semiconductor device 1. However, normally, the removal of air bubbles in the sealing resin filled below the step is hindered by the step, but in the present embodiment 1, it is possible to remove the air bubbles efficiently as described below.
[0042] 5 is an enlarged cross-sectional view for explaining sealing by the sealing resin 9 according to the present embodiment 1. In the present embodiment 1, as shown in FIG. 5, a through hole 6e that is in contact with the sealing resin 9 and extends in the vertical direction is provided in the step portion 6c of the resin case 6. As a result, air bubbles 9a in the sealing resin 9 that fills the lower side of the step portion 6c are discharged to above the step portion 6c through the through hole 6e. As a result, the air bubbles 9a in the sealing resin 9 can be reduced, and the insulating performance of the semiconductor device 1 can be improved.
[0043] In the present embodiment 1, as shown in FIG. 1, the step portion 6c has a square frame shape in a plan view, and the air bubbles 9a are filled at a relatively late stage of the sealing process, so they tend to accumulate in the four corners of the step portion 6c. For this reason, in the present embodiment 1, the through holes 6e are provided in the four corners of the step portion 6c in a plan view, as shown in FIG. 1. This makes it possible to further reduce the air bubbles 9a in the sealing resin 9, and further improve the insulating performance of the semiconductor device 1. In addition, when the diameter of the through hole is 0.4 mm or more, it becomes possible to discharge the air bubbles 9a having a diameter of 0.4 mm or more.
[0044] <Summary of the first embodiment> According to the semiconductor device 1 of the present embodiment 1 as described above, the step portion 6c of the resin case 6 has a step shape on the fixed portion 6a side in a cross-sectional view. This configuration can prevent the adhesive 5 from contacting the conductor pattern 2c, thereby improving the reliability of the insulating performance of the semiconductor device 1. Note that the step portion 6c does not have to have a step shape in all cross sections, and may have a tapered shape in some cross sections.
[0045] In the first embodiment, a through hole 6e extending in the up-down direction is provided in the step portion 6c of the resin case 6. With this configuration, the insulating performance of the semiconductor device 1 can be further improved.
[0046] In the first embodiment, the connection portion 8a between the metal wire 8 and the wire bond pad 7b is located above a part of the fixed portion 6a that is located on the insulating layer 2b. This configuration can suppress dissipation of the ultrasonic waves applied to the metal wire 8, thereby improving the bonding quality of the connection portion 8a.
[0047] Moreover, in the first embodiment, the plurality of external electrodes 7 are formed by cutting the tie bars 17a of the metal frame 17 while the step portion 6c is fixed by the clamp 16. With this configuration, it is possible to prevent the metal frame 17 from being cut more than necessary, and therefore an improvement in yield can be expected.
[0048] <Variation 1> 6(a) to 6(d) are top views of the semiconductor device showing the positional relationship between gel injection position 21, which is the position of the nozzle, and through-hole 6e in the sealing process of step S10.
[0049] 6(a), gel injection position 21 is the center position of resin case 6, and the four corners of resin case 6 that are the furthest horizontally from gel injection position 21 are the final destinations of the gel, which is sealing resin 9 before hardening. The injected gel spreads inside resin case 6 while entraining air bubbles, and the air bubbles eventually gather at the final destination of the gel, so through holes 6e are provided in the four corners of resin case 6 that are the final destinations of the gel.
[0050] In FIG. 6(b), the gel injection position 21 is the upper left position of the resin case 6. In the example of FIG. 6(b), the right side of the resin case 6, which is far from the gel injection position 21 in the horizontal direction, has more through holes 6e than the left side of the resin case 6, which is close to the gel injection position 21 in the horizontal direction. In this way, the multiple through holes 6e may be provided asymmetrically in the top view. With this configuration, air bubbles can be reduced, and therefore insulation properties can be improved. In addition, the orientation of the resin case 6 can be easily grasped, and therefore it is possible to prevent the insulating layer 2b of the substrate 2 from being fitted into the fixed portion 6a of the resin case 6 in the wrong direction.
[0051] In FIG. 6(c), multiple (three) gel injection positions 21 are provided. In FIG. 6(d), one gel injection position is movable. In these cases, air bubbles can also be reduced by placing the through holes 6e in a region that is the final destination of the gel. As described above, air bubbles can be reduced by aligning the through holes 6e with the final destination of the gel, that is, by aligning the gel injection position 21 with the position of the through holes 6e in the resin case 6 and placing it at the farthest position from the through holes 6e.
[0052] <Variation 2> 7(a) to 7(f) are cross-sectional views showing the lower part of the step portion 6c.
[0053] 7(a), the inner diameter db of the through hole 6e at the upper side of the step portion 6c is smaller than the inner diameter da of the through hole 6e at the lower side of the step portion 6c, and the through hole 6e has a tapered shape in which the inner diameter decreases from the bottom to the top. Note that the inner diameter db is larger than the diameter of the air bubbles to be reduced.
[0054] In this way, by expanding the diameter below the through hole 6e, air bubbles in the gel that reach the lower part of the step portion 6c are guided into the through hole 6e, improving the insulation. In addition, the tapered protrusion of the die for forming the tapered through hole 6e acts as a removal taper when the workpiece is removed from the die. This makes it difficult for the workpiece to chip when demolded, and is expected to improve the yield and the die life.
[0055] The through hole 6e in Figures 7(b) to (f) is a modified example of the through hole 6e in Figure 7(a). In any of Figures 7(b) to (f), the inner diameter of the through hole 6e becomes smaller from the bottom to the top, so that the same effect as in Figure 7(a) can be expected.
[0056] 8, in a cross section passing through the inner wall 6b and the step portion 6c of the resin case 6 without passing through the wire bond pad 7b, the inner diameter of the inner wall 6b below the step portion 6c may become smaller from the bottom to the top. In this case, too, it is possible to reduce air bubbles, and it is expected that the yield and the mold life will be improved, as in the above case.
[0057] <Embodiment 2> 9 is a top view showing the configuration of a semiconductor device 1 according to the second embodiment. In the second embodiment, instead of the through hole 6e, a notch 6f penetrating in the vertical direction in a cross-sectional view is provided in the inner periphery of the step portion 6c in a plan view. This notch 6f is provided in a portion of the step portion 6c where the wire bond pad 7b is not provided. The shape of the notch 6f in a plan view may be a semicircle, a semiellipse, a triangle, or a rectangle.
[0058] The upward movement of the gel through the notch 6f is not impeded by other parts of the resin case 6, so the gel has high fluidity and air bubbles can be easily removed. Air bubbles around the notch 6f gather at the notch 6f and are removed upward, so the number of air bubbles can be reduced and insulation can be improved.
[0059] <Embodiment 3> Fig. 10 is a top view showing the configuration of a semiconductor device 1 according to the third embodiment. Fig. 11 is a side view showing the semiconductor device 1 fixed to a chassis 26.
[0060] 10, in the present embodiment 3, the total area of the plurality of through holes 6e in plan view is ¼ or more of the area of the step portion 6c in plan view excluding the portion where the wire bond pad 7b is provided. Note that the shape of the through holes 6e in plan view is not limited to a circle, and may be an elongated hole or a rectangle as long as the above area relationship is satisfied.
[0061] In FIG. 11, the semiconductor device 1 is fastened to the chassis 26 by screws 28. A heat dissipation grease 27 is provided between the metal base plate 2a on the back surface of the semiconductor device 1 and the chassis 26, and the heat dissipation grease 27 efficiently transfers heat generated from the semiconductor device 1 to the chassis 26. Note that a heat dissipation sheet made of a gel-like material, a TIM (Thermal Interface Material), or the like may be used instead of the heat dissipation grease 27. The chassis 26 is cooled by an air-cooled fan or a water-cooled system (not shown), so that the semiconductor device 1 can be used at a higher output.
[0062] In order to ensure heat dissipation, the metal base plate 2a on the back surface of the semiconductor device 1 in Fig. 11 protrudes downward from the resin case 6 and is in contact with the heat dissipation grease 27. However, if the metal base plate 2a protrudes excessively, the screw fastening portion of the resin case 6 will not seat on the chassis 26 when the screws 28 are fastened, so an upper limit standard is set for the amount of protrusion.
[0063] After the bonding process (step S8 in FIG. 3) between the insulating layer 2b of the substrate 2 and the resin case 6, the substrate 2 may warp due to the difference in thermal expansion coefficient between the resin case 6 and the metal base plate 2a. In the third embodiment, the total area of the through holes 6e in plan view is set to be ¼ or more of the area of the step portion 6c in plan view excluding the portion where the wire bond pad 7b is provided. This can reduce the rigidity of the resin case 6, thereby suppressing the amount of warping. In addition, since the rigidity of the resin case 6 is reduced, the screw fastening portion of the semiconductor device 1 can be easily seated on the chassis 26, so that the design tolerance regarding the protrusion amount of the metal base plate 2a can be widened, and the yield of the bonding process can be increased.
[0064] <Fourth embodiment> The power conversion device according to the fourth embodiment includes the semiconductor device 1 according to the above-mentioned first embodiment. Although the power conversion device according to the fourth embodiment is not limited to a specific power conversion device, hereinafter, a case where the power conversion device according to the fourth embodiment is applied to a three-phase inverter will be described.
[0065] FIG. 12 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to the fourth embodiment is applied.
[0066] The power conversion system shown in Fig. 12 is composed of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various power sources, and may be composed of, for example, a DC system, a solar cell, or a storage battery, or may be composed of a rectifier circuit or an AC / DC converter connected to an AC system. The power source 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.
[0067] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 12, the power conversion device 200 includes a main conversion circuit 201 that converts input DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.
[0068] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.
[0069] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and free wheel diodes (not shown). The switching elements are switched to convert DC power supplied from the power source 100 into AC power, and supply the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the fourth embodiment is a two-level three-phase full bridge circuit, and can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element. Each switching element of the main conversion circuit 201 is configured by a semiconductor module 202 to which the semiconductor device 1 according to the first embodiment is applied. Two switching elements of the six switching elements are connected in series to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.
[0070] The main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built in the semiconductor module 202, or may be configured to include a drive circuit separate from the semiconductor module 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201, and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit outputs a drive signal that turns the switching element on and a drive signal that turns the switching element off to the control electrodes of each switching element in accordance with a control signal from a control circuit 203, which will be described later. When the switching element is to be maintained in the on state, the drive signal is a voltage signal (on signal) that is greater than the threshold voltage of the switching element, and when the switching element is to be maintained in the off state, the drive signal is a voltage signal (off signal) that is smaller than the threshold voltage of the switching element.
[0071] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by PWM (Pulse Width Modulation) control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
[0072] In the power conversion device according to the present embodiment 4 as described above, the semiconductor device 1 according to the present embodiment 1 is applied as a switching element of the main conversion circuit 201, and therefore the reliability of the insulation performance of the power conversion device can be improved.
[0073] In the above-described fourth embodiment, an example in which the semiconductor device 1 according to the first embodiment is applied to a two-level three-phase inverter has been described, but the fourth embodiment is not limited to this and can be applied to various power conversion devices. Although the power conversion device according to the fourth embodiment is described as a two-level power conversion device, it may be a three-level or multi-level power conversion device, and the power conversion device may be applied to a single-phase inverter when power is supplied to a single-phase load. Moreover, the semiconductor device 1 may be applied to a DC / DC converter or an AC / DC converter when power is supplied to a DC load or the like.
[0074] Furthermore, the power conversion device of this embodiment 4 is not limited to the case where the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.
[0075] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.
[0076] Various aspects of the present disclosure are summarized below as appendices.
[0077] (Appendix 1) An insulating layer provided on the metal plate; A conductor pattern selectively provided on the insulating layer; A semiconductor element mounted on the conductor pattern; an adhesive provided on an edge of the insulating layer; a resin case including a fixed portion fixed to the edge portion of the insulating layer by the adhesive, an inner wall located above the fixed portion, and a step portion protruding from the inner wall and having one or more stepped steps on the fixed portion side in a cross-sectional view; an external electrode having a first end located outside the resin case and a second end in contact with the step portion; a metal wire electrically connecting the second end and the semiconductor element; A semiconductor device comprising:
[0078] (Appendix 2) 2. The semiconductor device according to claim 1, a sealing resin surrounded by the insulating layer and the resin case, a through hole in contact with the sealing resin and extending in a vertical direction is provided in the step portion.
[0079] (Appendix 3) 3. The semiconductor device according to claim 2, The step portion has a rectangular frame shape in a plan view, The through holes are provided at four corners of the step portion in a plan view.
[0080] (Appendix 4) The semiconductor device according to claim 2 or 3, A semiconductor device, wherein the through hole has a diameter of 0.4 mm or more.
[0081] (Appendix 5) A semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 4, The semiconductor device, wherein the plurality of through holes are provided asymmetrically in a top view.
[0082] (Appendix 6) A semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 5, The inner diameter of the through hole decreases from the bottom to the top.
[0083] (Appendix 7) A semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 6, A semiconductor device, wherein in a cross section passing through the inner wall and the step portion of the resin case without passing through the second end portion, the inner diameter of the inner wall below the step portion becomes smaller from bottom to top.
[0084] (Appendix 8) A semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 7, A semiconductor device, wherein a total area of the plurality of through holes in a plan view is equal to or greater than 1 / 4 of an area of the step portion in a plan view excluding a portion where the second end portion is provided.
[0085] (Appendix 9) A semiconductor device according to any one of claims 1 to 8, A semiconductor device, wherein an inner periphery of the step portion in a plan view is provided with a notch penetrating therethrough in a vertical direction in a cross-sectional view.
[0086] (Appendix 10) A semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, The semiconductor device, wherein the conductor pattern partially overlaps the step portion of the resin case in a plan view.
[0087] (Appendix 11) A semiconductor device according to any one of claims 1 to 10, A semiconductor device, wherein the material of the semiconductor element includes a wide band gap semiconductor.
[0088] (Appendix 12) The semiconductor device according to claim 11, The semiconductor device, wherein the wide band gap semiconductor includes silicon carbide or diamond.
[0089] (Appendix 13) A semiconductor device according to any one of claims 1 to 11, At least a portion of the fixed portion is located on the insulating layer; A semiconductor device, wherein a connection portion between the metal wire and the second end is located above at least a portion of the fixed portion.
[0090] (Appendix 14) A main conversion circuit having the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 13, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit; A power conversion device comprising:
[0091] (Appendix 15) A method for manufacturing a semiconductor device according to any one of claims 1 to 13, comprising the steps of: forming the resin case integrated with a metal frame including a plurality of the external electrodes and a connecting portion that connects the plurality of external electrodes by insert molding; a step of cutting the connecting portion of the metal frame while the step portion is fixed with a clamp, thereby forming a plurality of the external electrodes. [Explanation of symbols]
[0092] 1 semiconductor device, 2a metal base plate, 2b insulating layer, 2c conductor pattern, 3 semiconductor element, 5 adhesive, 6 resin case, 6a fixing portion, 6b inner wall, 6c step portion, 6e through hole, 6f notch, 7 external electrode, 7a electrode terminal, 7b wire bond pad, 8 metal wire, 8a connection portion, 9 sealing resin, 16 clamp, 17 metal frame, 17a tie bar, 201 main conversion circuit, 203 control circuit.
Claims
1. An insulating layer provided on the metal plate; A conductor pattern selectively provided on the insulating layer; A semiconductor element mounted on the conductor pattern; an adhesive provided on an edge of the insulating layer; a resin case including a fixed portion fixed to the edge portion of the insulating layer by the adhesive, an inner wall located above the fixed portion, and a step portion protruding from the inner wall and having one or more stepped steps on the fixed portion side in a cross-sectional view; an external electrode having a first end located outside the resin case and a second end in contact with the step portion; a metal wire electrically connecting the second end and the semiconductor element; A semiconductor device comprising:
2. 2. The semiconductor device according to claim 1, a sealing resin surrounded by the insulating layer and the resin case, a through hole in contact with the sealing resin and extending in a vertical direction is provided in the step portion.
3. 3. The semiconductor device according to claim 2, The step portion has a rectangular frame shape in a plan view, The through holes are provided at four corners of the step portion in a plan view.
4. 4. The semiconductor device according to claim 2, A semiconductor device, wherein the through hole has a diameter of 0.4 mm or more.
5. 3. The semiconductor device according to claim 2, The semiconductor device, wherein the plurality of through holes are provided asymmetrically in a top view.
6. 3. The semiconductor device according to claim 2, The inner diameter of the through hole decreases from the bottom to the top.
7. 3. The semiconductor device according to claim 2, A semiconductor device, wherein in a cross section passing through the inner wall and the step portion of the resin case without passing through the second end portion, the inner diameter of the inner wall below the step portion becomes smaller from bottom to top.
8. 3. The semiconductor device according to claim 2, A semiconductor device, wherein a total area of the plurality of through holes in a plan view is equal to or greater than ¼ of an area of the step portion in a plan view excluding a portion where the second end portion is provided.
9. 2. The semiconductor device according to claim 1, A semiconductor device, wherein an inner periphery of the step portion in a plan view is provided with a notch penetrating therethrough in a vertical direction in a cross-sectional view.
10. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the conductor pattern partially overlaps the step portion of the resin case in a plan view.
11. 4. The semiconductor device according to claim 1, A semiconductor device, wherein the material of the semiconductor element includes a wide band gap semiconductor.
12. 12. The semiconductor device according to claim 11, The semiconductor device, wherein the wide band gap semiconductor includes silicon carbide or diamond.
13. 4. The semiconductor device according to claim 1, At least a portion of the fixed portion is located on the insulating layer; A semiconductor device, wherein a connection portion between the metal wire and the second end is located above at least a portion of the fixed portion.
14. A main conversion circuit having the semiconductor device according to any one of claims 1 to 3, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit; A power conversion device comprising:
15. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, comprising the steps of: forming the resin case integrated with a metal frame including a plurality of the external electrodes and a connecting portion that connects the plurality of external electrodes by insert molding; a step of cutting the connecting portion of the metal frame while the step portion is fixed with a clamp, thereby forming a plurality of the external electrodes.
Citation Information
Patent Citations
Semiconductor and method for manufacturing the same
JP2008252055A
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