Memory device

Abstract

To provide a memory device capable of performing accurate read operations.SOLUTION: A memory device according to the embodiment includes: a memory cell 20 including a first wiring 11, a second wiring 12, a resistance change memory element 30 capable of exhibiting first and second resistance states, and a selector 40 that transitions from an off state to an on state when a voltage equal to or greater than a first threshold voltage is applied, and is capable of storing data based on the resistance state set in the resistance change memory element; a switching element 61N that inputs a first signal VBL from the second wiring and outputs a second signal VT2 to a third wiring 13 different from the first and second wirings; a voltage applying circuit configured to apply the first voltage to the first wiring at a first time so that the voltage equal to or greater than the first threshold voltage is applied to the selector; and a determining circuit that determines the resistance state set in the resistance change memory element based on the second signal output to the third wiring at a second time.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present invention relates to a storage device. [Background technology]

[0002] 2. Description of the Related Art There has been proposed a memory device in which a plurality of memory cells, each of which includes a resistance change storage element such as a magnetoresistive effect element and a selector for selecting the resistance change storage element, are integrated on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-133577 A Summary of the Invention [Problem to be solved by the invention]

[0004] A storage device capable of performing an accurate read operation is provided. [Means for solving the problem]

[0005] The memory device according to the embodiment includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, a memory cell provided between the first wiring and the second wiring, the memory cell including a resistance change memory element capable of exhibiting a first resistance state and a second resistance state having a resistance higher than the first resistance state, and a selector connected in series to the resistance change memory element and transitioning from an off state to an on state when a voltage equal to or higher than a first threshold voltage is applied, the memory cell being capable of storing data based on the resistance state set in the resistance change memory element, a switching element inputting a first signal from the second wiring and outputting a second signal to a third wiring different from the first and second wirings, a voltage application circuit configured to apply a first voltage to the first wiring at a first time point so that a voltage equal to or higher than the first threshold voltage is applied to the selector, and a determination circuit configured to determine the resistance state set in the resistance change memory element based on the second signal output to the third wiring at a second time point after the first time point. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an overall configuration of a storage device according to a first embodiment. [Diagram 2] 1 is a perspective view showing a schematic configuration of a memory cell array unit of a memory device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view showing a schematic basic configuration of a magnetoresistive effect element of a memory device according to a first embodiment. [Figure 4] 1 is an electric circuit diagram showing a configuration of a circuit including switching elements and the like of a memory device according to a first embodiment. [Diagram 5] 2 is a diagram showing a voltage application circuit of the memory device according to the first embodiment. FIG. [Figure 6] 2 is a diagram illustrating a determination circuit of the memory device according to the first embodiment. FIG. [Figure 7] 4 is a timing chart illustrating a read operation of the memory device according to the first embodiment. [Figure 8] 5A to 5C are diagrams showing specific examples of voltage changes in bit lines and output lines in the memory device according to the first embodiment. [Figure 9] FIG. 11 is an electric circuit diagram showing a configuration of a circuit including switching elements and the like of a memory device according to a second embodiment. [Figure 10] 10 is a timing chart illustrating a read operation of the memory device according to the second embodiment. [Figure 11] 13A and 13B are diagrams showing specific examples of voltage changes in bit lines and output lines in the memory device according to the second embodiment. [Figure 12] FIG. 11 is an electric circuit diagram showing a configuration of a circuit including switching elements and the like of a memory device according to a third embodiment. [Figure 13] FIG. 13 is an electric circuit diagram showing a configuration of a circuit including switching elements and the like of a memory device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] (First embodiment) FIG. 1 is a block diagram showing the overall configuration of a storage device according to the first embodiment.

[0009] The memory device of this embodiment includes a memory cell array unit 100, a word line control circuit 200, a bit line control circuit 300, and a control circuit 400.

[0010] FIG. 2 is a perspective view showing a schematic configuration of the memory cell array unit 100. As shown in FIG.

[0011] The memory cell array section 100 includes a plurality of word lines (first wirings) 11 each extending in the X direction, a plurality of bit lines (second wirings) 12 each extending in the Y direction, and a plurality of memory cells 20 each provided (connected) between a corresponding word line 11 and a corresponding bit line 12.

[0012] Each memory cell 20 includes a magnetoresistive effect element 30 which is a resistance change memory element, and a selector 40 connected in series to the magnetoresistive effect element 30. The magnetoresistive effect element 30 and the selector 40 are stacked in the Z direction.

[0013] The above-mentioned X direction, Y direction, and Z direction intersect with each other. In this embodiment, the X direction, Y direction, and Z direction are perpendicular to each other.

[0014] 2, the word lines 11 are provided on the lower layer side and the bit lines 12 are provided on the upper layer side, but the word lines 11 may be provided on the upper layer side and the bit lines 12 on the lower layer side. Also, in the example shown in Fig. 2, the magnetoresistance effect element 30 is provided on the upper layer side and the selector 40 is provided on the lower layer side, but the magnetoresistance effect element 30 may be provided on the lower layer side and the selector 40 on the upper layer side.

[0015] FIG. 3 is a cross-sectional view that illustrates a basic configuration of the magnetoresistance effect element 30. As shown in FIG.

[0016] The magnetoresistance effect element 30 is an MTJ (magnetic tunnel junction) element, and includes a memory layer 31, a reference layer 32, and a tunnel barrier layer 33. The memory layer 31 is a ferromagnetic layer having a variable magnetization direction. The reference layer 32 is a ferromagnetic layer having a fixed magnetization direction. The tunnel barrier layer 33 is a non-magnetic layer, and is an insulating layer provided between the memory layer 31 and the reference layer 32. Note that, although the memory layer 31 is provided below the reference layer 32 in the example shown in FIG. 3, the memory layer 31 may be provided above the reference layer 32.

[0017] The magnetoresistance effect element 30 can exhibit a low resistance state and a high resistance state having a resistance higher than the low resistance state. When the magnetization direction of the memory layer 31 is parallel to the magnetization direction of the reference layer 32, the magnetoresistance effect element 30 exhibits a low resistance state. When the magnetization direction of the memory layer 31 is antiparallel to the magnetization direction of the reference layer 32, the magnetoresistance effect element 30 exhibits a high resistance state. Therefore, the magnetoresistance effect element 30 can store binary data according to its resistance state. That is, the memory cell 20 can store data based on the resistance state set in the magnetoresistance effect element 30.

[0018] The selector 40 is a bidirectional two-terminal switching element, and has the characteristic of transitioning from an OFF state to an ON state when a voltage equal to or greater than a threshold voltage is applied between two terminals (between a first terminal and a second terminal). For example, the selector 40 may be an element having a structure in which an insulating material is sandwiched between two electrodes (between two terminals). For example, silicon oxide containing arsenic or the like may be used as the insulating material.

[0019] When a voltage is applied between the selected word line 11 and the selected bit line 12 connected to the selected memory cell 20 (the memory cell 20 to be written or read) and a voltage equal to or greater than the threshold voltage is applied to the selector 40, the selector 40 included in the selected memory cell 20 turns on and a current flows through the magnetoresistance effect element 30 included in the selected memory cell 20. As a result, it becomes possible to write or read from the magnetoresistance effect element 30 included in the selected memory cell 20.

[0020] In the following explanation, unless otherwise specified, the selected memory cell 20, the magnetoresistive element 30 contained in the selected memory cell 20, the selector 40 contained in the selected memory cell 20, the selected word line 11 and the selected bit line 12 may be simply referred to as the memory cell 20, the magnetoresistive element 30, the selector 40, the word line 11 and the bit line 12.

[0021] A word line 11 is connected to the word line control circuit 200, and the word line 11 is controlled by the word line control circuit 200. A bit line 12 is connected to the bit line control circuit 300, and the bit line 12 is controlled by the bit line control circuit 300. By supplying control signals (drive signals) from the word line control circuit 200 and the bit line control circuit 300 to the word line 11 and the bit line 12, respectively, it is possible to write to or read from the memory cell 20.

[0022] The control circuit 400 controls the word line control circuit 200 and the bit line control circuit 300.

[0023] As shown in FIGS. 4, 5 and 6, the memory device according to this embodiment includes a switching element (an N-type MOS transistor 61N in the example of FIG. 4), a voltage application circuit 70, a determination circuit 80, and the like.

[0024] The MOS transistor 61N inputs a voltage signal (first signal) VBL from the bit line 12 and outputs a voltage signal (second signal) VT2 to an output wiring (third wiring) 13 different from the word line 11 and the bit line 12, and is provided for each bit line 12.

[0025] Specifically, the MOS transistor 61N includes a gate terminal, a first terminal corresponding to one of the source terminal and the drain terminal, and a second terminal corresponding to the other of the source terminal and the drain terminal. A voltage signal VBL is input from the bit line 12 to the gate terminal, a voltage signal VT1 is input to the first terminal, and a voltage signal VT2 is output from the second terminal to the output wiring 13. A body voltage VBD is applied to the body of the MOS transistor 61N.

[0026] A capacitor 62 is provided on the output wiring 13, and a resistor 63 is provided between the gate terminal of the MOS transistor 61N and the bit line 12. The capacitor 62 is associated with the output wiring 13, and a capacitor element may be used as the capacitor 62, or a parasitic capacitance component of the output wiring 13 or the like may be used as the capacitor 62. Similarly, a resistive element may be used as the resistor 63, or a parasitic resistance component of the wiring or the like may be used as the resistor 63.

[0027] 5 mainly applies a voltage signal to the word line 11 and the first terminal of the MOS transistor 61N. That is, a voltage signal VWL is applied to the word line 11, and a voltage signal VT1 is applied to the first terminal of the MOS transistor 61N. At least a part of the voltage application circuit 70 is included in the word line control circuit 200 shown in FIG.

[0028] 6 determines the resistance state (low resistance state, high resistance state) set in the magnetoresistance effect element 30. Specifically, the voltage signal VT2 of the output wiring 13 and a reference voltage VR are input to the determination circuit 80, and the resistance state set in the magnetoresistance effect element 30 is determined by comparing the voltage (potential) VT2 with the reference voltage (reference potential) VR. At least a part of the determination circuit 80 is included in the bit line control circuit 300 shown in FIG.

[0029] Next, the operation of the storage device according to this embodiment will be described.

[0030] Fig. 7 is a timing chart showing a typical read operation of the memory device according to this embodiment. Specifically, Fig. 7 shows the voltage (potential) VWL of the word line 11, the voltage (potential) VT1 of the first terminal of the MOS transistor 61N, the voltage (potential) VBL of the bit line 12, and the voltage (potential) VT2 of the second terminal of the MOS transistor 61N. For convenience, the vertical scales of the voltages VWL, VT1, VBL, and VT2 are different in Fig. 7.

[0031] In the initial state (state before time t1), the voltages VWL, VT1, VBL, and VT2 are the same voltage V0, and the bit line 12 and the output wiring 13 are maintained in a floating state. For example, the voltage V0 is 4 V, and the body voltage (body potential) VBD of the MOS transistor 61N is 2 V.

[0032] At time t1 (first time point), the voltage VWL of the word line 11 changes from V0 to V1, and the voltage VT1 of the first terminal of the MOS transistor 61N changes from V0 to V2 by the voltage application circuit 70. The difference (absolute value) between the voltages V0 and V1 is greater than the difference (absolute value) between the voltages V0 and V2. For example, the voltage V1 is 0V, and the voltage V2 is 2V. The body voltage VBD is maintained at 2V.

[0033] As described above, it is preferable that the point at which the voltage VT1 changes from V0 to V2 is synchronized (matches) with the point at which the voltage VWL changes from V0 to V1. However, the point at which the voltage VT1 changes may be slightly different from the point at which the voltage VWL changes, so long as the point at which the voltage VT1 changes is sufficiently prior to points t2, t3L, and t3H, which will be described later.

[0034] When the voltage VWL of the word line 11 becomes V1 (first voltage) at time t1, a voltage (V0-V1) is applied to the memory cell 20 connected between the word line 11 and the bit line 12, and the selector 40 transitions from an OFF state to an ON state. In other words, the values ​​of the voltages V0 and V1 are set so that a voltage equal to or greater than the threshold voltage of the selector 40 is applied to the selector 40 at time t1.

[0035] When the selector 40 is turned on at time t1 and a current flows through the memory cell 20, the voltage (potential) VBL of the bit line 12 gradually decreases. That is, since the bit line 12 is maintained in a floating state, the charge held in the bit line 12 is discharged, and the voltage (potential) VBL of the bit line 12 gradually decreases after time t1.

[0036] When the selector 40 is in the on state, the resistance of the memory cell 20 (the series resistance of the magnetoresistive element 30 and the selector 40) depends greatly on the resistance value of the magnetoresistive element 30. That is, the rate of decrease of the voltage (potential) VBLL of the bit line 12 when the magnetoresistive element 30 is in the low resistance state is greater than the rate of decrease of the voltage (potential) VBLH of the bit line 12 when the magnetoresistive element 30 is in the high resistance state.

[0037] Furthermore, when the voltage VT1 of the first terminal of the MOS transistor 61N changes from V0 to V2 at time t1, the MOS transistor 61N is turned on, and a potential difference occurs between the first and second terminals of the MOS transistor 61N. Therefore, a discharge current based on the charge held in the capacitor 62 flows through the MOS transistor 61N. As a result, the voltage (potential) VT2 of the output wiring 13 gradually decreases.

[0038] The voltage VBL of the bit line 12 is applied to the gate terminal of the MOS transistor 61N via a resistor 63. Therefore, the discharge characteristics of the capacitor 62 depend on the voltage (potential) VBL of the bit line 12, and the voltage (potential) VT2 of the output wiring 13 depends on the voltage (potential) VBL of the bit line 12. As shown in Fig. 7, when the voltage (potential) characteristics of the bit line 12 are VBLL, the change in the voltage (potential) of the output wiring 13 is VT2L, and when the voltage (potential) characteristics of the bit line 12 are VBLH, the change in the voltage (potential) of the output wiring 13 is VT2H.

[0039] 7, the rate of decrease of the voltage (potential) VBLL of the bit line 12 when the magnetoresistance effect element 30 is in the low resistance state is larger than the rate of decrease of the voltage (potential) VBLH of the bit line 12 when the magnetoresistance effect element 30 is in the high resistance state. Therefore, time t3L (third time point) at which the MOS transistor 61N turns to the off state when the magnetoresistance effect element 30 is in the low resistance state is before time t3H (third time point) at which the MOS transistor 61N turns to the off state when the magnetoresistance effect element 30 is in the high resistance state.

[0040] When the MOS transistor 61N is turned off, the discharge of the capacitor 62 stops, and the voltage (potential) VT2 of the output wiring 13 becomes a constant value. As described above, the time point t3L is before the time point t3H. Therefore, after the MOS transistor 61N is turned off, a large difference occurs between the voltage (potential) VT2L and the voltage (potential) VT2H of the wiring 13.

[0041] Therefore, at time t2 (second time point) after time t3L and t3H, the resistance state set in the magnetoresistive effect element 30 is determined by the determination circuit 80. That is, the resistance state set in the magnetoresistive effect element 30 is determined based on the voltage (potential) VT2 of the output signal output to the output wiring 13 at time t2. More specifically, the resistance state set in the magnetoresistive effect element 30 is determined by comparing the voltage (potential) VT2 of the output wiring 13 at time t2 with a reference voltage (reference potential) VR.

[0042] When the voltage (potential) VT2 is higher than the reference voltage (reference potential) VR, it is determined that the low resistance state is set in the magnetoresistance effect element 30. When the voltage (potential) VT2 is lower than the reference voltage (reference potential) VR, it is determined that the high resistance state is set in the magnetoresistance effect element 30.

[0043] 8 is a diagram showing a specific example of changes in the voltages (potentials) VBLL and VBLH of the bit lines 12 and changes in the voltages (potentials) VT2L and VT2H of the output wiring 13. As shown in FIG. 8, VBLL, VBLH, VT2L, and VT2H all exhibit the characteristics as described in FIG.

[0044] As described above, in this embodiment, the voltage signal VBL from the bit line 12 is input to the switching element (MOS transistor 61N), and the resistance state set in the magnetoresistance effect element 30 is determined based on the voltage signal VT2 output from the switching element (MOS transistor 61N) to the output wiring 13. This makes it possible to perform an accurate read operation.

[0045] If the resistance state of the magnetoresistive element 30 were to be determined using the voltage signal VBL on the bit line 12, the voltage signal VBL would simply decrease over time, making it difficult to perform the determination operation accurately at the right timing.

[0046] In this embodiment, the MOS transistor 61N transitions from an on state to an off state due to a decrease in the voltage signal VBL of the bit line 12. Since the rate of decrease in the voltage signal VBL of the bit line 12 depends on the resistance state of the magnetoresistance effect element 30, the time when the MOS transistor 61N transitions from an on state to an off state also depends on the resistance state of the magnetoresistance effect element 30. Therefore, a large difference can be generated in the voltage (potential) VT2 of the output wiring 13 when the MOS transistor 61N is in the off state between the case where the magnetoresistance effect element 30 is in the low resistance state and the case where the magnetoresistance effect element 30 is in the high resistance state. Therefore, it is possible to accurately determine the resistance state of the magnetoresistance effect element 30. In addition, after the MOS transistor 61N is in the off state, the value of the voltage (potential) VT2 of the output wiring 13 hardly changes. Therefore, in this embodiment, a sufficient margin can be obtained in terms of time, and an accurate read operation can be performed.

[0047] Second embodiment Next, a storage device according to a second embodiment will be described. Note that the basic features are similar to those of the first embodiment, and therefore the description of the features described in the first embodiment will be omitted.

[0048] FIG. 9 is an electric circuit diagram showing the configuration of a circuit including switching elements and the like of the memory device according to this embodiment.

[0049] In this embodiment, a P-type MOS transistor 61P is used as the switching element. The other basic configuration is the same as in the first embodiment.

[0050] Fig. 10 is a timing chart showing a read operation of the memory device according to this embodiment. Specifically, Fig. 10 shows the voltage (potential) VWL of the word line 11, the voltage (potential) VT1 of the first terminal of the MOS transistor 61P, the voltage (potential) VBL of the bit line 12, and the voltage (potential) VT2 of the second terminal of the MOS transistor 61P. Note that, like Fig. 7 of the first embodiment, the scales of the vertical axes of the voltages VWL, VT1, VBL, and VT2 are not the same.

[0051] The basic read operation of this embodiment is similar to that of the first embodiment described in Fig. 7, and the times t1, t2, t3L, and t3H are also similar to the times t1, t2, t3L, and t3H of the first embodiment. However, in this embodiment, since a P-type MOS transistor 61P is used as a switching element, the direction in which the voltage changes is different from that of the first embodiment.

[0052] In the initial state (state before time t1), similarly to the first embodiment, the voltages VWL, VT1, VBL, and VT2 are the same voltage V0, and the bit line 12 and the output wiring 13 are maintained in a floating state. In this embodiment, for example, the voltage V0 is 0V, and the body voltage (body potential) VBD of the MOS transistor 61P is 2V.

[0053] At time t1, similarly to the first embodiment, the voltage VWL of the word line 11 changes from V0 to V1, and the voltage VT1 of the first terminal of the MOS transistor 61P changes from V0 to V2. In this embodiment, too, the difference (absolute value) between the voltages V0 and V1 is greater than the difference (absolute value) between the voltages V0 and V2. For example, the voltage V1 is 4V, and the voltage V2 is 2V. The body voltage VBD is maintained at 2V.

[0054] In this embodiment, as in the first embodiment, the selector 40 transitions from an off state to an on state at time t1, and a current flows through the memory cell 20. However, in this embodiment, the voltage (potential) VBL of the bit line 12 gradually increases after time t1. In this embodiment, the rate of increase of the voltage (potential) VBLL of the bit line 12 when the magnetoresistance effect element 30 is in a low resistance state is greater than the rate of increase of the voltage (potential) VBLH of the bit line 12 when the magnetoresistance effect element 30 is in a high resistance state.

[0055] In this embodiment, as the voltage (potential) VBL of the bit line 12 increases, the voltage (potential) VT2 of the output wiring 13 also increases. Specifically, when the change in the voltage (potential) of the bit line 12 is VBLL, the change in the voltage (potential) of the output wiring 13 is VT2L, and when the change in the voltage (potential) of the bit line 12 is VBLH, the change in the voltage (potential) of the output wiring 13 is VT2H.

[0056] In this embodiment, as in the first embodiment, the time when the MOS transistor 61P transitions from the on state to the off state is time t3L when the magnetoresistance effect element 30 is in a low resistance state, and is time t3H when the magnetoresistance effect element 30 is in a high resistance state.

[0057] Therefore, in this embodiment, as in the first embodiment, the resistance state set in the magnetoresistance effect element 30 is determined at time t2, which is later than time t3L and time t3H. That is, the resistance state set in the magnetoresistance effect element 30 is determined by comparing the voltage (potential) VT2 of the output wiring 13 at time t2 with a reference voltage (reference potential) VR. In this embodiment, if the voltage (potential) VT2 is lower than the reference voltage (reference potential) VR, it is determined that the magnetoresistance effect element 30 is set to a low resistance state, and if the voltage (potential) VT2 is higher than the reference voltage (reference potential) VR, it is determined that the magnetoresistance effect element 30 is set to a high resistance state.

[0058] 11 is a diagram showing a specific example of changes in the voltages (potentials) VBLL and VBLH of the bit lines 12 and changes in the voltages (potentials) VT2L and VT2H of the output wiring 13. As shown in FIG. 11, VBLL, VBLH, VT2L, and VT2H all exhibit the characteristics as described in FIG.

[0059] In this embodiment, the basic configuration and basic operation are similar to those of the first embodiment, and it is possible to obtain the same effects as those of the first embodiment.

[0060] (Third embodiment) Next, a storage device according to a third embodiment will be described. Note that the basic features are similar to those of the first and second embodiments, and therefore the description of the features described in the first and second embodiments will be omitted.

[0061] 12 is an electric circuit diagram showing the configuration of a circuit including a switching element and the like of the memory device according to this embodiment. In this embodiment, a bipolar MOS transistor 61B is used as the switching element. As the MOS transistor 61B, a MOS transistor using germanium, a MOS transistor using graphene, a Schottky MOS transistor, or the like can be used. The other basic configurations are the same as those of the first and second embodiments.

[0062] The basic read operation of this embodiment is similar to the read operations of the first and second embodiments, and times t1, t2, t3L and t3H are similar to times t1, t2, t3L and t3H of the first and second embodiments.

[0063] In this embodiment, the basic configuration and basic operation are similar to those of the first and second embodiments, and it is possible to obtain the same effects as those of the first and second embodiments.

[0064] In addition, in this embodiment, a bipolar switching element is used, so the direction of the current flowing through the memory cell 20 does not need to be limited to one direction, and the design freedom can be increased.

[0065] (Fourth embodiment) Next, a storage device according to a fourth embodiment will be described. Note that the basic features are the same as those of the first and second embodiments, and therefore the description of the features described in the first and second embodiments will be omitted.

[0066] FIG. 13 is an electric circuit diagram showing the configuration of a circuit including switching elements and the like of the memory device according to this embodiment.

[0067] In this embodiment, a two-terminal switching element 64 including a first terminal and a second terminal is used as a switching element. The two-terminal switching element 64 has a characteristic of transitioning from an off state to an on state when a voltage equal to or greater than a threshold voltage is applied between the first terminal and the second terminal. Other basic configurations are the same as those of the first and second embodiments.

[0068] The basic read operation of this embodiment is similar to the read operations of the first and second embodiments, and times t1, t2, t3L and t3H are similar to times t1, t2, t3L and t3H of the first and second embodiments.

[0069] However, in this embodiment, a voltage signal VBL from the bit line 12 is input to a first terminal of a two-terminal switching element 64, and a voltage signal VT2 is output to the output wiring 13 from a second terminal of the two-terminal switching element 64.

[0070] When the voltage signal VBL on the bit line 12 decreases and the voltage applied between the first terminal and the second terminal of the two-terminal switching element 64 becomes lower than the threshold voltage, the two-terminal switching element 64 transitions from the ON state to the OFF state. That is, at the time point corresponding to the time point t3L or the time point t3H in the first embodiment, the two-terminal switching element 64 transitions from the ON state to the OFF state. Therefore, by performing a determination operation after the time point t3L and the time point t3H, it is possible to perform a determination operation similar to that in the first embodiment.

[0071] In this embodiment, the basic configuration and basic operation are similar to those of the first and second embodiments, and it is possible to obtain the same effects as those of the first and second embodiments.

[0072] Furthermore, in this embodiment, by using the two-terminal switching element 64 as the switching element, it is possible to simplify the entire configuration.

[0073] The two-terminal switching element 64 may be an element having a structure similar to that of the selector 40 included in the memory cell 20. In this case, it is preferable that the threshold voltage of the two-terminal switching element 64 is higher than that of the selector 40 so that the two-terminal switching element 64 turns off before the selector 40 turns off. By using an element having a structure similar to that of the selector 40 for the two-terminal switching element 64, it is possible to simplify the overall configuration.

[0074] In the above-described first to fourth embodiments, a magnetoresistance effect element is used as the resistance change memory element, but other resistance change memory elements may be used.

[0075] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0076] 11...word line (first wiring) 12...bit line (second wiring) 13…Output wiring 20…Memory cell 30...Magnetoresistance effect element (resistance change memory element) 31: memory layer; 32: reference layer; 33: tunnel barrier layer 40…Selector 61N...N-type MOS transistor (switching element) 61P...P-type MOS transistor (switching element) 61B...Bipolar MOS transistor (switching element) 62... Capacitor 63... Resistor 64...2-terminal switching element (switching element) 70: Voltage application circuit 80: Judgment circuit 100... memory cell array section 200... word line control circuit 300... bit line control circuit 400... control circuit

Claims

1. A first wiring extending in a first direction; A second wiring extending in a second direction intersecting the first direction; a memory cell provided between the first wiring and the second wiring, the memory cell including a resistance change memory element capable of exhibiting a first resistance state and a second resistance state having a resistance higher than the first resistance state, and a selector connected in series to the resistance change memory element and transitioning from an off state to an on state when a voltage equal to or higher than a first threshold voltage is applied, the memory cell being capable of storing data based on the resistance state set in the resistance change memory element; a switching element that receives a first signal from the second wiring and outputs a second signal to a third wiring different from the first and second wirings; a voltage application circuit configured to apply a first voltage to the first wiring at a first time point so that a voltage equal to or greater than the first threshold voltage is applied to the selector; a determination circuit configured to determine a resistance state set in the resistance change memory element based on the second signal output to the third wiring at a second time point after the first time point; A storage device comprising:

2. After the first time point, the potential of the first signal decreases or increases; The determination circuit is configured to determine a resistance state set in the resistance change memory element based on a potential of the second signal at the second time point, the potential depending on a potential of the first signal. The storage device according to claim 1 .

3. The determination circuit is configured to determine the resistance state set in the resistance change memory element by comparing the potential of the second signal at the second time point with a reference potential. The storage device according to claim 2.

4. The switching element transitions from an on state to an off state at a third time point due to a change in the potential of the first signal, which decreases or increases after the first time point. The storage device according to claim 2.

5. The second time point is a time point later than the third time point. The storage device according to claim 4.

6. The third point in time differs between when the resistance change memory element is set to a low resistance state and when the resistance change memory element is set to a high resistance state. The storage device according to claim 4.

7. A capacitor associated with the third wiring is further provided. The storage device according to claim 1 .

8. the switching element is a MOS transistor including a gate terminal, a first terminal corresponding to one of a source terminal and a drain terminal, and a second terminal corresponding to the other of the source terminal and the drain terminal; The first signal is input to the gate terminal, and the second signal is output from the second terminal. The storage device according to claim 1 .

9. The voltage application circuit changes the voltage of the first terminal at a time point prior to the second time point. The storage device according to claim 8.

10. The time point at which the voltage application circuit changes the voltage of the first terminal is synchronized with the first time point. The storage device according to claim 9.

11. The MOS transistor has a bipolar The storage device according to claim 8.

12. the switching element is a two-terminal switching element including a first terminal and a second terminal, and transitioning from an off state to an on state when a voltage applied between the first terminal and the second terminal becomes equal to or higher than a second threshold voltage; The first signal is input to the first terminal, and the second signal is output from the second terminal. The storage device according to claim 1 .

13. The second threshold voltage is higher than the first threshold voltage. The storage device of claim 12.

14. The resistance change memory element and the selector are stacked in a third direction intersecting the first and second directions. The storage device according to claim 1 .

15. The resistance change memory element is a magnetoresistance effect element. The storage device according to claim 1 .

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