Semiconductor storage device

Abstract

To improve a reliability of data written to a memory cell.SOLUTION: A semiconductor storage device of an embodiment includes a memory cell and a control circuit. The control circuit is configured to: generate a first voltage corresponding to first data by executing a first read-out in a read-out operation; write second data to the memory cell; generate a second voltage corresponding to the second data by executing a second read-out; and determine the first data based on the first voltage and the second voltage. When the first data and the second data are different, the control circuit performs a first operation, which includes a second write operation for writing the first data, and a verification read-out operation. The control circuit generates a third voltage corresponding to third data by executing the verification read-out, determines third data based on the third voltage and the first voltage or the second voltage, terminates the read-out operation when the first data and the third data are the same, and executes the first operation again when the first data and the third data are different.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor memory devices using resistance change elements as memory elements are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-47950 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the reliability of data written in a memory cell. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a memory cell and a control circuit. The memory cell includes a switching element and a resistance change element. The control circuit is configured to perform a first read on the memory cell in a read operation to generate a first voltage corresponding to the first data, perform a first write after the first read to write second data to the memory cell, perform a second read on the memory cell after the first write to generate a second voltage corresponding to the second data, and determine the first data based on the first voltage and the second voltage. In a read operation, the control circuit performs a first operation including a second write to write the first data to the memory cell and a verify read on the memory cell when the first data and the second data are different. The control circuit generates a third voltage corresponding to the third data by the verify read, determines the third data based on the third voltage and the first voltage or the second voltage, terminates the read operation when the first data and the third data are the same, and performs the first operation again when the first data and the third data are different. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the overall configuration of a memory system including a semiconductor memory device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a semiconductor memory device according to a first embodiment. [Diagram 3] 1 is a perspective view showing an example of a structure of a memory cell array included in a semiconductor memory device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell included in a memory cell array provided in the semiconductor memory device according to the first embodiment. [Diagram 5] 5 is a graph showing an example of characteristics of a memory cell included in a memory cell array of the semiconductor memory device according to the first embodiment. [Figure 6] FIG. 2 is a block diagram showing an example of the configuration of a read circuit included in the semiconductor memory device according to the first embodiment. [Figure 7]3 is a circuit diagram showing an example of a circuit configuration of a preamplifier included in a read circuit provided in the semiconductor memory device according to the first embodiment. [Figure 8] 3 is a circuit diagram showing an example of a circuit configuration of a sense amplifier included in a read circuit provided in the semiconductor memory device according to the first embodiment. [Figure 9] 5 is a flowchart showing an example of a sequence of a read operation of the semiconductor memory device according to the first embodiment. [Figure 10] 5 is a schematic diagram showing an overview of a data determination method in a read operation of the semiconductor memory device according to the first embodiment. [Figure 11] 5 is a schematic diagram showing an example of a change in voltage applied to a memory cell in a read operation of the semiconductor memory device according to the first embodiment. [Figure 12] 11 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the comparative example. [Figure 13] FIG. 11 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the first modified example. [Figure 14] FIG. 13 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the second modified example. [Figure 15] FIG. 13 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the third modified example. [Figure 16] FIG. 13 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the fourth modified example. [Figure 17] FIG. 13 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the fifth modified example. [Figure 18] FIG. 23 is a schematic diagram showing an example of a change in voltage applied to a memory cell when a write-back occurs in a read operation in the sixth modified example. [Figure 19] 10 is a flowchart showing an example of a sequence of a read operation in a semiconductor memory device according to a second embodiment. [Figure 20] 10 is a graph showing an example of the relationship between the write current and the write error rate in the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings referred to below are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are given the same reference symbols. Numbers following letters constituting the reference symbols are used to distinguish between elements that are referred to by the reference symbols containing the same letters and have similar configurations. When it is not necessary to distinguish between elements indicated by reference symbols containing the same letters, these elements are referred to by reference symbols containing only letters.

[0008] In this specification, "connection" refers to being electrically connected, and does not exclude the presence of another element between them. When a transistor or switch circuit is turned on, it is in a conductive state between one end and the other end. When a transistor or switch circuit is turned off, it does not exclude the flow of a minute current such as a leakage current. The "H" level is a voltage level at which an N-type transistor with the voltage applied to its gate terminal is turned on, and a P-type transistor with the voltage applied to its gate terminal is turned off. The "L" level is a voltage level at which an N-type transistor with the voltage applied to its gate terminal is turned off, and a P-type transistor with the voltage applied to its gate terminal is turned on.

[0009] <1> First embodiment The first embodiment relates to a semiconductor memory device 1 that executes a self-referencing read operation. The semiconductor memory device 1 according to the first embodiment executes a verify read after a write-back write in a self-referencing read operation. Details of the semiconductor memory device 1 according to the first embodiment will be described below.

[0010] <1-1> Configuration First, the configuration of a semiconductor memory device 1 according to the first embodiment will be described.

[0011] <1-1-1> Overall configuration of memory system MS Fig. 1 is a block diagram showing an example of an overall configuration of a memory system MS including a semiconductor memory device 1 according to a first embodiment. As shown in Fig. 1, the memory system MS includes a semiconductor memory device 1 and a memory controller 2. The semiconductor memory device 1 operates under the control of the memory controller 2. The memory controller 2 can instruct the semiconductor memory device 1 to perform a read operation, a write operation, etc. in response to a request (command) from an external host device.

[0012] The semiconductor memory device 1 is, for example, a magnetoresistive random access memory (MRAM). The MRAM is a memory device that uses a magnetic tunnel junction (MTJ) element in a memory cell, and is a type of resistance change memory. The MTJ element utilizes the magnetoresistance effect caused by a magnetic tunnel junction. The MTJ element is also called a magnetoresistance effect element. The semiconductor memory device 1 includes, for example, a memory cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0013] The memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. FIG. 1 shows one set of memory cells MC, word lines WL, and bit lines BL among the plurality of memory cells MC, the plurality of word lines, and the plurality of bit lines. The memory cells MC can store data in a non-volatile manner. The memory cells MC are connected between one word line WL and one bit line BL, and correspond to a set of a row and a column. A row address is assigned to the word line WL. A column address is assigned to the bit line BL. One or more memory cells MC can be specified by selecting one row and selecting one or more columns.

[0014] The input / output circuit 12 is connected to the memory controller 2 and controls communication between the semiconductor memory device 1 and the memory controller 2. The input / output circuit 12 transfers a control signal CNT and a command CMD received from the memory controller 2 to a control circuit 13. The input / output circuit 12 transfers a row address and a column address included in an address signal ADD received from the memory controller 2 to a row selection circuit 14 and a column selection circuit 15, respectively. The input / output circuit 12 transfers data DAT (write data) received from the memory controller 2 to a write circuit 16. The input / output circuit 12 transfers data DAT (read data) received from a read circuit 17 to the memory controller 2.

[0015] The control circuit 13 controls the overall operation of the semiconductor memory device 1. The control circuit 13 executes read operations, write operations, etc., based on, for example, control indicated by a control signal CNT and a command CMD. In a write operation, the control circuit 13 supplies a voltage used for writing data to the write circuit 16. In a read operation, the control circuit 13 supplies a voltage used for reading data to the read circuit 17.

[0016] The row selection circuit 14 is connected to a plurality of word lines WL. The row selection circuit 14 selects one word line WL specified by a row address. The selected word line WL is electrically connected to, for example, a driver circuit (not shown).

[0017] The column selection circuit 15 is connected to a plurality of bit lines BL. The column selection circuit 15 selects one or a plurality of bit lines BL specified by a column address. The selected bit line BL is electrically connected to, for example, a driver circuit (not shown).

[0018] The write circuit 16 supplies a voltage used for writing data to the column selection circuit 15, based on the control of the control circuit 13 and the data DAT (write data) received from the input / output circuit 12. When a current based on the write data flows through the memory cell MC, the desired data is written to the memory cell MC.

[0019] The read circuit 17 includes a plurality of sense amplifiers. The read circuit 17 supplies a voltage used for reading data to the column selection circuit 15 under the control of the control circuit 13. Then, each sense amplifier judges the data stored in the memory cell MC based on the voltage or current of the selected bit line BL. Then, the read circuit 17 transfers data DAT (read data) corresponding to the judgment result to the input / output circuit 12.

[0020] <1-1-2> Configuration of memory cell array 11 The following describes the configuration of the memory cell array 11. In the following description, the semiconductor memory device 1 is an MRAM.

[0021] (1: Circuit configuration of memory cell array 11) FIG. 2 is a circuit diagram showing an example of a circuit configuration of the memory cell array 11 included in the semiconductor memory device 1 according to the first embodiment. FIG. 2 shows two word lines WL0 and WL1 of the word lines WL and two bit lines BL0 and BL1 of the bit lines BL. As shown in FIG. 2, the bit lines BL and the word lines WL intersect in the memory cell array 11. Then, memory cells MC are arranged at the intersections of the bit lines BL and the word lines WL. That is, the memory cells MC are arranged in a matrix. Specifically, one memory cell MC is connected between WL0 and BL0, between WL0 and BL1, between WL1 and BL0, and between WL1 and BL1.

[0022] Each memory cell MC includes a resistive change element VR and a switching element SE. The switching element SE is a two-terminal switching element. A two-terminal switching element differs from a three-terminal switching element such as a transistor in that it does not include a third terminal. The resistive change element VR and the switching element SE are connected in series between an associated bit line BL and word line WL. For example, one end of the resistive change element VR is connected to the associated bit line BL. The other end of the resistive change element VR is connected to one end of the switching element SE. The other end of the switching element SE is connected to the associated word line WL.

[0023] The resistance state of the resistance change element VR can change depending on the current flowing through the resistance change element VR. The resistance change element VR stores data in a non-volatile manner based on the resistance state (resistance value). For example, a memory cell MC including a resistance change element VR in a high resistance state stores data "1". A memory cell MC including a resistance change element VR in a low resistance state stores data "0". Note that the allocation of data associated with the resistance value of the resistance change element VR may be set in other ways. When the semiconductor memory device 1 is an MRAM, a magnetoresistance effect element is used as the resistance change element VR.

[0024] The switching element SE controls the supply of current to the resistance change element VR. Specifically, the switching element SE is turned off when a voltage less than the threshold voltage of the switching element SE is applied to the memory cell MC, and is turned on when a voltage equal to or greater than the threshold voltage of the switching element SE is applied to the memory cell MC. The switching element SE in the off state functions as an insulator with a large resistance value. The switching element SE in the off state suppresses current flow through the resistance change element VR. The switching element SE in the on state functions as a conductor with a small resistance value. A current flows through the resistance change element VR connected in series to the switching element SE in the on state. For example, a bidirectional diode is used as the switching element SE. Other elements such as a transistor may also be used as the switching element SE.

[0025] (2: Structure of memory cell array 11) An example of the structure of the memory cell array 11 in the first embodiment will be described below. In the following description, an XYZ orthogonal coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction is a direction intersecting with each of the X direction and the Y direction, and corresponds to a vertical direction with respect to the surface of the substrate of the semiconductor memory device 1. The description of "lower" and its derivatives and related words indicate a position of a smaller coordinate on the Z axis. The description of "upper" and its derivatives and related words indicate a position of a larger coordinate on the Z axis. Hatching is appropriately added to the perspective view. The hatching added to the perspective view is not related to the material or characteristics of the component to which the hatching is added. In the perspective view and the cross-sectional view, the illustration of the configuration such as an interlayer insulating film is omitted.

[0026] 3 is a perspective view showing an example of the structure of the memory cell array 11 included in the semiconductor memory device 1 according to the first embodiment. As shown in FIG. 3, the memory cell array 11 includes a plurality of conductor layers 20 and a plurality of conductor layers 21.

[0027] Each of the multiple conductive layers 20 has a portion extending in the X direction and is separated from each other. The portions of the multiple conductive layers 20 extending in the X direction are aligned in the Y direction. Each conductive layer 20 is used as a word line WL. The multiple conductive layers 21 are provided above a wiring layer in which the multiple conductive layers 20 are provided. Each of the multiple conductive layers 21 has a portion extending in the Y direction and is separated from each other. The portions of the multiple conductive layers 21 extending in the Y direction are aligned in the X direction. Each conductive layer 21 is used as a bit line BL.

[0028] In the top view of FIG. 3, one memory cell MC is disposed at each of the intersections between the multiple conductor layers 20 and the multiple conductor layers 21. Each memory cell MC is provided in a columnar shape extending in the Z direction. In this example, the bottom surface of the memory cell MC contacts the conductor layer 20, and the top surface of the memory cell MC contacts the conductor layer 21. Specifically, in this example, a switching element SE is provided on the conductor layer 20. A resistance change element VR is provided on the switching element SE. A conductor layer 21 is provided on the resistance change element VR.

[0029] Although the above embodiment illustrates a case where the resistance change element VR is provided above the switching element SE, the present invention is not limited to this. Depending on the circuit configuration of the memory cell array 11, the resistance change element VR may be provided below the switching element SE. In addition, other elements or conductive layers may be inserted between the memory cell MC and the conductive layer 20. Similarly, other elements or conductive layers may be inserted between the memory cell MC and the conductive layer 21. Each of the conductive layers 20 and 21 may be called a "wiring".

[0030] (3: Structure of memory cell MC) 4 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell MC included in the memory cell array 11 of the semiconductor memory device 1 according to the first embodiment. As shown in FIG. 4, the memory cell MC has a structure in which, for example, a lower electrode 30, a selector material layer 31, an upper electrode 32, a ferromagnetic layer 40, a nonmagnetic layer 41, and a ferromagnetic layer 42 are stacked in this order from the bottom. The set of the lower electrode 30, the selector material layer 31, and the upper electrode 32 corresponds to the switching element SE. The set of the ferromagnetic layer 40, the nonmagnetic layer 41, and the ferromagnetic layer 42 corresponds to the resistance change element VR.

[0031] Each of the ferromagnetic layers 40 and 42 is made of a ferromagnetic material and has a magnetization direction perpendicular to the film surface. In the MRAM, for example, the magnetization direction of the ferromagnetic layer 40 is fixed, and the magnetization direction of the ferromagnetic layer 42 is variable. In this case, the ferromagnetic layer 40 functions as a reference layer of the MTJ element, and the ferromagnetic layer 42 functions as a storage layer of the MTJ element. The nonmagnetic layer 41 is made of an insulator such as MgO, and functions as a tunnel barrier layer. The ferromagnetic layers 40 and 42 form a magnetic tunnel junction together with the nonmagnetic layer 41. Such a resistance change element VR functions as a perpendicular magnetization type MTJ element utilizing the TMR (tunneling magnetoresistive) effect.

[0032] The resistance change element VR can be in either a low resistance state or a high resistance state depending on the relative relationship between the magnetization directions of the ferromagnetic layers 40 and 42. The resistance change element VR stores data depending on the magnetization direction of the ferromagnetic layer 42 (memory layer). For example, the resistance change element VR in which the magnetization directions of the reference layer and the memory layer are antiparallel (AP state) is in a high resistance state (data "1"). On the other hand, the resistance change element VR in which the magnetization directions of the reference layer and the memory layer are parallel (P state) is in a low resistance state (data "0").

[0033] In this example, the resistance change element VR is in the AP state when a write current is passed in a direction from the ferromagnetic layer 40 to the ferromagnetic layer 42, and is in the P state when a write current is passed in a direction from the ferromagnetic layer 42 to the ferromagnetic layer 40. A write method in which a write current is passed through the resistance change element VR in this way to inject spin torque into the memory layer and reference layer and control the magnetization direction of the memory layer is called a spin injection write method. The resistance change element VR is configured so that the magnetization direction of the ferromagnetic layer 40 does not change when a current of a magnitude capable of reversing the magnetization direction of the ferromagnetic layer 42 is passed through the resistance change element VR.

[0034] In this specification, "the magnetization direction is variable" means that the magnetization direction is changed by the write current. "The magnetization direction is fixed" means that the magnetization direction is not changed by the write current. In the resistance change element VR, the arrangement of the memory layer and the reference layer may be interchanged. The resistance change element VR may have other layers. For example, the resistance change element VR may have a shift cancellation layer that suppresses the influence of the leakage magnetic field of the reference layer, a SAF (Synthetic Anti-Ferromagnetic) structure, etc. In the following, a memory cell MC including a resistance change element VR in the AP state is referred to as a memory cell MC in the AP state. A memory cell MC including a resistance change element VR in the P state is referred to as a memory cell MC in the P state.

[0035] (4: Characteristics of memory cells MC) Fig. 5 is a graph showing an example of the characteristics of a memory cell MC included in the memory cell array 11 of the semiconductor memory device 1 according to the first embodiment. The horizontal axis of the graph shown in Fig. 5 indicates the magnitude of the terminal voltage of the memory cell MC. The vertical axis of the graph shown in Fig. 5 indicates the magnitude of the current flowing through the memory cell MC on a logarithmic scale. Furthermore, Fig. 5 shows the characteristics when the resistance change element VR of the memory cell MC is in a low resistance state and in a high resistance state by solid lines, and shows virtual characteristics that do not actually appear by dashed lines.

[0036] In the following, the terminal voltage of the memory cell MC, i.e., the difference in voltage applied to both ends of the memory cell MC, is also referred to as the "cell voltage." The current flowing through the memory cell MC is also referred to as the "cell current." The following description applies to both the cases where the resistance change element VR of the memory cell MC is in a low resistance state and a high resistance state.

[0037] When the control circuit 13 controls the cell voltage to increase from 0V, the cell current continues to increase until it reaches the threshold voltage Vth of the switching element SE. Until the cell voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is off. Then, when the cell voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC turns on, and the relationship between the cell voltage and the cell current shows a discontinuous change. Specifically, when the cell voltage reaches point A from 0V, the magnitude of the cell current changes to either point B1 or point B2 depending on the resistance state of the resistance change element VR of the memory cell MC. More specifically, the relationship between the cell voltage and the cell current shows the characteristics shown at point B1 when the resistance change element VR is in a low resistance state, and shows the characteristics shown at point B2 when the resistance change element VR is in a high resistance state. The magnitude of the cell current at points B1 and B2 is significantly larger than the magnitude of the cell current at point A.

[0038] When the cell voltage is controlled to be smaller from the state where the cell voltage and the cell current show the relationship shown at point B1 or point B2, the cell current decreases. Then, when the cell voltage is controlled to be smaller and reaches a certain magnitude, the switching element SE of the memory cell MC is turned off, and the relationship between the cell voltage and the cell current shows a discontinuous change. At this time, the cell voltage when the relationship between the cell voltage and the cell current starts to show discontinuity depends on the terminal voltage of the resistance change element VR of the memory cell MC. That is, it depends on whether the resistance change element VR is in a high resistance state or a low resistance state. Specifically, when the resistance change element VR is in a low resistance state, the relationship between the cell voltage and the cell current shows discontinuity from point C1. When the resistance change element VR is in a high resistance state, the relationship between the cell voltage and the cell current shows discontinuity from point C2.

[0039] The relationship between the cell voltage and the cell current shows the characteristic shown at point D1 when the cell voltage reaches point C1 from point B1, and shows the characteristic shown at point D2 when the cell voltage reaches point C2 from point B2. The magnitude of the cell current at point D1 is significantly smaller than the magnitude of the cell current at point C1. Similarly, the magnitude of the cell current at point D2 is significantly smaller than the magnitude of the cell current at point C2. The terminal voltage at point D1 of the memory cell MC including the resistance change element VR in the low resistance state is called the low hold voltage VhdL. The terminal voltage at point D2 of the memory cell MC including the resistance change element VR in the high resistance state is called the high hold voltage VhdH. The magnitude of the high hold voltage VhdH of each of the multiple memory cells MC may differ due to unintended variations in the characteristics of the memory cells MC. The magnitude of the low hold voltage VhdL of each of the multiple memory cells MC may differ due to unintended variations in the characteristics of the memory cells MC.

[0040] <1-1-3> Configuration of read circuit 17 Fig. 6 is a block diagram showing an example of the configuration of the read circuit 17 included in the semiconductor memory device 1 according to the first embodiment. As shown in Fig. 6, the read circuit 17 includes, for example, a pair of a preamplifier 171 and a sense amplifier 172. The pair of the preamplifier 171 and the sense amplifier 172 is associated with one bit line BL.

[0041] The preamplifier 171 is connected to the associated bit line BL and to the nodes NV1st and NV2nd. The preamplifier 171 is configured to supply a current (cell current) to the memory cell MC and to independently reflect a voltage based on the cell current to each of the nodes NV1st and NV2nd. Hereinafter, the voltage of the node NV1st is referred to as "V1st". The voltage of the node NV2nd is referred to as "V2nd".

[0042] The sense amplifier 172 is connected to the nodes NV1st and NV2nd and the nodes DQ and DQS. The sense amplifier 172 is configured to determine the data stored in the memory cell MC based on the voltage difference between the nodes NV1st and NV2nd and output the determination result to the nodes DQ and DQS. When the sense amplifier 172 determines the data, the voltage of the node DQS becomes a voltage of an inverse logic level to that of the node DQ.

[0043] The read circuit 17 may have multiple sets of preamplifiers 171 and sense amplifiers 172. A set of preamplifiers 171 and sense amplifiers 172 may be provided for each bit line BL, or may be shared by two or more bit lines BL. When a set of preamplifiers 171 and sense amplifiers 172 is shared by two or more bit lines BL, the preamplifiers 171 are connected to a global bit line. The global bit line is then connected to two or more bit lines BL via a switching element so as to be selectively conductive.

[0044] (1: Circuit configuration of preamplifier 171) 7 is a circuit diagram showing an example of a circuit configuration of a preamplifier included in a read circuit provided in the semiconductor memory device according to the first embodiment. FIG. 7 also shows a sense amplifier 172 and a memory cell MC associated with one preamplifier 171. As shown in FIG. 7, the preamplifier 171 includes, for example, transistors PM1 to PM3, transistors NM1 and NM2, and capacitors CP1 and CP2. In this specification, the transistor PM is a PMOS transistor. The transistor NM is an NMOS transistor.

[0045] The transistors PM1 and NM1 are connected in parallel between the bit line BL and the node NV1st. Specifically, one end of each of the transistors PM1 and NM1 is connected to the bit line BL. The other end of each of the transistors PM1 and NM1 is connected to the node NV1st. A control signal SW1B is supplied to the gate terminal of the transistor PM1. A control signal SW1P is supplied to the gate terminal of the transistor NM1. The control signal SW1B is a signal with an inverse logic level to the control signal SW1P. The pair of the transistors PM1 and NM1 functions as one switching element (selector) that controls whether or not to transfer a voltage based on the cell current to the node NV1st.

[0046] One electrode of the capacitor CP1 is connected to the node NV1st. The other electrode of the capacitor CP1 is connected to the ground node. A ground voltage is applied to the ground node. When the pair of the transistors PM1 and NM1 is in an on state, the capacitor CP1 is charged with a voltage based on the cell current. When the pair of the transistors PM1 and NM1 is in an off state, the capacitor CP1 functions to maintain the voltage of the node NV1st. Then, the voltage (V1st) of the node NV1st is supplied to the sense amplifier 172.

[0047] The transistors PM2 and NM2 are connected in parallel between the bit line BL and the node NV2nd. Specifically, one end of each of the transistors PM2 and NM2 is connected to the bit line BL. The other end of each of the transistors PM2 and NM2 is connected to the node NV2nd. A control signal SW2B is supplied to the gate terminal of the transistor PM2. A control signal SW2P is supplied to the gate terminal of the transistor NM2. The control signal SW2B is a signal with an inverse logic level to the control signal SW2P. The pair of the transistors PM2 and NM2 functions as one switching element (selector) that controls whether or not to transfer a voltage based on the cell current to the node NV2nd.

[0048] One electrode of the capacitor CP2 is connected to the node NV2nd. The other electrode of the capacitor CP2 is connected to the ground node. When the pair of the transistors PM2 and NM2 is in the on state, the capacitor CP2 is charged with a voltage based on the cell current. When the pair of the transistors PM2 and NM2 is in the off state, the capacitor CP2 functions to maintain the voltage of the node NV2nd. Then, the voltage (V2nd) of the node NV2nd is supplied to the sense amplifier 172.

[0049] The transistor PM3 is a driver circuit for applying a voltage to the bit line BL. One end of the transistor PM3 is connected to a power supply node. For example, a power supply voltage VDD is applied to the power supply node to which the transistor PM3 is connected. The other end of the transistor PM3 is connected to the bit line BL. A control signal DR is supplied to the gate end of the transistor PM3. For example, the control signal DR is set to an "L" level when a voltage is applied to the bit line BL, and is set to an "H" level when no voltage is applied to the bit line BL.

[0050] The preamplifier 171 may have other circuit configurations. For example, each of the capacitors CP1 and CP2 may be formed by a parasitic capacitance. Other switching elements may be used between the node NV1st and the bit line BL and between the node NV2nd and the bit line BL as long as they can be selectively made conductive. The transistor PM3 may be replaced by other elements or circuits. That is, a voltage may be applied to the bit line BL using an element other than a PMOS transistor.

[0051] Each of the control signals SW1P, SW1B, SW2P, SW2B, and DR used to control the preamplifier 171 is generated by, for example, the control circuit 13. The memory cells MC in the memory cell array 11 shown in FIG. 7 correspond to a state during a read operation. In this case, the memory cells MC are connected to a ground node via the word lines WL. When a reverse voltage is applied to the memory cells MC, for example, a voltage is applied to the word lines WL via a driver circuit (not shown), and the bit lines BL are connected to the ground node.

[0052] (2: Circuit configuration of sense amplifier 172) 8 is a circuit diagram showing an example of a circuit configuration of a sense amplifier 172 included in the read circuit 17 of the semiconductor memory device 1 according to the first embodiment. As shown in FIG 8, the sense amplifier 172 includes, for example, transistors PM4 to PM9, transistors NM3 to NM9, and nodes N1 to N3.

[0053] The transistor PM4 has one end connected to the power supply node, the other end connected to the node N1, and a gate end to which a control signal LATP is supplied. The transistor PM5 has one end connected to the node N1, the other end connected to the node DQS, and a gate end connected to the node DQ. The transistor PM6 has one end connected to the node N1, the other end connected to the node DQ, and a gate end connected to the node DQS.

[0054] The transistor PM7 has one end connected to the power supply node, the other end connected to the node DQS, and a gate end supplied with the control signal SEN1. The transistor PM8 has one end connected to the power supply node, the other end connected to the node DQ, and a gate end supplied with the control signal SEN1. The transistor PM9 has one end connected to the node DQ, the other end connected to the node DQS, and a gate end supplied with the control signal SEN1.

[0055] The transistor NM3 has one end connected to the node DQS and the other end connected to the node N2. The transistor NM4 has one end connected to the node DQ and the other end connected to the node N3. The transistor NM5 has one end connected to the node N2, the other end connected to the ground node, and a gate end to which the control signal SEN2 is input. The transistor NM6 has one end connected to the node N3, the other end connected to the ground node, and a gate end to which the control signal SEN2 is input.

[0056] The transistor NM7 has one end connected to the node N2, the other end connected to the ground node, and a gate end connected to the node NV1st. That is, the voltage V1st is applied to the gate end of the transistor NM7. The transistor NM8 has one end connected to the node N3, the other end connected to the ground node, and a gate end connected to the node NV2nd. That is, the voltage V2nd is applied to the gate end of the transistor NM8. The transistor NM9 has one end connected to the node N3, the other end connected to the ground node, and a gate end to which the control signal VSHIFT is supplied.

[0057] The set of transistors PM5, PM6, NM3, and NM4 functions as a latch circuit that stores the result of data determination by the sense amplifier 172. For example, when the control signals SEN1 and LATP are at the “L” level and the control signal SEN2 is at the “H” level, the voltages of the nodes DQ and DQS become approximately the same, and the output of the sense amplifier 172 (the voltages of the nodes DQ and DQS) is reset. After that, when the control signal SEN1 is controlled to the “H” level and the control signal SEN2 is controlled to the “L” level, the latch circuit determines data according to the magnitude of the current flowing through the nodes N2 and N3. The magnitude of the current flowing through the nodes N2 and N3 can change according to the magnitude of the current flowing through the transistors NM7 and NM8, that is, the magnitude of the voltages V1st and V2nd.

[0058] Hereinafter, the current flowing through the transistor NM7 is referred to as "INM7". The current flowing through the transistor NM8 is referred to as "INM8". The current flowing through the transistor NM9 is referred to as "IOFST". Each of the transistors NM7 and NM8 flows a current I0 when a voltage based on a cell current corresponding to "0" data is applied to the gate terminal, and flows a current I1 when a voltage based on a cell current corresponding to "1" data is applied to the gate terminal. In the self-referenced read operation in the first embodiment, INM7 can be I0 or I1, and INM8 can be I0. The current I0 flowing through the transistor NM7 and the current I0 flowing through the transistor NM8 are approximately the same.

[0059] Each of the control signals LATP, SEN1, and SEN2 used to control the sense amplifier 172 is generated by, for example, the control circuit 13. In the sense amplifier 172, a power supply voltage VDD is applied to a power supply node to which the transistors PM4, PM7, and PM8 are connected. In the sense amplifier 172, a ground voltage VSS is applied to a ground node to which the transistors NM5 to NM9 are connected. The circuit configuration of the sense amplifier 172 may be appropriately changed depending on the method of the self-referenced read operation. For example, one end of the transistor NM9 may be connected to the node N2, or a transistor used similarly to the transistor NM9 may be connected to each of the nodes N2 and N3.

[0060] <1-2> Operation Next, a description will be given of the operation of the semiconductor memory device 1 according to the first embodiment. The sequence of the self-referencing read operation executed by the semiconductor memory device 1 according to the first embodiment, a data determination method, and specific examples will be described below in order.

[0061] <1-2-1> Read operation sequence 9 is a flowchart showing an example of a sequence of a read operation of the semiconductor memory device 1 according to the first embodiment. The sequence of a read operation of the semiconductor memory device 1 according to the first embodiment will be described below with reference to FIG.

[0062] 9 (START) when the control circuit 13 of the semiconductor memory device 1 receives, for example, a read operation instruction and address information of the memory cell MC to be read from the memory controller 2. The operation described below corresponds to the processing for the memory cell MC to be read.

[0063] First, the control circuit 13 executes a first read (S10). The first read is an operation to reflect a voltage based on a cell current flowing through the memory cell MC to a node NV1st of the preamplifier 171. In the first read, the control circuit 13 controls each of the control signals DR, SW1B, and SW2P to the "L" level, controls each of the control signals SW1P and SW2B to the "H" level, and electrically connects the word line WL to the ground node. Then, the transistors PM3, PM1, and NM1 are turned on, and the transistors PM2 and NM2 are turned off. As a result, a voltage is applied to the bit line BL via the transistor PM3, and a cell current flows through the memory cell MC. Then, the voltage based on the cell current is reflected to the node NV1st via the pair of the transistors PM1 and NM1. After that, the pair of the transistors PM1 and NM1 is controlled to the off state.

[0064] Next, the control circuit 13 executes a reference write (S11). The reference write is an operation for writing "0" data to the memory cell MC. In the reference write, the control circuit 13 applies, for example, a write voltage to the bit line BL and a ground voltage to the word line WL. This causes a write current to flow from the word line WL to the bit line BL via the memory cell MC, and "0" data is written to the memory cell MC.

[0065] Next, the control circuit 13 executes a second read (S12). The second read is an operation of reflecting a voltage based on a cell current flowing through the memory cell MC to the node NV2nd of the preamplifier 171. The second read corresponds to reading "0" data. In the second read, the control circuit 13 controls each of the control signals DR, SW1P, and SW2B to the "L" level, controls each of the control signals SW1B and SW2P to the "H" level, and electrically connects the word line WL to the ground node. Then, the transistors PM3, PM2, and NM2 are turned on, and the transistors PM1 and NM1 are turned off. As a result, a voltage is applied to the bit line BL via the transistor PM3, and a cell current flows through the memory cell MC. Then, the voltage based on the cell current is reflected to the node NV2nd via the pair of the transistors PM2 and NM2. After that, the pair of the transistors PM2 and NM2 is controlled to be in the off state.

[0066] Next, the control circuit 13 executes data determination (S13). In the data determination, the control circuit 13 causes the latch circuit of the sense amplifier 172 to determine data based on the magnitude of the current flowing through each of the nodes N2 and N3. In this example, the data determination result corresponds to the output voltage of the node DQ.

[0067] Next, the control circuit 13 checks whether the determination result in the process of S13 is "1" data or not (S14). If it is confirmed that the determination result is not "1" data (S14: NO), the data stored in the memory cell MC before the read operation is still stored, so the control circuit 13 ends the series of processes in Fig. 9 (END). If it is confirmed that the determination result is "1" data (S14: YES), the data stored in the memory cell MC is different from the data stored in the memory cell before the read operation, so the control circuit 13 proceeds to the process of S15.

[0068] In the process of S15, the control circuit 13 executes a write-back write. The write-back write is an operation of writing "1" data to the memory cell MC. In the write-back write, the control circuit 13 applies, for example, a write voltage to the word line WL and a ground voltage to the bit line BL. This causes a write current to flow from the bit line BL to the word line WL via the memory cell MC, and "1" data is written to the memory cell MC. However, depending on the characteristics of the memory cell MC, the data stored in the memory cell MC in one write-back operation may not become "1" data.

[0069] Next, the control circuit 13 executes a verify read (S16). The verify read is an operation to read data stored in the memory cell MC where the write-back write has been executed. In the verify read, the control circuit 13 executes, for example, an operation similar to the first read, and reflects a voltage based on the cell current to the node NV1st.

[0070] Next, the control circuit 13 checks whether or not "1" data was read in the verify read of the immediately preceding process of S16 (S17). In the process of S17, the control circuit 13 executes the same data determination as in the process of S13. If it is confirmed that "1" data was not read (S17: NO), the control circuit 13 proceeds to the process of S15 and executes the processes of S15 to S17 again in order. If it is confirmed that "1" data was read (S17: YES), the control circuit 13 ends the series of processes in FIG. 9 (END).

[0071] In the above description, the case where the data stored in the memory cell MC is determined by comparing the result of the verify read with the result of the second read through the processes of S16 and S17 has been exemplified. However, the present invention is not limited to this. In the verify read, the control circuit 13 may execute the same operation as the second read and reflect the voltage based on the cell current to the node NV2nd. In this case, the data stored in the memory cell MC is determined by comparing the result of the verify read with the result of the first read.

[0072] <1-2-2> Data evaluation method 10 is a schematic diagram showing an overview of a data determination method in a read operation of the semiconductor memory device 1 according to the first embodiment. FIG. 10 shows the magnitude of a current associated with a read operation. As shown in FIG. 10, the magnitude of a current I1 associated with data "1" is greater than the current I0 associated with data "0". This is because the voltage of node NV1st or NV2nd based on the cell current of memory cell MC in the AP state storing data "1" is higher than the voltage of node NV1st or NV2nd based on the cell current of memory cell MC in the P state storing data "0".

[0073] In a self-reference read operation, the data stored in the memory cell MC is determined by comparing the result of a first read, which reads data stored in the memory cell MC, with the result of a second read, which reads fixed data stored in the same memory cell MC by executing a reference write. However, if the same data is read in the first read and the second read, the difference in the currents flowing through the nodes N2 and N3 of the sense amplifier 172 shown in FIG. 8 becomes small, which may result in an erroneous determination.

[0074] Therefore, the sense amplifier 172 has a configuration that can increase the difference between the currents flowing through the nodes N2 and N3 when "0" data is read out in both the first read and the second read by using the offset current IOFST. In this example, since the transistor NM9 that flows the offset current IOFST is connected to the node N3, the current flowing through the node N3 is equal to the sum of I0 and IOFST. This allows the sense amplifier 172 to determine that the data of the memory cell MC when the same data is read out in both the first read and the second read is "0" data.

[0075] The data determination method described above corresponds to an operation in which the cell current is larger in a memory cell MC in the P state than in a memory cell MC in the AP state, and the memory cell MC is written to the P state (data "1") in a write-back write. The data determination method by the sense amplifier 172 can be appropriately changed depending on the characteristics of the memory cell MC, the data written to the memory cell MC in a write-back write, and the circuit configurations of the preamplifier 171 and the sense amplifier 172. The semiconductor memory device 1 according to the first embodiment only needs to be configured to perform at least one set of write-back write and verify read when data written to the memory cell MC in a write-back write differs from data stored in the memory cell MC before the read operation in a self-referenced read operation.

[0076] <1-2-3> Example of read operation FIG. 11 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation of the semiconductor memory device 1 according to the first embodiment. The upper part of FIG. 11 shows a change in data stored in the memory cell MC to be read. The horizontal axis of the chart shown in FIG. 11 indicates time, and the vertical axis of the chart indicates the voltage between the terminals of the memory cell MC (cell voltage Vmtj). In the following, it is assumed that a positive cell voltage Vmtj is applied to the memory cell MC when the voltage of the bit line BL is higher than the voltage of the word line WL. As shown in FIG. 11, in this example, the memory cell MC stores data "1" at the start of the read operation.

[0077] In a read operation, first, a first read (1stRead) is executed. In the first read, a read voltage VREAD is applied to the memory cell MC. VREAD is a positive voltage that allows a read current to flow through the memory cell MC.

[0078] Next, a reference write (RW) is executed. In the reference write, a program voltage VPGM0 is applied to the memory cell MC. VPGM0 is a negative voltage that can write data "0" to the memory cell MC. As a result, data "0" is written to the memory cell MC.

[0079] Next, a second read (2ndRead) is executed. In the second read, a read voltage VREAD is applied to the memory cell MC.

[0080] Next, the first write-back write (WB1) is executed. In the write-back write, a program voltage VPGM1 is applied to the memory cell MC. VPGM1 is a positive voltage capable of writing data "1" to the memory cell MC. In other words, a current and a voltage are applied to the memory cell MC in the opposite direction to the reference write. The pulse width of VPGM1 in the first embodiment is a pulse width W1 similar to the program voltage used in the write operation of data "0". In this example, even after the first write-back write is executed, data "0" is stored in the memory cell MC.

[0081] Then, following the first write-back write, a first verify read (VR1) is executed. In the verify read, a read voltage VREAD is applied to the memory cell MC. In this example, since "0" data is read in the first verify read, the control circuit 13 executes the second write-back write and verify read in succession.

[0082] In this example, when the second write-back is performed, data "1" is written to the memory cell MC. Then, data "1" is read out in the second verify-read, so the control circuit 13 ends the read operation.

[0083] As described above, in both the first read and the second read, a current and a voltage are applied to the memory cell MC in the same direction. This direction is defined as the "1" direction. Then, in the reference write, a current and a voltage are applied to the memory cell MC in the opposite direction to the "1" direction. This direction is defined as the "0" direction. By setting the direction in which the current and the voltage are applied in this manner, erroneous writing during read can be suppressed. Also, data can be written with a low current during the reference write.

[0084] <1-3> Effects of the first embodiment According to the semiconductor memory device 1 according to the first embodiment described above, it is possible to improve the reliability of data written to the memory cells MC. The effects of the first embodiment will be described in detail below.

[0085] MRAM is known as a non-volatile memory that can operate at high speed and low voltage. A memory cell MC with a 1S1M type cell structure in which an MTJ element (resistance change element VR) and a switching element SE are stacked can achieve large capacity through high integration and three-dimensional stacking. However, the characteristics of the memory cell MC can differ due to unintended variations.

[0086] Therefore, a self-referenced read operation has been considered as a method for suppressing erroneous reads while taking into account the characteristic variations of memory cells MC. A self-referenced read operation temporarily destroys data stored in the memory cells MC. Then, in order to write the destroyed data back to the memory cells MC, a write-back operation is performed after the data is judged. 12 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the comparative example. In the read operation in the comparative example, a verify read is not executed after the write-back write. In this case, as shown in FIG. 12, if a write failure occurs during a write-back, a read failure occurs in the next read operation. As a method for reducing write failures, it is considered to write strongly using a high program voltage VPGM. However, the use of a high program voltage VPGM may deteriorate the durability of the memory cell MC and may cause a TDDB (Time Dependent Dielectric Breakdown) failure.

[0087] On the other hand, the semiconductor memory device 1 according to the first embodiment executes a verify read immediately after a write-back write in a self-referencing read operation. The semiconductor memory device 1 can detect the occurrence of a write failure by the verify read and can execute a write-back write again. As a result, the semiconductor memory device 1 according to the first embodiment can reduce the occurrence of read failures in the next read operation and can reduce TDDB failures. Therefore, the semiconductor memory device 1 according to the first embodiment can improve the reliability of data written to the memory cells MC.

[0088] <1-4> Modification of the first embodiment The read operation of the semiconductor memory device 1 according to the first embodiment can be modified in various ways. Below, first to sixth modifications of the first embodiment will be described in order.

[0089] (1: First modified example) FIG. 13 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the first modification. As shown in FIG. 13, in the first modification, the control circuit 13 gradually changes the voltage and current applied to the memory cell MC each time a write-back is performed. For example, each time the number of write-backs increases, a voltage obtained by adding DVPGM to the program voltage used in the previous write-back is applied to the memory cell MC. Specifically, the program voltage VPGM1 is applied to the memory cell MC in the first write-back (WB1), and VPGM1+DVPGM is applied to the memory cell MC in the second write-back (WB2). As a result, the first modification can write data "1" to the memory cell MC while suppressing stress on the memory cell MC. The pulse width of the program voltage VPGM1 used in the write-back is, for example, "W1" as in the normal write operation.

[0090] (2: Second Modification) FIG. 14 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the second modified example. As shown in FIG. 14, in the second modified example, the control circuit 13 changes the pulse width of the voltage applied to the memory cell MC in the write-back write from that in the normal write operation. For example, the pulse width of the program voltage VPGM1 used in the write-back write is set to "W2" narrower than that in the normal write operation. Without being limited to this, the pulse width of the program voltage VPGM1 used in the write-back write may be set wider than that in the normal write operation or may be changed each time a write-back write is performed. As a result, the second modified example can write "1" data to the memory cell MC while suppressing stress on the memory cell MC.

[0091] (3: Third Modification) 15 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the third modified example. As shown in FIG. 15, in the third modified example, the control circuit 13 executes a verify read and a next write-back write in succession. Specifically, after applying a read voltage VREAD to the memory cell MC in the first verify read (VR1), the control circuit 13 transitions the voltage of the memory cell MC to the program voltage VPGM1 in succession without transitioning it to 0V. This allows the third modified example to shorten the time of a read operation when a set of a write-back write and a verify write is executed multiple times.

[0092] (4: Fourth Modification) FIG. 16 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the fourth modified example. As shown in FIG. 16, in the fourth modified example, the control circuit 13 executes a second read and a first write-back write in succession. Specifically, after applying a read voltage VREAD to the memory cell MC in the second read, the control circuit 13 transitions the voltage of the memory cell MC to the program voltage VPGM1 in succession without transitioning it to 0V. This allows the fourth modified example to shorten the time of the read operation of the first embodiment. Note that FIG. 16 illustrates an example in which the fourth modified example and the third modified example are combined.

[0093] (5: Fifth Variation) FIG. 17 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the fifth modification. In the fifth modification, a snap-back selector is used as the switching element SE. In the fifth modification, as shown in FIG. 17, the control circuit 13 executes a read operation in which, for example, the third and fourth modifications are combined. When a snap-back selector is used, a spike current SC may occur when the selector is turned on. The occurrence of the spike current SC may deteriorate the durability of the memory cell MC. In contrast, the fifth modification can reduce the number of times the selector is turned on and off by combining the third and fourth modifications, and can reduce the number of occurrences of the spike current SC. As a result, the fifth modification can further suppress deterioration of the durability of the memory cell MC.

[0094] (6: Sixth Variation) FIG. 18 is a schematic diagram showing an example of a change in voltage applied to a memory cell MC when a write-back occurs in a read operation in the sixth modified example. As shown in FIG. 18, in the sixth modified example, a voltage in the opposite direction to that in the first embodiment is used in a read operation. Specifically, a negative read voltage VREADm is applied to the memory cell MC in each of the first read, the second read, and the verify read. In the reference write, a program voltage VPGM2 is applied to the memory cell MC. VPGM2 is a positive voltage capable of writing data "1" to the memory cell MC. In the write-back write, a program voltage VPGM3 is applied to the memory cell MC. VPGM3 is a negative voltage capable of writing data "0" to the memory cell MC. In this case, in the verify read, the control circuit 13 executes an operation similar to that in the second read, reflects a voltage based on the cell current to the node NV2nd, and compares the result of the verify read with the result of the first read. The sixth modified example can obtain the same effect as the first embodiment.

[0095] <2> Second embodiment The semiconductor memory device 1 according to the second embodiment limits the maximum number of executions of a set of write-back write and verify read in a read operation. The following describes the semiconductor memory device 1 according to the second embodiment, focusing mainly on the differences from the first embodiment.

[0096] <2-1> Configuration The configuration of the semiconductor memory device 1 according to the second embodiment is similar to that of the first embodiment.

[0097] <2-2> Operation The operation of the semiconductor memory device 1 according to the second embodiment is similar to that of the first embodiment, except for a part of the sequence of the read operation.

[0098] Fig. 19 is a flowchart showing an example of a sequence of a read operation of the semiconductor memory device 1 according to the second embodiment. As shown in Fig. 19, the sequence of a read operation of the semiconductor memory device 1 according to the second embodiment will be described below with reference to Fig. 19. Note that "N" used in the following description is a variable used by the control circuit 13 and corresponds to the number of times a set of write-back write and verify read is executed. "M" is a fixed number that is determined in advance before the read operation and is used to determine the maximum number of times a set of write-back write and verify read is executed.

[0099] For example, when the control circuit 13 of the semiconductor memory device 1 receives a read operation instruction and address information of the memory cell MC to be read from the memory controller 2, the control circuit 13 starts a series of processes in FIG. 19 (START).

[0100] First, the control circuit 13 executes the process of "N=1" (S20). That is, the control circuit 13 resets the count of the number of times a set of write-back write and verify read has been executed at the start of a read operation.

[0101] Next, the control circuit 13 executes a first read (S10) in the same manner as in the first embodiment.

[0102] Next, the control circuit 13 executes reference writing in the same manner as in the first embodiment (S11).

[0103] Next, the control circuit 13 executes the second read (S12) in the same manner as in the first embodiment.

[0104] Next, the control circuit 13 executes data judgment in the same manner as in the first embodiment (S13).

[0105] Next, the control circuit 13 checks whether the determination result in the process of S13 is "1" data (S14) as in the first embodiment. If it is confirmed that the determination result is not "1" data (S14: NO), the control circuit 13 ends the series of processes in Fig. 19 (END). If it is confirmed that the determination result is "1" data (S14: YES), the control circuit 13 proceeds to the process of S15.

[0106] In the process of S15, the control circuit 13 executes a write-back write, similarly to the first embodiment.

[0107] Next, the control circuit 13 executes a verify read, similarly to the first embodiment (S16).

[0108] Next, the control circuit 13 checks whether or not "1" data was read in the verify read of the immediately preceding process of S16 (S17), as in the first embodiment. If it is confirmed that "1" data was not read (S17: NO), the control circuit 13 proceeds to the process of S21. If it is confirmed that "1" data was read (S17: YES), the control circuit 13 ends the series of processes in FIG. 19 (END).

[0109] In the process of S21, the control circuit 13 checks whether or not "N>M" is satisfied. If it is confirmed that "N>M" is not satisfied (S21: NO), the control circuit 13 increments N (S22) and proceeds to the process of S15. That is, the control circuit 13 increases the count number of times that write-back write and verify read are executed, and executes the processes of S15 to S17 again in order. If it is confirmed that "N>M" is satisfied (S21: YES), the control circuit 13 ends the series of processes in FIG. 19 (END).

[0110] <2-3> Effects of the second embodiment If a write-back / write is performed indefinitely in a read operation, a TDDB failure may occur. In addition, if a memory cell MC in which a TDDB failure has occurred is accessed, it is impossible to perform a write-back, so that a write-back sequence may be performed indefinitely. If a write-back sequence is performed indefinitely, access to other memory cells MC may be hindered.

[0111] In contrast, the semiconductor memory device 1 according to the second embodiment predetermines the maximum number of times to execute a set of write-back write and verify read. As a result, even when the semiconductor memory device 1 according to the second embodiment accesses a memory cell MC in which a TDDB defect has occurred, it is possible to access other memory cells MC. The maximum number of times to execute write-back write can be changed as appropriate depending on the design of the memory cell MC.

[0112] FIG. 20 is a graph showing an example of the relationship between the write current and the write error rate in the semiconductor memory device according to the second embodiment. The horizontal axis of the graph shown in FIG. 20 indicates the magnitude of the write current. The vertical axis of the graph shown in FIG. 20 indicates the write error rate (WER). Ic corresponds to the write current with a write probability of 0.5 for the median bit. Iw corresponds to the actual write current. The median bit (Median) corresponds to the memory cell MC whose write characteristics correspond to the median value. The worst bit (Worst) corresponds to the memory cell MC whose write characteristics are the worst.

[0113] Typically, the worst bit WER is 10 -6 In order to ensure that writing can be performed with approximately the same stress, it is necessary to apply Iw, which is about 1.5 to 2 times Ic, to the memory cell MC. In this case, excessive stress is applied to the median bit. In contrast, by executing the combination of write-back writing and verify read described in the first embodiment, write-back is performed under lower stress conditions than normal writing. As a result, the occurrence of TDDB failures in the worst bit can be reduced. For example, as shown in FIG. 20, if the WER in one write-back writing to the worst memory cell MC is designed to be 0.1 or less, a maximum of about six write-back writings may be performed to achieve a WER of 1 ppm. In this case, by performing six write-back writings, the WER in the worst bit is reduced to 10 -6 is realized.

[0114] <3> others The first to sixth modified examples described in the first embodiment can be appropriately combined. For example, when the first and second modified examples are combined, the control circuit 13 may change the pulse width of the program voltage or the magnitude of the program voltage each time a set of write-back write and verify read is executed. In the above embodiment, the direction of the voltage applied to the memory cell MC is opposite between the first and second reads and the reference write, but the direction of the voltage applied to the memory cell MC may be the same between the first and second reads and the reference write.

[0115] In the above embodiment, the semiconductor memory device 1 is exemplified as an MRAM using a perpendicular magnetization type MTJ element in which the magnetization direction is perpendicular to the film surface, but is not limited thereto. The semiconductor memory device 1 may be an MRAM using an in-plane magnetization type MTJ element in which the magnetization direction is in the in-plane direction. The semiconductor memory device 1 may be a resistance change type memory other than MRAM. Even in a resistance change type memory other than MRAM, the same effect can be obtained by applying the above embodiment. Note that MRAM has a tendency that the characteristic difference between the low resistance state and the high resistance state is smaller than other resistance change type memories. Therefore, the above embodiment can exert a particularly large effect when applied to MRAM.

[0116] In the above embodiment, the bit line BL and the word line WL have a symmetrical relationship. That is, in the above embodiment, the bit line BL may be replaced with the word line WL, and the word line WL may be replaced with the bit line BL. The "0" direction may be called the APtoP direction because the memory cell MC changes from the AP state to the P state. The "1" direction may be called the PtoAP direction because the memory cell MC changes from the P state to the AP state.

[0117] In the above embodiment, the "pulse width" refers to, for example, the time interval between the time of the full width at half maximum from the rising edge of the pulse (voltage) to the peak and the time of the full width at half maximum from the peak to the falling edge of the pulse (voltage). In the above embodiment, one end of the transistor corresponds to one of the source end and the drain end of the transistor. And the other end of the transistor corresponds to the other of the source end and the drain end of the transistor. The correspondence relationship between the one end and the other end and the source end and the drain end may change depending on the type of the transistor (for example, whether the transistor is an NMOS transistor or a PMOS transistor).

[0118] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0119] 1...semiconductor memory device, 2...memory controller, 11...memory cell array, 12...input / output circuit, 13...control circuit, 14...row selection circuit, 15...column selection circuit, 16...write circuit, 17...read circuit, 20, 21...conductive layer, 30...lower electrode, 31...selector material layer, 32...upper electrode, 40, 42...ferromagnetic layer, 41...non-magnetic layer, 171...preamplifier, 172...sense amplifier, BL...bit line, WL...word line, CP1, CP2...capacitor, N1 to N3, NV1st, NV2nd...node, NM1 to NM9...transistor, PM1 to PM9...transistor, SEN1, SEN2, SW1B, SW1P, SW2B, SW2P...control signal

Claims

1. a memory cell including a switching element and a resistance change element; a control circuit configured to, in a read operation, perform a first read on the memory cell to generate a first voltage corresponding to first data, perform a first write after the first read to write second data to the memory cell, perform a second read on the memory cell after the first write to generate a second voltage corresponding to the second data, and determine the first data based on the first voltage and the second voltage; Equipped with In the read operation, the control circuit performing a first operation including a second write operation for writing the first data to the memory cell when the first data and the second data are different, and a verify read operation for the memory cell; generating a third voltage corresponding to third data by the verify read, and determining the third data based on the third voltage and the first voltage or the second voltage; terminate the read operation if the first data and the third data are the same, and execute the first operation again if the first data and the third data are different. Semiconductor memory device.

2. the control circuit is configured to change a program voltage applied to the memory cell in the second write in response to the number of times the first operation has been executed.

2. The semiconductor memory device according to claim 1.

3. the control circuit is configured to change an amount of current flowing through the memory cell in the second write operation according to the number of times the first operation has been executed.

2. The semiconductor memory device according to claim 1.

4. the control circuit is configured to change a pulse width of a program voltage applied to the memory cell in the second write in response to the number of times the first operation has been executed.

2. The semiconductor memory device according to claim 1.

5. the control circuit is configured to continuously execute the verify read of the first operation for an nth time (n is an integer equal to or greater than 1) and the second write of the first operation for an (n+1)th time; 2. The semiconductor memory device according to claim 1.

6. the control circuit is configured to continuously execute the second read and the second write of a first time of the first operation; 2. The semiconductor memory device according to claim 1.

7. The switching element is a snapback type selector.

7. The semiconductor memory device according to claim 5.

8. a direction in which the control circuit applies a voltage to the memory cell in each of the first read, the second read, and the verify read is opposite to a direction in which the control circuit applies a voltage to the memory cell in the first write; 2. The semiconductor memory device according to claim 1.

9. the control circuit is configured to terminate the read operation based on an mth execution of the first operation (m is an integer equal to or greater than 2); 2. The semiconductor memory device according to claim 1.

10. the resistance change element includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; 2. The semiconductor memory device according to claim 1.

11. The switching element is a two-terminal switching element.

2. The semiconductor memory device according to claim 1.

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