Storage device and method of controlling storage device
The storage device addresses the reliability issues in cross-point two-terminal storage devices by using a memory cell structure with controlled voltage applications to stabilize electrical resistance and reduce leakage current, thereby enhancing performance and durability.
Patent Information
- Application Number
- JP2023154017
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-20
- Publication Date
- 2025-04-02
AI Technical Summary
Existing cross-point two-terminal storage devices face challenges in maintaining the reliability of memory cells due to voltage stress during repeated write processes, leading to unstable electrical resistance and increased semi-selective leakage current.
The proposed storage device employs a memory cell structure with a first and second conductive layer and a memory layer capable of switching between low and high resistance states. A control circuit performs write processes by alternately applying specific voltages to change the state of the memory layer, thereby stabilizing the electrical resistance and reducing semi-selective leakage current.
This approach enhances the reliability of the storage device by stabilizing the electrical resistance of the memory layer and reducing semi-selective leakage current, thereby improving the overall performance and durability of the device.
Smart Images
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Abstract
Description
[Technical field]
[0001] An embodiment of the present invention relates to a storage device and a control method for the storage device. [Background technology]
[0002] Cross-point type two-terminal memory devices are large-capacity nonvolatile memory devices. Cross-point type two-terminal memory devices facilitate miniaturization and high integration of memory cells.
[0003] In a cross-point type two-terminal memory device, for example, there is a memory cell that has both a resistance change function and a switching function. By having the switching function, the current flowing to memory cells other than the selected memory cell is suppressed. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] US Patent Application Publication No. 2021 / 0366541 [Patent Document 2] US Patent Application Publication No. 2023 / 0051899 Summary of the Invention [Problem to be solved by the invention]
[0005] An object of the present invention is to provide a storage device having excellent characteristics. [Means for solving the problem]
[0006] A memory device according to an embodiment includes a memory cell including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer, the memory layer being capable of being in a first state and a second state having a higher electrical resistance than the first state, and a control circuit capable of executing a write process on the memory cell, wherein, when changing a state of the memory layer from the second state to the first state, the write process alternately applies a first voltage of positive polarity and a second voltage of negative polarity having an absolute value greater than that of the first voltage to the second conductive layer multiple times such that a voltage finally applied is the second voltage, and when changing a state of the memory layer from the first state to the second state, the write process alternately applies a third voltage of negative polarity and a fourth voltage of positive polarity having an absolute value greater than that of the third voltage to the second conductive layer multiple times such that a voltage finally applied is the fourth voltage. [Brief description of the drawings]
[0007] [Figure 1] FIG. 2 is a block diagram of a storage device according to the first embodiment. [Diagram 2] 2 is a schematic cross-sectional view of a memory cell of the memory device according to the first embodiment. [Diagram 3] FIG. 4 is a graph showing an example of current-voltage characteristics of the memory device according to the first embodiment. [Figure 4] FIG. 4 is an explanatory diagram of an example of a memory operation of the storage device of the first embodiment. [Diagram 5] FIG. 4 is an explanatory diagram of an example of a write process in the storage device of the first embodiment; [Figure 6] FIG. 4 is an explanatory diagram of a problem of the storage device of the first embodiment. [Figure 7] FIG. 11 is a graph showing an example of current-voltage characteristics of the memory device according to the second embodiment. [Figure 8] FIG. 11 is an explanatory diagram of an example of a memory operation of the storage device according to the second embodiment. [Figure 9] FIG. 11 is an explanatory diagram of an example of a write process in the storage device of the second embodiment; [Figure 10] FIG. 11 is an explanatory diagram of an example of a write process in the storage device of the second embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.
[0009] The qualitative and quantitative analysis of the chemical composition constituting the memory device in this specification can be performed by, for example, Rutherford Backscattering Spectroscopy (RBS), Secondary Ion Mass Spectroscopy (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS), etc. In addition, for example, a Transmission Electron Microscope (TEM) can be used to measure the thickness of the members constituting the memory device, the distance between the members, etc. In addition, to identify the constituent materials of the components that make up a memory device and measure their abundance ratios, bonding states, local structures (atomic distances, coordination numbers), and chemical states, it is possible to use, for example, X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure (XAFS), Raman spectroscopy (Raman), or EELS.
[0010] (First embodiment) A memory device of a first embodiment includes a memory cell including a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer and capable of taking a first state and a second state having a higher electrical resistance than the first state, and a control circuit capable of executing a write process on the memory cell, in which, when changing the state of the memory layer from the second state to the first state, the write process applies to the second conductive layer a first voltage of positive polarity and a second voltage of negative polarity whose absolute value is greater than that of the first voltage, alternately multiple times such that the last voltage applied is the second voltage, and, when changing the state of the memory layer from the first state to the second state, the write process applies to the second conductive layer a third voltage of negative polarity and a fourth voltage of positive polarity whose absolute value is greater than that of the third voltage, alternately multiple times such that the last voltage applied is the fourth voltage.
[0011] Moreover, a control method for a memory device of a first embodiment is a control method for a memory device having a memory cell including a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer and capable of taking a first state and a second state having a higher electrical resistance than the first state, in which a first voltage of positive polarity and a second voltage of negative polarity and having an absolute value greater than that of the first voltage are alternately applied multiple times to the second conductive layer such that the last voltage applied is the second voltage, thereby changing the state of the memory cell from the second state to the first state, and a third voltage of negative polarity and a fourth voltage of positive polarity and having an absolute value greater than that of the third voltage are alternately applied multiple times to the second conductive layer such that the last voltage applied is the fourth voltage, thereby changing the state of the memory cell from the first state to the second state.
[0012] FIG. 1 is a block diagram of a storage device according to the first embodiment.
[0013] The memory device of the first embodiment includes a memory cell array 100, a first control circuit 104, a second control circuit 105, and a sense circuit 106. The memory cell array 100 includes a semiconductor substrate 101, a plurality of word lines 102, and a plurality of bit lines 103.
[0014] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are examples of control circuits. The word line 102 is an example of a first wiring. The bit line 103 is an example of a second wiring.
[0015] The word lines 102 are provided, for example, on a semiconductor substrate 101. For example, an insulating layer is provided between the semiconductor substrate 101 and the word lines 102. The bit lines 103 are provided on the word lines 102. The bit lines 103 intersect with the word lines 102. The word lines 102 and the bit lines 103 extend, for example, in a direction parallel to the surface of the semiconductor substrate 101.
[0016] A plurality of memory cells MC are provided in an area where the word lines 102 and the bit lines 103 intersect. One memory cell MC is provided in an area where one word line 102 and one bit line 103 intersect. The storage device of the first embodiment is a two-terminal memory having a cross-point structure.
[0017] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are provided around the memory cell array 100, for example.
[0018] The word lines 102 are each connected to a first control circuit 104. The bit lines 103 are each connected to a second control circuit 105. The sense circuit 106 is connected to the first control circuit 104 and the second control circuit 105.
[0019] The first control circuit 104 and the second control circuit 105 can, for example, select a desired memory cell MC and execute a process of writing data to the memory cell MC and a process of reading data from the memory cell MC. When reading data, the data of the memory cell MC is read as the amount of current flowing between the word line 102 and the bit line 103 or as a potential change of the bit line 103. For example, the sense circuit 106 has a function of judging the amount of current flowing between the word line 102 and the bit line 103 to judge the polarity of the data. For example, it judges whether the data is "1" or "0".
[0020] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are configured, for example, as electronic circuits using semiconductor devices formed on the semiconductor substrate 101.
[0021] 2 is a schematic cross-sectional view of a memory cell in the memory device of the first embodiment. Fig. 2 shows a cross-section of one memory cell MC indicated by, for example, a dotted circle in the memory cell array 100 of Fig. 1.
[0022] 2, the memory cell MC includes a lower electrode 10, an upper electrode 20, and a memory layer 30. The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.
[0023] The bottom electrode 10 is connected to a word line 102. The bottom electrode 10 is, for example, a metal. The bottom electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The bottom electrode 10 may be a part of the word line 102.
[0024] The upper electrode 20 is connected to the bit line 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The upper electrode 20 may be a part of the bit line 103.
[0025] For example, the bottom electrode 10 comprises tungsten (W) and the top electrode 20 comprises carbon (C).
[0026] The memory layer 30 is provided between the lower electrode 10 and the upper electrode 20. The thickness of the memory layer 30 in a first direction from the lower electrode 10 to the upper electrode 20 is, for example, not less than 5 nm and not more than 50 nm.
[0027] The memory layer 30 has a characteristic that its electrical resistance changes when a predetermined voltage is applied. The memory layer 30 has a function of storing data by changing the resistance. The memory layer 30 can be in a low resistance state and a high resistance state in which the electrical resistance is higher than the low resistance state. The low resistance state is an example of a first state. The high resistance state is an example of a second state. The memory layer 30 has a resistance change function.
[0028] The memory layer 30 has a function of suppressing an increase in a half-selected leakage current flowing through a half-selected cell. The memory layer 30 has a nonlinear current-voltage characteristic in which the current rises steeply at a specific threshold voltage. The memory layer 30 has a switching function.
[0029] The memory layer 30 is, for example, a single layer. The memory layer 30 is, for example, a single layer, and has both a resistance change function and a switching function.
[0030] The memory layer 30 includes, for example, an oxide or oxynitride of a first element, which is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb), a compound of a second element, which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi), and a compound of a third element, which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se).
[0031] The memory layer 30 contains at least one oxide selected from the group consisting of, for example, zirconium oxide, aluminum oxide, yttrium oxide, tantalum oxide, lanthanum oxide, cerium oxide, titanium oxide, hafnium oxide, magnesium oxide, scandium oxide, vanadium oxide, and niobium oxide.
[0032] The memory layer 30 includes, for example, a chalcogenide of the second element. The memory layer 30 includes, for example, at least one chalcogenide selected from the group consisting of zinc telluride, tin telluride, gallium telluride, indium telluride, bismuth telluride, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, bismuth sulfide, zinc selenide, tin selenide, gallium selenide, indium selenide, and bismuth selenide.
[0033] The memory layer 30 includes, for example, zirconium oxide and zinc telluride.
[0034] The memory layer 30 includes, for example, an oxide or oxynitride of a first element, which is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb), and a second element, which is at least one element selected from the group consisting of antimony (Sb), carbon (C), boron (B), nitrogen (N), silicon (Si), and tin (Sn). Note that the memory layer 30 may further include zinc (Zn) in addition to the oxide or oxynitride of the first element, antimony (Sb), and the second element.
[0035] The memory layer 30 includes, for example, an oxide or oxynitride of a first element, which is at least one element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb), and a second element, which is at least one element selected from the group consisting of antimony (Sb), carbon (C), boron (B), nitrogen (N), silicon (Si), and tin (Sn). Note that the memory layer 30 may further include aluminum (Al) in addition to the oxide or oxynitride of the first element, antimony (Sb), and the second element.
[0036] Fig. 3 is an explanatory diagram of an example of the current-voltage characteristics of the memory device of the first embodiment. The horizontal axis is the voltage applied between the electrodes, and the vertical axis is the current flowing between the electrodes. In Fig. 3, the horizontal axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as a reference. Fig. 3 shows the current-voltage characteristics of the memory layer 30 of the first embodiment. Fig. 3 shows the current-voltage characteristics of the memory cell MC of the first embodiment.
[0037] The memory cell MC of the first embodiment exhibits different current-voltage characteristics when a predetermined negative voltage (Vn in FIG. 3) is applied to the upper electrode 20 and when a predetermined positive voltage (Vp in FIG. 3) is applied to the upper electrode 20. In FIG. 3, the current-voltage characteristics when a predetermined negative voltage Vn is applied to the upper electrode 20 are indicated by a dotted line, and the current-voltage characteristics when a predetermined positive voltage Vp is applied to the upper electrode 20 are indicated by a solid line.
[0038] When a predetermined negative voltage Vn is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first threshold voltage Vt1. When a predetermined negative voltage Vn is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the positive voltage side threshold voltage Vtp.
[0039] On the other hand, when a predetermined positive voltage Vp is applied to the upper electrode 20, the current rises sharply at the second threshold voltage Vt2 on the negative voltage side. The absolute value of the second threshold voltage Vt2 is greater than the absolute value of the first threshold voltage Vt1. When a predetermined positive voltage Vp is applied to the upper electrode 20, the current rises sharply at the positive voltage side threshold voltage Vtp on the positive voltage side, similar to when a predetermined negative voltage Vn is applied.
[0040] The absolute value of the predetermined negative voltage Vn is greater than the absolute value of the second threshold voltage Vt2.
[0041] The memory cell MC of the first embodiment can take a low resistance state and a high resistance state on the negative voltage side. The memory layer 30 of the first embodiment can take a low resistance state and a high resistance state on the negative voltage side. The low resistance state is an example of a first state. The high resistance state is an example of a second state.
[0042] The memory cells MC of the first embodiment are in a single resistance state on the positive voltage side. The memory layer 30 of the first embodiment is in a single resistance state on the positive voltage side.
[0043] The memory cell MC of the first embodiment has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage on both the negative voltage side and the positive voltage side, and has a current-voltage characteristic in which the threshold voltage changes when a predetermined voltage is applied on the negative voltage side.
[0044] Hereinafter, the low resistance state is defined as data “1” and the high resistance state as data “0.” The memory cell MC can take two values, “1” and “0,” making it possible to store 1-bit data.
[0045] Fig. 4 is an explanatory diagram of an example of memory operation of the storage device of the first embodiment. Fig. 4 shows a first write voltage Vw1, a second write voltage Vw2, a third write voltage Vw3, a fourth write voltage Vw4, a half voltage (Vw2 / 2) of the second write voltage Vw2, a half voltage (Vw4 / 2) of the fourth write voltage Vw4, and a read voltage Vr when performing memory operation.
[0046] The first write voltage Vw1 is an example of a first voltage. The second write voltage Vw2 is an example of a second voltage. The third write voltage Vw3 is an example of a third voltage. The fourth write voltage Vw4 is an example of a fourth voltage.
[0047] The first write voltage Vw1 is a positive voltage. The second write voltage Vw2 is a negative voltage. The absolute value of the second write voltage Vw2 is greater than the absolute value of the first write voltage Vw1. The absolute value of the second write voltage Vw2 is, for example, 1.1 times or more and 5 times or less than the absolute value of the first write voltage Vw1.
[0048] The absolute value of the current flowing through the memory layer 30 due to application of the second write voltage Vw2 is greater than the absolute value of the current flowing through the memory layer 30 due to application of the first write voltage Vw1. The absolute value of the current flowing through the memory layer 30 due to application of the second write voltage Vw2 is, for example, 1.1 to 5 times the absolute value of the current flowing through the memory layer 30 due to application of the first write voltage Vw1.
[0049] The third write voltage Vw3 is a negative voltage. The fourth write voltage Vw4 is a positive voltage. The absolute value of the fourth write voltage Vw4 is greater than the absolute value of the third write voltage Vw3. The absolute value of the fourth write voltage Vw4 is, for example, 1.1 times or more and 5 times or less than the absolute value of the third write voltage Vw3.
[0050] The absolute value of the current flowing through the memory layer 30 due to application of the fourth write voltage Vw4 is greater than the absolute value of the current flowing through the memory layer 30 due to application of the third write voltage Vw3. The absolute value of the current flowing through the memory layer 30 due to application of the fourth write voltage Vw4 is, for example, 1.1 to 5 times the absolute value of the current flowing through the memory layer 30 due to application of the third write voltage Vw3.
[0051] The absolute value of the third write voltage Vw3 is greater than the absolute value of the second threshold voltage Vt2. The absolute value of the second write voltage Vw2 is, for example, greater than the absolute value of the third write voltage Vw3.
[0052] The read voltage Vr is a negative voltage. The absolute value of the read voltage Vr is greater than the absolute value of the first threshold voltage Vt1 and less than the absolute value of the second threshold voltage Vt2. The absolute value of the read voltage Vr is less than the absolute value of the second write voltage Vw2.
[0053] First, a write process to the memory cell MC will be described. The write process is performed by using the first control circuit 104 and the second control circuit 105.
[0054] 5(a) and 5(b) are explanatory diagrams of an example of a write process in the memory device of the first embodiment. 5(a) and 5(b) show the change over time of the voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC during the write process. The voltage on the vertical axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as a reference.
[0055] The voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC is applied as, for example, a square wave or a triangular wave.
[0056] Fig. 5(a) shows a case where the state of the memory layer 30 is changed from a high resistance state to a low resistance state. That is, Fig. 5(a) shows a case where the data of the memory cell MC is changed from data "0" to data "1". In other words, Fig. 5(a) shows a case where data "1" is written to the memory cell MC.
[0057] When changing the state of the memory layer 30 from a high resistance state to a low resistance state, a first write voltage Vw1 of positive polarity and a second write voltage Vw2 of negative polarity and having an absolute value greater than the first write voltage Vw1 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the second write voltage Vw2.
[0058] 5(a) illustrates an example in which the first write voltage Vw1 and the second write voltage Vw2 are alternately applied four times, but the number of times the voltage is applied is not particularly limited as long as it is at least two. Also, while FIG. 5(a) illustrates an example in which the voltage applied first is the first write voltage Vw1, the voltage applied first may be the second write voltage Vw2.
[0059] Fig. 5(b) shows a case where the state of the memory layer 30 is changed from a low resistance state to a high resistance state. That is, Fig. 5(b) shows a case where the data of the memory cell MC is changed from data "1" to data "0". In other words, Fig. 5(b) shows a case where data "0" is written to the memory cell MC.
[0060] When changing the state of the memory layer 30 from a low resistance state to a high resistance state, a negative third write voltage Vw3 and a positive fourth write voltage Vw4 having an absolute value greater than that of the third write voltage Vw3 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fourth write voltage Vw4.
[0061] 5(b) illustrates an example in which the third write voltage Vw3 and the fourth write voltage Vw4 are alternately applied four times, but the number of times the voltage is applied is not particularly limited as long as it is at least two. Also, while FIG. 5(b) illustrates an example in which the voltage applied first is the third write voltage Vw3, the voltage applied first may be the fourth write voltage Vw4.
[0062] Next, a read process for the memory cell MC will be described. The read process is performed by using the first control circuit 104, the second control circuit 105, and the sense circuit .
[0063] In the read process, a read voltage Vr is applied to the upper electrode 20. The read voltage Vr is a negative voltage. The read voltage Vr is applied to the upper electrode 20, and for example, a current flowing between the lower electrode 10 and the upper electrode 20 is detected by the sense circuit 106. In addition, the read voltage Vr is applied to the upper electrode 20, and for example, a change in the potential of the upper electrode 20 is detected by the sense circuit 106. The change in the potential of the upper electrode 20 is detected as a change in the potential of the bit line 103, for example.
[0064] For example, when a current exceeding a predetermined threshold current flows between the lower electrode 10 and the upper electrode 20, the memory layer 30 is determined to be in a low resistance state, i.e., the data of the memory cell MC is determined to be data "1." Also, when a current exceeding a predetermined threshold current does not flow between the lower electrode 10 and the upper electrode 20, the memory layer 30 is determined to be in a high resistance state, i.e., the data of the memory cell MC is determined to be data "0."
[0065] Next, the operation and effects of the storage device and the control method for the storage device according to the first embodiment will be described.
[0066] In the memory device and the control method for the memory device of the first embodiment, when changing the state of the memory layer 30 from a high resistance state to a low resistance state, a first write voltage Vw1 of positive polarity and a second write voltage Vw2 of negative polarity whose absolute value is greater than that of the first write voltage Vw1 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the second write voltage Vw2.
[0067] For example, consider a case where only the second write voltage Vw2 of negative polarity is repeatedly applied to the upper electrode 20 without applying the first write voltage Vw1 of positive polarity. Even in this case, it is possible to change the state of the memory layer 30 from a high resistance state to a low resistance state. However, in this case, repeated write processes cause characteristic degradation of the memory layer 30 due to voltage stress. Specifically, for example, the electrical resistance of the memory layer 30 after the write process becomes unstable.
[0068] In the memory device and the control method of the memory device of the first embodiment, a first positive write voltage Vw1 and a second negative write voltage Vw2, the absolute value of which is greater than that of the first write voltage Vw1, are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the second write voltage Vw2, thereby suppressing deterioration of the characteristics of the memory layer 30 even if the write process is repeated. Specifically, for example, the electrical resistance of the memory layer 30 after the write process is stabilized. Therefore, the reliability of the memory device is improved.
[0069] In the memory device and the control method for the memory device of the first embodiment, when changing the state of the memory layer 30 from a low resistance state to a high resistance state, a third write voltage Vw3 of negative polarity and a fourth write voltage Vw4 of positive polarity whose absolute value is greater than that of the third write voltage Vw3 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fourth write voltage Vw4.
[0070] For example, consider a case where only the fourth write voltage Vw4 of positive polarity is repeatedly applied to the upper electrode 20 without applying the third write voltage Vw3 of negative polarity. Even in this case, it is possible to change the state of the memory layer 30 from a low resistance state to a high resistance state. However, in this case, repeated write processes cause characteristic degradation of the memory layer 30 due to voltage stress. Specifically, for example, the electrical resistance of the memory layer 30 after the write process becomes unstable.
[0071] In the memory device and the control method of the memory device of the first embodiment, a negative third write voltage Vw3 and a positive fourth write voltage Vw4 having an absolute value greater than that of the third write voltage Vw3 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fourth write voltage Vw4, thereby suppressing deterioration of the characteristics of the memory layer 30 even if the write process is repeated. Specifically, for example, the electrical resistance of the memory layer 30 after the write process is stabilized. Therefore, the reliability of the memory device is improved.
[0072] In the memory device and the control method for the memory device of the first embodiment, during a read process, a negative read voltage Vr is applied to the upper electrode 20. The absolute value of the read voltage Vr is greater than the absolute value of the first threshold voltage Vt1 and less than the absolute value of the second threshold voltage Vt2.
[0073] Since the read voltage Vr is a negative voltage, the data in the memory cell MC is not destroyed whether the data in the memory cell MC is data “0” or data “1.” Therefore, non-destructive readout of the memory cell MC can be realized.
[0074] Fig. 6 is an explanatory diagram of the problem of the memory device of the first embodiment. Fig. 6 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write process. Each memory cell MC is represented by an intersection of a word line and a bit line.
[0075] The selected memory cell MC is memory cell A (selected cell). A write voltage Vwrite is applied to the word line connected to memory cell A. In addition, 0 V is applied to the bit line connected to memory cell A.
[0076] In the following, an example will be described in which a voltage that is half the write voltage (Vwrite / 2) is applied to the word lines and bit lines that are not connected to memory cell A.
[0077] The voltage applied to memory cells C (unselected cells) connected to word lines and bit lines not connected to memory cells A is 0 V. In other words, no voltage is applied.
[0078] On the other hand, a voltage (Vwrite / 2) that is half the write voltage Vwrite is applied to memory cell B (half-selected cell) connected to the word line or bit line connected to memory cell A. Therefore, a half-selection leakage current flows through memory cell B (half-selected cell).
[0079] In addition, as an alternative to the above, a method may be adopted in which half the write voltage (Vwrite / 2) is applied to the word line connected to memory cell A, a negative voltage that is half the write voltage (-Vwrite / 2) is applied to the bit line, and 0V is applied to word lines and bit lines not connected to memory cell A.
[0080] If the half-selection leakage current is large, for example, it will lead to an increase in the power consumption of the chip. Also, for example, the voltage drop in the wiring will increase, and a sufficiently high voltage will not be applied to the selected cell, making the write process to the memory cell MC unstable. Therefore, a low half-selection leakage current is required for the current-voltage characteristics of the memory cell MC.
[0081] 3 and 4, the memory cell MC of the storage device of the first embodiment has a nonlinear current-voltage characteristic in which the current rises steeply at the first threshold voltage Vt1 or the second threshold voltage Vt2 on the negative voltage side. In other words, the memory layer 30 of the storage device of the first embodiment has a nonlinear current-voltage characteristic in which the current rises steeply at the first threshold voltage Vt1 or the second threshold voltage Vt2 on the negative voltage side.
[0082] 3 and 4, the memory cell MC of the storage device of the first embodiment has a nonlinear current-voltage characteristic in which the current rises steeply at the positive voltage side threshold voltage Vtp on the positive voltage side. In other words, in the memory layer 30 of the storage device of the first embodiment, the current rises steeply at the positive voltage side threshold voltage Vtp on the positive voltage side.
[0083] The memory cells MC of the storage device of the first embodiment have nonlinear current-voltage characteristics on both the negative voltage side and the positive voltage side, making it possible to realize a low semi-selected leakage current.
[0084] 4, from the viewpoint of suppressing the half-selection leakage current, the second write voltage Vw2 is set so that the absolute value of half the voltage (Vw2 / 2) of the second write voltage Vw2 is smaller than the absolute value of the first threshold voltage Vt1. Also, from the viewpoint of suppressing the half-selection leakage current, the fourth write voltage Vw4 is set so that the absolute value of half the voltage (Vw4 / 2) of the fourth write voltage Vw4 is smaller than the absolute value of the positive voltage side threshold voltage Vtp.
[0085] The memory layer 30 of the first embodiment can achieve, with a single layer, the function of storing data by resistance change and the function of suppressing a half-selection leakage current flowing through a half-selected cell.
[0086] As described above, according to the first embodiment, it is possible to realize a storage device and a control method for the storage device that have improved reliability.
[0087] Second embodiment The memory device of the second embodiment differs from the memory device of the first embodiment in that the memory cell can take a third state in which the electrical resistance is higher than that of the first state and lower than that of the second state, and a fourth state in which the electrical resistance is higher than that of the third state and lower than that of the second state, and in that the write process, when changing the state of the memory layer from the second state to the third state, applies a fifth voltage of positive polarity and a sixth voltage of negative polarity whose absolute value is greater than that of the fifth voltage to the second conductive layer multiple times in alternation such that the last applied voltage is the fifth voltage, and in that the write process, when changing the state of the memory layer from the first state to the fourth state, applies a seventh voltage of negative polarity and an eighth voltage of positive polarity whose absolute value is greater than that of the seventh voltage to the second conductive layer multiple times in alternation such that the last applied voltage is the seventh voltage. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.
[0088] Fig. 7 is an explanatory diagram of an example of the current-voltage characteristics of the memory device of the second embodiment. The horizontal axis is the voltage applied between the electrodes, and the vertical axis is the current flowing between the electrodes. In Fig. 7, the horizontal axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as a reference. Fig. 7 shows the current-voltage characteristics of the memory layer 30 of the second embodiment. Fig. 7 shows the current-voltage characteristics of the memory cell MC of the second embodiment.
[0089] 7, the memory cell MC of the second embodiment exhibits four different current-voltage characteristics by changing the conditions applied to the upper electrode 20.
[0090] In the first current-voltage characteristic, the current rises sharply at the first threshold voltage Vt1 on the negative voltage side, whereas in this case, the current rises sharply at the positive voltage side threshold voltage Vtp on the positive voltage side.
[0091] In the second current-voltage characteristic, the current rises sharply at the second threshold voltage Vt2 on the negative voltage side. The absolute value of the second threshold voltage Vt2 is greater than the absolute value of the first threshold voltage Vt1. In this case, the current rises sharply at the positive voltage side threshold voltage Vtp on the positive voltage side.
[0092] In the third current-voltage characteristic, the current rises sharply at a third threshold voltage Vt3 on the negative voltage side. The absolute value of the third threshold voltage Vt3 is greater than the absolute value of the first threshold voltage Vt1 and less than the absolute value of the second threshold voltage Vt2. In this case, the current rises sharply at a positive voltage side threshold voltage Vtp on the positive voltage side.
[0093] In the fourth current-voltage characteristic, the current rises sharply at a fourth threshold voltage Vt4 on the negative voltage side. The absolute value of the fourth threshold voltage Vt4 is greater than the absolute value of the third threshold voltage Vt3 and less than the absolute value of the second threshold voltage Vt2. In this case, the current rises sharply at a positive voltage side threshold voltage Vtp on the positive voltage side.
[0094] As in the first embodiment, when a predetermined negative voltage Vn is applied to the upper electrode 20, the current rises sharply at the first threshold voltage Vt1 on the negative voltage side. When a predetermined negative voltage Vn is applied to the upper electrode 20, the current rises sharply at the positive voltage side threshold voltage Vtp on the positive voltage side. This characteristic is the first current-voltage characteristic.
[0095] On the other hand, similar to the first embodiment, when a predetermined positive voltage Vp is applied to the upper electrode 20, the current rises sharply at the second threshold voltage Vt2 on the negative voltage side. The absolute value of the second threshold voltage Vt2 is greater than the absolute value of the first threshold voltage Vt1. When a predetermined positive voltage Vp is applied to the upper electrode 20, the current rises sharply at the positive voltage side threshold voltage Vtp on the positive voltage side, similar to the case where a predetermined negative voltage Vn is applied. This characteristic is the second current-voltage characteristic.
[0096] The absolute value of the predetermined negative voltage Vn is greater than the absolute value of the second threshold voltage Vt2.
[0097] The memory cell MC of the second embodiment can take a low resistance state, a first intermediate state, a second intermediate state, and a high resistance state on the negative voltage side. The memory layer 30 of the second embodiment can take a low resistance state, a first intermediate state, a second intermediate state, and a high resistance state on the negative voltage side. The first intermediate state is an example of a third state. The second intermediate state is an example of a fourth state.
[0098] The first intermediate state has a higher electrical resistance than the low resistance state and a lower electrical resistance than the high resistance state, and the second intermediate state has a higher electrical resistance than the first intermediate state and a lower electrical resistance than the high resistance state.
[0099] Hereinafter, the low resistance state is defined as data "11", the first intermediate state as data "10", the second intermediate state as data "01", and the high resistance state as data "00". The memory cell MC of the second embodiment can take four values, "11", "10", "01", and "00", and can therefore store two bits of data. The memory cell MC of the second embodiment can be multi-valued.
[0100] Fig. 8 is an explanatory diagram of an example of memory operation of the storage device of the second embodiment. Fig. 8 shows a first write voltage Vw1, a second write voltage Vw2, a third write voltage Vw3, a fourth write voltage Vw4, a fifth write voltage Vw5, a sixth write voltage Vw6, a seventh write voltage Vw7, an eighth write voltage Vw8, a half voltage (Vw2 / 2) of the second write voltage Vw2, a half voltage (Vw4 / 2) of the fourth write voltage Vw4, a half voltage (Vw6 / 2) of the sixth write voltage Vw6, a half voltage (Vw8 / 2) of the eighth write voltage Vw8, a first read voltage Vr1, a second read voltage Vr2, and a third read voltage Vr3 when performing memory operation.
[0101] The first write voltage Vw1 is an example of a first voltage. The second write voltage Vw2 is an example of a second voltage. The third write voltage Vw3 is an example of a third voltage. The fourth write voltage Vw4 is an example of a fourth voltage. The fifth write voltage Vw5 is an example of a fifth voltage. The sixth write voltage Vw6 is an example of a sixth voltage. The seventh write voltage Vw7 is an example of a seventh voltage. The eighth write voltage Vw8 is an example of an eighth voltage.
[0102] FIG. 8 illustrates an example in which the first write voltage Vw1 and the fifth write voltage Vw5 are the same voltage, the second write voltage Vw2 and the sixth write voltage Vw6 are the same voltage, the third write voltage Vw3 and the seventh write voltage Vw7 are the same voltage, and the fourth write voltage Vw4 and the eighth write voltage Vw8 are the same voltage, but each of these may be a different voltage.
[0103] The first write voltage Vw1 is a positive voltage. The second write voltage Vw2 is a negative voltage. The absolute value of the second write voltage Vw2 is greater than the absolute value of the first write voltage Vw1. The absolute value of the second write voltage Vw2 is, for example, 1.1 times or more and 5 times or less than the absolute value of the first write voltage Vw1.
[0104] The third write voltage Vw3 is a negative voltage. The fourth write voltage Vw4 is a positive voltage. The absolute value of the fourth write voltage Vw4 is greater than the absolute value of the third write voltage Vw3. The absolute value of the fourth write voltage Vw4 is, for example, 1.1 times or more and 5 times or less than the absolute value of the third write voltage Vw3.
[0105] The fifth write voltage Vw5 is a positive voltage. The sixth write voltage Vw6 is a negative voltage. The absolute value of the sixth write voltage Vw6 is greater than the absolute value of the fifth write voltage Vw5. The absolute value of the sixth write voltage Vw6 is, for example, 1.1 times or more and 5 times or less than the absolute value of the fifth write voltage Vw5.
[0106] The seventh write voltage Vw7 is a negative voltage. The eighth write voltage Vw8 is a positive voltage. The absolute value of the eighth write voltage Vw8 is greater than the absolute value of the seventh write voltage Vw7. The absolute value of the eighth write voltage Vw8 is, for example, 1.1 times or more and 5 times or less than the absolute value of the seventh write voltage Vw7.
[0107] The first read voltage Vr1 is a negative voltage. The absolute value of the first read voltage Vr1 is greater than the absolute value of the first threshold voltage Vt1 and less than the absolute value of the third threshold voltage Vt3. The absolute value of the first read voltage Vr1 is less than the absolute value of the second write voltage Vw2 and the absolute value of the sixth write voltage Vw6.
[0108] The second read voltage Vr2 is a negative voltage. The absolute value of the second read voltage Vr2 is greater than the absolute value of the third threshold voltage Vt3 and less than the absolute value of the fourth threshold voltage Vt4. The absolute value of the second read voltage Vr2 is less than the absolute value of the second write voltage Vw2 and the absolute value of the sixth write voltage Vw6.
[0109] The third read voltage Vr3 is a negative voltage. The absolute value of the third read voltage Vr3 is greater than the absolute value of the fourth threshold voltage Vt4 and less than the absolute value of the second threshold voltage Vt2. The absolute value of the third read voltage Vr3 is less than the absolute value of the second write voltage Vw2 and the absolute value of the sixth write voltage Vw6.
[0110] The absolute value of the third write voltage Vw3 is greater than the absolute value of the second threshold voltage Vt2. The absolute value of the second write voltage Vw2 is, for example, greater than the absolute value of the third write voltage Vw3.
[0111] The absolute value of the seventh write voltage Vw7 is greater than the absolute value of the second threshold voltage Vt2. The absolute value of the sixth write voltage Vw6 is, for example, greater than the absolute value of the seventh write voltage Vw7.
[0112] First, a description will be given of a write process to the memory cell MC of the second embodiment. The write process is performed using the first control circuit 104 and the second control circuit 105.
[0113] 9(a) and 9(b) are explanatory diagrams of an example of a write process in the memory device of the second embodiment. 9(a) and 9(b) show the change over time of the voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC during the write process. The voltage on the vertical axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as a reference.
[0114] The voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC is applied as, for example, a square wave or a triangular wave.
[0115] Fig. 9(a) shows a case where the state of the memory layer 30 is changed from a high resistance state to a low resistance state. That is, Fig. 9(a) shows a case where the data of the memory cell MC is changed from data "00" to data "11". In other words, Fig. 9(a) shows a case where data "11" is written to the memory cell MC.
[0116] When changing the state of the memory layer 30 from a high resistance state to a low resistance state, a first write voltage Vw1 of positive polarity and a second write voltage Vw2 of negative polarity whose absolute value is greater than that of the first write voltage Vw1 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the second write voltage Vw2.
[0117] 9(a) illustrates an example in which the first write voltage Vw1 and the second write voltage Vw2 are alternately applied four times, but the number of times the voltage is applied is not particularly limited as long as it is at least two. Also, while FIG. 9(a) illustrates an example in which the voltage applied first is the first write voltage Vw1, the voltage applied first may be the second write voltage Vw2.
[0118] Fig. 9(b) shows a case where the state of the memory layer 30 is changed from a low resistance state to a high resistance state. That is, Fig. 9(b) shows a case where the data of the memory cell MC is changed from data "11" to data "00". In other words, Fig. 9(b) shows a case where data "00" is written to the memory cell MC.
[0119] When changing the state of the memory layer 30 from a low resistance state to a high resistance state, a negative third write voltage Vw3 and a positive fourth write voltage Vw4 whose absolute value is greater than that of the third write voltage Vw3 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fourth write voltage Vw4.
[0120] 9(b) illustrates an example in which the third write voltage Vw3 and the fourth write voltage Vw4 are alternately applied four times, but the number of times the voltage is applied is not particularly limited as long as it is at least two. Also, while FIG. 9(b) illustrates an example in which the voltage applied first is the third write voltage Vw3, the voltage applied first may be the fourth write voltage Vw4.
[0121] 10(a) and 10(b) are explanatory diagrams of an example of a write process in the memory device of the second embodiment. Figures 10(a) and 10(b) show the change over time of the voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC during the write process. The voltage on the vertical axis shows the voltage applied to the upper electrode 20 with the potential of the lower electrode 10 as a reference.
[0122] The voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC is applied as, for example, a square wave or a triangular wave.
[0123] Fig. 10(a) shows a case where the state of the memory layer 30 is changed from a high resistance state to a first intermediate state. That is, Fig. 10(a) shows a case where the data of the memory cell MC is changed from data "00" to data "10". In other words, Fig. 10(a) shows a case where data "10" is written to the memory cell MC.
[0124] When changing the state of the memory layer 30 from the high resistance state to the first intermediate state, a fifth write voltage Vw5 of positive polarity and a sixth write voltage Vw6 of negative polarity whose absolute value is greater than that of the fifth write voltage Vw5 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fifth write voltage Vw5.
[0125] 10(a) illustrates an example in which the fifth write voltage Vw5 and the sixth write voltage Vw6 are alternately applied three times, but the number of times the voltage is applied is not particularly limited as long as it is at least two. Also, while FIG. 10(a) illustrates an example in which the first voltage applied is the fifth write voltage Vw5, the first voltage applied may be the sixth write voltage Vw6.
[0126] Fig. 10(b) shows a case where the state of the memory layer 30 is changed from the low resistance state to a second intermediate state. That is, Fig. 10(b) shows a case where the data of the memory cell MC is changed from data "11" to data "01". In other words, Fig. 10(b) shows a case where data "01" is written to the memory cell MC.
[0127] When changing the state of the memory layer 30 from the low resistance state to the second intermediate state, a negative seventh write voltage Vw7 and a positive eighth write voltage Vw8 whose absolute value is greater than that of the seventh write voltage Vw7 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the seventh write voltage Vw7.
[0128] 10(b) illustrates an example in which the seventh write voltage Vw7 and the eighth write voltage Vw8 are alternately applied three times, but the number of times the voltage is applied is not particularly limited as long as it is at least two. Also, while FIG. 10(b) illustrates an example in which the voltage applied first is the seventh write voltage Vw7, the voltage applied first may be the eighth write voltage Vw8.
[0129] Next, a read process for the memory cell MC will be described. The read process is performed by using the first control circuit 104, the second control circuit 105, and the sense circuit .
[0130] In the read process, a first read voltage Vr1, a second read voltage Vr2, or a third read voltage Vr3 is applied to the upper electrode 20. The first read voltage Vr1, the second read voltage Vr2, and the third read voltage Vr3 are negative voltages.
[0131] A first read voltage Vr1, a second read voltage Vr2, or a third read voltage Vr3 is applied to the upper electrode 20, and, for example, a current flowing between the lower electrode 10 and the upper electrode 20 is detected by the sense circuit 106. Also, a first read voltage Vr1, a second read voltage Vr2, or a third read voltage Vr3 is applied to the upper electrode 20, and, for example, a change in the potential of the upper electrode 20 is detected by the sense circuit 106. The change in the potential of the upper electrode 20 is detected as, for example, a change in the potential of the bit line 103.
[0132] For example, if a current exceeding a predetermined threshold current flows when the first read voltage Vr1 is applied, the memory layer 30 is determined to be in a low resistance state, that is, the data in the memory cell MC is determined to be data "11".
[0133] For example, if a current exceeding a predetermined threshold current does not flow when a first read voltage Vr1 is applied, and a current exceeding a predetermined threshold current flows when a second read voltage Vr2 is applied, the memory layer 30 is determined to be in a first intermediate state, i.e., the data in the memory cell MC is determined to be data “10”.
[0134] For example, if a current exceeding a predetermined threshold current does not flow when the second read voltage Vr2 is applied, and a current exceeding a predetermined threshold current flows when the third read voltage Vr3 is applied, the memory layer 30 is determined to be in the second intermediate state, i.e., the data in the memory cell MC is determined to be data “01”.
[0135] For example, if a current exceeding a predetermined threshold current does not flow when the third read voltage Vr3 is applied, the memory layer 30 is determined to be in a high resistance state, that is, the data in the memory cell MC is determined to be data "00".
[0136] Next, the operation and effects of the storage device and the control method for the storage device according to the second embodiment will be described.
[0137] In the memory device and the control method for the memory device according to the second embodiment, multi-level memory cells MC can be realized, and therefore, for example, a large capacity memory device can be easily realized.
[0138] In the memory device and the control method of the memory device of the second embodiment, similarly to the first embodiment, when changing the state of the memory layer 30 from a high resistance state to a low resistance state, a first write voltage Vw1 of positive polarity and a second write voltage Vw2 of negative polarity whose absolute value is greater than that of the first write voltage Vw1 are alternately applied multiple times to the upper electrode 20 so that the last voltage applied is the second write voltage Vw2. Therefore, similarly to the first embodiment, the reliability of the memory device is improved.
[0139] In the memory device and the control method of the memory device of the second embodiment, similarly to the first embodiment, when changing the state of the memory layer 30 from a low resistance state to a high resistance state, a negative third write voltage Vw3 and a positive fourth write voltage Vw4 having an absolute value greater than that of the third write voltage Vw3 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fourth write voltage Vw4. Therefore, similarly to the first embodiment, the reliability of the memory device is improved.
[0140] In the memory device and the control method for the memory device of the second embodiment, when changing the state of the memory layer 30 from a high resistance state to a first intermediate state, a fifth write voltage Vw5 of positive polarity and a sixth write voltage Vw6 of negative polarity whose absolute value is greater than that of the fifth write voltage Vw5 are applied alternately to the upper electrode 20 multiple times so that the last voltage applied is the fifth write voltage Vw5.
[0141] For example, consider a case where only a sixth write voltage Vw6 of negative polarity is repeatedly applied to the upper electrode 20, and finally a fifth write voltage Vw5 is applied. Even in this case, it is possible to change the state of the memory layer 30 from the high resistance state to the first intermediate state. However, in this case, repeated write processes cause characteristic degradation of the memory layer 30 due to voltage stress. Specifically, for example, the electrical resistance of the memory layer 30 after the write process becomes unstable.
[0142] In the memory device and the control method of the memory device of the second embodiment, a fifth write voltage Vw5 of positive polarity and a sixth write voltage Vw6 of negative polarity, the absolute value of which is greater than that of the fifth write voltage Vw5, are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the fifth write voltage Vw5, thereby suppressing deterioration of the characteristics of the memory layer 30 even if the write process is repeated. Specifically, for example, the electrical resistance of the memory layer 30 after the write process is stabilized. Therefore, the reliability of the memory device is improved.
[0143] In the memory device and the control method for the memory device of the second embodiment, when changing the state of the memory layer 30 from a low resistance state to a second intermediate state, a seventh write voltage Vw7 of negative polarity and an eighth write voltage Vw8 of positive polarity and having an absolute value greater than that of the seventh write voltage Vw7 are applied alternately to the upper electrode 20 multiple times so that the last voltage applied is the seventh write voltage Vw7.
[0144] For example, consider a case where only an eighth write voltage Vw8 of positive polarity is repeatedly applied to the upper electrode 20, and finally a seventh write voltage Vw7 is applied. Even in this case, it is possible to change the state of the memory layer 30 from the low resistance state to the second intermediate state. However, in this case, repeated write processes cause characteristic degradation of the memory layer 30 due to voltage stress. Specifically, for example, the electrical resistance of the memory layer 30 after the write process becomes unstable.
[0145] In the memory device and the control method of the memory device of the second embodiment, a seventh write voltage Vw7 of negative polarity and an eighth write voltage Vw8 of positive polarity and having an absolute value larger than that of the seventh write voltage Vw7 are alternately applied to the upper electrode 20 multiple times so that the last voltage applied is the seventh write voltage Vw7, thereby suppressing deterioration of the characteristics of the memory layer 30 even if the write process is repeated. Specifically, for example, the electrical resistance of the memory layer 30 after the write process is stabilized. Therefore, the reliability of the memory device is improved.
[0146] The memory cell MC of the memory device of the second embodiment, like the memory cell MC of the memory device of the second embodiment, has a nonlinear current-voltage characteristic on both the negative voltage side and the positive voltage side, making it possible to realize a low semi-select leakage current.
[0147] 8, from the viewpoint of suppressing the half-selection leak current, the second write voltage Vw2 and the sixth write voltage Vw6 are set so that the absolute value of the half voltage (Vw2 / 2) of the second write voltage Vw2 and the absolute value of the half voltage (Vw6 / 2) of the sixth write voltage Vw6 are smaller than the absolute value of the first threshold voltage Vt1. Also, from the viewpoint of suppressing the half-selection leak current, the fourth write voltage Vw4 and the eighth write voltage Vw8 are set so that the absolute value of the half voltage (Vw4 / 2) of the fourth write voltage Vw4 and the absolute value of the half voltage (Vw8 / 2) of the eighth write voltage Vw8 are smaller than the absolute value of the positive voltage side threshold voltage Vtp.
[0148] The memory layer 30 of the second embodiment achieves, with a single layer, the function of storing data by resistance change and the function of suppressing a half-selection leakage current flowing through a half-selected cell.
[0149] As described above, according to the second embodiment, it is possible to realize a storage device and a control method for the storage device that improve reliability. Also, according to the second embodiment, it is possible to realize a storage device and a control method for the storage device that can realize multi-level data.
[0150] In the first and second embodiments, a two-terminal memory device is described with an example structure in which the word lines 102 and the bit lines 103 extend in a direction parallel to the surface of the semiconductor substrate 101, but the present invention is not limited to the above structure. For example, the word lines 102 or the bit lines 103 may extend in a direction perpendicular to the surface of the semiconductor substrate 101.
[0151] In the first and second embodiments, the memory cells MC and memory layer 30 are described as being in a single resistance state on the positive voltage side, but the memory cells MC and memory layer 30 may be configured to be in a multiple resistance state on the positive voltage side, as on the negative voltage side.
[0152] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]
[0153] 10 Lower electrode (first conductive layer) 20 Upper electrode (second conductive layer) 30 Memory Layer 102 Word line (first wiring) 103 Bit line (second wiring) 104 First control circuit (control circuit) 105 Second control circuit (control circuit) 106 Sense circuit (control circuit) MC memory cell
Claims
1. A first conductive layer; and A second conductive layer; and a memory cell including a memory layer provided between the first conductive layer and the second conductive layer, the memory layer being capable of being in a first state and a second state having a higher electrical resistance than the first state; A control circuit capable of executing a write process for the memory cell; the write process, when changing the state of the memory layer from the second state to the first state, applies to the second conductive layer a first voltage of positive polarity and a second voltage of negative polarity whose absolute value is greater than that of the first voltage, alternately multiple times such that the last voltage applied is the second voltage; The write process, when changing the state of the memory layer from the first state to the second state, alternately applies a third voltage of negative polarity and a fourth voltage of positive polarity whose absolute value is greater than that of the third voltage to the second conductive layer multiple times so that the last voltage applied is the fourth voltage.
2. the absolute value of the second voltage is 1.1 times or more and 5 times or less than the absolute value of the first voltage, 2. The storage device according to claim 1, wherein the absolute value of said fourth voltage is 1.1 to 5 times the absolute value of said third voltage.
3. an absolute value of a current flowing through the memory layer due to application of the second voltage is 1.1 times or more and 5 times or less than an absolute value of a current flowing through the memory layer due to application of the first voltage; 2. The storage device according to claim 1, wherein an absolute value of a current flowing through said memory layer due to application of said fourth voltage is 1.1 to 5 times an absolute value of a current flowing through said memory layer due to application of said third voltage.
4. The control circuit is capable of executing a read process on the memory cell; 2. The memory device according to claim 1, wherein the read process applies a predetermined negative voltage to the second conductive layer and detects the current flowing between the first conductive layer and the second conductive layer or the potential of the second conductive layer.
5. 5. The memory device according to claim 4, wherein the absolute value of said predetermined negative voltage is smaller than the absolute value of said second voltage.
6. 2. The memory device according to claim 1, wherein the memory cell can be in a third state having a higher electrical resistance than the first state and a lower electrical resistance than the second state, and a fourth state having a higher electrical resistance than the third state and a lower electrical resistance than the second state.
7. the write process, when changing the state of the memory layer from the second state to the third state, applies to the second conductive layer a fifth voltage of positive polarity and a sixth voltage of negative polarity, the sixth voltage having an absolute value greater than that of the fifth voltage, alternately multiple times such that a last applied voltage is the fifth voltage; 7. The memory device of claim 6, wherein the write process, when changing the state of the memory layer from the first state to the fourth state, applies to the second conductive layer a seventh voltage of negative polarity and an eighth voltage of positive polarity whose absolute value is greater than that of the seventh voltage, alternately multiple times so that the last voltage applied is the seventh voltage.
8. The memory device according to claim 1 , wherein the memory layer is in contact with the first conductive layer and the second conductive layer.
9. The storage device according to claim 1 , wherein the memory layer is a single layer.
10. The memory layer comprises: an oxide or oxynitride of a first element, which is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb); a compound of a second element which is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), and bismuth (Bi) and a third element which is at least one element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se); The storage device of claim 1 , comprising:
11. The storage device of claim 1 , wherein the memory layer comprises zirconium oxide and zinc telluride.
12. The memory layer comprises: an oxide or oxynitride of a first element, which is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), scandium (Sc), vanadium (V), and niobium (Nb); Antimony (Sb), a second element which is at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), silicon (Si), and tin (Sn); The storage device of claim 1 , comprising:
13. 2. The memory device of claim 1, wherein said first conductive layer comprises tungsten (W) and said second conductive layer comprises carbon (C).
14. 2. The storage device according to claim 1, wherein said memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and said threshold voltage changes upon application of a predetermined voltage.
15. A plurality of first wirings; a plurality of second wirings intersecting the plurality of first wirings; 2. The memory device according to claim 1, wherein said memory cell is provided in a region where one of said plurality of first wirings and one of said plurality of second wirings intersect.
16. A first conductive layer; and A second conductive layer; and A method for controlling a storage device including a memory cell including a memory layer provided between the first conductive layer and the second conductive layer, the memory layer being capable of being in a first state and a second state having a higher electrical resistance than the first state, the method comprising the steps of: a first voltage of positive polarity and a second voltage of negative polarity, the absolute value of which is greater than that of the first voltage, are alternately applied to the second conductive layer a plurality of times such that a last applied voltage is the second voltage, thereby changing a state of the memory cell from the second state to the first state; A method for controlling a memory device, comprising: applying to the second conductive layer a third voltage of negative polarity and a fourth voltage of positive polarity whose absolute value is greater than that of the third voltage, alternately multiple times so that the last voltage applied is the fourth voltage, thereby changing the state of the memory cell from the first state to the second state.
17. 17. The method for controlling a storage device according to claim 16, further comprising the steps of: applying a predetermined negative voltage to the second conductive layer; and detecting a current flowing between the first conductive layer and the second conductive layer, or a potential of the second conductive layer.
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