Manufacturing method for semiconductor device and semiconductor device

Abstract

To provide a semiconductor device and a manufacturing method therefor that realize a reduction in the width of a termination region and a relaxation of an electric field in the termination region.SOLUTION: In a manufacturing method for a semiconductor device having a termination region in which a plurality of second semiconductor regions having a second conductivity type functioning as resurf regions are formed on the surface of a first semiconductor region having a first conductivity type around an active region, a mask for forming the second semiconductor region is used, in which, when a distance from the outermost reference window is defined as x, and the distance S(x) between an injection window at a position at the distance of x and an injection window on the side of one of the active regions is approximately equal to the value defined by S(x)=Smax-(Smax-Smin) (x / XN)β 0.3≤β≤0.5, to form the second semiconductor region by injecting impurities of the second conductivity type.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] In recent years, price competition has intensified in the field of power semiconductor devices, and cost reduction is required. To reduce costs, it is necessary to increase the diameter of wafers, lower the process temperature, and reduce the size of chips, which requires shallower junctions in the termination region, narrower width of the termination region, and relaxation of the electric field in the termination region.

[0003] Conventional techniques relating to the structure of the termination region are disclosed in, for example, Patent Document 1 and Patent Document 2.

[0004] Patent Document 1 describes a termination structure (32) provided on the outer periphery of a semiconductor element, which comprises an N-type drift region (1) formed in a semiconductor substrate (30) and a P-type impurity region (2) formed on an upper surface of the N-type drift region (1), and which describes that, when viewed macroscopically, the P-type impurity concentration of the P-type impurity region (2) decreases from the inner periphery to the outer periphery of the termination structure (32), and that, when viewed microscopically, the P-type impurity region (2) is composed of a plurality of P-type high concentration regions (2b) and low concentration regions (2a) surrounding them, with some portions of the low concentration regions (2a) spaced apart (summary, Figure 2).

[0005] Here, Patent Document 1 describes that the impurity concentration of the low concentration region (2a) is set to a value that satisfies the condition (RESURF condition) for the low concentration region (2a) to be completely depleted, and that the impurity concentration of the high concentration region (2b) is set to a value that determines whether or not the high concentration region (2b) will be depleted depending on the variations in the wafer process (paragraph 0020).

[0006] Patent Document 1 also describes that the aperture ratio of the implantation mask (20) used in the ion implantation to form such a P-type impurity region (2) is decreased toward the outside of the termination structure (32) (paragraph 0042), and describes that while functions for decreasing the aperture ratio include linear functions, functions with a high rate of decrease, such as exponential functions, are desirable, and that, for example, using a function that decreases according to an exponential function or polynomial that is convex downward when viewed macroscopically can alleviate local concentration of the electric field (paragraph 0043).

[0007] In Patent Document 2, a P resurf layer (3) (electric field relaxation layer) having a lower concentration than the P base layer (2) is formed so as to surround the P base layer (2), and the P resurf layer (3) is configured by alternately arranging high-concentration P resurf layers (7a, 8a, 9a, 10a) and low-concentration P resurf layers (8b, 9b, 10b, 11b), and the widths of each are expressed as w(7a)=w(8b)+w(8a)=w(9b)+w(9a)=w It is described that the width of the high concentration P resurf layers (7a, 8a, 9a, 10a) is gradually narrowed toward the outside, and the width of the low concentration P resurf layers (8b, 9b, 10b, 11b) is gradually widened toward the outside, while the sum of the widths of each pair of high concentration P resurf layers and low concentration P resurf layers is kept equal so that (10b) + w(10a) = w(11b) (paragraphs 0027 to 0039, Figures 3 to 4). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Publication No. 2014 / 054319 [Patent Document 2] International Publication No. 2013 / 136550 Summary of the Invention [Problem to be solved by the invention]

[0009] In Patent Document 1, a linear function, a downwardly convex exponential function (a x), a function that decreases according to a polynomial is described, and Patent Document 2 describes a structure in which the sum of the widths of each pair of high-concentration P resurf layers and low-concentration P resurf layers is kept equal, while the width of the high-concentration P resurf layers is gradually narrowed toward the outside and the width of the low-concentration P resurf layers is gradually widened toward the outside, in other words, a pseudo-linear decrease in concentration. However, as a result of simulations performed by the inventors of the present application, it was found that a different mask shape is desirable for reducing the width of the termination region and alleviating the electric field in the termination region.

[0010] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that are capable of reducing the width of a termination region and alleviating an electric field in the termination region. [Means for solving the problem]

[0011] In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention includes, for example, a method for manufacturing a semiconductor device having a termination region in which a plurality of second semiconductor regions having a second conductivity type are formed on a surface of a first semiconductor region having a first conductivity type around an active region, the second semiconductor regions being continuous with the active region and a depletion layer that spreads into the first semiconductor region when a voltage is applied, and at least one second semiconductor region including a second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions is completely depleted when a voltage is applied to the second semiconductor region, the termination region functioning as a resurf region, the method including: forming a mask for forming the second semiconductor regions; When an injection window corresponding to a second semiconductor region formed at a position farthest from an active region in the second semiconductor region where a depletion layer extending into one semiconductor region is continuous with the active region is taken as a reference window, the position of the reference window on the active region side is taken as X0, the distance between the active region side position of the injection window adjacent to the active region and X0 is taken as XN, the interval between the reference window and the injection window on that one active region side is taken as Smax, the interval between the edge of the active region and the injection window adjacent to the active region is taken as Smin, the distance from X0 is taken as x, and the power coefficient is taken as β, the interval S(x) between the injection window at a position of distance x and the injection window on that one active region side is given by S(x)=Smax-(Smax-Smin)·(x / XN) β 0.3≦β≦0.5 The second semiconductor region is formed by implanting the second conductive type impurity using a mask having a value substantially equal to that specified by

[0012] Moreover, the semiconductor device of the present invention is, for example, a semiconductor device having an active region and a termination region formed around the active region, wherein the termination region has a first semiconductor region having a first conductivity type, and a plurality of second semiconductor regions having a second conductivity type formed on the surface of the first semiconductor region, the depletion layer which spreads into the first semiconductor region when a voltage is applied is continuous with the active region, and when a voltage is applied, at least one second semiconductor region including a second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions becomes completely depleted and functions as a RESURF region, and the termination region has the second semiconductor region formed using the manufacturing method of the semiconductor device described above. Effect of the Invention

[0013] According to the present invention, it is possible to realize a semiconductor device and a manufacturing method thereof that are capable of reducing the width of the termination region and alleviating the electric field in the termination region. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view illustrating the shape of a mask according to the first embodiment. [Diagram 3] 4A and 4B are diagrams for explaining the distance between an implantation window of a mask in the first embodiment and an implantation window on one active region side, and the width of the implantation window. [Figure 4] FIG. 4 is a diagram for explaining a dose profile in the first embodiment. [Diagram 5] 13A and 13B are diagrams for explaining the effect of reducing the width of the termination region when β is changed. [Figure 6] FIG. 13 is a graph for explaining a change in breakdown voltage when β is changed. [Figure 7] FIG. 13 is a graph for explaining a change in the amount of breakdown voltage drop when β is changed. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device having a non-RESURF structure as a comparative example. [Figure 9]1A and 1B are diagrams for explaining the difference in electric field strength characteristics between a RESURF structure and a non-RESURF structure. [Figure 10] FIG. 11 is a diagram for explaining a dose profile in the second embodiment. [Figure 11] 13 is a diagram for explaining the distance between an implantation window of a mask in Example 3 and an implantation window on one active region side, and the width of the implantation window. FIG. [Figure 12] 13 is a diagram for explaining the distance between an implantation window of a mask in Example 4 and an implantation window on one active region side, and the width of the implantation window. FIG. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted. EXAMPLES

[0016] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

[0017] The semiconductor device 10 of the first embodiment has a termination region 12 in which a plurality of second semiconductor regions 2 having a second conductivity type (e.g., p type) are formed on the surface of a first semiconductor region 1 having a first conductivity type (e.g., n type) around an active region 11. Here, the first conductivity type is described as n type and the second conductivity type as p type, but the first conductivity type may be p type and the second conductivity type may be n type.

[0018] Although not shown, semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a diode are formed in the active region 11. The semiconductor substrate on which the semiconductor device 10 is formed may be made of, but is not limited to, Si or SiC.

[0019] A first semiconductor region 1 and a second semiconductor region 2 are also formed in the active region 11, and the second semiconductor region 2 in the active region 11 will be referred to herein as a second semiconductor region 2a.

[0020] The semiconductor device 10 also has a channel stopper 6 formed in the termination region 12 and having a first conductivity type with a higher concentration than the first semiconductor region 1, an oxide film 4 formed to cover the first semiconductor region 1, the second semiconductor region 2, and the channel stopper 6, and an electrode 5 formed in the active region 11. The electrode 5 is, for example, a gate electrode or an emitter electrode in the case of an IGBT, a gate electrode or a source electrode in the case of a MOSFET, and an anode electrode in the case of a diode. Note that FIG. 1 illustrates only the front side of the semiconductor device 10, and the back side is not illustrated. An electrode not illustrated, for example, a collector electrode in the case of an IGBT, a drain electrode in the case of a MOSFET, or a cathode electrode in the case of a diode, is provided on the back side of the semiconductor device 10.

[0021] In the semiconductor device 10 of the first embodiment, in a thermal equilibrium state, the depletion layer 3 spreading into the first semiconductor region 1 continues from the active region 11 to each second semiconductor region 2, and each second semiconductor region 2 becomes approximately an intrinsic region 7. One of the characteristics of the semiconductor device 10 of the first embodiment is that the depletion of each second semiconductor region 2 (shrinkage of the intrinsic region 7) caused by application of a voltage begins from the second semiconductor region 2 on the outer periphery side of the termination region 12 (the side farther from the active region 11).

[0022] Furthermore, in the semiconductor device 10 of Example 1, even when a voltage is applied, the depletion layer 3 extending into the first semiconductor region 1 up to the multiple second semiconductor regions 2 in the termination region 12 is continuous with the active region 11. Another feature of the semiconductor device 10 of Example 1 is that when a voltage is applied, at least one second semiconductor region 2 including a second semiconductor region 2 (2b described below) formed at a position farthest from the active region 11 among the multiple second semiconductor regions 2 is completely depleted and functions as a RESURF region 8.

[0023] The RESURF region 8 has a function of relaxing the electric field and increasing the breakdown voltage by RESURF (Reduced Surface Field). In the RESURF region 8, the second semiconductor region 2 is completely depleted and does not have the intrinsic region 7. If the impurity concentration of the second semiconductor region 2 is high, it will not be completely depleted and the intrinsic region 7 will remain, so the impurity concentration of the second semiconductor region 2 is set to a low value to the extent that the second semiconductor region 2 is completely depleted when a voltage is applied.

[0024] 1, it is desirable that the second semiconductor region 2 in the termination region 12 is overlapped with a plurality of second semiconductor regions 2 from the side closer to the active region 11 to the side farther from the active region 11. This allows the width of the termination region 12 to be reduced. However, this is not limited thereto, and the second semiconductor regions 2 in the termination region 12 may be overlapped with a plurality of second semiconductor regions 2 on the side closer to the active region 11, and the second semiconductor regions 2 may be separated from each other on the side farther from the active region 11. In either case, the second semiconductor region 2 in the termination region 12 is also continuous with the second semiconductor region 2a of the active region 11 on the side closer to the active region 11.

[0025] In a thermal equilibrium state, the depletion layer 3 extending into the first semiconductor region 1 is continuous with the active region 11, and the second semiconductor region 2 formed at a position furthest from the active region 11 is referred to as the outermost second semiconductor region 2b to which the depletion layer 3 is continuous.

[0026] Fig. 2 is a plan view for explaining the shape of the mask of Example 1. Fig. 3 is a view for explaining the interval between the implantation window of the mask of Example 1 and the implantation window on the next active region side, and the width of the implantation window. In order to make the figure easier to see, the number of implantation windows 22 in Fig. 2 is simplified to be less than the number of second semiconductor regions 2 in Fig. 1. The horizontal axis of Fig. 3 indicates the position POS, the vertical axis on the left side indicates the interval S (corresponding to the width of the shielding portion 21) between the implantation window 22 of the mask 20 and the implantation window 22 on the next active region 11 side, and the vertical axis on the right side indicates the width W of the implantation window 22.

[0027] 2, a second conductive type impurity is injected to form the second semiconductor region 2. The mask 20 has a shielding portion 21 that blocks the impurity and an injection window 22 that is an opening that allows the impurity to pass through. Note that the size of the second semiconductor region 2 is larger than the size of the injection window 22 due to diffusion of the injected impurity.

[0028] Here, among the injection windows 22, the injection window 22 corresponding to the second semiconductor region 2a of the active region 11 will be referred to as the active region injection window 22a, and the injection window 22 corresponding to the outermost second semiconductor region 2b to which the depletion layer 3 is continuous will be referred to as the reference window 22b.

[0029] The shape of the mask 20 in the first embodiment is such that, when the position of the reference window 22b on the active region 11 side is X0, the distance between the position of the injection window 22 adjacent to the active region 11 on the active region 11 side and X0 is XN, the distance between the reference window 22b and the injection window 22 on the one active region 11 side is Smax, the distance between the edge of the active region 11 and the injection window 22 adjacent to the active region 11 is Smin, the distance from X0 is x, and the power coefficient is β, the distance S(x) between the injection window 22 at the position of the distance x and the injection window 22 on the one active region 11 side is approximately equal to the value defined by the following formula (1). As described later, the range of β is preferably 0.3≦β≦0.5.

[0030] S(x)=Smax-(Smax-Smin)·(x / XN) β (1) This makes it possible to reduce the width of the termination region 12 and to alleviate the electric field in the termination region 12. The effect will be described in detail later.

[0031] Moreover, the shape of the mask 20 in Example 1 was such that the width W(x) of the implantation window 22 at the position of the distance x decreased with increasing distance from the active region 11.

[0032] This allows the width of the second semiconductor region 2 to be smaller than when the width W(x) of the implantation window 22 is constant regardless of the position of the distance x, and therefore the width of the termination region 12 can be reduced.

[0033] In the first embodiment, as shown in FIG. 3, the width W(x) of the injection window at the position of the distance x is made to decrease linearly with increasing distance from the active region 11.

[0034] Fig. 4 is a diagram for explaining the dose profile in Example 1. The horizontal axis of Fig. 4 indicates the position POS, and the vertical axis indicates the dose DO.

[0035] In order to form the RESURF region 8, it is necessary that the impurity concentration of the second semiconductor region 2 is set to a low value to the extent that the second semiconductor region 2 is completely depleted at least on the side farther from the active region 11 when a voltage is applied. To achieve this, the dose amount in the second semiconductor region 2 of the termination region 12 when implanting the second conductive type impurity using the mask 20 is set to 4×10 12 cm -2 That's it, 3 x 10 13 cm -2 It is desirable that the following:

[0036] Furthermore, in order to fully utilize the effect of alleviating the electric field by the RESURF region 8, it is desirable that when a voltage is applied up to the withstand voltage, at least the second semiconductor region 2 corresponding to the range of 0≦x≦XN / 2 is completely depleted and functions as the RESURF region 8. It is more desirable that at least the second semiconductor region 2 corresponding to the range of 0≦x≦XN×2 / 3 is completely depleted. However, it is not necessary to completely deplete the second semiconductor region 2 corresponding to x=XN.

[0037] In the first embodiment, when the second conductivity type impurity is implanted using the mask 20, the dose profile is set such that the dose in the second semiconductor region 2a of the active region 11 and the dose in the second semiconductor region 2 of the termination region 12 are approximately equal.

[0038] This makes it possible to form the second semiconductor region 2 by injecting the second conductivity type impurity using a single mask 20.

[0039] The dose amount may be smaller than the above-mentioned range, but since the second semiconductor region 2a of the active region 11 is used as a body region of a semiconductor element formed in the active region 11, the dose amount required for the second semiconductor region 2a of the active region 11 may be insufficient. Therefore, two masks 20 are required, but when the second conductivity type impurity is implanted using the masks 20, the dose amount in the second semiconductor region 2 of the termination region 12 may be smaller than the dose amount in the second semiconductor region 2a of the active region 11, as necessary.

[0040] Next, the effect of realizing a reduction in the width of the termination region 12 and a relaxation of the electric field in the termination region 12 due to the shape of the mask 20 of the first embodiment will be described in detail.

[0041] Fig. 5 is a diagram illustrating the effect of reducing the width of the termination region when β is changed. The horizontal axis of Fig. 5 indicates the position POS, and the vertical axis indicates the distance S (corresponding to the width of the shielding portion 21) between the implantation window 22 in the mask 20 and the implantation window 22 next to the active region 11.

[0042] It is assumed that the distance S(x) between an implantation window 22 at a position of a distance x from X0 and the implantation window 22 on one side of the active region 11 can be expressed by the following equation (2).

[0043] S(x)=Smax-(Smax-Smin)·(x / Lx(β)) β (2) When Lx(β)=XN, the result is the same as formula (1). Here, assuming that the number of implantation windows 22 is 19 and the distance between the position of the implantation window 22 adjacent to the active region 11 on the active region 11 side and X0 is Lx(β), the interval S(x) and Lx(0.3), Lx(0.4), Lx(0.5), Lx(1.0), and Lx(2.0) were calculated for β=0.3, 0.4, 0.5, 1.0, and 2.0, and are shown in FIG.

[0044] As a result, it is found that the smaller β is, the smaller Lx(β) is, that is, the width of termination region 12 can be made smaller.

[0045] Here, β=1.0 corresponds to the distance S(x) increasing linearly as it approaches the outer periphery of the termination region 12 (x approaches 0), and although not strictly the same, it roughly corresponds to the case in Patent Document 1 where the aperture ratio of the implantation mask (20) decreases according to a linear function toward the outside of the termination structure (32) or the case in Patent Document 2 where the concentration decreases pseudo-linearly toward the outside. Also, β=2.0 roughly corresponds to the case in Patent Document 1 where the aperture ratio of the implantation mask (20) decreases according to a polynomial toward the outside of the termination structure (32). However, in the case of β=1.0 or β=2.0, Lx(1.0) or Lx(2.0) becomes larger than Lx(0.3) to Lx(0.5), and it was found that this is not suitable for reducing the width of the termination region 12.

[0046] Although not shown in FIG. 5, an example of an exponential function is x (roughly equivalent to the case in Patent Document 1 where the aperture ratio of the implantation mask (20) decreases exponentially toward the outside of the termination structure (32)), but the results were roughly close to the case where β=2.0. Therefore, it was found that this case is also not suitable for reducing the width of the termination region 12.

[0047] 6 is a diagram illustrating the change in breakdown voltage when β is changed, in which the horizontal axis represents β and the vertical axis represents the breakdown voltage V.

[0048] In Figure 6, the interface charge density Qss is 0 cm -2 This is the result of calculating the withstand voltage V assuming a diode with a nominal withstand voltage of 750 V, and when β is smaller than 0.3, the slope of the decrease in withstand voltage V becomes steeper. When β≦0.3, the withstand voltage V is 850 V or higher, which is sufficiently higher than the nominal withstand voltage of 750 V.

[0049] Fig. 7 is a diagram for explaining the change in the amount of breakdown voltage drop when β is changed. The horizontal axis of Fig. 7 represents β, and the vertical axis represents the amount of breakdown voltage drop ΔV.

[0050] The breakdown voltage V shown in Figure 6 is the interface charge density Qss of 0 cm -2 Since it is assumed that β is 0.4, it corresponds to the initial breakdown voltage. However, during stress testing or in actual use, the interface charge density Qss changes, and as a result, the breakdown voltage V also changes. The change in the breakdown voltage V is the breakdown voltage drop ΔV shown in Figure 7, where the top of the vertical axis is 0V and the bottom of the vertical axis is a negative value. At β=0.4, the absolute value of the breakdown voltage drop ΔV (negative value) is the smallest (it is the peak in the graph in Figure 7), so it can be seen that the performance is the best. Also, in the range where β is smaller than 0.3 or larger than β, the slope of the breakdown voltage drop ΔV becomes steep, and it can be seen that the performance is likely to decrease. Therefore, it is desirable for 0.3≦β≦0.5.

[0051] FIG. 8 is a cross-sectional view of a semiconductor device having a non-RESURF structure, which is a comparative example.

[0052] In the case of the non-RESURF structure which is a comparative example, the impurity concentration of the second semiconductor region 2 of the termination region 12 is set high, and even when a voltage up to the withstand voltage is applied, the second semiconductor region 2 of the termination region 12 is not completely depleted, and the intrinsic region 7 remains. Therefore, the amount of the intrinsic region 7 which remains undepleted becomes dead space, and an area which is wasted in reducing the width of the termination region 12 exists.

[0053] 9 is a diagram for explaining the difference in electric field strength characteristics between the RESURF structure and the non-RESURF structure, in which the horizontal axis represents the position POS and the vertical axis represents the electric field strength E.

[0054] The dotted line graph labeled "Non RESURF" in Figure 9 shows the characteristics of the electric field strength E of the non-RESURF structure, which is a comparative example, and it can be seen that the electric field strength E changes significantly between the valley portion corresponding to the shielding portion 21 and the mountain portion corresponding to the injection window 22.

[0055] 9 shows the characteristics of the electric field strength E of the RESURF structure of this embodiment, and it can be seen that the change in the electric field strength E is small, so that the electric field concentration is suppressed and the electric field is relaxed. This makes it possible to ensure the breakdown voltage.

[0056] As described above, according to the first embodiment, a RESURF structure is adopted in the termination region 12, and the mask 20 is shaped so that the distance S(x) between the injection window 22 at the position of the distance x and the injection window 22 on the one active region 11 side is approximately equal to the value defined by equation (1) and 0.3≦β≦0.5, thereby making it possible to reduce the width of the termination region 12 and relax the electric field in the termination region 12. EXAMPLES

[0057] Fig. 10 is a diagram for explaining a dose profile in Example 2. Fig. 10 is a diagram corresponding to Fig. 4 in Example 1.

[0058] The dose profile of Example 2 is different from that of Example 1. As shown in FIG. 10, the dose profile of Example 2 is such that the dose of the second semiconductor region 2 in the termination region 12a closer to the active region 11 in the termination region 12 is greater than the dose of the second semiconductor region 2 in the termination region 12b farther from the active region 11. This has the effect of suppressing a decrease in breakdown voltage due to positive interface charges. However, in Example 2, in order to change the dose depending on the region, it is necessary to inject the second conductivity type impurity using two masks 20, which also differs from Example 1.

[0059] Other than the above, the present embodiment is the same as the first embodiment, and therefore a duplicated description will be omitted. EXAMPLES

[0060] Fig. 11 is a diagram for explaining the interval between the implantation window of the mask and the implantation window on the side of one active region, and the width of the implantation window in the third embodiment. Fig. 11 is a diagram corresponding to Fig. 3 in the first embodiment.

[0061] In Example 3, the width W(x) of the implantation window 22 at the position of the distance x is different from that in Example 1. The shape of the mask 20 in Example 3 is such that the width W(x) of the implantation window 22 at the position of the distance x decreases linearly with increasing distance from the active region 11, and the slope of the decrease on the side closer to the active region 11 (x>XN') is greater than the slope of the decrease on the side farther from the active region 11 (x≦XN'). In FIG. 11, Wmax' is the value of the width W(x) of the implantation window 22 at the position of the distance x XN'.

[0062] Next, the reason for changing the slope of the decrease in the width W(x) of the injection window 22 will be explained. The width of the second semiconductor region 2 expands and the peak concentration also decreases due to the heat treatment after the injection of the second conductive type impurity. The amount of decrease in the peak concentration is greater as the width W(x) of the injection window 22 is narrower, and is smaller as the width W(x) of the injection window 22 is wider. On the other hand, the width of the injection window 22 of the second semiconductor region 2a of the active region 11 is orders of magnitude wider than the width W(x) of the injection window of the termination region 12, so the decrease in the peak concentration of the second semiconductor region 2a of the active region 11 is smaller than that of the second semiconductor region 2 in the termination region 12. Therefore, the peak concentration is different between the active region 11 and the second semiconductor region 2 adjacent thereto. Here, if there is a large concentration difference, there is a concern that electric field concentration will occur at the edge of the active region 11, leading to a decrease in the breakdown voltage. Therefore, in the vicinity of the active region 11, it is preferable that the width W(x) of the injection window 22 is wider. On the other hand, if the width W(x) of the injection window 22 is wide, the overall width of the termination region 12 will become large, so it is better to make it as narrow as possible. Since the vicinity of the active region 11 is sufficient as a countermeasure against the electric field concentration at the end of the active region 11, by making the slope of the decrease on the side closer to the active region 11 (x>XN') greater than the slope of the decrease on the side farther from the active region 11 (x≦XN'), as shown in Figure 11, it is possible to narrow the overall width of the termination region 12 compared to the case of Figure 3 while taking measures against the electric field concentration at the end of the active region 11. This is the reason for changing the slope of the decrease in the width W(x) of the injection window 22.

[0063] This also has the effect of suppressing a decrease in breakdown voltage due to positive interface charges, as in the case of the second embodiment, even when a single mask 20 is used to inject impurities of the second conductivity type with the same dose profile as that shown in FIG. 4 of the first embodiment to form the second semiconductor region 2.

[0064] Other than the above, the present embodiment is the same as the first embodiment, and therefore a duplicated description will be omitted. EXAMPLES

[0065] Fig. 12 is a diagram for explaining the interval between the implantation window of the mask and the implantation window on the next active region side, and the width of the implantation window in the fourth embodiment Fig. 12 is a diagram corresponding to Fig. 3 in the first embodiment.

[0066] In Example 4, the width W(x) of the injection window 22 at the position of the distance x is different from Examples 1 and 3. The shape of the mask 20 in Example 4 is such that, when the width of the injection window 22 at the position of the distance XN is Wmax and the width of the injection window 22 of the reference window 22b is Wmin, the width W(x) of the injection window 22 at the position of the distance x is approximately equal to the value defined by the following formula (3).

[0067] W(x)=Wmax-(Wmax-Wmin)·(1-x / XN) β (3) In the fourth embodiment, the width W(x) of the injection window 22 can be changed smoothly instead of linearly, and a decrease in the breakdown voltage due to a positive interface charge can be suppressed.

[0068] Other than the above, the present embodiment is the same as the first and third embodiments, and therefore a duplicated description will be omitted. EXAMPLES

[0069] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment.

[0070] The fifth embodiment is an embodiment in which the semiconductor device 10 has, in a part of the second semiconductor region 2a in the active region 11, a high-concentration second semiconductor region 2c having a higher concentration of second conductivity type impurities than the surrounding area.

[0071] The high-concentration second semiconductor region 2c is provided, for example, in a part of the surface of the second semiconductor region 2a of the active region 11. This can further suppress the spread of the depletion layer 3 toward the surface side in the active region 11. In addition, the high-concentration second semiconductor region 2c is provided, for example, at a position in contact with the electrode 5. This can further reduce the contact resistance between the electrode 5 and the second semiconductor region 2a of the active region 11, which functions as a body region, for example.

[0072] The impurity concentration of the second conductivity type of the high-concentration second semiconductor region 2c is 1×10 14 cm -3 It is preferable that the second conductivity type impurity concentration of the high concentration second semiconductor region 2c is about 2×10 or higher. In other words, it is preferable that the second conductivity type impurity concentration of the high concentration second semiconductor region 2c is higher by one order of magnitude or more than the second conductivity type impurity concentration of the second semiconductor region 2a of the active region 11 around the high concentration second semiconductor region 2c and the second semiconductor region 2 of the termination region 12. In this embodiment, the second conductivity type impurity concentration of the high concentration second semiconductor region 2c is set to about 2×10 14 cm -3 It was decided.

[0073] Other than the above, the present embodiment is the same as the first to fourth embodiments, and therefore a duplicated description will be omitted. EXAMPLES

[0074] FIG. 14 is a cross-sectional view of a semiconductor device according to a sixth embodiment.

[0075] The sixth embodiment is an embodiment in which a channel stopper electrode 9 is provided.

[0076] The semiconductor device 10 of this embodiment has a channel stopper electrode 9 formed on the oxide film 4 and connected to the channel stopper 6 via an opening provided in the oxide film 4. The end of the channel stopper electrode 9 closer to the active region 11 is located closer to the active region 11 than the end of the channel stopper 6 closer to the active region 11. In other words, the channel stopper electrode 9 has a shape that protrudes further toward the active region 11 than the channel stopper 6.

[0077] In order to reduce the width of the termination region 12, it is necessary not only to reduce the overall dimensions of the second semiconductor region 2 in the termination region 12, but also to reduce the interval DCSP between the outermost second semiconductor region 2b where the depletion layer 3 is continuous and the channel stopper 6. The equipotential lines also spread in the region between the outermost second semiconductor region 2b where the depletion layer 3 is continuous and the channel stopper 6. When the interval DCSP is wide, the equipotential lines do not spread to the channel stopper 6, whereas when the interval DCSP is narrow, multiple equipotential lines reach the channel stopper 6. Since the channel stopper 6 has a high concentration, the equipotential lines do not spread inside the channel stopper 6. As a result, many equipotential lines are concentrated at the end of the channel stopper 6 close to the active region 11, and the electric field strength becomes extremely high locally. Therefore, there is a lower limit to the interval DCSP.

[0078] Therefore, in this embodiment, a channel stopper electrode 9 is provided, and the end of the channel stopper electrode 9 close to the active region 11 is located closer to the active region 11 than the end of the channel stopper 6 close to the active region 11. This causes a field plate effect of the channel stopper electrode 9. The equipotential lines that were concentrated at the end of the channel stopper 6 close to the active region 11 move to the end of the channel stopper electrode 9 close to the active region 11 by a certain percentage, so that the increase in local electric field strength that occurs at the end of the channel stopper 6 close to the active region 11 is reduced. This reduction effect is determined by the interval LFP between the end of the channel stopper electrode 9 close to the active region 11 and the end of the channel stopper 6 close to the active region 11. If the interval LFP is increased, a significant reduction effect can be obtained, but on the other hand, the electric field strength in the oxide film 4 below the end of the channel stopper electrode 9 close to the active region 11 increases. The appropriate value of the interval LFP depends on the breakdown voltage and the concentration of the low-concentration first semiconductor region 1, but it may be set to several μm to several tens of μm. In this embodiment, the interval LFP is set to 20 μm. As a result, the interval DCSP can be reduced by 10% or more compared to the case where the field plate effect of the channel stopper electrode 9 is not used.

[0079] Other than the above, the present embodiment is the same as the first to fourth embodiments, and therefore a duplicated description will be omitted.

[0080] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0081] 1. First semiconductor region 2. Second semiconductor region 2a: second semiconductor region of the active area 2b The outermost second semiconductor region where the depletion layer is continuous 2c High concentration second semiconductor region 3. Depletion Layer 4. Oxide film 5 electrodes 6 Channel Stopper 7 Intrinsic domain 8. Resurf Region 9 Channel stopper electrode 10 Semiconductor device 11 Active Area 12, 12a, 12b Termination Area 20 Mask 21 Shield part 22 Injection window 22a Active area injection window 22b Reference window S: Distance between the injection window and the injection window on the next active area side W Width of injection window x distance β Power coefficient DO dose POS location V Withstand voltage ΔV Voltage drop Qss interfacial charge density E Electric field strength

Claims

1. A method for manufacturing a semiconductor device having a termination region, the method comprising the steps of: forming a plurality of second semiconductor regions having a second conductivity type on a surface of a first semiconductor region having a first conductivity type around an active region; the second semiconductor regions having a second conductivity type and a depletion layer extending into the first semiconductor region when a voltage is applied thereto, the depletion layer being continuous with the active region; and at least one second semiconductor region including a second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions being completely depleted when a voltage is applied, the termination region functioning as a resurf region, the method comprising the steps of: A mask for forming the second semiconductor region, wherein an injection window corresponding to a second semiconductor region formed at a position farthest from an active region in the second semiconductor region where a depletion layer spreading into the first semiconductor region in a thermal equilibrium state is continuous with the active region is defined as a reference window, a position of the reference window on the active region side is defined as X0, a distance between a position of the injection window adjacent to the active region on the active region side and X0 is defined as XN, a spacing between the reference window and the injection window on one active region side is defined as Smax, a spacing between an end of the active region and the injection window adjacent to the active region is defined as Smin, a distance from X0 is defined as x, and a power coefficient is defined as β, the spacing S(x) between the injection window at a position of distance x and the injection window on one active region side is H.E.R. β ０．３≦β≦０．５ a mask having a value substantially equal to that specified by the formula (1) above, wherein the second semiconductor region is formed by implanting an impurity of the second conductivity type.

2. In claim 1, 4. The method for manufacturing a semiconductor device, wherein the mask has an implantation window width W(x) at the distance x that decreases with increasing distance from the active region.

3. In claim 2, The method for manufacturing a semiconductor device, wherein the mask has an implantation window width W(x) at the distance x that decreases linearly with increasing distance from the active region.

4. In claim 2, The method for manufacturing a semiconductor device, wherein the mask has an implantation window width W(x) at the distance x that linearly decreases with increasing distance from the active region, and the slope of the decrease on the side closer to the active region is greater than the slope of the decrease on the side farther from the active region.

5. In claim 2, In the mask, when the width of the injection window at the position of the distance XN is Wmax and the width of the injection window of the reference window is Wmin, the width of the injection window at the position of the distance x, W(x), is expressed as follows: W(x)=Wmax-(Wmax-Wmin)・(1-x / XN) β 4. A method for manufacturing a semiconductor device, comprising the steps of:

6. In claim 1, 2. A method for manufacturing a semiconductor device, comprising the steps of: injecting the second conductivity type impurity using the mask; and implanting a dose amount in the second semiconductor region of the active region and a dose amount in the second semiconductor region of the termination region that are approximately equal to each other.

7. In claim 1, A method for manufacturing a semiconductor device, characterized in that when implanting the second conductivity type impurity using the mask, the dose amount in the second semiconductor region of the termination region is smaller than the dose amount in the second semiconductor region of the active region.

8. In claim 1, A method for manufacturing a semiconductor device, characterized in that, when injecting the second conductivity type impurity using the mask, a dose of the second semiconductor region in the termination region on a side closer to the active region is greater than a dose of the second semiconductor region on a side farther from the active region.

9. In claim 1, The dose amount of the second conductive type impurity implanted into the second semiconductor region of the termination region using the mask is 4×10 １２ cm －２ That's it, 3 x 10 １３ cm －２ 1. A method for manufacturing a semiconductor device, comprising:

10. In claim 1, A method for manufacturing a semiconductor device, characterized in that when a voltage up to a breakdown voltage is applied, the second semiconductor region, which corresponds to at least a range of 0≦x≦XN / 2, is completely depleted and functions as the RESURF region.

11. A semiconductor device having an active area and a termination area formed around the active area, the termination region includes a first semiconductor region having a first conductivity type, and a plurality of second semiconductor regions having a second conductivity type formed on a surface of the first semiconductor region, the depletion layer extending into the first semiconductor region when a voltage is applied being continuous with the active region; when a voltage is applied, at least one of the second semiconductor regions including a second semiconductor region formed at a position farthest from the active region among the plurality of second semiconductor regions is completely depleted and functions as a resurf region; 11. A semiconductor device comprising the second semiconductor region formed by the method for manufacturing a semiconductor device according to claim 1 in the termination region.

12. In claim 11, A semiconductor device characterized in that, in a thermal equilibrium state, in a region of the second semiconductor region from a second semiconductor region formed by an injection window adjacent to the active region to a second semiconductor region formed by the reference window, the depletion layer spreading into the first semiconductor region is continuous from the active region, and each second semiconductor region is an approximately intrinsic region, and depletion of each of the second semiconductor regions due to the application of a voltage begins in the second semiconductor region formed by the reference window.

13. In claim 11, A semiconductor device comprising: a first semiconductor region formed by an implantation window adjacent to said active region; and a second semiconductor region formed by said reference window, said second semiconductor region overlapping said implantation window.

14. In claim 11, A semiconductor device characterized in that, in the second semiconductor region, a region from a second semiconductor region formed by an injection window adjacent to the active region to a second semiconductor region formed by the reference window, a plurality of the second semiconductor regions overlap on a side closer to the active region, and the second semiconductor regions are separated from each other on a side farther from the active region.

15. In claim 11, A semiconductor device comprising: a high-concentration second semiconductor region in a portion of the second semiconductor region in the active region, the high-concentration second semiconductor region having a higher concentration of impurities of the second conductivity type than a surrounding area.

16. In claim 11, a channel stopper formed in the termination region and having a first conductivity type and a higher concentration than the first semiconductor region; an oxide film formed to cover the first semiconductor region, the second semiconductor region, and the channel stopper; a channel stopper electrode formed on the oxide film and connected to the channel stopper through an opening in the oxide film; a channel stopper electrode having an end portion closer to the active region than an end portion of the channel stopper having an end portion closer to the active region;

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