Semiconductor device

Abstract

To provide a semiconductor device including a plurality of memory cells arranged in a matrix, in which a data reading speed is improved.SOLUTION: A semiconductor device includes: a plurality of first memory cells arranged in a matrix, a plurality of second memory cells arranged in at least a row, a plurality of bit line pairs provided in each column of the first memory cells and the second memory cells; and a row decoder for selecting the first memory cells and the second memory cells to be validated at the time of data reading for each row. The two second memory cells connected to the bit line pair for each row are both in an erased state or a programmed state at least at the time of reading data, and the row decoder validates the second memory cell and validates the first memory cell for each row at the time of reading data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of memory cells arranged in a matrix, in which the data writing speed is improved. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-102106 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a semiconductor device including a plurality of memory cells arranged in a matrix, which has an improved data read speed. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a plurality of first memory cells arranged in a matrix, a plurality of second memory cells arranged at least in a row, a plurality of word lines provided in each row of the first memory cells and the second memory cells, a plurality of bit line pairs provided in each column of the first memory cells and the second memory cells, a precharge circuit that applies a precharge potential to the bit line pairs when reading data, a row decoder that selects, for each row, the first memory cells and the second memory cells to be enabled when reading data, and a bit line that is the first to have a potential that is lowered when reading data. and a read amplifier which determines the value of the data based on the bit line which falls below the threshold, wherein data is written by setting one of the two first memory cells connected to the bit line pair for each row in an erased state and the other first memory cell in a programmed state, and the two second memory cells connected to the bit line pair for each row are both set to an erased state or a programmed state at least when data is read, and the row decoder enables the second memory cell and enables the first memory cell for each row when data is read. Effect of the Invention

[0006] According to the semiconductor device of the present disclosure, in a semiconductor device including a plurality of memory cells arranged in a matrix, it is possible to improve the data read speed. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present disclosure; [Diagram 2] 2 is a diagram showing a schematic configuration of a read amplifier of the semiconductor device. [Diagram 3] 4 is a timing chart showing operation timings when reading data in the semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Next, an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a diagram showing a schematic configuration of a semiconductor device 1 according to an embodiment of the present disclosure.

[0009] As shown in FIG. 1, the semiconductor device 1 of this embodiment includes a plurality of memory cells 10 arranged in a matrix, a plurality of dummy memory cells 20 arranged in a row, a plurality of word lines 30 provided in each row of the memory cells 10 and the dummy memory cells 20, a plurality of source lines 40 provided in each row of the memory cells 10 and the dummy memory cells 20, a plurality of bit line pairs 50 provided in each column of the memory cells 10 and the dummy memory cells 20, a precharge circuit 60, a row decoder 70, and a read amplifier 80.

[0010] The memory cell 10 and the dummy memory cell 20 are configured by a flash memory. The memory cell 10 is an example of a first memory cell in the technology of the present disclosure. The dummy memory cell 20 is an example of a second memory cell in the technology of the present disclosure.

[0011] The word line 30 is connected to the gate of the memory cell 10. The source line 40 is connected to the source of the memory cell 10. Two bit lines 51 and 52 constituting a bit line pair 50 are connected to the drain of the memory cell 10, respectively.

[0012] The precharge circuit 60 applies a precharge potential to the bit line pair 50 when reading data.

[0013] The row decoder 70 selects, for each row, the memory cells 10 and the dummy memory cells 20 to be enabled when reading data.

[0014] When reading data, the read amplifier 80 determines the value of the data held by the two memory cells 10 connected to the bit line pair 50 based on the bit line, of the two bit lines BL and BLN constituting the bit line pair 50, whose potential falls below the threshold first.

[0015] Here, a detailed description will be given of the operation of the read amplifier 80. Fig. 2 is a diagram showing a schematic configuration of the read amplifier 80. Note that Fig. 2 shows only the main parts of the read amplifier 80, and omits other parts.

[0016] As shown in FIG. 2, the read amplifier 80 includes a P-channel transistor 81 for drive control, P-channel transistors 82 and 83 for signal detection, and N-channel transistors 84 and 85 for signal detection.

[0017] 2, of the two bit lines 51 and 52 constituting the bit line pair 50, the bit line 51 is written as BL and the bit line 52 is written as BLN. A signal line for controlling the read amplifier 80 is written as SEN. An output signal line of the read amplifier 80, i.e., a signal line for outputting the data values ​​held by the two memory cells 10 connected to BL and BLN, is written as Dout.

[0018] In the semiconductor device 1, of the two memory cells 10 connected to the bit line pair 50 for each row, one memory cell 10 is set to an erased state and the other memory cell 10 is set to a programmed state, thereby performing data writing so that the two memory cells 10 hold data of 1 or 0.

[0019] The erased state is a state in which a current easily flows between the source and drain of the memory cell 10 when the memory cell 10 is enabled during data reading. The programmed state is a state in which a current does not easily flow between the source and drain of the memory cell 10 when the memory cell 10 is enabled during data reading.

[0020] When SEN connected to the gate of the P-channel transistor 81 is set to L level and the read amplifier 80 is performing a read operation, if the memory cell 10 connected to BL is in the erased state and the potential of BL falls below the threshold first, the read amplifier 80 outputs an L level (0 data) signal from Dout.

[0021] In addition, when SEN connected to the gate of the P-channel transistor 81 is set to L level and the read amplifier 80 is performing a read operation, if the memory cell 10 connected to BLN is in the erased state and the potential of BLN falls below the threshold first, the read amplifier 80 outputs a H level (1 data) signal from Dout.

[0022] Next, the operation of the semiconductor device 1 of this embodiment when reading data will be described below. Fig. 3 is a timing chart showing the operation timing of the semiconductor device 1 when reading data.

[0023] In FIG. 3, among the plurality of word lines 30, the word lines 30 connected to the dummy memory cells 20 are designated as WL_dum, and the word lines 30 connected to the memory cells 10 are designated as WL <0> ~WL <n>In addition, among the multiple source lines 40, the source lines 40 connected to the dummy memory cells 20 are denoted as SL_dum, and the source lines 40 connected to the memory cells 10 are denoted as SL_dum according to the row. <0> ~SL <n>Of the two bit lines 51 and 52 constituting the bit line pair 50, the bit line 51 will be referred to as BL and the bit line 52 will be referred to as BLN. Furthermore, a signal line for controlling the precharge circuit 60 will be referred to as PREC.

[0024] When reading data, all the dummy memory cells 20 are in an erased state.

[0025] As shown in FIG. 3, first, PREC, which is a signal line for controlling the precharge circuit 60, is transitioned from H level to L level, whereby a precharge voltage is applied from the precharge circuit 60 to BL and BLN, and BL and BLN are precharged to the H level.

[0026] Thereafter, PREC is changed from L level to H level, so that BL and BLN are precharged to H level and become floating.

[0027] Next, the row decoder 70 <0> ~WL <n>and transitioning the selected WL from L level to H level, thereby enabling the memory cell 10 connected to the selected WL.

[0028] Furthermore, the row decoder 70 transitions WL_dum from the L level to the H level, thereby enabling the dummy memory cells 20.

[0029] At the same time that the row decoder 70 enables the memory cells 10 and the dummy memory cells 20, the SEN in the read amplifier 80 is set to the L level, causing the read amplifier 80 to start a read operation.

[0030] The charges precharged to BL and BLN are discharged by flowing as a current through the enabled memory cells 10 and the dummy memory cells 20. As a result, BL and BLN transition from the H level to the L level.

[0031] As described above, by the data write operation to the memory cells 10, the two memory cells 10 connected to the pair of BL and BLN are in opposing states of erased state / programmed state or programmed state / erased state.

[0032] The erased state is a state in which current easily flows between the source and drain of the memory cell 10 when the memory cell 10 is enabled during data reading. The programmed state is a state in which current does not easily flow between the source and drain of the memory cell 10 when the memory cell 10 is enabled during data reading.

[0033] Due to these opposing states, the transition times of BL and BLN, which are in a floating state, to the L level differ, and either BL or BLN goes to the L level earlier.

[0034] Furthermore, since the dummy memory cells 20 in the erased state are connected to BL and BLN in the same way, the speed at which BL and BLN become L level is uniformly improved compared to the case where the dummy memory cells 20 are not connected.

[0035] In this way, by taking advantage of the difference between the speed at which BL goes to L level and the speed at which BLN goes to L level, the read amplifier 80 determines the values ​​of the data held by the two memory cells 10 connected to BL and BLN based on the signal line which first falls below the threshold T among the potentials of BL and BLN, and outputs a signal of H level (data 1) or L level (data 0) from Dout.

[0036] When the memory cell 10 connected to BL is in an erased state and the memory cell 10 connected to BLN is in a programmed state, a signal of L level (data 0) is output from Dout. When the memory cell 10 connected to BL is in a programmed state and the memory cell 10 connected to BLN is in an erased state, a signal of H level (data 1) is output from Dout.

[0037] FIG. 3 shows an example in which the memory cell 10 connected to BL is in a programmed state, and the memory cell 10 connected to BLN is in an erased state, so that an H level (1 data) signal is output from Dout.

[0038] As described above, the time from when the memory cell 10 and the dummy memory cell 20 are enabled until the signal at Dout is fixed at an H level (1 data) or an L level (0 data) is determined depending on the speed at which BL and BLN become an L level.

[0039] When reading data, if only the memory cell 10 to be read is enabled, the speed at which BL and BLN become L level is slow, so it takes time for the signal output from Dout to be determined to be H level (1 data) or L level (0 data), as shown by the dotted lines in the BL and BLN parts of Figure 3.

[0040] In contrast, in the semiconductor device 1 of this embodiment, when data is read, not only the memory cells 10 to be read but also the dummy memory cells 20 in an erased state are enabled, so that the speed at which BL and BLN become L level is improved across the board compared to when the dummy memory cells 20 are not connected. This reduces the time it takes for the signal output from Dout to be determined to be H level (1 data) or L level (0 data), as shown by the solid lines in the BL and BLN portions of FIG. 3, and therefore improves the data read speed.

[0041] [Variations] Although the semiconductor device 1 according to one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment and can be modified as appropriate.

[0042] For example, in the above embodiment, one row of dummy memory cells 20 is provided, but multiple rows of dummy memory cells 20 may be provided, that is, dummy memory cells 20 arranged in a matrix may be provided. By providing multiple rows of dummy memory cells 20, the data read speed can be improved in proportion to the number of rows of the dummy memory cells 20.

[0043] Furthermore, in the above embodiment, all the dummy memory cells 20 are in an erased state when reading data, but all the dummy memory cells 20 may be in a programmed state.

[0044] In addition, in the above embodiment, the memory cell 10 and the dummy memory cell 20 are flash memories, but the memory cell 10 and the dummy memory cell 20 may be any type of memory, such as a dynamic random access memory (DRAM), that stores one piece of data using two memory cells and reads out data using a precharge method.

[0045] In addition to the above, appropriate modifications may be made to the description and illustrations shown above, such as deleting unnecessary parts, adding new elements, or making substitutions, within the scope of the gist of the technology disclosed herein. [Explanation of symbols]

[0046] 1 Semiconductor device 10 Memory Cells 20 Dummy memory cell 30 Word Line 40 Source Line 50 bit line pairs 51, 52 bit lines 60 Precharge Circuit 70 Row Decoder 80 Lead Amp 81, 82, 83 P-channel transistors 84, 85 N-channel transistor< / n> < / n> < / n>

Claims

1. A plurality of first memory cells arranged in a matrix; a plurality of second memory cells arranged in at least a row; a plurality of word lines provided in each row of the first memory cells and the second memory cells; a plurality of bit line pairs provided in each column of the first memory cells and the second memory cells; a precharge circuit for applying a precharge potential to the bit line pair when reading data; a row decoder that selects, for each row, the first memory cells and the second memory cells to be enabled when reading data; a read amplifier that determines a value of data based on one of the two bit lines constituting the bit line pair, the potential of which falls below a threshold value first, when reading data; of the two first memory cells connected to the bit line pair for each row, one of the first memory cells is set to an erased state and the other of the first memory cells is set to a programmed state, thereby performing data writing; the two second memory cells connected to the bit line pair for each row are both set to an erased state or a programmed state at least during data reading; The row decoder enables the second memory cells and enables the first memory cells for each row when reading data. Semiconductor device.

2. The two second memory cells connected to the bit line pair for each row are both put into an erased state at least during data read. The semiconductor device according to claim 1 .

3. The first memory cell and the second memory cell are flash memory or dynamic random access memory. The semiconductor device according to claim 1 .

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