Semiconductor device and manufacturing method for semiconductor device

Abstract

To form a metal layer with different thickness in a final stage of a wiring step.SOLUTION: A semiconductor device in an embodiment includes a transistor, and a plurality of metal layers disposed in the respective layers stacked over the transistor. The metal layers include a first metal layer disposed in a lowermost layer among the layers, a second metal layer disposed in an uppermost layer among the layers and being thicker than the first metal layer, and a third metal layer disposed in the uppermost layer among the layers and being thicker than the second metal layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] When manufacturing a semiconductor device, a thick metal layer may be formed in the final stage of the wiring process by using electrolytic plating, etc. The thick metal layer can be used as a rewiring layer for changing the lead-out position of the underlying wiring, or as an electrode pad to which a bonding wire or the like can be connected. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4232576 [Patent Document 2] Patent No. 2679680 [Patent Document 3] US Patent Application Publication No. 2021 / 0098373 [Patent Document 4] US Patent Application Publication No. 2009 / 0267234 Summary of the Invention [Problem to be solved by the invention]

[0004] However, since even the rewiring layer for rewiring the lower wiring layer becomes a thick film, the wiring size increases, which may hinder miniaturization of the semiconductor device.

[0005] An object of one embodiment is to provide a semiconductor device and a method for manufacturing the semiconductor device that enable formation of metal layers with different thicknesses in the final stage of a wiring process. [Means for solving the problem]

[0006] A semiconductor device of an embodiment includes a transistor and a plurality of metal layers respectively arranged in a plurality of layers stacked above the transistor, the plurality of metal layers including a first metal layer arranged in a lowermost layer of the plurality of layers, a second metal layer arranged in an uppermost layer of the plurality of layers and thicker than the first metal layer, and a third metal layer arranged in the uppermost layer and thicker than the second metal layer. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of a configuration in a layer of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing an example of a procedure of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing an example of a procedure of the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view showing an example of a method for forming a wiring layer of a semiconductor device according to a comparative example. [Figure 6] FIG. 6 is a diagram illustrating an example of a configuration of the semiconductor device according to the second embodiment. As shown in FIG. [Figure 7] FIG. 7 is a diagram showing an example of a procedure of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing an example of a procedure of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a diagram showing an example of a procedure of the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. In addition, the components in the following embodiments include those that a person skilled in the art can easily imagine or that are substantially the same.

[0009] [Embodiment 1] Hereinafter, the first embodiment will be described in detail with reference to the drawings.

[0010] (Example of the configuration of a semiconductor device) Fig. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to embodiment 1. As shown in Fig. 1, the semiconductor device 1 of embodiment 1 includes a semiconductor substrate 10, a plurality of transistors TR, and a plurality of layers M0 to M4, R0, R1, etc. However, these layers M0 to M4, R0, R1, etc. are merely illustrative, and the semiconductor device 1 may include any number of layers.

[0011] The semiconductor substrate 10 is a silicon substrate or the like.

[0012] The plurality of transistors TR are provided, for example, on a semiconductor substrate 10. These transistors TR are field-effect transistors (FETs) or the like, and may be configured, for example, as double-diffused metal-oxide-semiconductor field-effect transistors (DMOS FETs).

[0013] These transistors TR are covered with an insulating layer 20, which is a silicon oxide layer or the like. Contacts 21 and a wiring layer 22, which are connected to these transistors TR, are arranged in the insulating layer 20. At least a part of the insulating layer 20, and at least the wiring layer 22 out of the contacts 21 and the wiring layer 22, belong to a layer M0 above the transistors TR. The contacts 21 and the wiring layer 22 are metal layers including, for example, a tungsten layer.

[0014] The layers M0 to M4, R0, R1, etc. including the bottom layer M0 are provided in this order above the transistor TR, and have a plurality of vias 31, 33, 41, 43, VA, and a plurality of wiring layers 22, 32, 34, 42, 44, WA, WB, etc. The design rules for these layers M0 to M4, R0, R1 are gradually expanded from the lower layer side closer to the transistor TR to the upper layer side. As an example, the diameter, extension length, pitch, etc. of the contact 21 directly connected to the transistor TR and the upper layer vias 31, 33, 41, 43, VA, etc. are larger toward the upper layer side, and the width, thickness, pitch, etc. of the wiring layers 22, 32, 34, 42, 44, WA, WB, etc. are larger toward the upper layer side.

[0015] The layers M1 and M2 are provided in this order on the bottom layer M0. The layer M1 is provided with a via 31 and a wiring layer 32 connected to the wiring layer 22 etc. of the layer M0, as well as an insulating layer 30a including the via 31 and the wiring layer 32 etc. Similarly, the layer M2 is provided with a via 33 and a wiring layer 34 connected to the wiring layer 32 etc. of the layer M1, as well as an insulating layer 30b including them.

[0016] The insulating layers 30a, 30b are, for example, silicon oxide layers. Hereinafter, these insulating layers 30a, 30b may be collectively referred to as insulating layer 30. The vias 31, 33 and wiring layers 32, 34 are, for example, metal layers including a Cu layer. The vias 31, 33 and wiring layers 32, 34 electrically connect, for example, a plurality of transistors TR to each other, and are also referred to as local interconnects.

[0017] The layers M3 and M4 are provided in this order on the layer M2. The layer M3 is provided with a via 41 and a wiring layer 42 connected to the wiring layer 34 of the layer M2, etc., and an insulating layer 40a including these. The layer M4 is provided with a via 43 and a wiring layer 44 connected to the wiring layer 42 of the layer M3, etc., and an insulating layer 40b including these.

[0018] The insulating layers 40a and 40b are, for example, silicon oxide layers. The vias 41 and 43 and the wiring layers 42 and 44 are, for example, metal layers including a Cu layer. The vias 41 and 43 and the wiring layers 42 and 44 electrically connect circuits each composed of, for example, a plurality of transistors TR, and are also called global interconnects.

[0019] The layers R0 and R1 are provided in this order on the layer M4. The layer R0 is provided with a via VA connected to the wiring layer 44 of the layer M4, and an insulating layer 40c including the via VA. Of the multiple layers M0 to M4, R0, R1, etc., the layer R1 is the uppermost layer, and is provided with a wiring layer WA connected to the via VA of the layer R0, a wiring layer WB thicker than the wiring layer WA, and an insulating layer 50 including the wiring layers WA and WB. The insulating layer 50 has an opening, and the upper surface of the wiring layer WB is exposed from the opening.

[0020] The insulating layer 40c is, for example, a silicon oxide layer, etc. Hereinafter, the insulating layers 40a to 40c may be collectively referred to as the insulating layer 40, etc. The insulating layer 50 is, for example, a polyimide layer, etc.

[0021] The vias VA and the wiring layers WA, WB, etc. are metal layers including, for example, a Cu layer, etc. In addition, as described later, the vias VA and the wiring layers WA, WB, etc. are also called redistribution layers (RDLs) formed using, for example, a redistribution layer formation technology.

[0022] However, in the semiconductor device 1 of the embodiment 1, of the wiring layers WA and WB, the wiring layer WB functions as an electrode pad connectable to an external device, etc. On the other hand, the wiring layer WA functions as a so-called rewiring layer in the narrow sense, which changes the lead-out position of the wiring layer 44 of the underlying layer M4, etc.

[0023] As described above, the configuration of the semiconductor device 1 shown in Fig. 1 is an example, and the number and combination of layers included in the semiconductor device 1 are not limited to the example in Fig. 1. For example, the semiconductor device 1 may include an intermediate wiring layer, a semi-global wiring layer, etc. between a local interconnect and a global interconnect. In this case, the design rules for the intermediate wiring layer and the semi-global wiring layer have values ​​between the design rules for the local interconnect and the global interconnect, and the intermediate wiring layer and the semi-global wiring layer may have the same design rule.

[0024] 1, the vias 31, 33, 41, 43, VA, etc. and the corresponding wiring layers 32, 34, 42, 44, WA, WB, etc. are depicted as being separate structures, but as described later, the vias 31, 33, 41, 43, VA, etc. and the corresponding wiring layers 32, 34, 42, 44, WA, WB, etc. may be formed separately or together. When a certain via and the corresponding wiring layer are formed together, the via and the wiring layer may be observed as being an integral structure.

[0025] FIG. 2 is a cross-sectional view showing an example of the configuration of layers R0 and R1 of the semiconductor device 1 according to the first embodiment.

[0026] As shown in Fig. 2, a plurality of vias 43, a plurality of wiring layers 44, and a plurality of vias VA are provided in this order in the insulating layer 40. The insulating layer 40 shown in Fig. 2 includes at least a part of the insulating layers 40b and 40c in Fig. 1 described above. The plurality of vias 43 are connected to any of the plurality of wiring layers 44, and any of the plurality of vias VA is connected to the plurality of wiring layers 44.

[0027] An insulating layer 50 having openings 50p, which is the uppermost layer of the semiconductor device 1, is disposed on the insulating layer 40. Each of the vias VA is connected to one of the wiring layers WA, WB included in the insulating layer 50.

[0028] More specifically, the wiring layers WA, WB are disposed on an insulating layer 40 belonging to layers M4, R0 below the layer R1 to which the wiring layers WA, WB belong. The wiring layer WA as the second metal layer is entirely embedded in the insulating layer 50, and at least a part of the upper surface of the wiring layer WB as the third metal layer is exposed from an opening 50p of the insulating layer 50. The insulating layer 50 may have an uneven upper surface in accordance with the unevenness of these wiring layers WA, WB.

[0029] The wiring layer WA is configured to be thicker than at least the wiring layer 22 (see FIG. 1) serving as the first metal layer in the lowermost layer M0, and may be configured to be thicker than the wiring layer 44 included in the insulating layer 40. The wiring layer WB is thicker than the wiring layer WA, and further has a thickness 40 times or more that of the wiring layer 22 in the lowermost layer M0.

[0030] For example, even if the process node is reduced to 130 nm, 90 nm, 65 nm, and 40 nm, the wiring layer WA can have a thickness of about 5 μm and the wiring layer WB can have a thickness of 10 μm or more, for example. Note that, for example, when the process node is said to be 130 nm, this means that the gate length of the transistor TR is 130 nm.

[0031] In this way, even if the process node is gradually reduced, the thicknesses of the wiring layers WA and WB may be maintained at about 5 μm and 10 μm or more, respectively. As described later, the wiring layers WA and WB are formed using a redistribution layer formation technique different from that of the wiring layers 22, 32, 34, 42, 44 of the lower layers M0 to M4, so that the thickness of the wiring layer WA, about 5 μm, is close to the minimum processing dimension. Also, as described later, the wiring layer WB is required to have a certain strength, so it is preferable to maintain the thickness at 10 μm or more.

[0032] On the other hand, as the process node is reduced to 130 nm, 90 nm, 65 nm, and 40 nm, the thickness of the wiring layer 22 in the lowermost layer M0 is gradually reduced, and the wiring layer WB having a thickness of 10 μm or more has a thickness, for example, 50 to 77 times that of the wiring layer 22. In this manner, the thickness of the wiring layer WB may be, for example, 40 times or more, and more preferably, 40 times or more and 80 times or less, of the thickness of the wiring layer 22.

[0033] The wiring layers WA, WB and the vias VA connected to the wiring layers WA, WB have a plating layer 52 as a first layer and a barrier metal layer 51 as a second layer.

[0034] The plating layer 52 is, for example, a Cu layer formed by electrolytic plating using a seed layer (not shown) provided on the barrier metal layer 51 as an electrode, and corresponds to the core material of the via VA and the main body of the wiring layer WA. The plating layer 52 is provided continuously over the via VA and the wiring layer WA.

[0035] The barrier metal layer 51 is a layer containing a metal different from the plating layer 52, such as a Ti layer or a TiW layer, and is provided on the lower surfaces of the wiring layers WA and WB except for the portion where the via VA is connected, and on the side and bottom surfaces of the via VA. The barrier metal layer 51 is provided continuously from the lower surfaces of the wiring layers WA and WB to the side and bottom surfaces of the via VA. This allows the barrier metal layer 51 to suppress the diffusion of the barrier metal layer 51 and plating layer 52, which are Cu layers, into the insulating layer 40, etc. Note that the barrier metal layer 51 is processed by, for example, wet etching, as described later, and may have a side-etched shape that is narrower than the plating layer 52 portion of the wiring layers WA and WB.

[0036] As described above, a seed layer (not shown) is disposed between the barrier metal layer 51 and the plating layer 52. That is, the seed layer is provided on the lower surfaces of the wiring layers WA and WB, excluding the portion where the via VA is connected, and on the side and bottom surfaces of the via VA, inside the barrier metal layer 51. The seed layer is, for example, a Cu layer or the like, like the plating layer 52, and serves as an electrode when the plating layer 52, which is a Cu layer or the like, is formed by electrolytic plating.

[0037] The wiring layer WB further has a covering layer 53 as a third layer on the surface of the plating layer 52 that is exposed from the opening 50p of the insulating layer 50. The covering layer 53 is configured to contain a metal different from that of the plating layer 52, and is, for example, a NiPd layer, a NiAu layer, a NiPdAu layer, or an Au layer. The outer edge of the covering layer 53 is covered and protected by the insulating layer 50.

[0038] The upper surface of the wiring layer WB including the covering layer 53 may not be flat, but may have a rounded shape with a rounded outer edge. The outer edge of the covering layer 53 may protrude from the outer edge of the plating layer 52. Even if the covering layer 53 has such a shape, the rounded shape of the wiring layer WB reduces stress concentration at the end of the wiring layer WB of the insulating layer 50 that protects the outer edge of the wiring layer WB, and prevents the insulating layer 50 from peeling off.

[0039] The wiring layer WB functions as, for example, an electrode pad to be connected to an external device of the semiconductor device 1. As described above, by providing the covering layer 53 on the upper surface of the wiring layer WB, for example, it is possible to connect a bonding wire to the wiring layer WB using the covering layer 53 as a bonding layer.

[0040] In contrast, the wiring layer WA functions as a rewiring layer that changes the lead-out position of the underlying wiring layer 44, etc., as described above. The wiring layer WA is configured to be thinner than the wiring layer WB, so that finer design rules can be applied than for the wiring layer WB. That is, in addition to the thickness, the width, pitch, etc. of the wiring layer WA may be configured to be finer than those of the wiring layer WB.

[0041] When the plating layer 52 of the wiring layers WA and WB is a Cu layer, Cu is an example of the first metal. When the covering layer 53 of the wiring layer WB is a NiPd layer, a NiAu layer, a NiPdAu layer, an Au layer, or the like, the metal used for the covering layer 53 is an example of the second metal.

[0042] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 1 of the embodiment 1 will be described with reference to Fig. 3 and Fig. 4. Fig. 3 and Fig. 4 are cross-sectional views showing an example of a procedure of the method for manufacturing the semiconductor device 1 according to the embodiment 1.

[0043] 3 and 4 mainly show methods for forming various components in layers R0 and R1 of the semiconductor device 1. Various components in layers M0 to M4 below the layers R0 and R1, and the transistor TR and the like, can be formed by a general semiconductor process.

[0044] 1, a transistor TR is formed by forming a gate insulating layer, a gate electrode, etc. on a semiconductor substrate 10, and forming source / drain regions by diffusing impurities of a predetermined conductivity type into the semiconductor substrate 10. Also, an insulating layer 20 covering the transistor TR is formed.

[0045] The process up to this point is also called, for example, the substrate process (FEOL: Front End of Line), while the process after this is also called the wiring process (BEOL: Back End of Line).

[0046] In the wiring process, when forming various components in the layers M0 to M4, precision processing processes such as plasma etching and CVD (Chemical Vapor Deposition) are exclusively used. That is, contact holes and wiring grooves are formed in the insulating layer 20 of the layer M0, and the contacts 21 and wiring layers 22 are formed in these contact holes and wiring grooves. In addition, while insulating layers 30a, 30b, 40a, 40b, etc. are formed in the upper layers M1 to M4, via holes and wiring grooves, etc. are sequentially formed therein, and vias 31, 33, 41, 43 and wiring layers 32, 34, 42, 44, etc. are formed in the via holes and wiring grooves, respectively.

[0047] More specifically, when a Cu layer is used as the metal layer, the formation methods include a single damascene method in which the vias 31, 33, 41, 43, etc. and the corresponding wiring layers 32, 34, 42, 44, etc. are formed individually, or a dual damascene method in which the vias 31, 33, 41, 43 and the wiring layers 32, 34, 42, 44, etc. are formed collectively.

[0048] For example, taking a combination of a via 31 and a wiring layer 32 as an example, in the single damascene method, a via hole is formed, a metal layer is filled in the via hole to form the via 31, and then a wiring trench is formed on the already formed via 31, and a metal layer is filled in the wiring trench to form the wiring layer 32.

[0049] On the other hand, in the dual damascene method, after the via holes and wiring trenches are formed, they are filled with a metal layer all at once to form the vias 31 and the wiring layer 32 at the same time.

[0050] Furthermore, when forming a via hole and a wiring trench using the dual damascene method, one of two methods is mainly adopted: a method in which a via hole is formed and then the upper end of the via hole is expanded to form a wiring trench (Via First method), and a method in which a wiring trench is formed and then a via hole is formed extending in the depth direction from the bottom of the wiring trench (Trench First method).

[0051] In the semiconductor device 1 of embodiment 1, the vias 31, 33, 41, 43 and the wiring layers 32, 34, 42, 44, etc. can be formed, for example, by any of the methods described above. Also, for example, different formation methods may be used for different layers. In addition, an Al layer, an Al-Si-Cu layer, etc. may be used as the wiring material.

[0052] The process of forming vias VA and wiring layers WA, WB, etc. in layers R0, R1 is the final stage of the wiring process, and is carried out as follows using low-cost processing processes with low manufacturing load, such as lift-off using photolithography, electrolytic plating, etc.

[0053] As shown in FIG. 3( a ), a via 43 and a wiring layer 44 have already been formed in the insulating layer 40 .

[0054] As shown in FIG. 3(b), the insulating layer 40 is processed to form a plurality of via holes VH reaching the wiring layer 44.

[0055] 3(c), a barrier metal layer 51b and a seed layer are formed in this order on the surface of the insulating layer 40 and on the side and bottom surfaces of the via holes VH. The barrier metal layer 51b is formed in the via holes VH by sputtering a target such as Ti or TiW. The seed layer is formed on the barrier metal layer 51b by sputtering a target such as Cu.

[0056] When forming the barrier metal layer 51b and the seed layer by sputtering or the like, it is preferable to continuously form the barrier metal layer 51b and the seed layer while the semiconductor substrate 10 to be processed is kept under vacuum. It is also preferable to use a material for the barrier metal layer 51b that has a barrier property against Cu and the like in the seed layer and plating layer 52 to be formed later, and that has high adhesion to the insulating layer 50. The above-mentioned Ti or TiW or the like meets these conditions.

[0057] 3(d), a mask pattern 71 as a first mask pattern such as a photoresist layer is formed to cover the insulating layer 40 and the barrier metal layer 51b on the insulating layer 40. The mask pattern 71 has openings OA, OBa as a plurality of second and first openings at positions where the via holes VH are to be formed.

[0058] 3(e), a plating layer 52 such as a Cu layer is formed by electrolytic plating or the like using the seed layer on the barrier metal layer 51b exposed in the openings OA, OBa of the mask pattern 71 as an electrode. The plating layer 52 as a first layer is formed to be thicker than at least the wiring layer 32 of the bottommost layer M0, and further thicker than the wiring layer 44 formed in the insulating layer 40 below the layer R0.

[0059] Of the openings OA and OBa, the plating layer 52 formed in the opening OA will later become the wiring layer WA that functions as a rewiring layer. Therefore, the openings OA of the mask pattern 71 described above are formed at positions that change the lead-out position of the wiring layer 44 so that the wiring layer WA can rewire the underlying wiring layer 44.

[0060] As shown in FIG. 3(f), the mask pattern 71 is removed by ashing using oxygen plasma or the like.

[0061] As described above, the process of forming a wiring pattern or the like using the mask pattern 71 or the like as a mold is also called lift-off.

[0062] 3(g), a mask pattern 72 as a second mask pattern such as a photoresist layer is formed to cover the insulating layer 40, as well as the barrier metal layer 51b and a part of the plating layer 52 on the insulating layer 40. The mask pattern 72 has an opening OBb as a third opening at a position overlapping with the opening OBa of the mask pattern 71 described above.

[0063] As a result, the plating layer 52 and the like already formed in the openings OA of the mask pattern 71 are covered by the mask pattern 72. In addition, the plating layer 52 is exposed from the openings OBb. At this time, from the viewpoint of the accuracy of aligning the mask pattern 72 with the plating layer 52, it is preferable that the openings OBb of the mask pattern 72 are formed larger than the openings OBa of the mask pattern 71.

[0064] 4(a), the plating layer 52 exposed in the opening OBb of the mask pattern 72 is used as an electrode to form a thicker Cu layer or the like by electrolytic plating or the like. In the opening OBb, the thickened plating layer 52 has a thickness 40 times or more greater than that of the wiring layer 22 of the bottom layer M0. In addition, the opening OBb of the mask pattern 72 is formed larger than the opening OBa of the mask pattern 71, so that further electrolytic plating is performed based on the plating layer 52 already formed to a size smaller than the opening OBb. As a result, the upper end of the thickened plating layer 52 can be made into a round shape.

[0065] As shown in FIG. 4(b), a coating layer 53 such as a NiPd layer, a NiAu layer, a NiPdAu layer, or a Au layer is formed as a second layer on the thick plating layer 52 formed in the opening OBb of the mask pattern 72 by, for example, electroless plating.

[0066] As shown in FIG. 4(c), the mask pattern 72 is removed by ashing using oxygen plasma or the like.

[0067] 4(d), the seed layer and barrier metal layer 51b (not shown) are removed by wet etching or the like from the surface of the insulating layer 40 in the portion not covered with the plating layer 52 or the like. As a result, the seed layer and barrier metal layer 51 having the patterns of the wiring layers WA and WB are formed, and the thin wiring layer WA without the covering layer 53 and the thick wiring layer WB having the covering layer 53 are formed.

[0068] During wet etching of the barrier metal layer 51, etc., side etching occurs in the seed layer and the barrier metal layer 51, and a part of the plating layer 52 on the barrier metal layer 51 is also etched. This reduces the width of the plating layer 52, and the coating layer 53 on the plating layer 52 may have a shape that protrudes from the end of the plating layer 52 like an eaves.

[0069] 4(e), an insulating layer 50 such as a polyimide layer is formed having an opening 50p at the formation position of the wiring layer WB and covering the insulating layer 40 including the wiring layer WA. At this time, unevenness may be generated on the upper surface of the insulating layer 50 depending on the wiring layers WA and WB.

[0070] In this manner, the semiconductor device 1 of the first embodiment is manufactured.

[0071] (Comparative Example) Next, an example of forming wiring layers WAx and WBx of a comparative example will be described with reference to FIG.

[0072] Fig. 5 is a cross-sectional view showing an example of a method for forming wiring layers WAx, WBx of a semiconductor device according to a comparative example. As shown in Fig. 5, in a process for forming a redistribution layer by lift-off using photolithography or the like and electrolytic plating or the like, it is difficult to make the thicknesses of the wiring layers WAx, WBx different, and these wiring layers WAx, WBx are formed to have a uniform thickness.

[0073] That is, as shown in Fig. 5(a), a barrier metal layer 51xb and the like are formed, as shown in Fig. 5(b), a mask pattern 77 is formed to cover the barrier metal layer 51xb, a plating layer 52x is formed in the openings OAx, OBx of the mask pattern 77, and a covering layer 53x is further formed as shown in Fig. 5(c). After removing the mask pattern 77 as shown in Fig. 5(d), the barrier metal layer 51xb and the like in the exposed portion are removed as shown in Fig. 5(e) to form wiring layers WAx, WBx having the same thickness. Thereafter, as shown in Fig. 5(f), an insulating layer 50x is formed by covering the wiring layer WAx and exposing the upper surface of the wiring layer WBx.

[0074] As a result, the wiring layer WAx that functions as a redistribution layer and the wiring layer WBx that functions as an electrode pad are formed.

[0075] In this way, in the semiconductor device of the comparative example, the wiring layer WAx that functions as a redistribution layer is formed to match the thickness of the wiring layer WBx that functions as an electrode pad, for example. Therefore, the expanded design rule for the thick film process is also applied to the wiring layer WAx, making it difficult to miniaturize the wiring layer WAx. This can be one of the factors that hinder the miniaturization of semiconductor devices.

[0076] In addition, the coating layer 53x, which serves as a bonding layer for the bonding wire, is also formed on the wiring layer WAx, which does not require a bonding layer, resulting in an increase in process costs. Furthermore, since there is a risk of peeling off of the insulating layer 50x, which serves as a protective layer, in thick-film wiring patterns, visual inspection is essential to ensure bonding reliability and improve yield. Since both the wiring layers WAx and WBx are formed as thick films, the total number of inspections increases, further increasing process costs.

[0077] Therefore, it is conceivable to form a wiring layer WAx serving as a redistribution layer separately in a layer below the wiring layer WBx serving as an electrode pad. However, an increase in the number of layers of the semiconductor device ultimately increases the manufacturing load and process cost.

[0078] According to the semiconductor device 1 of embodiment 1, the semiconductor device includes a wiring layer 22 arranged in the lowest layer M0 of the multiple layers M0 to M4, R0, R1, a wiring layer WA arranged in the highest layer R1 and thicker than the wiring layer 22, and a wiring layer WB arranged in the highest layer R1, thicker than the wiring layer WA, and having a thickness at least 40 times that of the wiring layer 22.

[0079] In this manner, it becomes possible to form wiring layers WA and WB having different thicknesses in the final stage of the wiring process.

[0080] Furthermore, by making the wiring layer WB, for example, 40 times thicker than the wiring layer 22, when the wiring layer WB is made to function as an electrode pad connected to a bonding wire, the on-resistance can be reduced and the output of the transistor TR can be improved. Also, the heat dissipation characteristics of the wiring layer WB can be improved to improve the breakdown resistance, and damage to the underlying layers M0 to M4, etc., caused by the load applied when bonding with the bonding wire can be suppressed.

[0081] On the other hand, by making the wiring layer WA, which functions as, for example, a redistribution layer, etc., thin, it becomes possible to apply finer design rules to the wiring layer WA, and there is no increase in the number of layers of the semiconductor device 1. This makes it easier to reduce process costs and to miniaturize the semiconductor device 1.

[0082] As described above, it is possible to simultaneously satisfy the different demands of improving element characteristics by increasing the thickness of the film and narrowing the design rule.

[0083] According to the semiconductor device 1 of the first embodiment, the wiring layer WB has an upper surface exposed from the opening 50p of the insulating layer 50. This allows the wiring layer WB to function as an electrode pad.

[0084] According to the semiconductor device 1 of embodiment 1, the wiring layer WA includes a plating layer 52 containing a metal such as Cu, and a barrier metal layer 51 containing a metal different from the plating layer 52 and arranged below the plating layer 52, and a coating layer 53 containing a metal such as Ti or TiW different from the metal of the plating layer 52 and arranged above the plating layer 52 is selectively arranged on the plating layer 52 of the wiring layer WB.

[0085] In this manner, the covering layer 53 is formed only on the wiring layer WB, and the wiring layer WA does not have the unnecessary covering layer 53, so that the process cost can be further reduced.

[0086] [Embodiment 2] Hereinafter, a detailed description will be given of the second embodiment with reference to the drawings. The semiconductor device of the second embodiment differs from the first embodiment in that a part of the wiring layer is formed without contacting the lower layer.

[0087] In the following drawings, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0088] (Example of the configuration of a semiconductor device) Fig. 6 is a diagram showing an example of the configuration of a semiconductor device according to embodiment 2. More specifically, Fig. 6(a) is a cross-sectional view of a portion of the configuration including the uppermost layer of the semiconductor device of embodiment 2, and Fig. 6(b) is a top view of the uppermost layer of the semiconductor device of embodiment 2. However, Fig. 6(b) shows the configuration covered by the insulating layer 50 through the insulating layer 50.

[0089] 6, in the semiconductor device of the second embodiment, an insulating layer 50 is disposed in the uppermost layer, and an insulating layer 40 is disposed below the uppermost layer. In the insulating layer 40, a via 45 and a wiring layer 46 which belong to the layer below the uppermost layer are disposed.

[0090] Furthermore, a plurality of vias VB connected to the wiring layer 46 are arranged in the insulating layer 40, and these vias VB are connected to a wiring layer WD arranged in the insulating layer 50 belonging to the uppermost layer. A wiring layer CB is also arranged in the insulating layer 50.

[0091] The wiring layer CB as the second metal layer has, for example, a meandering shape in which thin wires meander multiple times when viewed from above, and is disposed above the insulating layer 40 without contacting the underlying insulating layer 40. As a result, the wiring layer CB is disposed, for example, inside the insulating layer 50 and separated from the insulating layer 40. However, the wiring layer CB may have a comb-tooth shape or a membrane shape. In either case, the wiring layer CB is configured mainly to include the intermediate layer 57.

[0092] The wiring layer WD as the third metal layer has, for example, a pad shape when viewed from above, and a part of the upper surface is exposed from the opening 50p of the insulating layer 50. The wiring layer WD also has a thickness 40 times, more preferably 40 to 80 times, that of the wiring layer of the bottom layer.

[0093] The wiring layer WD has a configuration in which a barrier metal layer 55 as a second layer, a plating layer 56 as a first layer, and a coating layer 58 are laminated in this order. The wiring layer WD also has an intermediate layer 57 as a third layer interposed in the plating layer 56, and a seed layer (not shown) interposed between the barrier metal layer 55 and the plating layer 56.

[0094] The barrier metal layer 55 is, for example, a Ti layer or a TiW layer, similar to the above-mentioned barrier metal layer 51. The seed layer and plating layer 56 (not shown) is, for example, a Cu layer, similar to the above-mentioned seed layer and plating layer 52. In this case, Cu is an example of the first metal. The intermediate layer 57 is, for example, a Si layer or a Pd layer. In this case, Si or Pd is an example of the second metal. The coating layer 58 is, for example, a NiPd layer, a NiAu layer, a NiPdAu layer, or a Au layer, similar to the above-mentioned coating layer 53.

[0095] The intermediate layer 57 of the wiring layer WD is connected to the intermediate layer 57 of the wiring layer CB, and thus the wiring layer WD functions as an anchor supporting the wiring layer WA disposed above the insulating layer 40. The wiring layer WD may also function as an electrode pad.

[0096] The wiring layer WD is disposed on one side or both sides of the above-mentioned wiring layer CB to support the wiring layer CB, so that the wiring layer CB has a cantilever beam structure or a double-fixed beam structure.

[0097] On the other hand, the thin wiring layer CB functions as, for example, an inductor. Alternatively, the thin wiring layer CB may function as a sensor for sensing the pressure, gas, or sound waves in the atmosphere around the semiconductor device of the second embodiment, or as a movable spring or micromirror. In this case, instead of burying the wiring layer CB in the insulating layer 50, a gap may be provided around the wiring layer CB to provide a movable range for the wiring layer CB.

[0098] In this manner, the uppermost layer portion of the semiconductor device of the second embodiment can be configured as, for example, an inductor or a MEMS (Micro Electro Mechanical System).

[0099] Furthermore, in layers below the top layer, the semiconductor device of the second embodiment may have transistors, contacts connected to the transistors, vias, wiring layers, etc., similar to the semiconductor device 1 of the above-described embodiment. Such a lower layer portion of the semiconductor device is configured as, for example, a control circuit for controlling the inductor or MEMS in the top layer portion.

[0100] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing a semiconductor device according to embodiment 2 will be described with reference to Fig. 7 to Fig. 9. Fig. 7 to Fig. 9 are diagrams showing an example of a procedure for the method for manufacturing a semiconductor device according to embodiment 2. Among Fig. 7 to Fig. 9, Fig. 7(e) and Fig. 9(c) are top views of the semiconductor device during manufacture, and the rest are cross-sectional views of the semiconductor device during manufacture.

[0101] 7 to 9 mainly show a method for forming various components in the uppermost layer of the semiconductor device of the second embodiment.

[0102] As shown in FIG. 7( a ), a via 45 and a wiring layer 46 have already been formed in the insulating layer 40 .

[0103] As shown in FIG. 7(b), the insulating layer 40 is processed to form a plurality of via holes VH reaching the wiring layer 46.

[0104] 7(c), a barrier metal layer 55b and a seed layer are formed by, for example, sputtering on the surface of the insulating layer 40 and the side and bottom surfaces of the via holes VH. It is preferable that the barrier metal layer 55b and the seed layer are formed continuously.

[0105] 7(d), a mask pattern 73 as a first mask pattern such as a photoresist layer is formed to cover the insulating layer 40 and the barrier metal layer 55b on the insulating layer 40. The mask pattern 73 has an opening ODa as a second opening at a position where the via hole VH is to be formed, and has an opening OC as a first opening at a position away from the opening ODa.

[0106] As shown in FIG. 7(e), the opening OC of the mask pattern 73 has a meandering shape in which the opening of a narrow groove meanders multiple times, and a part of the opening OC is connected to the opening ODa.

[0107] 8(a), a plating layer 56 of a first metal such as Cu is formed by electrolytic plating or the like using the seed layer on the barrier metal layer 55b exposed in the openings OC, ODa of the mask pattern 73 as an electrode. The plating layer 56 as the first metal layer is formed to be thicker than at least the wiring layer of the lowermost layer, and further thicker than the wiring layer 46 formed on the insulating layer 40 below.

[0108] 8(b), an intermediate layer 57 such as a Si layer or a Pd layer is formed as a second layer on the plating layer 56 in the openings OC, ODa of the mask pattern 73. The Si layer can be formed by CVD, for example, and the Pd layer can be formed by electroless plating, for example. The metal such as Si or Pd constituting the intermediate layer 57 is an example of a second metal, and has a higher wet etching resistance than, for example, the metal constituting the barrier metal layer 55b and the plating layer 56, etc.

[0109] As shown in FIG. 8(c), the mask pattern 73 is removed by ashing using oxygen plasma or the like.

[0110] 8(d), a mask pattern 74 as a second mask pattern such as a photoresist layer is formed to cover the insulating layer 40, as well as the barrier metal layer 51b and a part of the plating layer 52 and intermediate layer 57 on the insulating layer 40. The mask pattern 74 has an opening ODb as a third opening, which is larger than the opening ODa, at a position overlapping with the opening ODa of the mask pattern 73 described above.

[0111] 8(e), using the intermediate layer 57 exposed in the opening ODb of the mask pattern 74 as an electrode, a third metal such as Cu is formed thicker by electrolytic plating or the like. As a result, using the already formed small-sized plating layer 56 and intermediate layer 57 as a base, a thick plating layer 56 is formed having a rounded upper surface and a thickness 40 times or more greater than that of the wiring layer of the bottom layer.

[0112] As shown in FIG. 8(f), a coating layer 58 such as a NiPd layer, a NiAu layer, a NiPdAu layer, or a Au layer is formed on the thick plating layer 56 formed in the opening ODb of the mask pattern 74 by, for example, electroless plating.

[0113] As shown in FIG. 9(a), the mask pattern 74 is removed by ashing using oxygen plasma or the like.

[0114] As shown in FIG. 9B, the barrier metal layer 55b and the seed layer are removed by wet etching or the like from the surface of the insulating layer 40 in the portion not covered with the intermediate layer 57 or the covering layer 58 or the like.

[0115] As a result, in the portion covered with the covering layer 58, the barrier metal layer 55 and the seed layer having the pattern of the wiring layer WD are formed with a side-etched shape relative to the upper plating layer 56, and a portion of the plating layer 56 itself is also etched to form the wiring layer WD that is recessed in the width direction.

[0116] On the other hand, in the portion covered with the intermediate layer 57, the intermediate layer 57 and the plating layer 56 are in the form of thin lines, so that the barrier metal layer 55 and the seed layer disappear together with the upper plating layer 56. At this time, the intermediate layer 57 containing a metal having a higher wet etching resistance than the seed layer, the plating layer 56, etc. remains without disappearing. As a result, a wiring layer CB is formed that is spaced upward from the insulating layer 40 and has the intermediate layer 57 supported by the wiring layer WD. This state is shown in the top view of FIG. 9(c).

[0117] As shown in FIG. 9D, an insulating layer 50 such as a polyimide layer is formed, which has an opening 50p at the position where the wiring layer WD is to be formed and covers the insulating layer 40 including the wiring layer CB.

[0118] In this manner, the semiconductor device of the second embodiment is manufactured.

[0119] (Overview) According to the semiconductor device of the second embodiment, the wiring layer CB is disposed above the lower layer without contacting the lower layer. By configuring the wiring layer CB in this way, a semiconductor device including an inductor or MEMS can be configured at low cost.

[0120] According to the semiconductor device of the second embodiment, the wiring layer CB is configured to contain a metal such as Si or Pd different from the metal of the plating layer 56, and the wiring layer WD includes an intermediate layer 57 in the plating layer 56 at a height position equal to that of the wiring layer CB, the intermediate layer 57 containing the above-mentioned metal different from the metal of the plating layer 56. By configuring each layer of the wiring layers WD and CB in this manner, it is possible to configure the wiring layer CB so that it is disposed above the lower layer without contacting the lower layer.

[0121] According to the semiconductor device of the second embodiment, the wiring layer WD is connected to the wiring layer CB to serve as an anchor supporting the wiring layer CB, and the wiring layer CB has a comb-tooth, meandering, or membrane-like cantilever structure or a double-fixed beam structure, which allows the wiring layer CB to function as an inductor, a sensor, or the like.

[0122] In addition, the semiconductor device of the second embodiment has the same effects as the semiconductor device 1 of the first embodiment described above.

[0123] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0124] 1...semiconductor device, 10...semiconductor substrate, 20, 30, 40, 50...insulating layer, 21...contact, 22, 32, 34, 42, 44...wiring layer, 31, 33, 41, 43...via, 50p...opening, 51, 55...barrier metal layer, 52, 56...plating layer, 53, 58...coating layer, 57...intermediate layer, CB, WA, WB, WD...wiring layer, M0 to M4, R0, R1...layer, TR...transistor, VA, VB...via.

Claims

1. A transistor; a plurality of metal layers disposed in a plurality of layers stacked above the transistor; The plurality of metal layers include a first metal layer disposed in a lowermost layer of the plurality of layers; a second metal layer disposed in a topmost layer of the plurality of layers, the second metal layer being thicker than the first metal layer; a third metal layer disposed on the top layer, the third metal layer being thicker than the second metal layer; Semiconductor device.

2. The third metal layer comprises: having a thickness of 40 times or more than that of the first metal layer; The semiconductor device according to claim 1 .

3. The third metal layer comprises: The outer edge has a rounded shape. The semiconductor device according to claim 1 .

4. an insulating layer disposed on the top layer and having an opening; The second metal layer comprises: covered with the insulating layer, The third metal layer comprises: having an upper surface exposed from the opening, The semiconductor device according to claim 1 .

5. The third metal layer comprises: a first layer comprising a first metal; a second layer comprising a metal different from the first metal and disposed below the first layer; a third layer disposed above the first layer and including a second metal different from the first metal; The semiconductor device according to claim 4.

6. The second metal layer comprises: the first layer; the second layer, The third layer comprises: Of the second and third metal layers, the third metal layer is selectively disposed on the first layer; The semiconductor device according to claim 5 .

7. At least a portion of the metal layers disposed in a layer below the uppermost layer among the plurality of metal layers is electrically connected to the transistor; The second metal layer comprises: a redistribution layer for changing the lead-out position of at least a part of the metal layer; The third metal layer comprises: An electrode pad that can be connected to an external device. The semiconductor device according to claim 4.

8. The third metal layer comprises: disposed on a layer below the top layer; The second metal layer comprises: disposed above the underlying layer without contacting the underlying layer; The semiconductor device according to claim 1 .

9. The third metal layer comprises: a first layer comprising a first metal; a second layer comprising a metal different from the first metal and disposed below the first layer; The semiconductor device according to claim 8.

10. The second metal layer comprises: The second metal is different from the first metal, The third metal layer comprises: The first layer further includes a third layer including the second metal at a height equal to that of the second metal layer. The semiconductor device according to claim 9.

11. The third metal layer comprises: a second metal layer connected to the second metal layer and serving as an anchor for supporting the second metal layer; The second metal layer comprises: The cantilever beam structure has a comb-like, meandering, or membrane-like shape, or a fixed-both-end beam structure. The semiconductor device according to claim 8.

12. The third metal layer comprises: An electrode pad that can be connected to an external device. The semiconductor device according to claim 11.

13. forming a transistor on a substrate; depositing a plurality of layers above the transistor, each layer including a plurality of metal layers; When forming the lowest layer of the plurality of layers, forming a first metal layer that is part of the plurality of metal layers and is electrically connected to the transistor; When forming the uppermost layer of the plurality of layers, forming a first mask pattern on a layer below the top layer, the first mask pattern having first and second openings; forming a second metal layer, which is a part of the plurality of metal layers and is thicker than the first metal layer, in each of the first and second openings by electrolytic plating; forming a second mask pattern on the underlying layer, the second mask pattern having a third opening at a position overlapping the first opening; further performing electrolytic plating on the second metal layer exposed from the third opening, to form a third metal layer, which is a part of the plurality of metal layers and is a thick film of the second metal layer, in the third opening; A method for manufacturing a semiconductor device.

14. The third metal layer comprises: having a thickness of 40 times or more than that of the first metal layer; The method for manufacturing a semiconductor device according to claim 13.

15. When forming the second metal layer, forming a first layer including a first metal in the first and second openings by the electrolytic plating; The method for manufacturing a semiconductor device according to claim 13.

16. When forming the third metal layer, forming a second layer on the first layer, the second layer comprising a second metal different from the first metal; The method for manufacturing a semiconductor device according to claim 15.

17. forming an insulating layer on the underlying layer, the insulating layer covering the second metal layer and having an opening through which an upper surface of the third metal layer is exposed; The method for manufacturing a semiconductor device according to claim 16.

18. When forming the plurality of metal layers, At least a part of the metal layer disposed in the lower layer among the plurality of metal layers is electrically connected to the transistor; When forming the first mask pattern, the second metal layer is formed at a position where a lead-out position of at least a portion of the metal layer is changed; the third metal layer forms the second opening at a position connectable to an external device; The method for manufacturing a semiconductor device according to claim 17.

19. When forming the second metal layer, forming a second layer on the first layer, the second layer comprising a second metal different from the first metal; After forming the third metal layer, the first layer of the second metal layer formed in the second opening is removed to place the second layer of the second metal layer above the underlying layer without contacting the underlying layer. The method for manufacturing a semiconductor device according to claim 15.

20. When forming the third metal layer, a portion of the second metal layer formed in the second opening; When removing the first layer, forming the second layer having a comb-like, meandering, or membrane-like cantilever structure or a fixed-both-end structure; The method for manufacturing a semiconductor device according to claim 19.

Images