Semiconductor device

Abstract

To provide a semiconductor device that can relax an electric field.SOLUTION: A semiconductor device comprises first to fourth electrodes, first to fourth semiconductor regions, and first and second insulating parts. The third electrode includes a first electrode region extending along a second direction and arranged side by side with the second semiconductor region in a third direction, a second electrode region extending in the third direction and arranged side by side with the second semiconductor region in the second direction, and a third electrode region connecting the first electrode region and the second electrode region to each other. The first insulating part includes a first insulating region including first and second insulating portions, a second insulating region including third and fourth insulating portions, and a third insulating region including fifth and sixth insulating portions. The sixth insulating portion is provided between the first semiconductor region and the third electrode region in a first direction. The fourth electrode is arranged side by side with the first semiconductor region and the third electrode in the second and third directions. The fourth semiconductor region is provided below the sixth insulating portion.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, etc. In the semiconductor device, it is desirable to reduce an electric field. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-40105 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing an electric field. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a second electrode, a third electrode, a first insulating portion, a fourth electrode, a second insulating portion, and a fourth semiconductor region of the second conductivity type. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode includes a first electrode region, a second electrode region, and a third electrode region. The first electrode region extends along a second direction. The second direction is perpendicular to a first direction from the first electrode to the second electrode. The first electrode region is aligned with the second semiconductor region in a third direction. The third direction is perpendicular to the first direction and intersects with the second direction. The second electrode region extends along the third direction. The second electrode region is aligned with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region. The first insulating portion includes a first insulating region, a second insulating region, and a third insulating region. The first insulating region includes a first insulating portion and a second insulating portion. The first insulating portion is provided between the second semiconductor region and the first electrode region in the third direction. The second insulating portion is provided between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion. The third insulating portion is provided between the second semiconductor region and the second electrode region in the second direction. The fourth insulating portion is provided between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes a fifth insulating portion and a sixth insulating portion. The fifth insulating portion is provided between the second semiconductor region and the third electrode region in a fourth direction. The fourth direction is perpendicular to the first direction and intersects with the second direction and the third direction. The sixth insulating portion is provided between the first semiconductor region and the third electrode region in the first direction.The fourth electrode is aligned with the first semiconductor region and the third electrode in the second direction and the third direction. The second insulating portion is provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction. The fourth semiconductor region is provided under the sixth insulating portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view illustrating a portion of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view illustrating a portion of a semiconductor device according to a first embodiment. [Figure 6] FIG. 4 is a cross-sectional view illustrating a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 7] FIG. 11 is a cross-sectional view illustrating a part of a semiconductor device according to a second modified example of the first embodiment. [Figure 8] FIG. 11 is a cross-sectional view illustrating a portion of a semiconductor device according to a third modified example of the first embodiment. [Figure 9] FIG. 11 is a plan view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a cross-sectional view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 11] 11(a) to 11(e) are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 12(a) to 12(h) are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. In other words, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are included in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] (First embodiment) FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment. FIG. 2 is a plan view illustrating a portion of the semiconductor device according to the first embodiment. 3 to 5 are cross-sectional views illustrating a part of the semiconductor device according to the first embodiment. FIG. 2 represents region II shown in FIG. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is a cross-sectional view taken along line VV shown in FIG.

[0009] The semiconductor device 100 according to the first embodiment is a vertical MOSFET. The semiconductor device 100 is a MOSFET with a so-called dot FP structure.

[0010] As shown in FIGS. 1 to 5, the semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate pad 15, a n - A p-type drift region 21 (first semiconductor region), a p-type base region 22 (second semiconductor region), + A source region 23 (third semiconductor region), p + Semiconductor region 24 (fourth semiconductor region), p + Contact area 27, n + The semiconductor device 100 includes a gate drain region 28, a gate insulating portion 31 (first insulating portion), an FP insulating portion 32 (second insulating portion), a first connection portion 41, and an insulating layer 51. In the semiconductor device 100, the first conductivity type is n-type, and the second conductivity type is p-type. In FIG. 2, the source electrode 12 and the insulating layer 51 are omitted.

[0011] In the following description of each embodiment, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the drain electrode 11 toward the source electrode 12 is defined as the first direction D1. One of the directions perpendicular to the first direction D1 is defined as the second direction D2. One of the directions intersecting the first direction D1 and the second direction D2 is defined as the third direction D3. The third direction D3 may be perpendicular to the second direction D2 or inclined with respect to the second direction D2. Also, a direction perpendicular to the first direction D1 and intersecting the second direction D2 and the third direction D3 is defined as the fourth direction D4. Also, for ease of explanation, the direction from the drain electrode 11 toward the source electrode 12 is defined as the upward direction, and the opposite direction is defined as the downward direction, but these directions are unrelated to the direction of gravity. Viewing from above is defined as a "planar view".

[0012] 1, a source electrode 12 and a gate pad 15 are provided on the upper surface of the semiconductor device 100. The source electrode 12 and the gate pad 15 are electrically isolated from each other.

[0013] 3 to 5, a drain electrode 11 is provided on the bottom surface of the semiconductor device 100. +Through the n-type drain region 28 - A shaped drift region 21 is provided. - The drift region 21 is + It is electrically connected to the drain electrode 11 via the drain region 28. - A p-type base region 22 is provided on the n-type drift region 21. + The source region 23 and p + The p-type contact region 27 is provided. + A source electrode 12 is provided on the source region 23 via an insulating layer 51. The source electrode 12 is connected to the first connection portion 41 and + The p-type base region 22 and the n-type contact region 27 are + The source region 23 is electrically connected to the source region 23 .

[0014] The gate electrode 13 is aligned with the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. As shown in Figures 2 to 5, the gate electrode 13 includes a first electrode region 13a, a second electrode region 13b, and a third electrode region 13c.

[0015] The first electrode region 13a extends along the second direction D2. The first electrode region 13a is aligned with the p-type base region 22 in the third direction D3. In the semiconductor device 100, a part of the first electrode region 13a is aligned with the n-type base region 22 in the third direction D3. - In the semiconductor device 100, a part of the first electrode region 13a is aligned with the n-type drift region 21 in the third direction D3. + The first electrode region 13a is aligned with the first source region 23. In the semiconductor device 100, a part of the first electrode region 13a is aligned with the first connection portion 41 in the third direction D3.

[0016] The second electrode region 13b extends along the third direction D3. The second electrode region 13b is aligned with the p-type base region 22 in the second direction D2. In the semiconductor device 100, a part of the second electrode region 13b is aligned with the n-type base region 22 in the second direction D2. -In the semiconductor device 100, a part of the second electrode region 13b is aligned with the n-type drift region 21 in the second direction D2. + The second electrode region 13b is aligned with the first source region 23. In the semiconductor device 100, a part of the second electrode region 13b is aligned with the first connection portion 41 in the second direction D2.

[0017] The third electrode region 13c connects the first electrode region 13a and the second electrode region 13b. The third electrode region 13c is located at the intersection of the first electrode region 13a and the second electrode region 13b. In the semiconductor device 100, the third electrode region 13c is aligned with the p-type base region 22 in the fourth direction D4. In the semiconductor device 100, a part of the third electrode region 13c is aligned with the n-type base region 22 in the fourth direction D4. - In the semiconductor device 100, a part of the third electrode region 13c is aligned with the n-type drift region 21 in the fourth direction D4. + In the semiconductor device 100, a part of the third electrode region 13c is aligned with the p + The first connecting portion 41 is aligned with the contact region 27 .

[0018] In the semiconductor device 100, the upper ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are located at the same height. The upper ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c may be located at different heights.

[0019] In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are located at the same height. The lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c may be located at different heights.

[0020] In the semiconductor device 100, the lower end of the first electrode region 13a, the lower end of the second electrode region 13b, and the lower end of the third electrode region 13c are each located higher than the lower end of the FP electrode 14. In the semiconductor device 100, the lower end of the first electrode region 13a, the lower end of the second electrode region 13b, and the lower end of the third electrode region 13c are each located higher than the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14. In Figures 3 to 5, the center position between the upper end of the FP electrode 14 and the lower end of the FP electrode 14 is indicated by a dashed line.

[0021] The gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. As shown in FIGS. 2 to 5, the gate insulating portion 31 includes a first insulating region 31a, a second insulating region 31b, and a third insulating region 31c.

[0022] The first insulating region 31a includes a first insulating portion 31a1 and a second insulating portion 31a2. The first insulating portion 31a1 is provided between the p-type base region 22 and the first electrode region 13a in the third direction D3. The second insulating portion 31a2 is provided between the n-type base region 22 and the first electrode region 13a in the first direction D1. - The second insulating portion 31a2 is provided between the drift region 21 and the first electrode region 13a. The second insulating portion 31a2 is located below the first electrode region 13a.

[0023] The second insulating region 31b includes a third insulating portion 31b1 and a fourth insulating portion 31b2. The third insulating portion 31b1 is provided between the p-type base region 22 and the second electrode region 13b in the second direction D2. The fourth insulating portion 31b2 is provided between the n-type base region 22 and the second electrode region 13b in the first direction D1. - The fourth insulating portion 31b2 is provided between the drift region 21 and the second electrode region 13b. The fourth insulating portion 31b2 is located below the second electrode region 13b.

[0024] The third insulating region 31c connects the first insulating region 31a and the second insulating region 31b. The third insulating region 31c is located at an intersection of the first insulating region 31a and the second insulating region 31b. As shown in FIG. 5, the third insulating region 31c includes a fifth insulating portion 31c1 and a sixth insulating portion 31c2. The fifth insulating portion 31c1 is provided between the p-type base region 22 and the third electrode region 13c in the fourth direction D4. The sixth insulating portion 31c2 is provided between the n-type base region 22 and the third electrode region 13c in the first direction D1. - The sixth insulating portion 31c2 is provided between the drift region 21 and the third electrode region 13c. The sixth insulating portion 31c2 is located below the third electrode region 13c.

[0025] In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are located at the same height. The lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) may be located at different heights.

[0026] In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are each located above the lower end of the FP electrode 14. In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are each located above the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14.

[0027] In the semiconductor device 100, the thickness T1 of the first insulating portion 31a1 in the third direction D3, the thickness T3 of the third insulating portion 31b1 in the second direction D2, and the thickness T5 of the fifth insulating portion 31c1 in the fourth direction D4 are all the same. The thicknesses T1, T3, and T5 may be different from each other.

[0028] In the semiconductor device 100, the thickness T2 of the second insulating portion 31a2 in the first direction D1, the thickness T4 of the fourth insulating portion 31b2 in the first direction D1, and the thickness T6 of the sixth insulating portion 31c2 in the first direction D1 are all the same. The thicknesses T2, T4, and T6 may be different from each other.

[0029] In the semiconductor device 100, thickness T2 is the same as thickness T1. Thickness T2 may be different from thickness T1. In the semiconductor device 100, thickness T4 is the same as thickness T3. Thickness T4 may be different from thickness T3. In the semiconductor device 100, thickness T6 is the same as thickness T5. Thickness T6 may be different from thickness T5.

[0030] The gate electrode 13 is electrically connected to the gate pad 15. The gate pad 15 is electrically isolated from the source electrode 12. The gate electrode 13 may be electrically connected to the gate pad 15 via a gate wiring layer (not shown).

[0031] The FP electrode 14 has n - In the semiconductor device 100, a portion of the FP electrode 14 is aligned with the p-type drift region 21 and the gate electrode 13 in the second direction D2, the third direction D3, and the fourth direction D4. A portion of the FP electrode 14 is aligned with the n-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. + The source region 23 is aligned with the source region 23 .

[0032] The FP insulating portion 32 is disposed between the FP electrode 14 and n electrodes in the second direction D2, the third direction D3, and the fourth direction D4. - In the semiconductor device 100, a portion of the FP insulation portion 32 is provided between the FP electrode 14 and the p-type drift region 21 and between the FP electrode 14 and the gate electrode 13. In the semiconductor device 100, a portion of the FP insulation portion 32 is provided between the FP electrode 14 and the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. A portion of the FP insulation portion 32 is provided between the FP electrode 14 and the n-type drift region 21 and between the FP electrode 14 and the gate electrode 13 in the second direction D2, the third direction D3, and the fourth direction D4. +A part of the FP insulating portion 32 is disposed between the FP electrode 14 and the n-type source region 23 in the first direction D1. - The FP electrode 14 is disposed between the first region 12 and the second region 21. The FP electrode 14 is electrically connected to the source electrode 12.

[0033] The first connection portion 41 is provided between the third insulating region 31c of the gate insulating portion 31 and the FP insulating portion 32 in the second direction D2, the third direction D3, and the fourth direction D4. + The first connection portion 41 is connected to the source electrode 12 and the p-type base region 22 (p + The contact region 27 is electrically connected to the contact area 28.

[0034] Under the sixth insulating portion 31c2 of the third insulating region 31c of the gate insulating portion 31, p + A semiconductor region 24 is provided. + The semiconductor region 24 has an n-type lattice structure in the second direction D2, the third direction D3, and the fourth direction D4. - The semiconductor device 100 includes a p + The shaped semiconductor region 24 is provided under the third insulating region 31c (sixth insulating portion 31c2) of the gate insulating portion 31, and is not provided under the first insulating region 31a (second insulating portion 31a2) or under the second insulating region 31b (fourth insulating portion 31b2).

[0035] In the semiconductor device 100, p + The lower end of the semiconductor region 24 is located above the lower end of the FP electrode 14. + The bottom end of the shaped semiconductor region 24 is located above the center between the top end of the FP electrode 14 and the bottom end of the FP electrode 14. In Fig. 5, the center position between the top end of the FP electrode 14 and the bottom end of the FP electrode 14 is indicated by a dashed dotted line.

[0036] In addition, in the semiconductor device 100, p +The semiconductor region 24 includes a first semiconductor portion 24a and a second semiconductor portion 24b. The first semiconductor portion 24a overlaps with the gate electrode 13 (third electrode region 13c) in the first direction D1. The second semiconductor portion 24b does not overlap with the gate electrode 13 (third electrode region 13c) in the first direction D1.

[0037] 2, in the semiconductor device 100, a plurality of FP electrodes 14 and FP insulating portions 32 are provided in a plan view. The FP electrodes 14 are arranged in a quadrangular shape in a plan view. The FP electrodes 14 may be arranged in a triangular shape in a plan view, for example. The gate electrode 13 is provided along a space between the plurality of FP electrodes 14.

[0038] 2, the FP electrode 14 and the FP insulating portion 32 have a circular shape in a plan view in the semiconductor device 100. The FP electrode 14 and the FP insulating portion 32 may have a polygonal shape, such as a triangle, a rectangle, or a hexagon, in a plan view.

[0039] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 11 relative to the source electrode 12, a voltage equal to or greater than the threshold is applied to the gate electrode 13. This forms a channel (inversion layer) in the p-type base region 22, turning the semiconductor device 100 on. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. When the voltage applied to the gate electrode 13 then becomes lower than the threshold, the channel in the p-type base region 22 disappears, turning the semiconductor device 100 off.

[0040] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 with respect to the source electrode 12 increases. - The potential difference between the n-type drift region 21 and the FP electrode 14 increases. - From the interface with the drift region 21, -The depletion layer spreads toward the n-type drift region 21. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage of the n-type drift region 21. - By increasing the concentration of impurities that act as donors in the drift region 21, the on-resistance of the semiconductor device 100 can be reduced.

[0041] An example of the material of each component of the semiconductor device 100 will be described. The drain electrode 11, the source electrode 12, and the gate pad 15 comprise a metal such as aluminum or copper.

[0042] n - p-type drift region 21, p-type base region 22, n + Shape source area 23, p + Semiconductor region 24, p + The n+ type contact region 27 and the n+ type drain region 28 include silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as a donor impurity. Boron can be used as an acceptor impurity.

[0043] The gate electrode 13 and the FP electrode 14 include a conductive material such as polysilicon. Impurities may be added to the conductive material.

[0044] The gate insulating portion 31, the FP insulating portion 32, and the insulating layer 51 include an insulating material. The gate insulating portion 31, the FP insulating portion 32, and the insulating layer 51 include, for example, silicon oxide or silicon nitride.

[0045] The first connection portion 41 and a second connection portion 42 described below contain a metal such as tungsten, aluminum, or copper.

[0046] The effects of the first embodiment will be described. In the semiconductor device 100, a plurality of FP electrodes 14 are provided in the second direction D2 and the third direction D3. According to this structure, the n-type FP electrodes 14 that serve as a current path are arranged more efficiently than when the FP electrodes 14 extend continuously in one direction. - The volume of the drift region 21 can be increased. This can reduce the on-resistance of the semiconductor device 100. In the semiconductor device 100, the gate electrode 13 includes a first electrode region 13a extending in the third direction D3 and a second electrode region 13b extending in the second direction D2. With this structure, channels are formed in more regions than when the gate electrode 13 extends continuously in one direction. The channel density is improved, and the on-resistance of the semiconductor device 100 is further reduced. For example, when the on-resistance of the semiconductor device 100 is reduced, the current density flowing through the semiconductor device 100 can be improved. The improvement in current density allows the semiconductor device 100 to be miniaturized. Alternatively, the number of semiconductor devices 100 required to pass a predetermined current can be reduced.

[0047] In the semiconductor device 100, as shown in FIG. 5, a p + The gate electrode 13 and the drain electrode 11 are provided with a shaped semiconductor region 24. This can reduce the electric field under the third electrode region 13c. In addition, the extraction of holes is promoted, and the avalanche resistance under the third electrode region 13c can be improved. In addition, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced.

[0048] Also, p + The p-type semiconductor region 24 includes a first semiconductor portion 24a overlapping with the gate electrode 13 (third electrode region 13c) in the first direction D1 and a second semiconductor portion 24b not overlapping with the gate electrode 13 (third electrode region 13c) in the first direction D1, so that the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 can be reduced. Also, the hole current path of the avalanche breakdown can be enlarged. Also, holes flowing from the trench side during avalanche breakdown can be removed with low resistance to the first connection portion 41 and the second connection portion 42 (trench contact). This makes it difficult for a parasitic bipolar due to a potential rise in the p-type base region 22 to turn on, improving the avalanche resistance.

[0049] Also, p + By positioning the lower end of the shaped semiconductor region 24 higher than the lower end of the FP electrode 14, the depletion layer is prevented from spreading too far toward the substrate side more than necessary, and, for example, it is possible to prevent the depletion layer from connecting with the substrate during avalanche breakdown (punch-through).

[0050] (First Modification) FIG. 6 is a cross-sectional view illustrating a portion of a semiconductor device according to a first modification of the first embodiment. FIG. 6 shows a cross section taken along line VV in FIG. As shown in FIG. 6, in the semiconductor device 100A according to the first modification of the first embodiment, p + The shape of the semiconductor region 24 is different from that of the semiconductor device 100. Other than that, the semiconductor device 100 is the same as the semiconductor device 100.

[0051] In the semiconductor device 100A, p + The gate semiconductor region 24 includes a third semiconductor portion 24c and a fourth semiconductor portion 24d. The third semiconductor portion 24c contacts the third insulating region 31c of the gate insulating portion 31. The fourth semiconductor portion 24d is provided below the third semiconductor portion 24c. In the semiconductor device 100A, the fourth semiconductor portion 24d is separated from the third semiconductor portion 24c. In the semiconductor device 100A, a plurality of fourth semiconductor portions 24d are provided. The plurality of fourth semiconductor portions 24d are aligned in the first direction D1. The plurality of fourth semiconductor portions 24d are separated from each other. There may be only one fourth semiconductor portion 24d.

[0052] In the semiconductor device 100A, p + The lower end of the semiconductor region 24 is located above the lower end of the FP electrode 14. + The lower end of the shaped semiconductor region 24 is located below the center between the upper end and the lower end of the FP electrode 14. In Fig. 6, the position of the center between the upper end and the lower end of the FP electrode 14 is indicated by a dashed dotted line.

[0053] p +Since the dot semiconductor region 24 includes the third semiconductor portion 24c in contact with the third insulating region 31c and the fourth semiconductor portion 24d provided below the third semiconductor portion 24c, the distance between the FP electrodes 14 is long in the dot FP structure, and the electric field in the fourth direction D4 where charge balance is not achieved in the second direction D2 and the third direction D3 can be alleviated. This improves the breakdown voltage, which is the rate-limiting factor in the fourth direction D4. The improved breakdown voltage allows the n - The concentration of impurities acting as donors in the drift region 21 can be increased, and the on-resistance (Ron) can be reduced. + The semiconductor region 24 can be formed in multiple stages. This allows the electric field to be relaxed while the n - This can compensate for the area of ​​the depletion layer in the drift region 21, and can suppress a decrease in the breakdown voltage due to a reduction in the area of ​​the depletion layer.

[0054] (Second Modification) FIG. 7 is a cross-sectional view illustrating a portion of a semiconductor device according to a second modification of the first embodiment. FIG. 7 shows a cross section taken along line VV in FIG. As shown in FIG. 7, in the semiconductor device 100B according to the second modification of the first embodiment, p + The shape of the semiconductor region 24 is different from that of the semiconductor device 100. Other than that, the semiconductor device 100 is the same as the semiconductor device 100.

[0055] In the semiconductor device 100B, p + The gate insulating region 24 includes a third semiconductor portion 24c and a fourth semiconductor portion 24d. The third semiconductor portion 24c contacts the third insulating region 31c of the gate insulating portion 31. The fourth semiconductor portion 24d is provided below the third semiconductor portion 24c. In the semiconductor device 100B, the fourth semiconductor portion 24d contacts the third semiconductor portion 24c.

[0056] In the semiconductor device 100B, p + The lower end of the semiconductor region 24 is located above the lower end of the FP electrode 14. +The lower end of the shaped semiconductor region 24 is located below the center between the upper end and the lower end of the FP electrode 14. In Fig. 7, the position of the center between the upper end and the lower end of the FP electrode 14 is indicated by a dashed dotted line.

[0057] p + Since the dot semiconductor region 24 includes the third semiconductor portion 24c in contact with the third insulating region 31c and the fourth semiconductor portion 24d provided below the third semiconductor portion 24c, the distance between the FP electrodes 14 is long in the dot FP structure, and the electric field in the fourth direction D4 where charge balance is not achieved in the second direction D2 and the third direction D3 can be alleviated. This improves the breakdown voltage, which is the rate-limiting factor in the fourth direction D4. The improved breakdown voltage allows the n - This can increase the concentration of impurities that act as donors in the drift region 21, thereby reducing the on-resistance (Ron). In addition, since the fourth semiconductor portion 24d contacts the third semiconductor portion 24c, the area of ​​the depletion layer is reduced compared to the first modification, but the electric field in the fourth direction D4 is constant in the first direction D1 (depth direction), and the electric field is relaxed, thereby improving the breakdown voltage compared to the first modification.

[0058] (Third Modification) FIG. 8 is a cross-sectional view illustrating a portion of a semiconductor device according to a third modification of the first embodiment. FIG. 8 shows a cross section taken along line VV in FIG. As shown in FIG. 8, in the semiconductor device 100C according to the third modification of the first embodiment, p + The shape of the semiconductor region 24 is different from that of the semiconductor device 100. Other than that, the semiconductor device 100 is the same as the semiconductor device 100.

[0059] In the semiconductor device 100C, p +The shaped semiconductor region 24 includes a fifth semiconductor portion 24e and a sixth semiconductor portion 24f. The fifth semiconductor portion 24e overlaps with the gate electrode 13 (third electrode region 13c) in the fourth direction D4. The sixth semiconductor portion 24f does not overlap with the gate electrode 13 (third electrode region 13c) in the fourth direction D4. In the semiconductor device 100C, the sixth semiconductor portion 24f is in contact with the fifth semiconductor portion 24e.

[0060] In the semiconductor device 100C, p + The lower end of the shaped semiconductor region 24 is located above the lower end of the FP electrode 14. + The bottom end of the shaped semiconductor region 24 is located above the center between the top end of the FP electrode 14 and the bottom end of the FP electrode 14. In Fig. 8, the position of the center between the top end of the FP electrode 14 and the bottom end of the FP electrode 14 is indicated by a dashed dotted line.

[0061] p + The semiconductor region 24 includes a fifth semiconductor portion 24e that overlaps with the gate electrode 13 (third electrode region 13c) in the fourth direction D4 and a sixth semiconductor portion 24f that does not overlap with the gate electrode 13 (third electrode region 13c) in the fourth direction D4, so that the hole current path flowing from the gate electrode 13 side to the first connection portion 41 can be expanded and the resistance can be reduced. Also, the capacitance (Cgs) between the gate electrode 13 and the source electrode 12 can be reduced.

[0062] Second embodiment FIG. 9 is a plan view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 10 shows a cross section taken along line XX shown in FIG. The cross sections taken along lines III-III and IV-IV shown in FIG. 9 are the same as those in FIG. 3 and FIG. 4, respectively, and therefore will be omitted. 9 and 10, the semiconductor device 200 according to the second embodiment is different from the semiconductor device 100 in the shape of the gate electrode 13 (third electrode region 13c), the shape of the gate insulating portion 31 (third insulating region 31c), and the provision of the second connection portion 42. Other than that, it is the same as the semiconductor device 100.

[0063] In the semiconductor device 200, under the sixth insulating portion 31c2, + The gate electrode 13 and the drain electrode 11 are provided with a shaped semiconductor region 24. This can reduce the electric field under the third electrode region 13c. Also, the avalanche resistance under the third electrode region 13c can be improved. Also, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced.

[0064] In the semiconductor device 200, p + The p-type semiconductor region 24 includes a first semiconductor portion 24a and a second semiconductor portion 24b. This reduces the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11. Also, the hole current path of the avalanche breakdown can be enlarged. Also, holes flowing from the trench side during avalanche breakdown can be removed with low resistance to the first connection portion 41 and the second connection portion 42 (trench contact). This makes it difficult for a parasitic bipolar transistor caused by a potential rise in the p-type base region 22 to turn on, improving the avalanche resistance. + The semiconductor region 24 does not necessarily have to include the first semiconductor portion 24a and the second semiconductor portion 24b.

[0065] In the semiconductor device 200, p + The semiconductor region 24 includes a third semiconductor portion 24c and a fourth semiconductor portion 24d. + The semiconductor region 24 can be formed in multiple stages. This allows the electric field to be relaxed while the n - This can compensate for the area of ​​the depletion layer in the drift region 21, and can suppress a decrease in breakdown voltage due to a reduction in the area of ​​the depletion layer. + The semiconductor region 24 does not necessarily have to include the third semiconductor portion 24c and the fourth semiconductor portion 24d.

[0066] In the semiconductor device 200, p + The semiconductor region 24 includes a fifth semiconductor portion 24e and a sixth semiconductor portion 24f. This allows the hole current path flowing from the gate electrode 13 side to the first connection portion 41 to be expanded and the resistance to be reduced. In addition, the capacitance (Cgs) between the gate electrode 13 and the source electrode 12 can be reduced. + The semiconductor region 24 does not necessarily have to include the fifth semiconductor portion 24e and the sixth semiconductor portion 24f.

[0067] In the semiconductor device 200, p + The lower end of the shaped semiconductor region 24 is located above the lower end of the FP electrode 14. This prevents the depletion layer from spreading too far toward the substrate, and prevents the depletion layer from joining the substrate (punch-through) during avalanche breakdown, for example. + The lower end of the shaped semiconductor region 24 is located above the center between the upper end and the lower end of the FP electrode 14. In FIG. 10, the center between the upper end and the lower end of the FP electrode 14 is indicated by a dashed line. + The lower end of the semiconductor region 24 may be located at the same height as the lower end of the FP electrode 14. + The lower end of the shaped semiconductor region 24 may be located lower than the lower end of the FP electrode 14 .

[0068] In the semiconductor device 200, the lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located lower than the lower end of the second insulating portion 31a2 (first insulating region 31a). The lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located lower than the lower end of the fourth insulating portion 31b2 (second insulating region 31b). This allows the electric field under the third electrode region 13c to be relaxed. The lower end of the sixth insulating portion 31c2 (third insulating region 31c) may be located at the same height as the lower end of the second insulating portion 31a2 (first insulating region 31a). The lower end of the sixth insulating portion 31c2 (third insulating region 31c) may be located at the same height as the lower end of the fourth insulating portion 31b2 (second insulating region 31b). In the semiconductor device 200, the lower end of the second insulating portion 31a2 (first insulating region 31a) is located at the same height as the lower end of the fourth insulating portion 31b2 (second insulating region 31b). The lower end of the second insulating portion 31a2 (first insulating region 31a) may be located at a different height from the lower end of the fourth insulating portion 31b2 (second insulating region 31b).

[0069] In the semiconductor device 200, the thickness T6 is greater than the thickness T2. The thickness T6 is greater than the thickness T4. This allows the electric field under the third electrode region 13c to be relaxed. Also, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced. The thickness T6 may be the same as the thickness T2. The thickness T6 may be smaller than the thickness T2. The thickness T6 may be the same as the thickness T4. The thickness T6 may be smaller than the thickness T4. In the semiconductor device 200, the thickness T2 is the same as the thickness T4. The thickness T2 may be different from the thickness T4.

[0070] In the semiconductor device 200, the thickness T6 is greater than the thickness T5. This allows the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 to be reduced. In addition, the distance between the FP electrodes 14 is large, and the region where the effect is less effective is filled with an oxide film or the like, thereby suppressing a decrease in the breakdown voltage. The thickness T6 may be the same as the thickness T5. The thickness T6 may be smaller than the thickness T5. In the semiconductor device 200, the thickness T2 is the same as the thickness T1. The thickness T2 may be different from the thickness T1. In the semiconductor device 200, the thickness T4 is the same as the thickness T3. The thickness T4 may be different from the thickness T3. In the semiconductor device 200, the thickness T1, the thickness T3, and the thickness T5 are the same as each other. The thickness T1, the thickness T3, and the thickness T5 may be different from each other.

[0071] In the semiconductor device 200, the thickness T6 is greater than half the length L1 of the third electrode region 13c in the first direction D1. This provides effects such as reducing the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 and suppressing a decrease in breakdown voltage without making the cross-sectional area of ​​the gate electrode 13 smaller than necessary (i.e., while suppressing an excessive increase in gate resistance). The thickness T6 may be less than half the length L1. In the semiconductor device 200, the thickness T6 is less than the length L1. The thickness T6 may be the same as the length L1. The thickness T6 may be greater than the length L1.

[0072] In the semiconductor device 200, the lower end of the third electrode region 13c is located lower than the lower end of the first electrode region 13a. The lower end of the third electrode region 13c is located lower than the lower end of the second electrode region 13b. This allows the electric field under the third electrode region 13c to be relaxed. The lower end of the third electrode region 13c may be located at the same height as the lower end of the first electrode region 13a. The lower end of the third electrode region 13c may be located higher than the lower end of the first electrode region 13a. The lower end of the third electrode region 13c may be located at the same height as the lower end of the second electrode region 13b. The lower end of the third electrode region 13c may be located higher than the lower end of the second electrode region 13b. In the semiconductor device 200, the lower end of the first electrode region 13a is located at the same height as the lower end of the second electrode region 13b. The lower end of the first electrode region 13a may be located at a different height than the lower end of the second electrode region 13b.

[0073] In the semiconductor device 200, the lower end of the third electrode region 13c is located above the lower end of the FP electrode 14. This prevents the depletion layer from spreading too far toward the substrate, and prevents the depletion layer from connecting with the substrate (punch-through) during avalanche breakdown. In the semiconductor device 200, the lower end of the third electrode region 13c is located above the center between the upper end and the lower end of the FP electrode 14. The lower end of the third electrode region 13c may be located at the same height as the lower end of the FP electrode 14. The lower end of the third electrode region 13c may be located below the lower end of the FP electrode 14.

[0074] The semiconductor device 200 further includes a second connection portion 42 in addition to the first connection portion 41. The second connection portion 42 is provided between the third insulating region 31c of the gate insulating portion 31 and the first connection portion 41 in the fourth direction D4. In the first direction D1, a p-type base region 22 is provided between the second connection portion 42 and the p-type base region 22. + The second connection portion 42 is connected to the source electrode 12 and the p-type base region 22 (p +The second connection portion 42 is electrically connected to the gate electrode 13 and the drain electrode 11. This makes it possible to improve the avalanche resistance under the third electrode region 13c. Also, it is possible to reduce the capacitance between the gate electrode 13 and the drain electrode 11. The second connection portion 42 does not necessarily have to be provided.

[0075] In the semiconductor device 200, the second connection portion 42 contacts the third insulating region 31c. The upper end of the third electrode region 13c is located lower than the lower end of the second connection portion 42. This allows the thickness of the portion of the gate insulating portion 31 located between the gate electrode 13 and the second connection portion 42 connected to the source electrode 12 to be equal to or greater than the thickness of the fifth insulating portion 31c1. This makes it possible to suppress a short circuit between the gate electrode 13 and the source electrode 12.

[0076] The second connection portion 42 may be separated from the third insulating region 31c. In this case, it is preferable that the upper end of the third electrode region 13c is located higher than the lower end of the second connection portion 42. This makes it possible to shorten the current path of holes during avalanche breakdown, and effectively suppress the increase in potential of the p-type base region 22 due to the hole current (turning on of the parasitic bipolar).

[0077] In the semiconductor device 200, the upper end of the third electrode region 13c is located lower than the lower end of the second connection portion 42, and the lower end of the third electrode region 13c is located lower than the lower end of the first electrode region 13a. This makes it possible to prevent a short circuit between the gate electrode 13 and the source electrode 12, while preventing the cross-sectional area of ​​the gate electrode 13 from becoming too small (i.e., the gate resistance from becoming too large).

[0078] In the semiconductor device 200, the lower end of the first connection portion 41 is located at the same height as the lower end of the second connection portion 42. The lower end of the first connection portion 41 may be located higher than the lower end of the second connection portion 42, or may be located lower than the lower end of the second connection portion 42.

[0079] In the semiconductor device 200, the lower end of the first connection portion 41 and the lower end of the second connection portion 42 are located above the lower end of the p-type base region 22. The lower end of the second connection portion 42 may be located below the lower end of the p-type base region 22. + Since the p-type semiconductor region 24 is provided, for example, when the lower end of the second connection portion 42 is located lower than the lower end of the p-type base region 22, the avalanche resistance can be further improved while suppressing leakage between the source electrode 12 and the drain electrode 11.

[0080] In the semiconductor device 200, the second connection portion 42 does not extend along the second direction D2 and the third direction D3. The second connection portion 42 may extend along the second direction D2 and the third direction D3. The second connection portion 42 may be L-shaped having a portion along the first electrode region 13a of the gate electrode 13 and a portion along the second electrode region 13b.

[0081] (1st manufacturing method) 11(a) to 11(e) are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. As shown in Fig. 11(a) to Fig. 11(e), the first manufacturing method includes the first to fifth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. Fig. 11(a) corresponds to the first step. Fig. 11(b) corresponds to the second step. Fig. 11(c) corresponds to the third step. Fig. 11(d) corresponds to the fourth step. Fig. 11(e) corresponds to the fifth step. Each step will be described below.

[0082] As shown in FIG. 11(a), in the first step, trenches 65 are formed in a semiconductor region 61a of a first conductivity type (for example, n-type). FIGS. 11(a) to 11(e) show positions of intersections of the trenches 65. The semiconductor region 61a is - This corresponds to the shaped drift region 21. The trench 65 is formed by, for example, etching or the like.

[0083] 11(b), in the second step, an insulating region 62a is formed inside the trench 65 and on the semiconductor region 61a. The insulating region 62a corresponds to the above-mentioned gate insulating portion 31 (third insulating region 31c). The insulating region 62a is formed by, for example, thermal oxidation or CVD (Chemical Vapor Deposition).

[0084] 11C, in the third step, a semiconductor region 61b of a second conductivity type (for example, p-type) is formed under the trench 65. The semiconductor region 61b is + This corresponds to the semiconductor region 24. The semiconductor region 61b is formed by, for example, injecting impurities including boron (B), BF2, and at least one of them into the semiconductor region 61a.

[0085] As shown in FIG. 11(d), in the fourth step, first, a conductive region 63a is formed inside the trench 65 in which the insulating region 62a is formed. The conductive region 63a corresponds to the above-mentioned gate electrode 13 (third electrode region 13c). The conductive region 63a is formed, for example, by depositing a metal such as polysilicon or tungsten (W). The polysilicon may be undoped or may be doped with impurities. In the fourth step, next, an insulating region 62b is formed on the conductive region 63a. The insulating region 62b corresponds to the above-mentioned insulating layer 51. The insulating region 62b is formed, for example, by thermal oxidation or CVD. The insulating region 62b may be formed, for example, by oxidizing a part of the conductive region 63a by an annealing step during the formation of the conductive region 63a.

[0086] 11(e), in the fifth step, a semiconductor region 61c of a second conductivity type (e.g., p-type) is formed on the upper part of the semiconductor region 61a. The semiconductor region 61c corresponds to the above-mentioned p-type base region 22. The semiconductor region 61c is formed by, for example, injecting impurities including boron (B), BF2, and at least one of them into the semiconductor region 61a.

[0087] According to the first manufacturing method, the p + Therefore, a semiconductor device that can reduce an electric field can be easily manufactured.

[0088] (Second manufacturing method) 12(a) to 12(h) are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. As shown in Fig. 12(a) to Fig. 12(h), the second manufacturing method includes the first to eighth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. The sixth step is performed after the fifth step. The seventh step is performed after the sixth step. The eighth step is performed after the seventh step. Fig. 12(a) corresponds to the first step. Fig. 12(b) corresponds to the second step. Fig. 12(c) corresponds to the third step. Fig. 12(d) corresponds to the fourth step. Fig. 12(e) corresponds to the fifth step. Fig. 12(f) corresponds to the sixth step. Fig. 12(g) corresponds to the seventh step. Fig. 12(h) corresponds to the eighth step. Each step will be described below.

[0089] As shown in FIG. 12(a), in the first step, trenches 75 are formed in a semiconductor region 71a of a first conductivity type (for example, n-type). FIGS. 12(a) to 12(h) show positions of intersections of the trenches 75. The semiconductor region 71a is - The trench 75 corresponds to the drift region 21. The trench 75 is formed by, for example, etching.

[0090] 12(b), in the second step, a semiconductor region 71b of a second conductivity type (e.g., p-type) is formed under the trench 75. The semiconductor region 71b is formed by, for example, injecting impurities including boron (B), BF2, and at least one of them into the semiconductor region 71a.

[0091] 12(c), in the third step, the semiconductor region 71b is changed to an insulating region 72a, and the insulating region 72b is formed inside the trench 75 and on the semiconductor region 71a. The insulating region 72a and the insulating region 72b correspond to the above-mentioned gate insulating portion 31 (third insulating region 31c). The insulating region 72a and the insulating region 72b are formed by, for example, enhanced oxidation.

[0092] 12(d), in the fourth step, a semiconductor region 71c and a semiconductor region 71d of a second conductivity type (for example, p-type) are formed under the insulating region 72a. + The semiconductor region 71c corresponds to the semiconductor region 24. The semiconductor region 71c and the semiconductor region 71d are formed by, for example, injecting impurities including boron (B), BF2, and at least one of them into the semiconductor region 71a.

[0093] As shown in FIG. 12(e), in the fifth step, first, a conductive region 73a is formed inside the trench 75 in which the insulating region 72b is formed. The conductive region 73a corresponds to the above-mentioned gate electrode 13 (third electrode region 13c). The conductive region 73a is formed, for example, by embedding polysilicon or a metal such as tungsten (W). The polysilicon may be undoped or may be doped with impurities. An insulating region 72c is formed on the conductive region 73a by oxidizing a part of the conductive region 73a by an annealing step during the formation of the conductive region 73a.

[0094] 12(f), in the sixth step, first, the insulating region 72b formed on the semiconductor region 71a and the insulating region 72c formed on the conductive region 73a are removed. The insulating region 72b and the insulating region 72c are removed by, for example, CMP (Chemical Mechanical Polishing) or etching. The etching is, for example, CDE (Chemical Dry Etching). In the sixth step, next, a part (upper part) of the conductive region 73a is removed to form a via 76. The via 76 is formed by, for example, etching.

[0095] As shown in FIG. 12(g), in the seventh step, first, an insulating region 72d is formed inside the via 76, and an insulating region 72e is formed on the insulating region 72d and the semiconductor region 71a. The insulating region 72d corresponds to the above-mentioned gate insulating section 31 (third insulating region 31c). The insulating region 72e corresponds to the above-mentioned insulating layer 51. The insulating region 72d and the insulating region 72e are formed by, for example, thermal oxidation or CVD. In the seventh step, next, a semiconductor region 71e of a second conductivity type (for example, p-type) is formed on the upper part of the semiconductor region 71a. The semiconductor region 71e corresponds to the above-mentioned p-type base region 22. The semiconductor region 71e is formed by, for example, injecting boron (B), BF2, and impurities including at least one of them into the semiconductor region 71a.

[0096] As shown in FIG. 12(h), in the eighth step, first, conductive regions 73b are formed on both sides of a portion of the insulating region 72d that is located on the conductive region 73a. The conductive region 73b corresponds to the above-mentioned second connection portion 42. The conductive region 73b is formed, for example, by CVD embedding of tungsten (W) or sputtering of a barrier metal. In the eighth step, next, a conductive region 73c is formed on the insulating region 72e and the conductive region 73b. The conductive region 73c corresponds to the above-mentioned source electrode 12. The conductive region 73c is formed, for example, by deposition of a metal such as aluminum (Al).

[0097] According to the second manufacturing method, p + It is possible to easily manufacture a semiconductor device in which a shaped semiconductor region 24 is provided, the lower end of the third insulating region 31c (sixth insulating portion 31c2) of the gate insulating portion 31 is located lower than the lower end of the first insulating region 31a (second insulating portion 31a2) and the lower end of the second insulating region 31b (fourth insulating portion 31b2), and the second connecting portion 42 is provided on the side of the third insulating region 31c of the gate insulating portion 31. Therefore, it is possible to easily manufacture a semiconductor device that can relax the electric field.

[0098] The embodiment may include the following features.

[0099] (Configuration 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a first electrode region extending along a second direction perpendicular to a first direction from the first electrode toward the second electrode and aligned with the second semiconductor region in a third direction perpendicular to the first direction and intersecting the second direction; a second electrode region extending along the third direction and aligned with the second semiconductor region in the second direction; a third electrode region connecting the first electrode region and the second electrode region; A third electrode including a first insulating region including a first insulating portion provided between the second semiconductor region and the first electrode region in the third direction and a second insulating portion provided between the first semiconductor region and the first electrode region in the first direction; a second insulating region including a third insulating portion provided between the second semiconductor region and the second electrode region in the second direction and a fourth insulating portion provided between the first semiconductor region and the second electrode region in the first direction; a third insulating region that connects the first insulating region and the second insulating region, and includes a fifth insulating portion that is provided between the second semiconductor region and the third electrode region in a fourth direction that is perpendicular to the first direction and intersects the second direction and the third direction, and a sixth insulating portion that is provided between the first semiconductor region and the third electrode region in the first direction; A first insulating portion including: a fourth electrode aligned with the first semiconductor region and the third electrode in the second direction and the third direction; a second insulating portion provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction; a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion; A semiconductor device comprising:

[0100] (Configuration 2) 2. The semiconductor device according to claim 1, wherein the fourth semiconductor region includes a first semiconductor portion that overlaps with the third electrode in the first direction and a second semiconductor portion that does not overlap with the third electrode in the first direction.

[0101] (Configuration 3) 3. The semiconductor device according to claim 1, wherein the fourth semiconductor region includes a third semiconductor portion in contact with the third insulating region and a fourth semiconductor portion provided below the third semiconductor portion.

[0102] (Configuration 4) The semiconductor device according to any one of configurations 1 to 3, wherein the fourth semiconductor region includes a fifth semiconductor portion that overlaps with the third electrode in the fourth direction, and a sixth semiconductor portion that does not overlap with the third electrode in the fourth direction.

[0103] (Configuration 5) 5. The semiconductor device according to any one of configurations 1 to 4, wherein a lower end of the fourth semiconductor region is located higher than a lower end of the fourth electrode.

[0104] (Configuration 6) 6. The semiconductor device according to any one of configurations 1 to 5, wherein a lower end of the sixth insulating portion is located lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion.

[0105] (Configuration 7) a first connection portion provided between the third insulating region and the second insulating portion in the second direction and the third direction, the first connection portion electrically connecting the second electrode and the second semiconductor region; a second connection portion provided between the third insulating region and the first connection portion in the fourth direction and electrically connecting the second electrode and the second semiconductor region; The semiconductor device according to any one of configurations 1 to 6, further comprising:

[0106] As described above, according to the embodiment, a semiconductor device capable of reducing an electric field can be provided.

[0107] Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0108] 11: Drain electrode (first electrode) 12: Source electrode (second electrode) 13: Gate electrode (third electrode) 13a: 1st electrode area 13b: Second electrode area 13c: 3rd electrode area 14:FP electrode (4th electrode) 15: Gate Pad 21:n - Drift region (first semiconductor region) 22: p-type base region (second semiconductor region) 23:n + Source region (third semiconductor region) 24:p + Semiconductor region (fourth semiconductor region) 24a: first semiconductor portion 24b: second semiconductor portion 24c: Third semiconductor part 24d: Fourth semiconductor part 24e: 5th semiconductor part 24f: 6th semiconductor part 27:p + Contact area 28:n + Shaped drain region 31: Gate insulation part (first insulation part) 31a: First insulating region 31a1: First insulating part 31a2: Second insulating part 31b: second insulating region 31b1: Third insulating part 31b2: 4th insulating part 31c: Third insulating region 31c1: 5th insulating part 31c2: 6th insulating part 32: FP insulation part (second insulation part) 41: First connection part 42: Second connection part 51: Insulating layer 61a, 61b, 61c: semiconductor regions 62a, 62b: Insulation area 63a: Conductive area 65: Trench 71a, 71b, 71c, 71d, 71e: semiconductor regions 72a, 72b, 72c, 72d, 72e: Insulation area 73a, 73b, 73c: conductive area 75: Trench 76: Beer 100, 100A, 100B, 100C, 200: Semiconductor device

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; a first electrode region extending along a second direction perpendicular to a first direction from the first electrode toward the second electrode and aligned with the second semiconductor region in a third direction perpendicular to the first direction and intersecting the second direction; a second electrode region extending along the third direction and aligned with the second semiconductor region in the second direction; a third electrode region connecting the first electrode region and the second electrode region; A third electrode including a first insulating region including a first insulating portion provided between the second semiconductor region and the first electrode region in the third direction and a second insulating portion provided between the first semiconductor region and the first electrode region in the first direction; a second insulating region including a third insulating portion provided between the second semiconductor region and the second electrode region in the second direction and a fourth insulating portion provided between the first semiconductor region and the second electrode region in the first direction; a third insulating region that connects the first insulating region and the second insulating region, and includes a fifth insulating portion that is provided between the second semiconductor region and the third electrode region in a fourth direction that is perpendicular to the first direction and intersects the second direction and the third direction, and a sixth insulating portion that is provided between the first semiconductor region and the third electrode region in the first direction; A first insulating portion including: a fourth electrode aligned with the first semiconductor region and the third electrode in the second direction and the third direction; a second insulating portion provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction; a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion; A semiconductor device comprising:

2. 2 . The semiconductor device according to claim 1 , wherein the fourth semiconductor region includes a first semiconductor portion that overlaps with the third electrode in the first direction, and a second semiconductor portion that does not overlap with the third electrode in the first direction.

3. 2 . The semiconductor device according to claim 1 , wherein said fourth semiconductor region includes a third semiconductor portion in contact with said third insulating region, and a fourth semiconductor portion provided below said third semiconductor portion.

4. 2 . The semiconductor device according to claim 1 , wherein the fourth semiconductor region includes a fifth semiconductor portion overlapping with the third electrode in the fourth direction, and a sixth semiconductor portion not overlapping with the third electrode in the fourth direction.

5. The semiconductor device according to claim 1 , wherein a lower end of said fourth semiconductor region is located higher than a lower end of said fourth electrode.

6. 6. The semiconductor device according to claim 1, wherein a lower end of said sixth insulating portion is located lower than a lower end of said second insulating portion and a lower end of said fourth insulating portion.

7. a first connection portion provided between the third insulating region and the second insulating portion in the second direction and the third direction, the first connection portion electrically connecting the second electrode and the second semiconductor region; a second connection portion provided between the third insulating region and the first connection portion in the fourth direction and electrically connecting the second electrode and the second semiconductor region; The semiconductor device according to claim 1, further comprising:

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