Multi value magnetic memory element, magnetic memory device, method for controlling multi value magnetic memory element and control program

Abstract

To provide a multi value magnetic memory element that can realize multi bit memory with a simple circuit configuration.SOLUTION: In a multi value magnetic memory element (11), when a first current with an average current value equal to or greater than the first threshold value and less than the second threshold value flows, a magnetic domain having the same magnetization direction as that of the magnetic domain on the side of the other end (27) of a magnetic fine wire (22) is written into the magnetic fine wire, and when a second current with an average current value equal to or greater than the second threshold value flows, a magnetic domain with a magnetization direction different from that of the magnetic domain on the side of the other end of the magnetic fine wire is written into the magnetic fine wire.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multi-valued magnetic memory element including a nanoscale magnetic structure, a magnetic memory device, a control method for a multi-valued magnetic memory element, and a control program. [Background technology]

[0002] Conventionally, from the viewpoint of reducing power consumption or operating without failure in adverse environments with a lot of vibration, development of non-volatile memories that do not require power to retain stored data has been promoted. Non-volatile memories that utilize magnetism include magnetic memories such as MRAM (Magnetoresistive Random Access Memory), which is a single-bit memory, and racetrack memory or vertical columnar memory, which are multi-value memories.

[0003] The magnetic memory includes a layer or region with a variable magnetization direction as a data storage region. Data is written by utilizing the property that the magnetization direction changes by injecting spins into the storage region. The magnetic memory also includes a non-magnetic layer and a fixed layer (pinned layer) that maintains a predetermined magnetization direction in addition to the storage region. The storage region, the non-magnetic layer, and the fixed layer form a magnetic resistance effect (MR) element. Data is read and written by utilizing the property that the electrical resistance of the MR element changes depending on the magnetization direction of the storage region. In the racetrack memory, the long data storage region and the MR element are arranged perpendicular to each other. The racetrack memory includes wiring with four or more terminals for operation (moving, writing, and reading data). In the vertical pillar memory, the MR element is provided at one end of the long data storage region. In the vertical pillar memory, non-magnetic metal wiring is provided at the other end of the long data storage region for writing data. The vertical pillar memory includes wiring with three terminals for operation (moving, writing, and reading data).

[0004] Non-Patent Document 1 discloses a racetrack memory with four-terminal wiring. Non-Patent Document 2 and Patent Document 1 disclose a vertical columnar memory with three-terminal wiring. Patent Document 2 discloses a memory with three-terminal wiring.

[0005] Patent Documents 2 and 3 disclose an MR element including a free layer (the above-mentioned storage region), a fixed layer, and an insulating layer (the above-mentioned nonmagnetic layer) formed between the free layer and the fixed layer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2022-59441 [Patent Document 2] International Publication No. 2009 / 057504 [Patent Document 3] Special Publication No. 2018-530097 [Non-patent literature]

[0007] [Non-Patent Document 1] SSP Parkin, M. Hayashi, L. Thomas, “Magnetic Domain-Wall Racetrack Memory” Science, Vol 320, Issue 5873, pp. 190-194 (2008) [Non-Patent Document 2] YM Hung, T. Li, R. Hisatomi, Y. Shiota, T. Moriyama, T. Ono, “Low Current Driven Vertical Domain Wall Motion Memory with an Artificial Ferromagnet” Journal of the Magnetics Society of Japan, Volume 45, Issue 1, Pages 6-11 (2021) Summary of the Invention [Problem to be solved by the invention]

[0008] Typically, in the multi-value magnetic memory element as described above, in order to inject two types of spins into the storage area, the element is connected to a controller via three terminals. Since it is necessary to connect the three terminals of the multiple multi-value magnetic memory elements to the controller, there is a problem that the circuit design of the memory device becomes complicated. In addition, in the configurations described in Non-Patent Documents 1 and 2 and Patent Documents 1, 2, and 3, in order to inject two types of spins into the storage area, it is necessary to change the direction of the current flow. In such a case, there is also a problem that the circuit design of the memory device becomes complicated. Furthermore, the configurations described in Patent Documents 2 and 3 are limited to single-bit memories.

[0009] An object of one embodiment of the present invention is to provide a multi-value magnetic memory element that can realize a multi-bit memory with a simple circuit configuration. [Means for solving the problem]

[0010] In order to solve the above problems, a multi-valued magnetic memory element according to a first aspect of the present invention is a magnetic nanowire capable of writing a plurality of magnetic domains corresponding to a plurality of bits, each of the plurality of magnetic domains having magnetization in a direction substantially parallel to the extension direction of the magnetic nanowire, a fixed layer having magnetization in a direction substantially parallel to the extension direction of the magnetic nanowire, a non-magnetic first intermediate layer disposed between one end of the magnetic nanowire and the fixed layer, and a non-magnetic second intermediate layer electrically connected to the other end of the magnetic nanowire and having a magnetization substantially parallel to the magnetization of the magnetic nanowire. and an in-plane magnetization layer having perpendicular magnetization, wherein when a first current having an average current value greater than or equal to a first threshold and less than a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having the same magnetization direction as the magnetic domain on the other end of the magnetic nanowire is written into the magnetic nanowire, and when a second current having an average current value greater than or equal to a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end of the magnetic nanowire is written into the magnetic nanowire.

[0011] In order to solve the above problems, a multi-valued magnetic memory element according to a second aspect of the present invention comprises a magnetic nanowire capable of writing a plurality of magnetic domains corresponding to a plurality of bits, a fixed layer, a first intermediate layer disposed between one end of the magnetic nanowire and the fixed layer, and an in-plane magnetized layer electrically connected to the other end of the magnetic nanowire, wherein the magnetic nanowire has an easy axis of magnetization in an extension direction, the fixed layer has an easy axis of magnetization in a thickness direction, the in-plane magnetized layer has an easy axis of magnetization in an in-plane direction, and the other end of the magnetic nanowire has a magnetic easy axis in the extension direction. When a first current having an average current value greater than or equal to a first threshold and less than a second threshold flows from the magnetic nanowire to the in-plane magnetization layer with the in-plane magnetization layer being magnetized in the in-plane direction, a magnetic domain having the same magnetization direction as the magnetic domain on the other end of the magnetic nanowire is written into the magnetic nanowire, and when a second current having an average current value greater than or equal to a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end of the magnetic nanowire is written into the magnetic nanowire.

[0012] According to the above configuration, by controlling the magnitude of the current flowing from the magnetic nanowire to the in-plane magnetization layer, it is possible to write a magnetic domain having an upward magnetization direction or a magnetic domain having a downward magnetization direction in the magnetic nanowire. According to the configuration in which the bits to be written are switched by controlling the magnitude of the current, it is possible to realize writing and reading of multiple bits while keeping the connection terminals of the multi-valued magnetic memory element to two terminals. Furthermore, since it is not necessary to change the direction of the current flowing in the multi-valued magnetic memory element, it is easy to control the current by the controller. Therefore, a multi-bit memory can be realized with a simple circuit configuration.

[0013] The multi-valued magnetic memory element according to a third aspect of the present invention may be configured in such a manner that, in the first or second aspect, it further comprises a non-magnetic second intermediate layer disposed between the other end of the magnetic nanowire and the in-plane magnetization layer.

[0014] In a multi-valued magnetic memory element according to a fourth aspect of the present invention, in any one of the first to third aspects, at least one of the first current and the second current may be a constant current.

[0015] In a multi-valued magnetic memory element according to a fifth aspect of the present invention, in any one of the first to third aspects, at least one of the first current and the second current may be a pulse current.

[0016] A magnetic memory device according to a sixth aspect of the present invention comprises a multi-valued magnetic memory element according to any one of the first to fifth aspects, and a controller which, during writing, writes a magnetic domain in the magnetic nanowire by passing the first current or the second current from the magnetic nanowire to the in-plane magnetization layer.

[0017] In a magnetic memory device according to aspect 7 of the present invention, in accordance with aspect 6 above, the device further comprises a first wiring which is a path through which the first current and the second current flow from the controller to the multi-value magnetic memory element, and a second wiring which is a path through which the first current and the second current flow from the multi-value magnetic memory element to the controller, and the controller may, during reading, read a bit corresponding to the magnetization direction of the magnetic domain on the one end side of the magnetic nanowire by passing a third current through the first intermediate layer via the first wiring and the second wiring.

[0018] In a magnetic memory device according to aspect 8 of the present invention, in aspect 6 or 7 above, the controller may write at least one bit less than the number of magnetic domains of the magnetic nanowire by flowing the first current or the second current for a predetermined period of time before writing the write data.

[0019] In a magnetic memory device according to aspect 9 of the present invention, in aspect 6 or 7 above, the magnetic nanowire may have magnetic domains one more than the number of bits of the write data, and the controller may write a reference bit indicating the last bit of the write data into the magnetic domain on the one end side of the magnetic nanowire.

[0020] In a magnetic memory device according to aspect 10 of the present invention, in aspect 6 or 7 above, the magnetic nanowire may have magnetic domains one more than the number of bits of write data, and the controller may write a dummy bit, which is a predetermined bit, into the magnetic domain on the other end of the magnetic nanowire.

[0021] In a magnetic memory device according to aspect 11 of the present invention, in aspect 6 or 7 above, the magnetic nanowire has a number of magnetic domains that is one more than the number of bits of write data, and when writing a first value, the controller writes a magnetic domain into the magnetic nanowire having the same magnetization direction as the magnetic domain at the other end of the magnetic nanowire, and when writing a second value different from the first bit, the controller writes a magnetic domain into the magnetic nanowire having a magnetization direction different from the magnetization direction of the magnetic domain at the other end of the magnetic nanowire.

[0022] In a magnetic memory device according to aspect 12 of the present invention, in aspects 6 to 11 above, the controller may include a latch circuit that reads out a bit corresponding to the magnetization direction of the magnetic domain on the one end side of the magnetic nanowire, and a pulse gate that generates a pulse current which is the first current or the second current in accordance with write data.

[0023] In a magnetic memory device according to aspect 13 of the present invention, in any of aspects 6 to 11 above, the controller may include a latch circuit that reads out a bit corresponding to the magnetization direction of the magnetic domain at the one end of the magnetic nanowire, a high-voltage side gate connected to a high-voltage source, and a low-voltage side gate connected to a low-voltage source.

[0024] In a magnetic memory device according to aspect 14 of the present invention, in accordance with aspects 6 to 13 above, the multi-value magnetic memory element includes a first multi-value magnetic memory element in which the upstream wiring is connected to one end side of the magnetic nanowire, and a second multi-value magnetic memory element in which the upstream wiring is connected to the other end side of the magnetic nanowire, and in the multi-value magnetic memory element, when a current flows from the in-plane magnetization layer to the magnetic nanowire, the magnetic domains do not have to move.

[0025] A NAND flash memory according to a fifteenth aspect of the present invention includes the multi-valued magnetic memory element according to any one of the first to fifth aspects.

[0026] A solid state drive device according to aspect 16 of the present invention comprises an SSD controller and one or more NAND flash memories, at least one of which is the NAND flash memory according to aspect 15 above.

[0027] A solid state drive device according to a seventeenth aspect of the present invention includes an SSD controller and one or more NAND flash memories, the SSD controller including a multi-valued magnetic memory element according to any one of the first to fifth aspects.

[0028] In order to solve the above problem, a control method for a multi-value magnetic memory element according to an eighteenth aspect of the present invention is a control method for a multi-value magnetic memory element comprising: a magnetic nanowire capable of writing multiple magnetic domains corresponding to multiple bits, each of the multiple magnetic domains having a magnetization in a direction approximately parallel to the extension direction of the magnetic nanowire; a fixed layer having a magnetization in a direction approximately parallel to the extension direction of the magnetic nanowire; a non-magnetic first intermediate layer arranged between one end of the magnetic nanowire and the fixed layer; and an in-plane magnetization layer electrically connected to the other end of the magnetic nanowire and having magnetization approximately perpendicular to the magnetization of the magnetic nanowire, wherein, during writing, a first current having an average current value greater than or equal to a first threshold and less than a second threshold, or a second current having an average current value greater than or equal to the second threshold, is passed from the magnetic nanowire to the in-plane magnetization layer to write the magnetic domains in the magnetic nanowire.

[0029] The controller of the magnetic memory device according to each aspect of the present invention may be realized by a computer. In this case, the control program of the controller that realizes the controller on a computer by causing the computer to operate as each part (software element) of the controller, and the computer-readable recording medium on which it is recorded, also fall within the scope of the present invention. Effect of the Invention

[0030] According to one aspect of the present invention, a multi-bit memory can be realized with a simple circuit configuration. [Brief description of the drawings]

[0031] [Figure 1] 1 is a perspective view showing a schematic configuration of a magnetic memory device according to an embodiment; [Diagram 2] 2 is a block diagram showing a schematic configuration of a controller in the magnetic memory device. [Diagram 3] FIG. 2 is a diagram illustrating a schematic diagram of a state in which a new magnetic domain is written in a multi-valued magnetic memory element by passing a first current. [Figure 4] FIG. 13 is a diagram illustrating a schematic diagram of a state in which a new magnetic domain is written in a multi-valued magnetic memory element by passing a second current. [Diagram 5] FIG. 13 is a diagram showing current control by a current control unit when writing using a constant current. [Figure 6] FIG. 13 is a diagram showing current control by a current control unit when writing using a pulse current and a constant current. [Figure 7] FIG. 10 is a diagram showing an example of a result of simulating the writing of a new magnetic domain in a multi-level magnetic memory element. [Figure 8] 11A and 11B are diagrams showing another example of the results of simulating the writing of new magnetic domains in a multi-level magnetic memory element. [Figure 9] FIG. 11 is a diagram illustrating an example of a method for writing write data. [Figure 10] FIG. 11 is a diagram illustrating current control in another example of a method for writing write data. [Figure 11] FIG. 11 is a diagram for explaining a magnetic memory device corresponding to FIG. [Figure 12] FIG. 11 is a diagram showing current control in yet another example of a method for writing write data. [Figure 13] FIG. 13 is a diagram for explaining a magnetic memory device corresponding to FIG. 12. [Figure 14]FIG. 11 is a diagram showing current control in yet another example of a method for writing write data. [Figure 15] FIG. 15 is a diagram for explaining a magnetic memory device corresponding to FIG. 14. [Figure 16] FIG. 15 is a diagram illustrating a magnetic memory device showing bits similar to those of FIG. 14. [Figure 17] 1 is a perspective view showing a part of a schematic configuration of a magnetic memory device. [Figure 18] FIG. 11 is a perspective view showing a part of a schematic configuration of another example of a magnetic memory device. [Figure 19] FIG. 2 is a diagram showing an example of a circuit configuration of a controller in a magnetic memory device. [Figure 20] 20 is a graph showing a change over time in voltage at a node N1 in the circuit configuration shown in FIG. 19. [Figure 21] FIG. 13 is a diagram showing another example of a circuit configuration of a controller in a magnetic memory device. [Figure 22] FIG. 1 is a diagram showing a schematic configuration of a magnetic memory device including a plurality of multi-valued magnetic memory elements. [Diagram 23] FIG. 13 is a diagram showing a schematic configuration of another example of a magnetic memory device including a plurality of multi-valued magnetic memory elements. [Figure 24] FIG. 13 is a diagram showing a schematic configuration of yet another example of a magnetic memory device including a plurality of multi-valued magnetic memory elements. [Diagram 25] FIG. 13 is a diagram showing a schematic configuration of yet another example of a magnetic memory device including a plurality of multi-valued magnetic memory elements. [Figure 26] 1A and 1B are a front view and a top view showing a schematic structure of a 3D-NAND element to which a multi-valued magnetic memory element is applied. [Figure 27] 1A and 1B are a front view and a top view showing a schematic structure of another example of a 3D-NAND element to which a multi-valued magnetic memory element is applied. [Figure 28] FIG. 1 is a diagram showing a schematic configuration of a solid-state drive device to which a 3D-NAND element is applied. [Figure 29] FIG. 1 is a diagram showing a schematic configuration of a solid-state drive device in which the above-mentioned multi-valued magnetic memory element is applied to a controller. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] [Embodiment 1] Hereinafter, the embodiments of the present invention will be described in detail. For the sake of convenience, the same reference numerals are used for members having the same functions as those in the embodiments, and the description thereof will be omitted as appropriate. In addition, directions are specified using x, y, and z shown in the drawings.

[0033] 1 is a perspective view showing a schematic configuration of a magnetic memory device according to an embodiment. The magnetic memory device 1 includes a multi-valued magnetic memory element 11, a controller 12, a first wiring 51, and a second wiring 52. The first wiring 51 and the second wiring 52 are wirings that connect the multi-valued magnetic memory element 11 and the controller 12.

[0034] (Multi-valued magnetic memory element) The multi-value magnetic memory element 11 includes a magnetic nanowire 22, a first intermediate layer 23, a fixed layer 24, and an in-plane magnetized layer 26. The multi-value magnetic memory element 11 may include a second intermediate layer 25. The multi-value magnetic memory element 11 is a magnetic memory element capable of storing multiple bits.

[0035] The magnetic wire 22 is a magnetic body in which a plurality of magnetic domains corresponding to a plurality of bits can be written. Here, the magnetic domain is a section corresponding to one bit of information written in the magnetic wire 22. Hereinafter, the boundary of the section corresponding to one bit is referred to as a bit boundary 41. Each of the plurality of magnetic domains has magnetization in a direction substantially parallel to the extension direction of the magnetic wire 22 (the Z-axis direction in FIG. 1). In this embodiment, unless otherwise specified, a magnetic domain having an upward magnetization direction corresponds to a bit "1" which is a second value, and a magnetic domain having a downward magnetization direction corresponds to a bit "0" which is a first value. The magnetic wire 22 is a magnetic body having magnetic anisotropy. The magnetic wire 22 has an easy axis of magnetization in the extension direction of the magnetic wire 22. The magnetic wire 22 is formed as a magnetic body having an elongated shape. In FIG. 1, the magnetic wire 22 is a thin wire extending in the Z-axis direction. The magnetic wire 22 may be a columnar member. The magnetic wire 22 may be a ferromagnetic metal member. The magnetic wire 22 functions as a domain wall motion memory in which a domain wall (a boundary between sections having a certain magnetization direction) moves when a current flows through the magnetic wire 22. The memory capacity increases when the magnetic wire 22 is made longer. If the width of the magnetic wire 22 is approximately constant (if the magnetic wire 22 is columnar), the motion of the magnetic domain is stable. The width of the columnar magnetic wire 22 may change continuously and gradually (the thickness may be different at both ends).

[0036] For example, the magnetic nanowire 22 is preferably composed of a Co / Ni multilayer film, a CoNi-based alloy, a Co / Pd multilayer film, a CoPd alloy, a Co / Pt multilayer film, a CoPt alloy, an Fe / Pt multilayer film, an Fe / Pd multilayer film, an FePt alloy, an FePd alloy, a Tb / FeCo multilayer film, a TbFeCo alloy, a CoFe alloy, a CoFeB alloy, an Fe / Ni multilayer film, an FeNi alloy, an MnGa alloy, an MnAl alloy, an MnBi alloy, an MnGe alloy, a CrPt3 alloy, an MnCr / AlGe multilayer film, etc. Also, these alloys and multilayer films may be arranged in a series with a thickness of about 1 nanometer to 20 nanometers.

[0037] The cross section of the magnetic nanowire 22 can have a wide variety of cross-sectional shapes, such as a circle, an ellipse, or a polygon. The thickness (width of the cross section) of the magnetic nanowire 22 may vary within the same nanowire. However, it is desirable that the magnetic nanowire 22 has a cross-sectional shape with few corners, such as a circle, has a uniform width, and is long in the extension direction. It is preferable that the length in the extension direction is longer than the width. The number of bits of information stored in the magnetic nanowire 22 can be increased by increasing the length in the extension direction.

[0038] The first intermediate layer 23 is disposed between one end 28 of the magnetic nanowire 22 and the fixed layer 24. The first intermediate layer 23, one end 28 of the magnetic nanowire 22, and the fixed layer 24 form a magnetic tunnel junction. The first intermediate layer 23 is structurally connected to one end 28 of the magnetic nanowire 22. The first intermediate layer 23 is, for example, a thin film of a nonmagnetic insulator. For example, the first intermediate layer 23 is a layer mainly composed of an insulating material. The first intermediate layer 23 is composed of an insulating film such as MgO. Note that, as a material constituting the first intermediate layer 23, an oxide having a NaCl structure is preferable, and in addition to the above-mentioned MgO, Al2O3, CaO, SrO, TiO, VO, NbO, etc. can be mentioned, but there is no particular limitation as long as it does not impair the function of the first intermediate layer 23. As the material, for example, spinel type MgAl2O4, etc. may be used. In this embodiment, the magnetic nanowire 22, the first intermediate layer 23 which is an insulator, and the fixed layer 24 constitute a TMR (tunnel magnetoresistance) element, but the present invention is not limited to this. For example, the first intermediate layer 23 may be a thin conductor layer of a metal such as Cu. In this case, the magnetic nanowire 22, the first intermediate layer 23 which is a conductor, and the fixed layer 24 constitute a GMR (giant magnetoresistance) element. In this case, the metal constituting the first intermediate layer 23 is preferably a non-magnetic metal.

[0039] The fixed layer 24 is a layer that maintains a predetermined magnetization direction (i.e., upward or downward) in the film thickness direction (in FIG. 1, the magnetization direction is fixed to the upward direction). The fixed layer 24 is a ferromagnetic material having perpendicular magnetic anisotropy. That is, the fixed layer 24 is a layer that has magnetic anisotropy in a direction substantially parallel to the extension direction of the magnetic nanowire 22 (having magnetization in a direction substantially parallel to the extension direction of the magnetic nanowire 22). In other words, the fixed layer 24 has an easy axis of magnetization in the film thickness direction. One end of the fixed layer 24 is structurally connected to the first intermediate layer 23. The fixed layer 24 is connected to the controller 12 via a first wiring 51 connected to the fixed layer 24. For example, the fixed layer 24 may be composed of an Fe-based material such as CoFeB, CoFe, or an FePt alloy, a CoPt alloy, a Co / Pt multilayer film, a TbFeCo alloy, Cr2O3, or a combination thereof. Also, the fixed layer 24 may be configured by stacking these ferromagnetic metals and antiferromagnetic layers. The thickness of the fixed layer 24 is, for example, 1 nm or more and 10 nm or less. The fixed layer 24 preferably has a thickness equal to or greater than the spin diffusion length of the material that constitutes the fixed layer 24.

[0040] The second intermediate layer 25 is disposed between the other end 27 of the magnetic nanowire 22 and the in-plane magnetized layer 26. The second intermediate layer 25 has a function of isolating the in-plane magnetized layer 26 from the magnetic nanowire 22 so as to reduce the influence of the magnetization of the magnetic nanowire 22 on the magnetization of the in-plane magnetized layer 26 described later. The second intermediate layer 25 may be omitted as long as the thickness of the in-plane magnetized layer 26 is sufficiently large and does not interfere with the function of the in-plane magnetized layer 26 described later. However, it is preferable to form the second intermediate layer 25 in order to facilitate the separation of the magnetization of the magnetic nanowire 22 and the in-plane magnetized layer 26. The second intermediate layer 25 is a nonmagnetic thin film. The second intermediate layer 25 is preferably a nonmagnetic metal layer in order to reduce the power consumption during the operation of the magnetic memory device 1. The second intermediate layer 25 may be a nonmagnetic insulating layer. The details of the material constituting the second intermediate layer 25 may be the same as those of the first intermediate layer 23. The thickness of the second intermediate layer 25 is, for example, not less than 0.1 nm and not more than 2 nm.

[0041] The in-plane magnetization layer 26 has magnetization (on the XY plane) that is approximately perpendicular to the magnetization (in the Z-axis direction) of the magnetic nanowire 22. In the example shown in FIG. 1, the in-plane magnetization layer 26 has magnetization in the positive direction of the X-axis. The magnetization direction of the in-plane magnetization layer 26 is not limited to the positive direction of the X-axis, and may be any direction on the XY plane. The magnetization direction of the in-plane magnetization layer 26 does not need to be fixed, and may be any direction on the XY plane. The in-plane magnetization layer 26 is a layer that has magnetic anisotropy in the in-plane direction (parallel to the main surface of the in-plane magnetization layer 26 (the surface in contact with the second intermediate layer 25), and perpendicular to the direction in which each member of the multi-value magnetic memory element 11 is stacked). In other words, the in-plane magnetization layer 26 has an easy axis of magnetization in the in-plane direction. The in-plane magnetization layer 26 is electrically connected to the other end 27 of the magnetic nanowire 22 (through the second intermediate layer 25 in FIG. 1). The in-plane magnetization layer 26 is connected to the controller 12 through the second wiring 52. The in-plane magnetization layer 26 is preferably an FeCo-based material such as CoFeB or CoFe, or an FeNi-based material such as permalloy. The in-plane magnetization layer 26 may be made of the same material as the magnetic nanowire 22, or may be made of the same material as the fixed layer 24. The thickness of the in-plane magnetization layer 26 is, for example, 2 nm or more and 10 nm or less. The in-plane magnetization layer 26 preferably has a thickness of about twice the spin diffusion length of the material constituting the in-plane magnetization layer 26. The in-plane magnetization layer 26 may be a cylindrical shape having the same diameter as the magnetic nanowire 22, as shown in FIG. 1. Alternatively, the cross-sectional shape of the in-plane magnetization layer 26 may be different from the cross-sectional shape of the magnetic nanowire 22.

[0042] When a current is passed from the magnetic wire 22 to the in-plane magnetization layer 26, electrons flow from the in-plane magnetization layer 26 (through the second intermediate layer 25) to the other end 27 of the magnetic wire 22. Here, the electrons are spin polarized in the in-plane direction of the in-plane magnetization layer 26 (for example, the positive direction of the X-axis). Therefore, the magnetization direction at the other end 27 of the magnetic wire 22 is the in-plane direction of the in-plane magnetization layer 26. In other words, when a current is passed from the magnetic wire 22 to the in-plane magnetization layer 26, electrons with spins biased in the in-plane direction of the in-plane magnetization layer 26 are injected into the other end 27 of the magnetic wire 22.

[0043] When a predetermined current is applied from the magnetic nanowire 22 to the in-plane magnetized layer 26, the magnetic domains and magnetic walls move toward the one end 28 (upward) due to electrons flowing from the in-plane magnetized layer 26 to the other end 27 of the magnetic nanowire 22. Here, the predetermined current is applied when the first threshold value i th1 A current having an average current value (current value per unit time) equal to or greater than the first threshold i th1 Even if a current having an average current value less than this is passed, the multiple magnetic domains and domain walls will not move.

[0044] Furthermore, the average current value of the current flowing from the magnetic nanowire 22 to the in-plane magnetization layer 26 is equal to or lower than a predetermined second threshold i th2 (>i th1 ) or greater than a given second threshold i th2 The magnetization direction of the magnetic domain newly written by the above-mentioned spin injection is determined depending on whether the average current value of the current flowing from the magnetic nanowire 22 to the in-plane magnetization layer 26 is less than the first threshold i th1 and the second threshold i th2 When the average current value of the current flowing from the magnetic wire 22 to the in-plane magnetized layer 26 is less than the second threshold value i th2 In the above manner, a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end 27 side of the magnetic nanowire 22 is written in the magnetic nanowire 22. th1 and the second threshold i th2 varies depending on the material and structure of each portion of the multi-valued magnetic memory element 11.

[0045] (controller) The controller 12 writes and reads information to the multi-valued magnetic memory element 11. The controller 12 also moves information (magnetic domains) in the magnetic nanowire 22. When writing, the controller 12 writes a magnetic domain in the magnetic nanowire 22 by passing a current from the fixed layer 24 (i.e., from one end 28 of the magnetic nanowire 22) to the in-plane magnetized layer 26.

[0046] 2 is a block diagram showing a schematic configuration of the controller 12 in the magnetic memory device 1. The controller 12 includes a current control unit 31, a write instruction unit 34, a read instruction unit 35, and a measurement unit 36.

[0047] The current control unit 31 controls the magnitude of the current flowing from the magnetic nanowire 22 to the in-plane magnetization layer 26 and the timing of flowing the current. When writing, the current control unit 31 writes a magnetic domain in the magnetic nanowire 22 by flowing a first current I1 or a second current I2 from the magnetic nanowire 22 to the in-plane magnetization layer 26. The first current I1 or the second current I2 flows from the controller 12 to the multi-valued magnetic memory element 11 via the first wiring 51 and the second wiring 52. Here, the average current value of the second current I2 (second average current value i ave2 ) is the average current value of the first current I1 (the first average current value i ave1 ) is greater than the first average current value i ave1 is the first threshold i th1 and the second threshold i th2 is less than the second average current value i ave2 is the second threshold i th2 That is all. In detail, when writing a magnetic domain to the magnetic wire 22, the current control unit 31 acquires the magnetization direction of the magnetic domain at the other end 27 of the magnetic wire 22 at that time. When writing a magnetic domain having the same magnetization direction as the magnetic domain at the other end 27 of the magnetic wire 22 to the magnetic wire 22, the current control unit 31 passes a first current I1 through the multi-value magnetic memory element 11. When writing a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain at the other end 27 of the magnetic wire 22 to the magnetic wire 22, the current control unit 31 passes a second current I2 through the multi-value magnetic memory element 11. Hereinafter, the average current value of the current is also simply referred to as the magnitude of the current.

[0048] The write instruction unit 34 instructs the current control unit 31 to write data acquired from an external device into the multi-valued magnetic memory element 11 .

[0049] The read instruction unit 35 instructs the measurement unit 36 ​​and the current control unit 31 to read data from the multi-value magnetic memory element 11. The read instruction unit 35 specifies the magnetization direction of the magnetic domain formed on the one end 28 side of the magnetic nanowire 22 from the measurement result of the measurement unit 36, and specifies the value of the bit corresponding to the specified magnetization direction. The read instruction unit 35 also moves the multiple magnetic domains and domain walls written in the magnetic nanowire 22 to the one end 28 side (the fixed layer 24 side) by passing a predetermined third current I3 through the multi-value magnetic memory element 11. As a result of the movement of the multiple magnetic domains and domain walls, the first magnetic domain formed from the one end 28 side disappears, and the second magnetic domain formed becomes adjacent to the first intermediate layer 23. The read instruction unit 35 reads the multiple bits written in the multi-value magnetic memory element 11 by repeating the reading of the magnetization direction of the magnetic domain and the movement of the magnetic domain.

[0050] During reading, the measurement unit 36 ​​measures the resistance value of the magnetic tunnel junction (TMR element) constituted by the first intermediate layer 23, one end 28 of the magnetic nanowire 22, and the fixed layer 24 by passing a third current I3 through the magnetic tunnel junction. Here, the measurement unit 36 ​​passes the third current I3 through the first intermediate layer 23 via the first wiring 51 and the second wiring 52 (through the same path as the first current I1 and the second current I2). For example, the measurement unit 36 ​​measures the voltage applied between the fixed layer 24 and the in-plane magnetized layer 26 when a constant third current I3 flows through the TMR element. Alternatively, the measurement unit 36 ​​measures the third current I3 when a constant voltage is applied between the fixed layer 24 and the in-plane magnetized layer 26. The measurement unit 36 ​​outputs the measurement result to the read instruction unit 35. By passing the third current I3 through the same path as the first current I1 and the second current I2, a multi-valued memory can be realized with a two-terminal structure.

[0051] The measurement unit 36 ​​determines a first threshold value i th1 By passing a third current I3 having an average current value less than the first threshold i th1By passing the third current I3 having an average current value equal to or greater than this value, reading accompanied by movement of magnetic domains is possible (that is, reading accompanied by bit driving is possible).

[0052] (Write operation) FIG. 3 is a diagram showing a schematic diagram of a state where new magnetic domains are written in the multi-valued magnetic memory element 11 by passing a first current I1. FIG. 4 is a diagram showing a schematic diagram of a state where new magnetic domains are written in the multi-valued magnetic memory element 11 by passing a second current I2. Reference numerals 301 to 303 in FIG. 3 and reference numerals 401 to 403 in FIG. 4 indicate the time-dependent changes in the magnetic domains in the magnetic nanowire 22. FIG. 3 and FIG. 4 illustrate an example of the multi-valued magnetic memory element 11 in which the magnetic nanowire 22 has four magnetic domains. Hereinafter, with reference to FIG. 3 and FIG. 4, the time-dependent changes in the multiple magnetic domains written in the magnetic nanowire 22 when a new magnetic domain is written in the magnetic nanowire 22 will be described.

[0053] As shown in FIG. 3, a first average current value i ave1 When the first current I1 flows, (the first average current value i ave1 is the first threshold i th1 Since the magnetic nanowire 22 has four magnetic domains and a magnetic wall 29, the magnetic nanowire 22 moves toward the one end 28. ave1 When the first current I1 flows for a first predetermined time (determined according to), the first magnetic domain formed from the one end 28 side before the first current I1 flows disappears, and the second to fourth magnetic domains formed from the one end 28 side move by one bit toward the one end 28 side. Also, a first average current value i ave1 When the first current I1 flows, (the first average current value i ave1 is the first threshold i th1 and the second threshold i th2 is less than the first current I1), a magnetic domain having the same magnetization direction as the magnetic domain at the other end 27 of the magnetic wire 22 is written in the magnetic wire 22. In the example shown in Fig. 3, a magnetic domain having a new upward magnetization direction is written in the other end 27 of the magnetic wire 22 so as to maintain the upward magnetization direction of the magnetic domain formed at the other end 27 before the first current I1 is passed.

[0054] As shown in FIG. 4, a second average current value i ave2 When the second current I2 flows, (the second average current value i ave2 is the first threshold i th1 Since the magnetic nanowire 22 has four magnetic domains and a magnetic wall 29, the magnetic nanowire 22 moves toward the one end 28. ave2 When the second current I2 is passed for a second predetermined time (determined according to), the first magnetic domain from the one end 28 side before the second current I2 is passed disappears, and the second to fourth magnetic domains from the one end 28 side move by one bit toward the one end 28 side. Also, a second average current value i ave2 When the second current I2 flows, (the second current I2 is equal to or smaller than the second threshold i th2 As a result, a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end 27 of the magnetic wire 22 is written in the magnetic wire 22. In the example shown in Fig. 4, the upward magnetization direction of the magnetic domain formed on the other end 27 before the second current I2 is passed is reversed, and a magnetic domain having a new downward magnetization direction is written in the other end 27 of the magnetic wire 22.

[0055] 5 and 6 are diagrams showing current control by the current control unit 31 when writing predetermined write data to the magnetic nanowire 22. 5 and 6 show current control when writing write data "01001101" to the magnetic nanowire 22 in which 8-bit data "00000000" has been written. The graph shown by the solid line in FIG. 5 shows current control when constant currents are passed from the magnetic nanowire 22 to the in-plane magnetized layer 26 as the first current I1 and the second current I2. The graph shown by the dotted line in FIG. 6 shows current control when a pulse current is passed from the magnetic nanowire 22 to the in-plane magnetized layer 26 as the first current I1.

[0056] When writing a predetermined bit to the magnetic wire 22, the current control unit 31 obtains a bit (hereinafter referred to as the other end bit) corresponding to the magnetization direction of the magnetic domain at the other end 27 of the magnetic wire 22 at that time. When the predetermined bit is the same as the other end bit, the current control unit 31 writes a magnetic domain having the same magnetization direction as the magnetic domain at the other end 27 of the magnetic wire 22 to the magnetic wire 22, so that the current control unit 31 passes a first current I1 to the multi-valued magnetic memory element 11 for only a first predetermined time T1. When the predetermined bit is different from the other end bit, the current control unit 31 passes a second current I2 to the multi-valued magnetic memory element 11 for only a second predetermined time T2, so that the current control unit 31 writes a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain at the other end 27 of the magnetic wire 22 to the magnetic wire 22.

[0057] For example, the first bit "0" of the write data is the same as the other end bit "0" when writing the bit "0" (i.e., the eighth bit "0" of the data already written in the magnetic nanowire 22). Therefore, as shown in FIG. 5 and FIG. 6, when writing the first bit "0" of the write data, the current control unit 31 passes a first current I1 to the multi-valued magnetic memory element 11 for a first predetermined time T1. Also, the second bit "1" of the write data is different from the other end bit "0" when writing the bit "1" (i.e., the first bit "0" of the write data). Therefore, as shown in FIG. 5 and FIG. 6, when writing the second bit "1" of the write data, the current control unit 31 passes a second current I2 to the multi-valued magnetic memory element 11 for a second predetermined time T2. The current control unit 31 controls the magnitude of the current and the time for passing the current for the remaining bits in the same manner.

[0058] According to the above configuration, by controlling the magnitude of the current flowing from the magnetic nanowire 22 to the in-plane magnetization layer 26, it is possible to write a magnetic domain having an upward magnetization direction (i.e., a bit "1") or a magnetic domain having a downward magnetization direction (i.e., a bit "0") in the magnetic nanowire 22. Then, according to the configuration in which the bit to be written is switched by controlling the magnitude of the current, it is possible to realize writing and reading of a plurality of bits while keeping the number of connection terminals of the multi-valued magnetic memory element 11 to which the wiring from the controller 12 is connected to two terminals. Then, since it is not necessary to change the direction of the current flowing in the multi-valued magnetic memory element 11, it is possible to easily control the current by the controller 12. Therefore, a multi-bit memory can be realized with a simple circuit configuration.

[0059] (Current control) The first current I1 may be a constant current of a first current value i1 (see FIG. 5). The second current I2 may be a constant current of a second current value i2 (when the first current I1 is a constant current of the first current value i1, the second current value i2>the first current value i1) (see FIGS. 5 and 6). At least one of the first current I1 and the second current I2 may be a constant current. By making the current flowing from the magnetic wire 22 to the in-plane magnetized layer 26 a constant current, the circuit design in the controller 12 can be facilitated.

[0060] The first current I1 may be a pulse current (see FIG. 6). For example, the first current I1 may be a pulse current including a current of the third current value i3 and a current of the fourth current value i4 (<the third current value i3). The fourth current value i4 may be, for example, a zero current. The second current I2 may be a constant current of the third current value i3 (see FIG. 6). The second current I2 may be a pulse current including a current of the third current value i3 and a current of the fourth current value i4, in which the proportion of the current of the third current value i3 is greater than that of the first current I1. At least one of the first current I1 and the second current I2 may be a pulse current. This allows the control of the magnitude of the current flowing from the magnetic nanowire 22 to the in-plane magnetized layer 26 to be realized by the pulse current. In particular, when the fourth current value i4 is a zero current, the control of the magnitude of the current flowing from the magnetic nanowire 22 to the in-plane magnetized layer 26 can be realized by switching between the zero current and the third current value i3 (i.e., controlling the current on and off). For example, when a pulse current between the third current value i3 and zero current is applied as the first current I1, the duration of one cycle of the pulse current is preferably equal to or less than half the first predetermined time T1.

[0061] (Simulation results) FIG. 7 is a diagram showing an example of a result of simulating the writing of a new magnetic domain in the multi-valued magnetic memory element 11. FIG. 8 is a diagram showing another example of a result of simulating the writing of a new magnetic domain in the multi-valued magnetic memory element 11. FIGS. 7 and 8 show cross-sectional views of the magnetic nanowire 22. The large white arrows in FIGS. 7 and 8 indicate the magnetization directions of the magnetic domains, and the small arrows at each position indicate the magnetization direction at that position. The horizontal magnetization direction is indicated by the small black arrow, and the upward and downward magnetization directions are indicated by the small white arrows. In FIGS. 7 and 8, the domain walls 29 appear as dark regions.

[0062] Reference numerals 701 to 708 in FIG. 7 sequentially indicate the time change of the magnetic domains in the magnetic nanowire 22 when a current is passed from the magnetic nanowire 22 to the in-plane magnetized layer 26. Reference numeral 701 in FIG. 7 indicates the state of the magnetic nanowire 22 before a current is passed. A plurality of magnetic domains having a downward magnetization direction are formed throughout the magnetic nanowire 22 before a current is passed. Reference numerals 702 to 708 in FIG. 7 respectively indicate the states 0.1 ns, 0.3 ns, 0.4 ns, 0.5 ns, 0.6 ns, 0.8 ns, and 1.0 ns after the current starts to pass. In this simulation, the second current I2 continues to pass until 1.0 ns after the current starts to pass.

[0063] When the second current I2 is passed from the magnetic wire 22 to the in-plane magnetization layer 26, electrons first flow from the in-plane magnetization layer 26 to the other end 27 of the magnetic wire 22, and the magnetization of the other end 27 of the magnetic wire 22 rotates to a horizontal direction (reference numerals 702 and 703). Then, the first domain wall 29a is formed by the magnetization that has rotated to a horizontal direction. The magnetic domain above the first domain wall 29a and the first domain wall 29a move toward the one end 28. The magnetization of the other end 27 of the magnetic wire 22 further rotates to an upward direction (reference numerals 704 and 605). As a result, a magnetic domain having a new upward magnetization direction is written to the other end 27 of the magnetic wire 22. When the second current I2 continues to be passed from the magnetic wire 22 to the in-plane magnetization layer 26, the magnetization of the other end 27 of the magnetic wire 22 further rotates to a horizontal direction (reference numeral 706). Then, the second domain wall 29b is formed by the magnetization rotated laterally. The magnetic domain above the first domain wall 29a, the first domain wall 29a, the magnetic domain between the first domain wall 29a and the second domain wall 29b, and the second domain wall 29b move toward the one end 28. The magnetization of the other end 27 of the magnetic wire 22 further rotates to become downward (reference numeral 707). As a result, a magnetic domain having a new downward magnetization direction is written to the other end 27 of the magnetic wire 22. As a result, magnetic domains having downward, upward, and downward magnetization directions are written in the magnetic wire 22 in this order from the one end 28 side (reference numeral 708).

[0064] Reference numerals 801 to 807 in Fig. 8 sequentially indicate the time changes of the magnetic domains in the magnetic nanowire 22 when a current is passed from the magnetic nanowire 22 to the in-plane magnetized layer 26. Reference numeral 801 in Fig. 8 indicates the state of the magnetic nanowire 22 before a current is passed. Reference numerals 802 to 807 respectively indicate the states 0.5 ns, 0.7 ns, 0.9 ns, 1.1 ns, 1.3 ns, and 1.5 ns after the current starts to pass. In this simulation, the second current I2 was passed until 0.5 ns after the current started to pass, and the first current I1 was passed from 0.5 ns to 1.5 ns.

[0065] 7, when a second current I2 is passed from the magnetic wire 22 to the in-plane magnetization layer 26, a first domain wall 29a is formed, and a magnetic domain having a new upward magnetization direction is written to the other end 27 of the magnetic wire 22 (reference numerals 801, 802). Next, when a first current I1 is passed from the magnetic wire 22 to the in-plane magnetization layer 26, electrons flow from the in-plane magnetization layer 26 to the other end 27 of the magnetic wire 22, and the magnetization of the other end 27 of the magnetic wire 22 rotates to a horizontal direction. However, the first current I1 is higher than the second threshold i th2 Since the magnetization of the other end 27 of the magnetic nanowire 22 does not rotate any further, a new magnetic domain wall is not formed, and only the magnetic domain above the first magnetic domain wall 29a and the first magnetic domain wall 29a move toward the one end 28 (reference numerals 803 to 807). As a result, a magnetic domain having a new upward magnetization direction is written to the other end 27 of the magnetic nanowire 22.

[0066] The simulations shown in Figures 7 and 8 were performed under the following conditions. The simulation model is a micromagnetic simulation based on the Landau-Lifshitz-Gilbert equation (LLG equation) incorporating the term of the spin transfer torque STT due to the spin-polarized current. The magnetic nanowire 22 has a cylindrical shape, with a diameter of 20 nm and a length of 102 nm. The saturation magnetization of the magnetic nanowire 22 is set to 400 kA / m. The energy of the magnetocrystalline anisotropy in the z direction of the in-plane magnetized layer 26 is set to 0.0 MJ / m. 3 The magnetic nanowire 22 has a magnetocrystalline anisotropy energy of 0.0 MJ / m along the z direction. 3 and 0.2MJ / m 3The regions are arranged alternately in the z direction at intervals of 3 nm in thickness. The energy of the magnetocrystalline anisotropy is 0.2 MJ / m 3 The exchange stiffness constant of the region is 10.0 pJ / m, and the energy of the magnetocrystalline anisotropy is 0.0 MJ / m. 3 The other end 27 of the magnetic nanowire 22 has a magnetocrystalline anisotropy energy of 0.0 MJ / m 3 The greater the energy of the magnetocrystalline anisotropy in the z direction, the easier it is for magnetization to be oriented in the z direction. Therefore, in a region where the energy of the magnetocrystalline anisotropy in the z direction is large, the written magnetic domain is more likely to be stable, and in a region where the energy of the magnetocrystalline anisotropy in the z direction is small, the domain wall 29 is more likely to be stable. Note that the magnetocrystalline anisotropy in the magnetic nanowire 22 may be uniform. The spin polarization rate P is set to 0.5. The current density of the first current I1 flowing through the magnetic nanowire 22 is 3.5×10 11 A / m 2 The current density of the second current I2 flowing through the magnetic nanowire 22 is 7.0×10 11 A / m 2 It was decided.

[0067] The total z-direction magnetocrystalline anisotropy energy is 0.2 MJ / m 3 In a simulation using the magnetic nanowire 22 having a length of 100 mm, multiple magnetic domains could be written at intervals similar to those in the simulation results shown in Figures 7 and 8. In the simulation results shown in Figures 7 and 8, 4 bits of information were stored, but by using a longer nanowire as the magnetic nanowire 22, it is possible to write more bits of information (for example, even 512 bits or more) in one magnetic nanowire without changing the structure and mechanism of other parts.

[0068] (How to write data) FIG. 9 is a diagram showing an example of a write method of write data. FIG. 10 is a diagram showing current control of another example of a write method of write data. FIG. 11 is a diagram explaining a magnetic memory device corresponding to FIG. 10. FIG. 12 is a diagram showing current control of yet another example of a write method of write data. FIG. 13 is a diagram explaining a magnetic memory device corresponding to FIG. 12. FIG. 14 is a diagram showing current control of yet another example of a write method of write data. FIG. 15 is a diagram explaining a magnetic memory device corresponding to FIG. 14. FIG. 16 is a diagram explaining a magnetic memory device showing the same bits as FIG. 14. The graphs of FIG. 9, FIG. 10, FIG. 12 and FIG. 14 show current control when writing write data "01001101" to the magnetic nanowire 22 in which 8-bit data "00010001" has already been written. 9, 10, 12 and 14 show current control in the case where constant currents are passed from the magnetic wire 22 to the in-plane magnetized layer 26 as the first current I1 and the second current I2.

[0069] As described above, when writing data to the multi-valued magnetic memory element 11 of the present embodiment, if the bit to be written is the same as the other end bit (the bit corresponding to the magnetization direction of the magnetic domain at the other end 27), the first current I1 is passed for a first predetermined time T1, and if it is different, the second current I2 is passed for a second predetermined time T2. Therefore, when writing the first bit of the write data, the controller 12 must control the magnitude of the current passed through the multi-valued magnetic memory element 11 according to the last bit (the other end bit) of the data already written in the magnetic nanowire 22. That is, there are cases where it is necessary to recognize whether the other end bit is "0" or "1". In the above example, since 8-bit data "00010001" has already been written, there are cases where it is necessary to recognize that the last bit (the other end bit) is "1". Various write methods for dealing with such situations will be described later with reference to Figs. 9 to 16.

[0070] The controller 12 may write at least one bit less than the number of magnetic domains of the magnetic wire 22 before writing the write data. In an example shown in FIG. 9, the magnetic wire 22 has eight magnetic domains, which is the same number as the number of bits of the write data. The controller 12 causes the first current I1 to flow for a time (7T1) that is seven times the first predetermined time T1 so as to write seven bits, which is one less than the number of magnetic domains of the magnetic wire 22, before writing the write data. As a result, 8-bit data "11111111" is written in the magnetic wire 22. That is, the magnetic domain corresponding to the other end bit "1" of the already written data moves to the first position from the one end 28 side. Also, the other end bit of the newly written data becomes the same bit "1" as the other end bit "1" of the already written data. Therefore, the controller 12 can obtain the other end bit "1" that is the same as the bit by reading the first bit from the one end 28 side after flowing the first current I1 for 7T1. Even if the last bit (other end bit) is "0", the other end bit "0" can be obtained by reading the first bit from one end 28 after flowing the first current I1 for 7T1.

[0071] After acquiring the other end bit in this manner, the controller 12 writes the write data. When writing the first bit "0" of the write data, the controller 12 passes a second current I2 through the multi-valued magnetic memory element 11 for only a second predetermined time T2 based on the acquired other end bit "1". Next, when writing the remaining bits, the controller 12 controls the magnitude of the current based on the bit previously written as the other end bit (see FIG. 9).

[0072] The number of bits written before writing the write data may be equal to or greater than the number of magnetic domains. Also, the controller 12 may pass the second current I2 for a time (7T2) that is 7 times the second predetermined time T2 before writing the write data. In this case, 8-bit data "10101010" is written to the magnetic nanowire 22. The other end bit of the newly written data is a bit "0" that is different from the other end bit "1" of the data already written. Therefore, the controller 12 passes the second current I2 for 7T2, and then reads the first bit from the one end 28 side, thereby obtaining the other end bit "0" that is different from the bit.

[0073] The magnetic wire 22 may have magnetic domains one more than the number of bits of the write data, and the controller 12 may write a reference bit indicating the last bit of the write data to the magnetic domain at one end 28 of the magnetic wire 22. In an example shown in Figs. 10 and 11, the magnetic wire 22 has nine magnetic domains, one more than the number of bits of the write data. Of the nine magnetic domains, a reference bit, which is the same bit as the last bit of the write data, is written to the magnetic domain at one end 28 of the magnetic wire 22, and the write data is written to the remaining magnetic domains. The reference bit may be a bit different from the last bit of the write data.

[0074] Before writing the write data, the controller 12 reads out the magnetic domain on one end 28 of the magnetic wire 22 corresponding to the reference bit of the already written data. Here, the reference bit is the same bit "1" as the last bit "1" of the already written data "00010001" (i.e., the bit on the other end before writing the write data). Therefore, the controller 12 can obtain the bit "1" of the other end by reading out the magnetic domain on one end 28 of the magnetic wire 22.

[0075] After acquiring the other end bit in this way, the controller 12 writes the reference bit of the write data. Here, the reference bit is the same bit "1" as the last bit "1" of the write data "01001101". When writing the reference bit "1", the controller 12 passes a first current I1 for a first predetermined time T1 based on the acquired other end bit "1". Next, when writing the write data, the controller 12 controls the magnitude of the current based on the bit written immediately before as the other end bit (see FIG. 10). As a result, after the write data is written, the reference bit of the write data is written in the magnetic domain on one end 28 side of the magnetic nanowire 22.

[0076] The magnetic wire 22 may have magnetic domains one more than the number of bits of the write data, and the controller 12 may write a dummy bit, which is a predetermined bit, to the magnetic domain on the other end 27 of the magnetic wire 22. In an example shown in Figures 12 and 13, the magnetic wire 22 has nine magnetic domains, one more than the number of bits of the write data. Of the nine magnetic domains, a dummy bit, which is a bit "0", is written to the magnetic domain on the other end 27 of the magnetic wire 22, and write data is written to the remaining magnetic domains. In other words, the bit at the other end before the write data is written is a dummy bit. The dummy bit may be a bit "1".

[0077] When writing the first bit "0" of the write data, the controller 12 passes a first current I1 through the multi-valued magnetic memory element 11 for a first predetermined time T1 based on the dummy bit "0" which is the other end bit. Next, when writing the remaining bits, the controller 12 controls the magnitude of the current based on the bit written immediately before as the other end bit (see FIG. 12).

[0078] The magnetic wire 22 may have magnetic domains whose number is one more than the number of bits of the write data. In an example shown in FIG. 14, FIG. 15, and FIG. 16, the magnetic wire 22 has nine magnetic domains whose number is one more than the number of bits of the write data. Then, instead of writing the write data by making the magnetic domains whose magnetization direction is upward correspond to the bit "1" which is the second value and the magnetic domains whose magnetization direction is downward correspond to the bit "0" which is the first value, the controller 12 may write the write data as follows. That is, when writing the first value (e.g., bit "0"), the controller 12 may write the magnetic domains whose magnetization direction is the same as the magnetization direction of the magnetic domains on the other end 27 of the magnetic wire 22 into the magnetic wire 22. Also, when writing the second value (e.g., bit "1"), the controller 12 may write the magnetic domains whose magnetization direction is different from the magnetization direction of the magnetic domains on the other end 27 of the magnetic wire 22 into the magnetic wire 22.

[0079] When writing the write data, the controller 12 first writes one magnetic domain having an arbitrary magnetization direction to the magnetic nanowire 22. That is, the controller 12 may pass the first current I1 for a first predetermined time T1, or pass the second current I2 for a second predetermined time T2. In the example shown in FIG. 14 and FIG. 15, the second current I2 is passed for the second predetermined time T2, and as a result, a magnetic domain having a downward magnetization direction is written to the magnetic nanowire 22. After writing the write data, the magnetic domain is at the first position from the one end 28 side.

[0080] Next, the controller 12 writes a magnetic domain having the same magnetization direction as the magnetic domain at the other end 27 of the magnetic wire 22 (downward magnetization direction in Figures 14 and 15) based on the first value "0" of the write data in the magnetic wire 22. That is, the controller 12 passes a first current I1 for a first predetermined time T1 based on the first value "0" of the write data. As a result, a magnetic domain having a downward magnetization direction is written in the magnetic wire 22. After the write data is written, the magnetic domain comes to the second position from the one end 28 side.

[0081] Next, the controller 12 writes a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end 27 of the magnetic wire 22 (downward magnetization direction in Figures 14 and 15) based on the second value "1" of the write data to the magnetic wire 22. That is, the controller 12 passes a second current I2 for a second predetermined time T2 based on the second value "1" of the write data. As a result, a magnetic domain having an upward magnetization direction is written to the magnetic wire 22. After the write data is written, the magnetic domain is at the third position from the one end 28 side.

[0082] Similarly, the controller 12 flows the first current I1 or the second current I2 based on the remaining value of the write data. In Fig. 14 and Fig. 15, the magnetic domains having the downward magnetization direction are written first, but in Fig. 16, the magnetic domains having the upward magnetization direction are written first.

[0083] According to such a configuration, by focusing on the bit boundary 41 and setting a first value (bit "0") when the magnetization state of the magnetic domains above and below the bit boundary 41 continues, and a second value (bit "1") when it switches, it is possible to write write data regardless of the other end bit of data already written in the magnetic nanowire 22. The controller 12 does not need to obtain the other end bit before writing the write data.

[0084] (Action and effect) As described above, according to the multi-valued magnetic memory element 11 of this embodiment, it is possible to write and read multiple bits using only a current in the vertical direction (the extension direction of the magnetic nanowire 22) without passing a current in the horizontal direction (the direction perpendicular to the extension direction of the magnetic nanowire 22). In other words, a large-capacity multi-valued magnetic memory element can be realized with a current in one direction, and there is no need to change the direction of the current to write bits "0" and "1". A multi-valued memory that could previously only be realized with a three-terminal structure can now be realized with a two-terminal structure, simplifying the structure of the magnetic memory device 1.

[0085] (Modification) The controller 12 may write only one domain wall in the magnetic wire 22 of the multi-valued magnetic memory element 11. The controller 12 may then associate the position of the domain wall in the magnetic wire 22 with a multi-valued bit. For example, the controller 12 associates the states in which the domain wall is located at 1 / 10, 2 / 10, and so on of the length of the magnetic wire 22 from the other end of the magnetic wire 22 in the extension direction with data values ​​"1", "2", and so on. The controller 12 places the domain wall at a predetermined position corresponding to the write data by passing a current for a predetermined time after writing the domain wall. The controller 12 also reads the data written in the multi-valued magnetic memory element 11 from the time it takes for the domain wall to reach the top.

[0086] The multi-valued magnetic memory element 11 can also be used in a learning device. The controller 12 writes only one domain wall in the magnetic nanowire 22 of the multi-valued magnetic memory element 11. Each time the memory becomes stronger through learning, the controller 12 moves the domain wall a predetermined amount in a predetermined direction. This is repeated, and when the domain wall reaches the end in the predetermined direction, it is considered that memory is complete.

[0087] (Active matrix magnetic memory device) Fig. 17 is a perspective view showing a part of a schematic configuration of a magnetic memory device 2 of an embodiment. In Fig. 17, black arrows indicate fixed magnetization directions, and white arrows indicate rewritable magnetization directions. The magnetic memory device 2 includes a plurality of multi-valued magnetic memory elements 11(j, k) arranged in a matrix, a plurality of upstream wirings U(j) (column wirings), and a plurality of downstream wirings D(k) (row wirings). Here, the jth column and the kth row are represented as (j, k).

[0088] The downstream wiring D(k) is connected to the in-plane magnetization layers 26 of the multiple multi-value magnetic memory elements 11 in the kth row. The upstream wiring U(j) is connected to the fixed layers 24 of the multiple multi-value magnetic memory elements 11 in the jth column. The downstream wiring D(k) and the upstream wiring U(j) are connected to the controller 12. The controller 12 includes switching elements (not shown) connected to each wiring, and switches between electrical continuity and non-conduction with each wiring.

[0089] For example, when writing magnetic domains to a plurality of multi-valued magnetic memory elements 11 in a j-th column, the controller 12 operates as follows. The controller 12 makes one selected upstream wiring U(j) of a plurality of upstream wirings U conductive and makes the other upstream wirings U non-conductive. Similarly, the controller 12 makes one selected downstream wiring D(k) of a plurality of downstream wirings D conductive and makes the other upstream wirings U non-conductive. As a result, a current flows from the selected upstream wiring U(j) through the multi-valued magnetic memory element 11(j, k) to the selected downstream wiring D(k). That is, a magnetic domain is written to the multi-valued magnetic memory element 11(j, k). The controller 12 controls the magnitude of the current flowing through the multi-valued magnetic memory element 11(j, k) according to the bit to be written to the multi-valued magnetic memory element 11(j, k). For example, the controller 12 controls the magnitude of the current flowing through the downstream wiring D(k) by switching the circuit (resistance element) connected to the downstream wiring D(k), or the like.

[0090] The downstream wiring D and the upstream wiring U are made of a metal such as Cu. It is preferable that the downstream wiring D has low electrical resistance. The downstream wiring D may be made of the same material as the in-plane magnetization layer 26.

[0091] FIG. 18 is a perspective view showing a part of the schematic configuration of another example of the magnetic memory device (magnetic memory device 2A). The magnetic memory device 2A shown in FIG. 18 differs from the magnetic memory device 2 shown in FIG. 17 in that an in-plane magnetization layer 26 is used as a substitute for the downstream wiring D. Specifically, the magnetic memory device 2A differs from the magnetic memory device 2 in which each multi-value magnetic memory element 11 has an in-plane magnetization layer 26 in that a plurality of multi-value magnetic memory elements 11 in the same column share an in-plane magnetization layer 26A extending in the column direction. In addition, the multi-value magnetic memory elements 11 sharing the in-plane magnetization layer 26 and the multi-value magnetic memory elements 11 connected by the downstream wiring D may be mixed.

[0092] (Circuit configuration of controller 12) 19 is a diagram showing an example of a circuit configuration of the controller 12 in the magnetic memory device 1. The circuit configuration of the controller 12 for reading and / or writing (R / W) data from and to the multi-valued magnetic memory element 11 will be described below with reference to FIG.

[0093] 19, the controller 12 includes an R / W circuit 60 and a selection gate 70. The R / W circuit 60 includes a pulse gate 61, a latch circuit 62 (read circuit), and a capacitor 63. One end of the pulse gate 61, the latch circuit 62 (read circuit), and the capacitor 63 are connected to the fixed layer 24 of the multi-valued magnetic memory element 11. The other end of the pulse gate 61 is connected to a voltage V high The other end of the latch circuit 62 is connected to a lead terminal. The other end of the capacitor 63 is connected to ground. One end of the selection gate 70 is connected to the in-plane magnetization layer 26 of the multi-value magnetic memory element 11. The other end of the selection gate 70 is connected to ground.

[0094] The pulse gate 61 opens and closes to generate a pulse current that is the first current I1 or the second current I2 according to the write data. Specifically, the pulse gate 61 switches the number of pulses of the voltage supplied to the multi-valued magnetic memory element 11 or the time for which the voltage is supplied to the multi-valued magnetic memory element 11 by opening and closing.

[0095] The latch circuit 62 includes a latch gate 66, an inverter loop section 67, and a read gate 68. The latch circuit 62 is a circuit for reading out a bit corresponding to the magnetization direction of the magnetic domain on the side of one end 28 of the magnetic nanowire 22. One end of the latch gate 66 is connected to a node N1 connected to the multi-value magnetic memory element 11. One end of the inverter loop section 67 is connected to the other end of the latch gate 66. One end of the read gate 68 is connected to the other end of the inverter loop section 67. The other end of the read gate 68 is a lead terminal.

[0096] The inverter loop unit 67 has two inverters connected in a loop shape. The latch circuit 62 has a function of fixing (latching) the voltages on the left and right of the inverter loop unit 67 to 1 / 0 or 0 / 1.

[0097] Fig. 20 is a graph showing the change over time in voltage at node N1 in the circuit configuration shown in Fig. 19. The procedure for R / W of the multi-valued magnetic memory element 11 will be described below with reference to Fig. 20.

[0098] <Read> The reading of data from the multi-valued magnetic memory element 11 will be described. In the initial state, all gates are OFF. First, the pulse gate 61 is turned ON (time t1). As a result, the voltage V at the node N1 becomes V high It rises to.

[0099] Next, the pulse gate 61 is turned OFF, and the selection gate 70 is turned ON (time t2), which causes charges to flow through the multi-valued magnetic memory element 11 to the ground, causing the voltage V to decrease over time.

[0100] Here, the way in which the voltage V drops varies depending on the magnitude of the resistance value R of the interface in the magnetic tunnel junction of the multi-valued magnetic memory element 11. Specifically, when the resistance value R is in a high resistance state (R high ) is in the low resistance state (R low ) the voltage V drops more slowly.

[0101] When the selection gate 70 is turned OFF at a predetermined timing after an appropriate time has passed, the voltage V stops decreasing. At this point, the latch gate is turned ON (time t3). The voltage V stops decreasing when the threshold value (V th ) is latched to 1, and to 0 if it is lower. th R high and R low The above-mentioned predetermined timing is designed so that it falls between the above.

[0102] Finally, the latch gate is turned OFF (time t4). This causes the resistance state (R high or R low The read gate 68 is then turned on to read out the 1 / 0 value of the latch circuit 62, thereby reading out the information from the multi-valued magnetic memory element 11. The 1 / 0 value of the latch circuit 62 that is read out is opposite to the 1 / 0 value of the voltage V described above.

[0103] <Write> The writing of data to the multi-valued magnetic memory element 11 will now be described. In the initial state, all gates are OFF. First, the selection gate is turned ON. Next, the pulse gate 61 is opened and closed so that the number of pulses or the time elapsed corresponds to the write data.

[0104] 19, the data of one multi-value magnetic memory element 11 that can be read at one time by the R / W circuit 60 is only the data written in the magnetic domain on one end 28 of the magnetic nanowire 22. When reading a plurality of data written in the multi-value magnetic memory element 11, the magnetic domains are moved, so that the reading is basically destructive. Therefore, in order to retain the read data, it is preferable to store the read data in another memory or write the data to the other end 27 of the magnetic nanowire 22 immediately after or simultaneously with the reading.

[0105] FIG. 21 is a diagram showing another example of the circuit configuration of the controller 12 in the magnetic memory device 1. In the example shown in FIG. 21, the controller 12 includes an R / W circuit 60A and a selection gate 70. The R / W circuit 60A differs from the R / W circuit 60A in that the R / W circuit 60A includes a high-voltage side gate 64 and a low-voltage side gate 65 instead of the pulse gate 61. One end side of the high-voltage side gate 64 and the low-voltage side gate 65 are connected to the fixed layer 24 of the multi-level magnetic memory element 11. The other end side of the high-voltage side gate 64 is connected to a voltage V high The other end of the low-voltage side gate 65 is connected to a high-voltage source that supplies a voltage V Low ( <V high ) is connected to a low voltage source that supplies

[0106] The read process by the R / W circuit 60A is similar to the read process by the above-mentioned R / W circuit 60. The read process by the R / W circuit 60A differs from that of the R / W circuit 60 in that either the high-voltage side gate 64 or the low-voltage side gate 65 is turned ON in response to the write data.

[0107] In the following description, unless otherwise specified, the "R / W circuit 60" may be replaced with the "R / W circuit 60A."

[0108] [Embodiment 2] (Circuit configuration of magnetic memory device) FIG. 22 is a diagram showing a schematic configuration of a magnetic memory device 101 including a plurality of multi-value magnetic memory elements 11. The magnetic memory device 101 includes n R / W circuits 60 arranged in a first direction, and m multi-value magnetic memory elements 11 arranged in a second direction (i.e., n×m multi-value magnetic memory elements 11 arranged in a matrix) connected in parallel to each R / W circuit 60. The magnetic memory device 101 also includes a selection gate 70 (i.e., n×m selection gates 70) connected downstream of each multi-value magnetic memory element 11, m selection gate wirings 71 arranged in the second direction, and a selector circuit 80 connected to the m selection gate wirings 71. Each selection gate wiring 71 is connected to n selection gates 70 arranged in the first direction. When R / W is executed by the R / W circuit 60, the selector circuit 80 applies a voltage to the selection gate wiring 71 corresponding to a specific multi-value magnetic memory element 11, thereby allowing R / W to be executed on the specific multi-value magnetic memory element 11. In addition, FIG. 22 shows an example where n=4 and m=3.

[0109] 22, the ground wiring of six multi-level magnetic memory elements 11 connected to two R / W circuits 60 is a common wiring. This allows space saving compared to a configuration in which a different ground wiring is used for each R / W circuit 60. Note that a configuration in which a different ground wiring is used for each R / W circuit 60 may also be used. Also, a common R / W circuit 60 may be connected to n×m multi-level magnetic memory elements 11.

[0110] 23 is a diagram showing a schematic configuration of another example (magnetic memory device 101A) of a magnetic memory device including a plurality of multi-value magnetic memory elements 11. In the magnetic memory device 101A shown in FIG. 23, four multi-value magnetic memory elements 11 connected to the same R / W circuit 60 share an in-plane magnetized layer 26A. Also, a selection gate 70 is disposed upstream of the multi-value magnetic memory elements 11.

[0111] Fig. 24 is a diagram showing a schematic configuration of yet another example (magnetic memory device 101B) of a magnetic memory device including a plurality of multi-value magnetic memory elements 11. As shown in Fig. 24, in the magnetic memory device 101B, two multi-value magnetic memory elements 11 are connected in series to an R / W circuit 60, and one selection gate 70 is disposed between the two multi-value magnetic memory elements 11.

[0112] The two multi-value magnetic memory elements 11 include a first multi-value magnetic memory element 11-1 whose upstream wiring (R / W circuit 60 side) is connected to one end 28 of the magnetic nanowire 22, and a second multi-value magnetic memory element 11-2 whose upstream wiring is connected to the other end 27 of the magnetic nanowire 22. In an example shown in Fig. 24, of the two multi-value magnetic memory elements 11, the upstream multi-value magnetic memory element 11 is the first multi-value magnetic memory element 11-1, and the downstream multi-value magnetic memory element 11 is the second multi-value magnetic memory element 11-2. The R / W circuit 60 has a circuit configuration that can apply a positive voltage V or a negative voltage -V to the two multi-value magnetic memory elements 11.

[0113] In the multi-valued magnetic memory elements 11-1 and 11-2, a current (a second threshold value i th2Even if a current having a predetermined average current value or more is passed through the magnetic wire 22, the magnetic domains and magnetic domain walls do not move. For example, as shown in FIG. 24, in the multi-valued magnetic memory elements 11-1 and 11-2, the portions of the magnetic wire 22 defined by the four magnetic domains each have a shape in which the cross section gradually increases toward the fixed layer 24. This allows the multi-valued magnetic memory elements 11-1 and 11-2 to have a structure in which the magnetic domains and magnetic domain walls are unlikely to move downward. In other words, the multi-valued magnetic memory elements 11-1 and 11-2 have a structure in which the magnetic domains and magnetic domain walls are unlikely to move downward due to the current from the in-plane magnetized layer 26 to the magnetic wire 22. Note that the structure in which the magnetic domains and magnetic domain walls are unlikely to move downward is not limited to this.

[0114] Therefore, when the R / W circuit 60 applies a positive voltage to the multi-value magnetic memory element 11, a current flows from the magnetic nanowire 22 to the in-plane magnetized layer 26 in the first multi-value magnetic memory element 11-1, and a current flows from the in-plane magnetized layer 26 to the magnetic nanowire 22 in the second multi-value magnetic memory element 11-2. As a result, R / W is executed for the first multi-value magnetic memory element 11-1, and R / W is not executed for the second multi-value magnetic memory element 11-2. Conversely, when the R / W circuit 60 applies a negative voltage to the multi-value magnetic memory element 11, R / W is executed for the second multi-value magnetic memory element 11-2, and R / W is not executed for the first multi-value magnetic memory element 11-1. That is, according to the above configuration, it is possible to selectively execute R / W for one of the two multi-value magnetic memory elements 11 connected in series.

[0115] 25 is a diagram showing a schematic configuration of yet another example (magnetic memory device 101C) of a magnetic memory device including a plurality of multi-value magnetic memory elements 11. In the magnetic memory device 101C, the multi-value magnetic memory elements 11 shown in FIG. 24 are arranged in a matrix. With such a configuration, the magnetic memory device 101C only needs to include one selection gate 70 for two multi-value magnetic memory elements 11, thereby making it possible to reduce the space required for the magnetic memory device 101C.

[0116] [Embodiment 3] FIG. 26 is a front view (reference numeral 2601) and a top view (reference numeral 2602) showing a schematic structure of a 3D-NAND element 200 (NAND flash memory) to which a multi-level magnetic memory element 11 (NV-FIFO: non-volatile-first in first out) is applied. As shown by reference numeral 2602 in FIG. 26, the 3D-NAND element 200 has a structure in which a NAND array region 210 and a CMOS region 220 are arranged side by side in the horizontal direction. The CMOS region 220 includes a page register 221 and a peripheral circuit 222. The peripheral circuit 222 includes a page selection circuit, an R / W circuit, a power supply circuit, and an interface circuit for performing data communication with the outside. A memory cell layer is located above the NAND array region 210, and a wiring layer is located above the CMOS region 220.

[0117] Conventionally, data read / write to a 3D-NAND element is performed via a page register. A read is performed by writing data read by a R / W circuit from a NAND cell selected by a page selection circuit to the page register, and then reading the data via an interface circuit. A write is performed by writing data to be written in advance to the page register via the interface circuit, and then writing the data to a NAND cell selected by the page selection circuit using a write circuit.

[0118] Here, the page register is a volatile circuit made of CMOS, so even if data is written to the page register, if the power is cut off before the data is written to the NAND, the data will be lost.

[0119] 26, the 3D-NAND element 200 further includes a pillar memory region 230 including a plurality of multi-value magnetic memory elements 11 on an upper portion of a BEOL (Back End of Line) layer 240 (wiring layer). Also, as shown in FIG. 26, the 3D-NAND element 200 further includes an NV-FIFO R / W circuit 223 in the CMOS region 220.

[0120] Writing in this embodiment differs from conventional writing in that data to be written is written in advance to a page register via an interface circuit, and at the same time, the NV-FIFO R / W circuit 223 also writes the data to the pillar memory area 230.

[0121] Thus, according to this embodiment, the write data is written not only to the page register 221 but also to the columnar memory area 230. Since the multi-valued magnetic memory element 11 is non-volatile, the data will not be lost even if the power is cut off before the data is written to the NAND.

[0122] The capacity of the pillar memory area 230 does not necessarily have to be the same as that of the page register 221. The pillar memory area 230 to which the data in the page register 221 is to be written may be selected in advance, so that data can be stored in multiple pillar memory areas 230.

[0123] 27 is a front view (reference numeral 2701) and a top view (reference numeral 2702) showing a schematic structure of another example (3D-NAND element 200A) of a 3D-NAND element to which the multi-level magnetic memory element 11 is applied. The 3D-NAND element 200A differs from the 3D-NAND element 200 shown in FIG. 26 in that the CMOS region 220 is laminated below the BEOL layer 240. This allows a memory cell layer to be formed also above the CMOS region 220, thereby improving the ratio of the memory cell area to the chip area.

[0124] In this case, as indicated by reference numeral 2701 in Fig. 27, the 3D-NAND element 200A includes a pillar memory region 230 in the lower part of the BEOL layer 240. Also, as indicated by reference numeral 2702 in Fig. 27, the 3D-NAND element 200A includes an NV-FIFO R / W circuit 223 in the CMOS region 220. The pillar memory region 230 may be located in the upper part of the BEOL layer 240.

[0125] In the following description, unless otherwise specified, the "3D-NAND element 200" may be replaced with the "3D-NAND element 200A."

[0126] FIG. 28 is a diagram showing a schematic configuration of a solid-state drive device 300 (SSD device) to which the above-mentioned 3D-NAND element 200 is applied.

[0127] The solid-state drive device 300 includes a controller 310 (SSD-controller), a peripheral circuit 320, and one or more NAND elements 330 (SSD-NAND flash memory). In an example shown in FIG. 28, the solid-state drive device 300 includes six NAND elements 330. The controller 310 includes a circuit that performs the main functions of an SSD, such as an R / W circuit and an L2P table for the NAND elements. The peripheral circuit 320 includes a power supply circuit and an interface circuit with the outside. At least one of the one or more NAND elements 330 is the above-mentioned 3D-NAND element 200. In an example shown in FIG. 28, all of the six NAND elements 330 are the 3D-NAND elements 200. In this way, the above-mentioned 3D-NAND element 200 can be applied to the NAND elements 330 of the SSD device.

[0128] Fig. 29 is a diagram showing a schematic configuration of a solid-state drive 300A in which the above-mentioned multi-level magnetic memory element 11 is applied to a controller 310A. Reference numeral 2901 in Fig. 29 is a block diagram of the solid-state drive 300A. Reference numerals 2902 and 2903 in Fig. 29 are a top view and a front view, respectively, of the controller 310A of the solid-state drive 300A.

[0129] The solid-state drive device 300A includes a controller 310A (SSD-controller), a peripheral circuit 320, and one or more NAND elements 330. The controller 310A includes a NAND array region 410 and a CMOS region 420 stacked below the NAND array region 410. The NAND array region 410 includes a bit selector 411, a word selector 412, a sense amplifier 413, a peripheral circuit 414, and a pillar memory region 430. The pillar memory region 430 includes a plurality of multi-value magnetic memory elements 11. That is, the controller 310A includes a pillar memory region 430 in which a plurality of multi-value magnetic memory elements 11 are applied to the NAND array region 410. In this way, the multi-value magnetic memory element 11 can also be applied to the temporary memory of the controller of the SSD device.

[0130] [Embodiment 4] In this embodiment, an application example of the multi-value magnetic memory element 11 will be described.

[0131] (Application example 1) Conventionally, when the chunk size of a random write is smaller than the NAND page size, multiple write data (chunks) are buffered in volatile memory until the total size of the data exceeds the page size.

[0132] If power is cut off during buffering, the data that has already been written will be lost, and the information that is about to be written will also be lost.

[0133] To prevent this, important data must be written to the NAND even in small chunks, resulting in reduced throughput and increased endurance cycles.

[0134] On the other hand, in this embodiment, the multi-valued magnetic memory element 11 is used for buffering, which can prevent data loss and multiple writing to the NAND.

[0135] (Application example 2) The L2P table is a table for associating addresses (logical addresses) seen from an external interface with actual addresses (physical addresses) in the NAND flash memory. The L2P table is written in the NAND flash memory in the SSD.

[0136] Basically, with NAND flash memory, once data has been written to a certain physical address, new data cannot be written until it is erased. However, when trying to erase data from a certain physical address in NAND flash memory, a large unit (block) of data is erased at once, and since this takes significantly longer than R / W, it is not practical to perform an erase operation every time data is rewritten.

[0137] Therefore, when changing data at a certain logical address, the changed data is written to a new physical address and the physical address corresponding to that logical address stored in the L2P table is updated to the new physical address. In this way, the next time that logical address is read, the changed data written to the new physical address is read.

[0138] In this way, the data in the L2P table is frequently rewritten. Therefore, it is not realistic to write the data in the L2P table to the NAND flash memory every time it is rewritten. Usually, the data in the L2P table is written to DRAM or SRAM when the SSD is turned on, and is written back to the NAND when the SSD is turned off.

[0139] In this case, if the power to the SSD is suddenly cut off, the data in the L2P table that has been updated up to that point will be lost, and it will become impossible to know which physical address the data at a certain logical address is written to. In other words, the integrity of the data in the SSD will be lost. However, data in the L2P table that has not been updated will not be lost because it has been written to the NAND flash memory.

[0140] Therefore, in this embodiment, the data of the updated L2P table (pairs of logical addresses and physical addresses) are written to the multi-valued magnetic memory element 11 of the 3D-NAND element and / or the multi-valued magnetic memory element 11 arranged on the controller. In this way, even if the power is suddenly cut off, the updated L2P table is not lost and the consistency of the data in the SSD is not lost.

[0141] The method of operating the L2P table executed by the SSD according to this embodiment will be described below.

[0142] First, like a conventional SSD, the SSD according to this embodiment reads the L2P table from the NAND flash memory when the power is turned on, and loads it into the DRAM or SRAM.

[0143] Next, the SSD reads the multi-level magnetic memory element 11, and if data of the L2P table is written, updates the previously developed L2P table. As will be described later, the fact that data remains in the multi-level magnetic memory element 11 means that an unexpected power outage has occurred.

[0144] During operation, the SSD updates the L2P table in the same manner as a conventional SSD, except that it writes the data of the L2P table to the multi-level magnetic memory element 11.

[0145] When the power is turned off in normal operation, the SSD writes the data of the L2P table to the NAND flash memory, and at the same time erases the data of the L2P table written in the multi-valued magnetic memory element 11. This allows the SSD to determine whether or not an unexpected power interruption has occurred when the power is turned on.

[0146] If the capacity of the multi-valued magnetic memory element 11 is not large enough, there is a possibility that the capacity of the multi-valued magnetic memory element 11 will be used up by the update data before the power is turned off. In this case, the SSD writes the data of the L2P table to the NAND flash memory even if the power is not turned off.

[0147] (Application example 3) Data is often handled internally in files. However, when storing files on an SSD, a single file may be written in multiple blocks (a set of logical addresses).

[0148] Software that manipulates files (file systems) manages files using metadata that indicates, for example, the order in which the data contained in a file with a certain identifier (name) is written and in which blocks.

[0149] When you edit an existing file and save it over the SSD, or when you create a new file and write it to the SSD, the file system writes the new data to new blocks or to blocks that are no longer needed, overwriting the metadata mentioned above, so that the data corresponding to a certain file name can be replaced with new data.

[0150] However, if an unexpected power outage occurs before the new data and metadata are written to the SSD, all or part of the new data may not be written, or the metadata may be corrupted, making it impossible to handle the files correctly. In other words, the integrity of the files is lost.

[0151] For this reason, ideally, the data and metadata of the file contents should all be written at the same time. Writing multiple blocks of data at the same time (indivisibly) like this is called an Atomic Write.

[0152] In reality, it is difficult to realize an SSD that can perform atomic writes of any number of blocks. Usually, people prepare for the above-mentioned problems by using uninterruptible power supplies to prevent unexpected power outages, or by periodically backing up files or storage.

[0153] In this embodiment, the purpose is to provide a function equivalent to Atomic Write in practice by using the multi-valued magnetic memory element 11. A method of overwriting or creating an atomic file executed by the SSD according to this embodiment will be described below.

[0154] First, the SSD according to this embodiment prepares data blocks that need to be newly written, and prepares blocks to write write completion flags corresponding to those data blocks. At this point, there are no blocks for which writing has been completed, so the values ​​of all flags are 0. In addition, link information such as the address of the block to which the write completion flag is written is written to the metadata of the corresponding file.

[0155] Next, the SSD writes new data to the prepared data block. At this time, as soon as writing to the block is completed, the SSD rewrites the write completion flag to 1.

[0156] Once all blocks have been written, the SSD invalidates the old blocks of the file (a trim operation). Finally, the SSD replaces the metadata with the new one.

[0157] In the SSD according to this embodiment, at least the write completion flag among the above data is written to the multi-valued magnetic memory element 11. This prevents the file integrity from being lost even if an unexpected power outage occurs before all operations are completed. Specifically, if all new data writing is completed at the time of power outage, the contents of the file can be unified with the new data. Also, if even one block is not completed, the file integrity can be maintained by unifying it with the old data. Also, even if data is frequently rewritten as described above, the life of the SSD is not significantly shortened.

[0158] Note that the same operation may be performed in the opposite manner to the above, with 1 indicating before completion of writing and 0 indicating after completion of writing. Furthermore, instead of a 0 / 1 flag, completion of writing may be determined by writing an invalid address and an actual block address.

[0159] [Software implementation example] The functions of the controller 12 (hereinafter referred to as the "device") are realized by a program for causing a computer to function as the device, and can be realized by a program for causing a computer to function as each control block of the device (current control unit 31, write instruction unit 34, read instruction unit 35, and measurement unit 36).

[0160] In this case, the device includes a computer having at least one control device (e.g., a processor) and at least one storage device (e.g., a memory) as hardware for executing the program. The control device and storage device execute the program to realize each function described in each of the above embodiments.

[0161] The program may be non-transitory and may be recorded in one or more computer-readable recording media. The recording media may or may not be included in the device. In the latter case, the program may be provided to the device via any wired or wireless transmission medium.

[0162] In addition, some or all of the functions of each of the control blocks can be realized by a logic circuit. For example, an integrated circuit in which a logic circuit that functions as each of the control blocks is formed is also included in the scope of the present invention. In addition, the functions of each of the control blocks can be realized by, for example, a quantum computer.

[0163] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0164] 1, 2 Magnetic memory device 11 Multi-valued magnetic memory element 12 Controller 22 Magnetic thin wire 23 First Middle Class 24 Fixed layer 25 The second middle class 26 In-plane magnetization layer 27 Other end 28 one end 51 1st wiring 52 2nd wiring 61 Pulse Gate 62 Latch Circuit 64 High voltage side gate 65 Low voltage side gate 11-1 First multi-valued magnetic memory element 11-2 Second multi-valued magnetic memory element 200 3D-NAND elements (NAND flash memory) 310 Controller (SSD-Controller) 330 NAND element (SSD-NAND flash memory)

Claims

1. a magnetic nanowire capable of writing a plurality of magnetic domains corresponding to a plurality of bits, each of the plurality of magnetic domains having a magnetization direction substantially parallel to an extension direction of the magnetic nanowire; a pinned layer having a magnetization direction substantially parallel to the extending direction of the magnetic nanowire; a non-magnetic first intermediate layer disposed between one end of the magnetic nanowire and the pinned layer; an in-plane magnetized layer electrically connected to the other end of the magnetic nanowire and having a magnetization substantially perpendicular to the magnetization of the magnetic nanowire; when a first current having an average current value equal to or greater than a first threshold and less than a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having the same magnetization direction as a magnetic domain on the other end of the magnetic nanowire is written in the magnetic nanowire; A multi-value magnetic memory element in which, when a second current having an average current value greater than or equal to a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end of the magnetic nanowire is written to the magnetic nanowire.

2. a magnetic nanowire capable of writing a plurality of magnetic domains corresponding to a plurality of bits; A fixed layer; a first intermediate layer disposed between one end of the magnetic nanowire and the fixed layer; an in-plane magnetized layer electrically connected to the other end of the magnetic nanowire; the magnetic nanowire has an easy axis of magnetization in the extending direction; the pinned layer has an easy axis of magnetization in a thickness direction; the in-plane magnetization layer has an easy axis of magnetization in an in-plane direction; In a state where the other end of the magnetic nanowire is magnetized in the extending direction and the in-plane magnetized layer is magnetized in the in-plane direction, when a first current having an average current value equal to or greater than a first threshold and less than a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having the same magnetization direction as a magnetic domain on the other end of the magnetic nanowire is written in the magnetic nanowire; A multi-value magnetic memory element in which, when a second current having an average current value greater than or equal to a second threshold flows from the magnetic nanowire to the in-plane magnetization layer, a magnetic domain having a magnetization direction different from the magnetization direction of the magnetic domain on the other end of the magnetic nanowire is written to the magnetic nanowire.

3. 3. The multi-valued magnetic memory element according to claim 1, further comprising a non-magnetic second intermediate layer disposed between the other end of the magnetic nanowire and the in-plane magnetization layer.

4. 3. The multi-valued magnetic memory element according to claim 1, wherein at least one of the first current and the second current is a constant current.

5. 3. The multi-valued magnetic memory element according to claim 1, wherein at least one of the first current and the second current is a pulse current.

6. A multi-valued magnetic memory element according to claim 1 or 2, a controller that, in a writing operation, writes a magnetic domain in the magnetic nanowire by passing the first current or the second current from the magnetic nanowire to the in-plane magnetization layer.

7. a first wiring which is a path through which the first current and the second current flow from the controller to the multi-valued magnetic memory element; a second wiring which is a path through which the first current and the second current flow from the multi-valued magnetic memory element to the controller; The magnetic memory device of claim 6, wherein the controller, during reading, reads out a bit corresponding to the magnetization direction of the magnetic domain on the one end side of the magnetic nanowire by passing a third current through the first intermediate layer via the first wiring and the second wiring.

8. 7. The magnetic memory device according to claim 6, wherein the controller writes at least one bit less than the number of magnetic domains of the magnetic nanowire by passing the first current or the second current for a predetermined period of time before writing write data.

9. the magnetic nanowire has magnetic domains whose number is one more than the number of bits of write data; 7. The magnetic memory device according to claim 6, wherein the controller writes a reference bit indicating a last bit of the write data in the magnetic domain on the one end side of the magnetic nanowire.

10. the magnetic nanowire has magnetic domains whose number is one more than the number of bits of write data; 7. The magnetic memory device according to claim 6, wherein the controller writes a dummy bit, which is a predetermined bit, in the magnetic domain on the other end side of the magnetic nanowire.

11. the magnetic nanowire has magnetic domains whose number is one more than the number of bits of write data; The controller: When writing a first value, a magnetic domain having the same magnetization direction as the magnetic domain at the other end of the magnetic nanowire is written in the magnetic nanowire; 7. The magnetic memory device according to claim 6, wherein when a second value is written, a magnetic domain having a magnetization direction different from a magnetization direction of the magnetic domain on the other end side of the magnetic nanowire is written in the magnetic nanowire.

12. The controller: a latch circuit for reading out a bit corresponding to a magnetization direction of a magnetic domain on the one end side of the magnetic nanowire; 7. The magnetic memory device according to claim 6, further comprising: a pulse gate that generates a pulse current that is the first current or the second current in response to write data.

13. The controller: a latch circuit for reading out a bit corresponding to a magnetization direction of a magnetic domain on the one end side of the magnetic nanowire; A high voltage side gate connected to a high voltage source; 7. The magnetic memory device of claim 6, further comprising: a low-voltage side gate connected to a low-voltage source.

14. As the multi-value magnetic memory element, a first multi-value magnetic memory element having an upstream wiring connected to the one end side of the magnetic nanowire; the multi-value magnetic memory element includes a second multi-value magnetic memory element having an upstream wiring connected to the other end of the magnetic nanowire; 7. The magnetic memory device according to claim 6, wherein in said multi-value magnetic memory element, when a current flows from said in-plane magnetization layer to said magnetic nanowire, magnetic domains do not move.

15. A NAND flash memory comprising the magnetic memory element according to claim 1 or 2.

16. An SSD-controller; One or more SSD-NAND flash memories; A solid-state drive device, wherein at least one of the one or more SSD-NAND flash memories is the NAND flash memory according to claim 15.

17. An SSD-controller; One or more SSD-NAND flash memories; 3. A solid-state drive device, wherein the SSD-controller includes the multi-valued magnetic memory element according to claim 1.

18. a magnetic nanowire capable of writing a plurality of magnetic domains corresponding to a plurality of bits, each of the plurality of magnetic domains having a magnetization direction substantially parallel to an extension direction of the magnetic nanowire; a pinned layer having a magnetization direction substantially parallel to the extending direction of the magnetic nanowire; a non-magnetic first intermediate layer disposed between one end of the magnetic nanowire and the pinned layer; a control method for a multi-value magnetic memory element including an in-plane magnetized layer electrically connected to the other end of the magnetic nanowire and having a magnetization substantially perpendicular to a magnetization of the magnetic nanowire, the method comprising: A method for controlling a multi-valued magnetic memory element, in which, during writing, a magnetic domain is written in the magnetic nanowire by passing a first current, the average current value of which is greater than or equal to a first threshold and less than a second threshold, or a second current, the average current value of which is greater than or equal to a second threshold, from the magnetic nanowire to the in-plane magnetization layer.

19. 7. A control program for causing a computer to function as the controller of the magnetic memory device according to claim 6.

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