Semiconductor device

Abstract

To provide a semiconductor device capable of reducing leakage current.SOLUTION: A semiconductor device includes: a first electrode; a semiconductor part located on the first electrode; an insulating member located in the semiconductor part; a first insulating film located on a portion of the semiconductor part; a second insulating film located on another portion of the semiconductor part, the second insulating film being thicker than the first insulating film; a second electrode located in the insulating member; first wiring connected to the second electrode and located on the insulating member and on the second insulating film but not located on the first insulating film; and a third electrode located on the semiconductor part, on the insulating member, and on the first insulating film.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In a vertical power control semiconductor device, a gate electrode may be disposed in a trench, and in such a semiconductor device, it is desirable to reduce leakage current in an off state. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-185593 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device capable of reducing leakage current. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment comprises a first electrode, a semiconductor portion provided on the first electrode, an insulating member provided within the semiconductor portion, a first insulating film provided on a portion of the semiconductor portion, a second insulating film provided on another portion of the semiconductor portion and thicker than the first insulating film, a second electrode provided within the insulating member, a first wiring connected to the second electrode, provided on the insulating member and the second insulating film, and not provided on the first insulating film, and a third electrode provided on the semiconductor portion, on the insulating member, and on the first insulating film. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Diagram 2]FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line CC' shown in FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line DD' shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line EE' shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line FF' shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line GG' shown in FIG. [Figure 9] FIG. 9 is a plan view showing a semiconductor device according to a comparative example. [Figure 10] FIG. 10 is a cross-sectional view taken along line HH' shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line II' shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <Embodiment> FIG. 1 is a plan view showing a semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. FIG. 4 is a cross-sectional view taken along line CC' shown in FIG. FIG. 5 is a cross-sectional view taken along line DD' shown in FIG. FIG. 6 is a cross-sectional view taken along line EE' shown in FIG. FIG. 7 is a cross-sectional view taken along line FF' shown in FIG. FIG. 8 is a cross-sectional view taken along line GG' shown in FIG. In addition, the drawings are schematic and have been appropriately emphasized or simplified, and even when the same components are shown, the positions and dimensional ratios are not necessarily strictly consistent between the drawings.

[0008] 1 to 8, in the semiconductor device 1 according to this embodiment, a cell region Rc, an extraction region Rd, and a termination region Re are defined. The termination region Re is arranged in a frame shape along an edge 1e of the semiconductor device 1. The cell region Rc is surrounded by the termination region Re. The extraction region Rd is arranged in a part of the region between the termination region Re and the cell region Rc.

[0009] The semiconductor device 1 includes a drain electrode 11 (first electrode), a semiconductor portion 20, a gate electrode 12 (second electrode), an FP (field plate) electrode 13 (fourth electrode), a source electrode 14 (third electrode), a gate lead wiring 15 (first wiring), an FP lead wiring 16, a termination conductive film 17, a gate wiring 18, an FP wiring 19, an insulating member 31, a thin insulating film 32 (first insulating film), a thick insulating film 33 (second insulating film), and an interlayer insulating film 34.

[0010] 1 illustrates the semiconductor portion 20, the gate electrode 12, the FP electrode 13, the gate lead wiring 15, the FP lead wiring 16, the termination conductive film 17, the insulating member 31, the insulating thin film 32, and the insulating thick film 33, while omitting the source electrode 14, the gate wiring 18, the FP wiring 19, and the interlayer insulating film 34. Also, in FIG. 1, the edge 1e of the semiconductor device 1 is on the left side of the figure, and the region in which the termination region Re, the lead region Rd, and the cell region Rc are arranged is shown toward the right side of the figure.

[0011] The semiconductor portion 20 is disposed on the drain electrode 11. The semiconductor portion 20 is made of a semiconductor material, for example, contains silicon (Si), and is formed of, for example, single crystal silicon. In the semiconductor portion 20, impurities are selectively introduced into each portion to define the conductivity type and carrier concentration. The detailed configuration of the semiconductor portion 20 will be described later.

[0012] A plurality of insulating members 31 are provided. Each insulating member 31 is disposed within the upper portion of the semiconductor portion 20 in the cell region Rc and the extraction region Rd, and extends in one direction (the X direction described below). The upper portion of the semiconductor portion 20 is disposed between adjacent insulating members 31. In the Y direction described below, the multiple insulating members 31 are arranged parallel to each other, for example, periodically.

[0013] The insulating thin film 32 is disposed on the insulating member 31 and on the semiconductor portion 20 between the insulating members 31 in the cell region Rc. The insulating thin film 32 is in contact with the semiconductor portion 20 and the insulating member 31.

[0014] The thick insulating film 33 is disposed on the insulating member 31 and between the insulating members 31 and on the semiconductor portion 20 in the extraction region Rd. The thick insulating film 33 contacts the semiconductor portion 20, the insulating member 31, and the insulating thin film 32. The thick insulating film 33 is disposed on the termination region Re side of the insulating thin film 32. The thick insulating film 33 is thicker than the insulating thin film 32 and thinner than the insulating member 31.

[0015] The insulating member 31, the insulating thin film 32, and the insulating thick film 33 are made of an insulating material, and contain, for example, silicon oxide (SiO). As shown in Fig. 4, on the semiconductor portion 20, the bottom surface of the insulating thick film 33 and the bottom surface of the insulating thin film 32 are located at substantially the same position. On the other hand, the top surface of the insulating thick film 33 is located higher than the top surface of the insulating thin film 32. For this reason, a step 35 is formed at the boundary between the top surface of the insulating thin film 32 and the top surface of the insulating thick film 33.

[0016] For convenience of explanation, an XYZ Cartesian coordinate system is used in the following description. The direction in which the insulating members 31 extend is defined as the "X direction" (first direction), the arrangement direction of the insulating members 31 is defined as the "Y direction" (second direction), and the direction from the drain electrode 11 toward the source electrode 14 is defined as the "Z direction" (third direction). The Z direction is also referred to as "up" and the opposite direction as "down", but these expressions are also for convenience and are unrelated to the direction of gravity.

[0017] The gate electrode 12 and the FP electrode 13 are disposed in an insulating member 31, and each extends in the X direction. In each insulating member 31, the gate electrode 12 and the FP electrode 13 are arranged along the Y direction, and one FP electrode 13 is disposed between two gate electrodes 12. The FP electrode 13 is insulated from the gate electrode 12 by the insulating member 31. The lower end of the FP electrode 13 is located lower than the lower end of the gate electrode 12. In addition, the end of the FP electrode 13 in the X direction is located closer to the termination region Re than the end of the gate electrode 12 in the X direction. The gate electrode 12 and the FP electrode 13 are made of a conductive material, for example, polysilicon containing impurities.

[0018] The gate lead wiring 15 is disposed on the insulating member 31 and the insulating thick film 33 in the lead region Rd. The gate lead wiring 15 is not disposed on the insulating thin film 32. The gate lead wiring 15 is made of a conductive material, for example, polysilicon containing impurities. The gate lead wiring 15 is connected to at least one end of the gate electrode 12 in the X direction. In this specification, "connection" means electrical connection. Specifically, the lower surface of the portion of the gate lead wiring 15 on the cell region Rc side is integrated with the upper surface of the portion of the gate electrode 12 on the termination region Re side.

[0019] The FP lead wiring 16 is disposed on the insulating member 31 and the insulating thick film 33 in the lead region Rd. The FP lead wiring 16 is not disposed on the insulating thin film 32. The FP lead wiring 16 is disposed closer to the termination region Re than the gate lead wiring 15, and is separated from the gate lead wiring 15. The FP lead wiring 16 is made of a conductive material, for example, polysilicon containing impurities. The FP lead wiring 16 is connected to the X-direction end of the FP electrode 13. Specifically, the lower surface of the portion of the FP lead wiring 16 on the cell region Rc side is integrated with the upper surface of the portion of the FP electrode 13 on the termination region Re side.

[0020] Termination conductive film 17 is disposed on insulating thick film 33 in a portion of termination region Re on the side of extension region Rd. Termination conductive film 17 is separated from FP extension wiring 16. Termination conductive film 17 is made of, for example, polysilicon containing impurities.

[0021] The interlayer insulating film 34 is disposed on the insulating member 31, the thin insulating film 32, and the thick insulating film 33 in the cell region Rc, the lead region Rd, and the portion of the termination region Re on the lead region Rd side. The interlayer insulating film 34 covers the gate lead wiring 15, the FP lead wiring 16, and the termination conductive film 17.

[0022] The gate wiring 18 is disposed on the interlayer insulating film 34 in the lead-out region Rd. When viewed from above, the gate wiring 18 is disposed in a region overlapping with the gate lead-out wiring 15, and is connected to the gate lead-out wiring 15 via a gate contact 18a penetrating the interlayer insulating film 34. The gate lead-out wiring 15 is connected to a gate pad (not shown) disposed on the interlayer insulating film 34. Therefore, the gate electrode 12 is connected to the gate pad via the gate lead-out wiring 15 and the gate wiring 18.

[0023] The FP wiring 19 is disposed on the interlayer insulating film 34 in the drawing region Rd. When viewed from above, the gate wiring 18 is disposed in a region overlapping with the FP drawing wiring 16, and is connected to the FP drawing wiring 16 via an FP contact 19a penetrating the interlayer insulating film 34.

[0024] The source electrode 14 is disposed on the interlayer insulating film 34 in the cell region Rc. Therefore, the source electrode 14 is disposed on the semiconductor portion 20, the insulating member 31, and the insulating thin film 32. The source electrode 14 is connected to the semiconductor portion 20 via a source contact 14a that penetrates the interlayer insulating film 34. The source electrode 14 is also connected to the FP wiring 19. As a result, the FP electrode 13 is connected to the source electrode 14 via the FP extraction wiring 16 and the FP wiring 19.

[0025] An insulating protective film (not shown) is provided on the semiconductor portion 20, the interlayer insulating film 34, the gate wiring 18, the FP wiring 19, and the source electrode 14. However, a part of the source electrode 14 and a part of the gate pad (not shown) are exposed from the protective film, and are regions to which external wiring is bonded.

[0026] In the semiconductor portion 20, a drain layer 21, a drift layer 22, a base layer 23, a base contact layer 24, a source layer 25, a source contact layer 26, a termination p-type layer 28, and a termination n-type layer 29 are provided.

[0027] The drain layer 21 is disposed over the entire surface of the drain electrode 11 and is in contact with the drain electrode 11. The conductivity type of the drain layer 21 is n + The drift layer 22 is disposed on the entire surface of the drain layer 21 and is in contact with the drain layer 21. The conductivity type of the drift layer 22 is n - It is of the type "n + "N-type" means that the carrier concentration is higher than that of "n-type", and "n - "N-type" indicates that the carrier concentration is lower than that of "n-type." The same applies to p-type. The drain layer 21 and drift layer 22 form a first semiconductor layer.

[0028] The base layer 23 is disposed on a part of the drift layer 22 in the cell region Rc. The base layer 23 faces the gate electrode 12 via an insulating member 31. The conductivity type of the base layer 23 is p-type. The base contact layer 24 is disposed between the base layer 23 and the source electrode 14, and is in contact with the base layer 23 and the source electrode 14. The conductivity type of the base contact layer 24 is p + The base layer 23 is connected to the source contact 14a of the source electrode 14 via the base contact layer 24. When viewed from above, the base layer 23 and the base contact layer 24 are separated from the gate extension wiring 15. The base layer 23 and the base contact layer 24 form a second semiconductor layer.

[0029] The source layer 25 is disposed on the base layer 23 in a region in contact with the insulating member 31. The conductivity type of the source layer 25 is n-type. The source contact layer 26 is disposed on the base layer 23 between two adjacent source layers 25. The source contact layer 26 is in contact with the base layer 23 and the source layer 25, and is separated from the insulating member 31. The conductivity type of the source contact layer 26 is n-type. + The upper surface of the source layer 25 and the upper surface of the source contact layer 26 are in contact with the lower surface of the source contact 14a of the source electrode 14. As a result, the source layer 25 and the source contact layer 26 are connected to the source electrode 14. The source layer 25 and the source contact layer 26 form a third semiconductor layer.

[0030] The termination p-type layer 28 is disposed on the drift layer 22 in the termination region Re. The conductivity type of the termination p-type layer 28 is p-type. The termination n-type layer 29 is disposed on a part of the termination p-type layer 28 and is separated from the drift layer 22 via the termination p-type layer 28. The conductivity type of the termination n-type layer 29 is n + It is a type.

[0031] Next, the effects of this embodiment will be described. In the semiconductor device 1, when a source potential, for example, a ground potential, is applied to the source electrode 14, a drain potential higher than the source potential is applied to the drain electrode 11, and an on potential, for example, a positive potential, is applied to the gate electrode 12, an inversion layer is formed in the portion of the base layer 23 that contacts the insulating member 31, and the semiconductor device 1 is turned on. As a result, a current flows between the source and drain.

[0032] On the other hand, when an off potential, for example, a ground potential, is applied to the gate electrode 12, the inversion layer disappears and the semiconductor device 1 is turned off. This cuts off the current between the source and drain. At this time, the drain layer 21, the drift layer 22, and the base layer 23 are at the drain potential.

[0033] In the semiconductor device 1, the gate extension wiring 15 is separated from the drift layer 22 via the insulating thick film 33 that is thicker than the insulating thin film 32, and is therefore less susceptible to the potential of the drift layer 22. In addition, as viewed from above, the gate extension wiring 15 is separated from the base layer 23 and the base contact layer 24, and is therefore also less susceptible to the potential of the base layer 23. This makes it possible to suppress the potential of the gate electrode 12 from increasing from the off potential due to capacitive coupling, and thus reduces the leakage current in the off state.

[0034] <Comparative Example> FIG. 9 is a plan view showing a semiconductor device according to this comparative example. FIG. 10 is a cross-sectional view taken along line HH' shown in FIG. FIG. 11 is a cross-sectional view taken along line II' shown in FIG.

[0035] 9 to 11, in the semiconductor device 101 according to this comparative example, a portion 15a of the gate extension wiring 15 on the cell region Rc side is disposed on the insulating thin film 32. As a result, the gate extension wiring 15 faces the base layer 23 and the drift layer 22 via the insulating thin film 32.

[0036] Therefore, when the semiconductor device 101 is turned off, the gate extension wiring 15 is capacitively coupled to the base layer 23 and the drift layer 22, and the potential of the gate extension wiring 15 rises above the off potential. As a result, the potential of the gate electrode 12 also rises from the off potential, and the leakage current increases.

[0037] According to the embodiment described above, a semiconductor device capable of reducing leakage current can be realized.

[0038] Although the embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0039] The present invention includes the following aspects.

[0040] (Appendix 1) A first electrode; A semiconductor portion provided on the first electrode; an insulating member provided within the semiconductor portion; a first insulating film provided on a portion of the semiconductor portion; a second insulating film provided on another part of the semiconductor portion and thicker than the first insulating film; A second electrode provided within the insulating member; a first wiring connected to the second electrode, provided on the insulating member and the second insulating film, and not provided on the first insulating film; a third electrode provided on the semiconductor portion, the insulating member, and the first insulating film; A semiconductor device comprising:

[0041] (Appendix 2) 2. The semiconductor device according to claim 1, further comprising a fourth electrode provided within the insulating member, insulated from the second electrode, and connected to the third electrode.

[0042] (Appendix 3) The insulating member extends in a first direction, In the insulating member, the second electrode and the fourth electrode are arranged along a second direction perpendicular to the first direction, 3. The semiconductor device according to claim 2, wherein the first direction and the second direction intersect with a third direction extending from the first electrode to the third electrode.

[0043] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the second insulating film is located on a terminal end side of the insulating member with respect to the first insulating film.

[0044] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the insulating member is in contact with the first insulating film and the second insulating film.

[0045] (Appendix 6) The semiconductor portion is a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of a second conductivity type provided on a portion of the first semiconductor layer and facing the second electrode via the insulating member; a third semiconductor layer of a first conductivity type provided on a portion of the second semiconductor layer and connected to the third electrode; 6. The semiconductor device according to claim 1, further comprising:

[0046] (Appendix 7) 7. The semiconductor device according to claim 6, wherein the second semiconductor layer is spaced apart from the first wiring when viewed from above.

[0047] (Appendix 8) the semiconductor portion comprises silicon; 8. The semiconductor device according to claim 1, wherein the insulating member, the first insulating film, and the second insulating film contain silicon oxide.

[0048] (Appendix 9) A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of a second conductivity type provided on a portion of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on a portion of the second semiconductor layer; a second electrode facing the second semiconductor layer via an insulating member; a first wiring provided on the first semiconductor layer, connected to the second electrode, and spaced apart from the second semiconductor layer when viewed from above; a third electrode connected to the third semiconductor layer and the second electrode; A semiconductor device comprising: [Explanation of symbols]

[0049] 1 Semiconductor device 1e edge 11 Drain electrode 12 Gate electrode 13 FP electrode 14 Source electrode 14a Source Contact 15 Gate lead wiring 15a part 16 FP extraction wiring 17 Termination Conductive Film 18 Gate wiring 18a Gate Contact 19 FP wiring 19a FP Contact 20 Semiconductor part 21 Drain layer 22 Drift Layer 23 Base Layer 24 Base contact layer 25 Source Layer 26 Source Contact Layer 28 Terminated p-type layer 29 Terminated n-type layer 31 Insulating materials 32 Thin insulating film 33 Insulating thick film 34 Interlayer insulating film 35 steps 101 Semiconductor device Rc Cell Area Rd drawer area Re termination area

Claims

1. A first electrode; A semiconductor portion provided on the first electrode; an insulating member provided within the semiconductor portion; a first insulating film provided on a portion of the semiconductor portion; a second insulating film provided on another part of the semiconductor portion and thicker than the first insulating film; A second electrode provided within the insulating member; a first wiring connected to the second electrode, provided on the insulating member and the second insulating film, and not provided on the first insulating film; a third electrode provided on the semiconductor portion, the insulating member, and the first insulating film; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , further comprising a fourth electrode provided within the insulating member, insulated from the second electrode, and connected to the third electrode.

3. The insulating member extends in a first direction, In the insulating member, the second electrode and the fourth electrode are arranged along a second direction perpendicular to the first direction, The semiconductor device according to claim 2 , wherein the first direction and the second direction intersect with a third direction extending from the first electrode toward the third electrode.

4. 2. The semiconductor device according to claim 1, wherein the second insulating film is located on a terminal end side of the insulating member with respect to the first insulating film.

5. The semiconductor device according to claim 1 , wherein the insulating member is in contact with the first insulating film and the second insulating film.

6. The semiconductor portion is a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of a second conductivity type provided on a portion of the first semiconductor layer and facing the second electrode via the insulating member; a third semiconductor layer of the first conductivity type provided on a portion of the second semiconductor layer and connected to the third electrode; 6. The semiconductor device according to claim 1, further comprising:

7. The semiconductor device according to claim 6 , wherein the second semiconductor layer is spaced apart from the first wiring when viewed from above.

8. the semiconductor portion comprises silicon; The semiconductor device according to claim 1 , wherein the insulating member, the first insulating film, and the second insulating film contain silicon oxide.

9. A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of a second conductivity type provided on a portion of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on a portion of the second semiconductor layer; a second electrode facing the second semiconductor layer via an insulating member; a first wiring provided on the first semiconductor layer, connected to the second electrode, and spaced apart from the second semiconductor layer when viewed from above; a third electrode connected to the third semiconductor layer and the second electrode; A semiconductor device comprising:

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