Semiconductor package containing insulating material

Abstract

To provide a semiconductor package containing an insulating material.SOLUTION: A semiconductor package 1000 contains: a re-wiring structure body 300 that contains a re-wiring layer containing copper (Cu) and an insulation layer 310 surrounding the re-wiring layer; a semiconductor chip 100 that is mounted onto the re-wiring structure body, and contains a plurality of chip-coupling members 130; an internal coupling terminal 134 that is arranged between the re-wiring structure body and the semiconductor chip, and electrically connects the re-wiring layer and a connection pad; an external coupling terminal 600 that is adhered to a lower side of the re-wiring structure body, and is electrically connected to the re-wiring layer; and a sealing member 250 that surrounds the semiconductor chip and the internal coupling terminal on the re-wiring structure body. The insulation layer is made of an insulating material, where K satisfies 20 or more in a TC index.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including an insulating material that constitutes a redistribution structure. [Background technology]

[0002] Recently, the electronics market has seen a rapid increase in the demand for portable electronic devices, which has led to a continuous demand for smaller and lighter electronic components mounted in the portable electronic devices. To achieve the smaller and lighter electronic components, the total thickness of the semiconductor package is decreasing, but the demand for increased memory capacity is increasing. Therefore, in order to efficiently arrange semiconductor chips within a limited semiconductor package structure, wafer level packaging is becoming more and more common. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem that the technical idea of ​​the invention aims to solve is to provide a semiconductor package with improved reliability by forming an insulating layer included in a rewiring structure from an insulating material that prevents physical damage.

[0004] The problems that the technical idea of ​​the present invention is intended to solve are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] A semiconductor package according to the technical idea of ​​the present invention includes a first rewiring structure including a plurality of first rewiring patterns having a plurality of first bottom connection pads and a plurality of first top connection pads, and a first rewiring insulating layer surrounding the plurality of first rewiring patterns; a first semiconductor chip mounted in a first chip mounting area on the first rewiring structure; a plurality of first solder bumps attached to the plurality of first bottom connection pads at a lower portion of the first rewiring structure; a second rewiring structure disposed on the first semiconductor chip and the first rewiring structure, the second rewiring structure including a plurality of second rewiring patterns having a plurality of second bottom connection pads and a plurality of second top connection pads, and a second rewiring insulating layer surrounding the plurality of second rewiring patterns; a second semiconductor chip mounted in a solder mounting area; a plurality of second solder bumps attached to the plurality of second upper connection pads between the second rewiring structure and the second semiconductor chip; a plurality of conductive posts connecting some of the plurality of first upper connection pads and some of the plurality of second lower connection pads and disposed around the first semiconductor chip; and an encapsulant filling a space between the first rewiring structure and the second rewiring structure and surrounding the plurality of conductive posts and the first semiconductor chip; wherein each of the plurality of first rewiring patterns and the plurality of second rewiring patterns is made of a conductive material, and each of the first rewiring insulating layer and the second rewiring insulating layer is made of an insulating material in which K satisfies 20 or more in the following TC index. [TC Index]

number

[0006] A semiconductor package according to the technical idea of ​​the present invention includes a redistribution structure including a redistribution layer including copper (Cu) and an insulating layer surrounding the redistribution layer; a semiconductor chip mounted on the redistribution structure and including a connection pad; an internal connection terminal disposed between the redistribution structure and the semiconductor chip and electrically connecting the redistribution layer and the connection pad; an external connection terminal attached to a lower portion of the redistribution structure and electrically connecting the redistribution layer; and an encapsulant surrounding the semiconductor chip and the internal connection terminal on the redistribution structure; wherein the insulating layer is made of an insulating material having a TC index, K, of 20 or more as shown below. [TC Index]

number

[0007] A semiconductor package according to the technical idea of ​​the present invention includes a redistribution structure including a first insulating layer, at least one second insulating layer on the first insulating layer, and a plurality of redistribution layers disposed on the first insulating layer and the at least one second insulating layer, respectively, and electrically connected to each other; a semiconductor chip mounted on the redistribution structure and including connection pads; internal connection terminals disposed between the redistribution structure and the semiconductor chip, electrically connecting the plurality of redistribution layers and the connection pads; external connection terminals attached to a lower portion of the redistribution structure and electrically connected to the plurality of redistribution layers; and an encapsulant surrounding the semiconductor chip and the internal connection terminals on the redistribution structure; wherein each of the first insulating layer and the at least one second insulating layer is made of an insulating material having a TC index below, where K is 20 or more. [TC Index]

number

[0008] The semiconductor package according to the technical concept of the present invention has the effect of improving its reliability by forming the insulating layer contained in the redistribution structure from an optimal insulating material that can prevent physical damage by taking into account various physical properties. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a main configuration of a semiconductor package according to an embodiment of the technical concept of the present invention; [Diagram 2] 2 is an enlarged cross-sectional view showing a portion AA of FIG. 1 in an enlarged manner. [Diagram 3] 3 is a scanning electron microscope photograph showing the surrounding area of ​​the under-bump metal of FIG. 2. [Figure 4] 1 is a graph showing the degree of crack occurrence due to various physical properties of insulating materials constituting an insulating layer included in a redistribution structure. [Diagram 5] 1 is a graph showing the degree of crack occurrence due to various physical properties of insulating materials constituting an insulating layer included in a redistribution structure. [Figure 6] 1 is a graph showing the degree of crack occurrence due to various physical properties of insulating materials constituting an insulating layer included in a redistribution structure. [Figure 7] 11 is a cross-sectional view showing a main configuration of a semiconductor package according to another embodiment of the technical concept of the present invention. [Figure 8]FIG. 8 is an enlarged cross-sectional view showing a portion BB in FIG. 7. [Figure 9] 2 is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the technical concept of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 23] 1 is a schematic diagram showing a configuration of a semiconductor package according to an embodiment of the technical concept of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0011] Fig. 1 is a cross-sectional view showing the main structure of a semiconductor package according to an embodiment of the technical concept of the present invention. Fig. 2 is an enlarged cross-sectional view showing an enlarged portion AA of Fig. 1. Fig. 3 is a scanning electron microscope photograph showing the surrounding area of ​​the under-bump metal of Fig. 2.

[0012] 1 to 3, a semiconductor package 1000 may include a first semiconductor chip 100, conductive posts 200 arranged around the first semiconductor chip 100, a first redistribution structure 300 arranged on the bottom of the first semiconductor chip 100, a second redistribution structure 400 arranged on the top of the first semiconductor chip 100, and a second semiconductor chip 500 arranged on the top of the second redistribution structure 400.

[0013] The semiconductor package 1000 may also be a Package-on-Package (PoP) structure. In particular, the semiconductor package 1000 may also be a Fan Out Semiconductor Package in which the horizontal width and horizontal area of ​​the first redistribution structure 300 are greater than the horizontal width and horizontal area of ​​the first semiconductor chip 100. In some embodiments, the semiconductor package 1000 may be a Fan Out Wafer Level Package (FOWLP) or a Fan Out Panel Level Package (FOPLP). Package, FOPLP).

[0014] In some embodiments, the first redistribution structure 300 and the second redistribution structure 400 may be formed by a redistribution process. Here, the first redistribution structure 300 and the second redistribution structure 400 may also be referred to as a lower redistribution structure and an upper redistribution structure.

[0015] The first redistribution structure 300 may include a first redistribution insulating layer 310 and a plurality of first redistribution patterns 330. The first redistribution insulating layer 310 may surround the plurality of first redistribution patterns 330. In some embodiments, the first redistribution structure 300 may include a plurality of stacked first redistribution insulating layers 310. For example, the plurality of first redistribution insulating layers 310 may include, but are not limited to, a first insulating layer 312, a second insulating layer 314, and a third insulating layer 316 in sequence. The first insulating layer 312, the second insulating layer 314, and the third insulating layer 316 may be made of the same material or different materials. The first redistribution insulating layer 310 may be made of, for example, a photo imageable dielectric (PID) material. For example, at least one of the first insulating layer 312, the second insulating layer 314, and the third insulating layer 316 may be configured to include insulating materials having different K values ​​in the following TC index 1 or TC index 2. This will be described in detail later.

[0016] The first redistribution patterns 330 may include a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334. The first redistribution patterns 330 may be made of, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy of the above metals, but are not limited thereto.

[0017] The first redistribution line patterns 332 may be disposed on at least one of an upper surface and a lower surface of the first redistribution insulating layer 310. For example, when the first redistribution structure 300 includes a plurality of stacked first redistribution insulating layers 310, the first redistribution line patterns 332 may be disposed on an upper surface of the uppermost first redistribution insulating layer 310, a lower surface of the lowermost first redistribution insulating layer 310, and between adjacent first redistribution insulating layers 310.

[0018] The first redistribution vias 334 may be connected to some of the first redistribution line patterns 332 through the first redistribution insulating layer 310. In some embodiments, the first redistribution vias 334 may have a tapered shape in which the horizontal width increases from the lower side to the upper side.

[0019] In some embodiments, some of the first redistribution line patterns 332 may be formed integrally with some of the first redistribution vias 334. For example, the first redistribution line patterns 332 and the first redistribution vias 334 in contact with the lower surface of the first redistribution line patterns 332 may be formed integrally with each other.

[0020] Some of the first redistribution patterns 330 disposed adjacent to the lower surface of the first redistribution structure 300 are referred to as a plurality of first lower connection pads 330P1, and some of the first redistribution patterns 330 disposed adjacent to the upper surface of the first redistribution structure 300 are referred to as a plurality of first upper connection pads 330P2. In other words, the first lower connection pads 330P1 are also some of the first redistribution line patterns 332 disposed adjacent to the lower surface of the first redistribution structure 300, and the first upper connection pads 330P2 are also some of the first redistribution line patterns 332 disposed adjacent to the upper surface of the first redistribution structure 300.

[0021] A plurality of external connection terminals 600 may be attached to the plurality of first lower connection pads 330P1. The plurality of external connection terminals 600 may connect the semiconductor package 1000 to the outside. In some embodiments, the plurality of external connection terminals 600 may be solder bumps or solder balls. Meanwhile, a plurality of chip connecting members 130 may be attached to some of the plurality of first upper connection pads 330P2, and a plurality of conductive posts 200 may be attached to the other portion.

[0022] In some embodiments, a plurality of under bump metals UBM may be disposed between the plurality of first lower connection pads 330P1 and the plurality of external connection terminals 600. That is, a plurality of under bump metal UBM may be disposed under the plurality of first lower connection pads 330P1, and a plurality of external connection terminals 600 may be disposed under the plurality of under bump metal UBM. Thus, the plurality of under bump metal UBM may be disposed to protrude downward from the bottom surface of the first redistribution insulating layer 310.

[0023] In some embodiments, a plurality of external connection terminals 600 may be attached to some of the first lower connection pads 330P1, and a passive element 610 may be attached to another of the first lower connection pads 330P1.

[0024] A plurality of external connection terminals 600 may be formed on an upper surface of the first redistribution structure 300. The plurality of external connection terminals 600 may include, for example, solder balls, conductive bumps, conductive paste, a ball grid array (BGA), a lead grid array (LGA), a pin grid array (PGA), or a combination thereof.

[0025] The passive element 610 may include at least one selected from a resistor, a capacitor, an inductor, a thermistor, an oscillator, a ferrite bead, an antenna, and a varistor. For example, the passive element 610 may include a multi-layer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), a land side capacitor (LSC), a varistor, and a varistor. Capacitor, Integrated Passive Device (IPD), etc., but are not limited to these.

[0026] The outer underfill layer 650 may surround the sidewalls of the solder bumps 630 disposed under the passive elements 610 and fill the gaps between the adjacent solder bumps 630. During the process of electrically connecting the passive elements 610 and the solder bumps 630, gaps may be formed between the passive elements 610 and the solder bumps 630. Since such gaps may cause problems in the connection reliability between the passive elements 610 and the solder bumps 630, the outer underfill layer 650 may be injected and cured to reinforce the connection.

[0027] The outer underfill layer 650 allows the passive components 610 to be more stably fixed on the solder bumps 630 so that the passive components 610 and the solder bumps 630 are not electrically isolated from each other despite the difference in thermal expansion coefficients between the passive components 610 and the solder bumps 630 .

[0028] The first upper surface connection pads 330P2 may be disposed on the upper surface of the first redistribution insulating layer 310. For example, when the first redistribution structure 300 includes a plurality of stacked first redistribution insulating layers 310, the first upper surface connection pads 330P2 may be disposed on the upper surface of the uppermost first redistribution insulating layer 310.

[0029] At least one first semiconductor chip 100 may be mounted on the first redistribution structure 300. That is, the first semiconductor chip 100 may be composed of one or more first semiconductor chips 100. The first semiconductor chip 100 may include a semiconductor substrate 110 having an active surface and a non-active surface facing each other, a semiconductor element 112 formed on the active surface of the semiconductor substrate 110, and a plurality of chip pads 120 disposed on a first surface of the first semiconductor chip 100. For example, the first semiconductor chip 100 may have a thickness 100T of about 150 μm or more.

[0030] Here, the first and second surfaces of the first semiconductor chip 100 face each other, and the second surface of the first semiconductor chip 100 refers to the inactive surface of the semiconductor substrate 110. Since the active surface of the semiconductor substrate 110 is adjacent to the first surface of the first semiconductor chip 100, the illustration of the distinction between the active surface of the semiconductor substrate 110 and the first surface of the first semiconductor chip 100 is omitted.

[0031] In some embodiments, the first semiconductor chip 100 may have a face-down configuration in which the first surface faces the first redistribution structure 300 and may be mounted on the top surface of the first redistribution structure 300. In this case, the first surface of the first semiconductor chip 100 may be referred to as the bottom surface of the first semiconductor chip 100, and the second surface of the first semiconductor chip 100 may be referred to as the top surface of the first semiconductor chip 100.

[0032] A plurality of chip connecting members 130 may be interposed between some of the plurality of chip pads 120 of the first semiconductor chip 100 and the plurality of first upper surface connection pads 330P2 of the first rewiring structure 300. For example, each of the plurality of chip connecting members 130 may be a solder ball or a microbump. The first semiconductor chip 100 and the first rewiring pattern 330 of the first rewiring structure 300 may be electrically connected through the plurality of chip connecting members 130. The plurality of chip connecting members 130 may include a bump layer 132 disposed on the plurality of chip pads 120 and an internal connection terminal 134 covering the bump layer 132. The plurality of chip connecting members 130 may be made of, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Tin), gold (Au), or solder, but is not limited thereto.

[0033] The semiconductor substrate 110 may include a semiconductor material such as, for example, silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 110 may include, for example, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 110 may include a compound semiconductor material such as a phosphate. The semiconductor substrate 110 may include a well doped with impurities, which is a conductive region. The semiconductor substrate 110 may have various isolation structures, such as a shallow trench isolation (STI) structure.

[0034] A semiconductor device 112 including a variety of types of individual devices may be formed on the active surface of the semiconductor substrate 110. The individual devices may be electrically connected to the conductive region of the semiconductor substrate 110. The semiconductor device 112 may further include conductive wiring or conductive plugs that electrically connect the individual devices to the conductive region of the semiconductor substrate 110. In addition, each of the individual devices may be electrically isolated from adjacent individual devices by an insulating film.

[0035] In some embodiments, the first semiconductor chip 100 may include logic elements. For example, the first semiconductor chip 100 may be a central processing unit chip, a graphic processing unit chip, or an application processor chip. In other embodiments, when the semiconductor package 1000 includes multiple first semiconductor chips 100, one of the multiple first semiconductor chips 100 may be a central processing unit chip, a graphic processing unit chip, or an application processor chip, and the other may be a memory semiconductor chip including memory elements.

[0036] For example, the memory device may be a flash memory, a phase-change random access memory (PRAM), a magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory) or RRAM (Resistive In some embodiments, the memory device may be a non-volatile memory device, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0037] The second redistribution structure 400 may include a second redistribution insulating layer 410 and a plurality of second redistribution patterns 430. The second redistribution insulating layer 410 may surround the plurality of second redistribution patterns 430. In some embodiments, the second redistribution structure 400 may include a plurality of stacked second redistribution insulating layers 410. For example, the plurality of second redistribution insulating layers 410 may include, but are not limited to, a fourth insulating layer 412, a fifth insulating layer 414, and a sixth insulating layer 416 in sequence. The fourth insulating layer 412, the fifth insulating layer 414, and the sixth insulating layer 416 may be made of the same material or different materials. The second redistribution insulating layer 410 may be made of, for example, a PID material. For example, at least one of the fourth insulating layer 412, the fifth insulating layer 414, and the sixth insulating layer 416 may be configured to include insulating materials having different K values ​​in the following TC index 1 or TC index 2. This will be explained in more detail later.

[0038] In some embodiments, the second redistribution structure 400 may include a plurality of stacked second redistribution insulating layers 410. The plurality of second redistribution patterns 430 may include a plurality of second redistribution line patterns 432 and a plurality of second redistribution vias 434. The plurality of second redistribution patterns 430 may also be a metal or a metal alloy. In some embodiments, the plurality of second redistribution patterns 430 may be formed by stacking a metal or a metal alloy on a seed layer.

[0039] The second redistribution line patterns 432 may be disposed on at least one of an upper surface and a lower surface of the second redistribution insulating layer 410. For example, when the second redistribution structure 400 includes a plurality of stacked second redistribution insulating layers 410, the second redistribution line patterns 432 may be disposed on an upper surface of the uppermost second redistribution insulating layer 410, a lower surface of the lowermost second redistribution insulating layer 410, and between adjacent second redistribution insulating layers 410.

[0040] A portion of the second redistribution patterns 430 adjacent to the lower surface of the second redistribution structure 400 is referred to as a plurality of second lower connection pads 430P1, and a portion of the second redistribution patterns 430 adjacent to the upper surface of the second redistribution structure 400 is referred to as a plurality of second upper connection pads 430P2. For example, the second lower connection pads 430P1 are also a portion of the second redistribution line patterns 432 adjacent to the lower surface of the second redistribution structure 400, and the second upper connection pads 430P2 are also a portion of the second redistribution line patterns 432 adjacent to the upper surface of the second redistribution structure 400. In another embodiment, the second lower connection pads 430P1 are also a portion of the second redistribution vias 434 adjacent to the lower surface of the second redistribution structure 400.

[0041] The second semiconductor chip 500 may have a second semiconductor element 512 and a plurality of second pads 530. The second semiconductor chip 500 may be electrically connected to the second redistribution structure 400 by a plurality of internal connection terminals 550 interposed between the plurality of second pads 530 and the plurality of second top surface connection pads 430P2. The second semiconductor chip 500 may be mounted on the second redistribution structure 400 such that the plurality of second pads 530 face the second redistribution structure 400.

[0042] In some embodiments, the second semiconductor chip 500 may be electrically connected to the first redistribution patterns 330 of the first redistribution structure 300 through a plurality of internal connection terminals 550 attached to the second pads 530, a plurality of second redistribution patterns 430, and a plurality of conductive posts 200.

[0043] In some embodiments, the second semiconductor device 512 is also a memory device. For example, the memory device may be a non-volatile memory device, such as flash memory, PRAM, MRAM, FeRAM, or RRAM. In some embodiments, the memory device may be a volatile memory device, such as DRAM or SRAM.

[0044] The second lower surface connection pads 430P1 may be disposed on the lower surface of the second redistribution insulating layer 410. For example, when the second redistribution structure 400 includes a plurality of stacked second redistribution insulating layers 410, the second lower surface connection pads 430P1 may be disposed on the lower surface of the lowest second redistribution insulating layer 410.

[0045] The second upper surface connection pads 430P2 may be disposed on an upper surface of the second redistribution insulating layer 410. For example, when the second redistribution structure 400 includes a plurality of stacked second redistribution insulating layers 410, the second upper surface connection pads 430P2 may be disposed on an upper surface of the uppermost second redistribution insulating layer 410.

[0046] The plurality of second redistribution vias 434 may penetrate the second redistribution insulating layer 410 and be in contact with and connected to portions of the plurality of second redistribution line patterns 432. In some embodiments, some of the plurality of second redistribution line patterns 432 may be formed integrally with some of the plurality of second redistribution vias 434. For example, the second redistribution line pattern 432 and the second redistribution via 434 in contact with a lower surface of the second redistribution line pattern 432 may be formed integrally together.

[0047] In some embodiments, the second redistribution vias 434 may have a tapered shape that narrows in horizontal width from top to bottom. That is, the first redistribution vias 334 and the second redistribution vias 434 may extend in the same direction and each have a narrow horizontal width, but are not limited thereto.

[0048] Here, the first redistribution insulating layer 310, the first redistribution pattern 330, the first redistribution line pattern 332, and the first redistribution via 334 are also referred to as a first insulating layer, a first wiring pattern, a first wiring line pattern, and a first wiring via. Also, the second redistribution insulating layer 410, the second redistribution pattern 430, the second redistribution line pattern 432, and the second redistribution via 434 are also referred to as a second insulating layer, a second wiring pattern, a second wiring line pattern, and a second wiring via.

[0049] The encapsulant 250 may surround the first semiconductor chip 100 on the top surface of the first redistribution structure 300. The encapsulant 250 may fill a space between the first redistribution structure 300 and the second redistribution structure 400. For example, the encapsulant 250 may be a molding material including an epoxy mold compound (EMC). The encapsulant 250 may further include a filler.

[0050] In some embodiments, an internal underfill layer 150 surrounding the plurality of chip connecting members 130 may be interposed between the first semiconductor chip 100 and the first redistribution structure 300. In some embodiments, the internal underfill layer 150 may fill a space between the first semiconductor chip 100 and the first redistribution structure 300 and cover a lower portion of a side surface of the first semiconductor chip 100. The internal underfill layer 150 may be formed by, for example, a capillary underfill process and may be made of epoxy resin.

[0051] In some embodiments, a side of the first redistribution structure 300, a side of the encapsulant 250, and a side of the second redistribution structure 400 may be vertically aligned with one another and may be coplanar.

[0052] The conductive posts 200 may penetrate the encapsulant 250 to electrically connect the first redistribution structure 300 and the second redistribution structure 400. The encapsulant 250 may surround the conductive posts 200.

[0053] The conductive posts 200 may be interposed between the first redistribution structure 300 and the second redistribution structure 400 so as to be horizontally separated from the first semiconductor chip 100. For example, the conductive posts 200 may be arranged around the first semiconductor chip 100 in an outer region of the first redistribution structure 300 so as to be horizontally separated from the first semiconductor chip 100.

[0054] The conductive posts 200 may be interposed between the first upper connection pads 330P2 and the second lower connection pads 430P1. The lower surfaces of the conductive posts 200 may be in contact with the first upper connection pads 330P2 of the first redistribution structure 300 to be electrically connected to the first redistribution patterns 330, and the upper surfaces of the conductive posts 200 may be in contact with the second lower connection pads 430P1 of the second redistribution structure 400 to be electrically connected to the second redistribution patterns 430. In some embodiments, the conductive posts 200 may include, but are not limited to, copper (Cu) or a copper (Cu) alloy.

[0055] The lower surface of each of the conductive posts 200 may contact the upper surface of the first upper surface connection pad 330P2 and the lower surface of the second lower surface connection pad 430P1.

[0056] Recently, the electronic product market has seen a rapid increase in the demand for portable electronic devices, which has led to a continuous demand for smaller and lighter electronic components mounted in the portable electronic devices. To achieve the smaller and lighter electronic components, the total thickness of the semiconductor package 1000 is decreasing, but the demand for increased memory capacity is increasing. Therefore, in order to efficiently arrange the first semiconductor chip 100 within the limited structure of the semiconductor package 1000, fan-out wafer level packaging is being applied.

[0057] In such a limited semiconductor package 1000 structure, due to heat dissipation from the first semiconductor chip 100, in the first redistribution structure 300 constituting the fan-out wafer level package, cracks may occur in the first redistribution insulating layer 310, which has a relatively low strength, due to the difference in thermal expansion coefficient between the first redistribution insulating layer 310, which is an insulating material, and the first redistribution pattern 330, which is a conductive material.

[0058] Similarly, in the second redistribution structure 400 constituting a fan-out wafer-level package, cracks may occur in the second redistribution insulating layer 410, which has relatively low strength, due to the difference in thermal expansion coefficient between the second redistribution insulating layer 410, which is an insulating material, and the second redistribution pattern 430, which is a conductive material.

[0059] In order to solve the problem of cracks, various insulating materials are used to form the first redistribution insulating layer 310 and the second redistribution insulating layer 410. However, due to the different characteristics of the various materials that form the semiconductor package 1000, it is difficult to grasp the problem in advance.

[0060] Accordingly, the inventors have invented a new TC index for applying a highly reliable insulating material to the first redistribution insulating layer 310 and the second redistribution insulating layer 410, thereby minimizing the problem of crack generation.

[0061] In some embodiments, each of the first redistribution insulating layer 310 and the second redistribution insulating layer 410 may include an insulating material having K of 20 or more in the following TC index 1. [TC Index 1]

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[0062] The inventors have found that when the first redistribution insulating layer 310 and the second redistribution insulating layer 410 are respectively formed of the insulating material and the first redistribution pattern 330 and the second redistribution pattern 430 are respectively formed of the conductive material, the TC index of 1 reduces cracks to a considerable level.

[0063] Here, the insulating material may be, for example, a PID (Photo Imageable Dielectric) material or a photosensitive polyimide (PSPI). The PID material may be, for example, PHS (Polyhydroxystyrene), The insulating material may be any one selected from PBO (Polybenzoxazole) and PI (Polyimide). Also, the PI (Polyimide) may be a negative photosensitive insulating material or a positive photosensitive insulating material. However, the insulating material is not limited to the above-listed materials.

[0064] Here, the conductive material constituting each of the first redistribution pattern 330 and the second redistribution pattern 430 may be, but is not limited to, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy of the metals. In general, each of the first redistribution pattern 330 and the second redistribution pattern 430 may include copper (Cu).

[0065] Here, U T is about 1 mJ / mm 3 ~110mJ / mm 3 and the α 1 is about 40 ppm / ℃ to 70 ppm / ℃, and the α 2is about 16.7 ppm / ° C., which is the thermal expansion coefficient of copper (Cu), the ΔT is 175° C. or 215° C., and the E is about 2 Gpa to 4 Gpa.

[0066] The value of ΔT may be different between harsh conditions and extreme conditions. For example, the harsh conditions indicate a temperature characteristic test (temperature cycling) with temperature changes from -55°C to 120°C, and the extreme conditions indicate a temperature characteristic test with temperature changes from -65°C to 150°C.

[0067] In another embodiment, each of the first redistribution insulating layer 310 and the second redistribution insulating layer 410 may include an insulating material in which K satisfies 20 or more in the following TC index 2. [TC Index 2]

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[0068] Specifically, in FIG. 1 indicates the vertical distance from the bottom surface of the first semiconductor chip 100 to the top surface of the external connection terminal 600, and d 2 indicates the vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the first insulating layer 312, and d 3 indicates the vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the second insulating layer 314. That is, d2 Instead of d 3 can be substituted.

[0069] [Table 1]

[0070] In some embodiments, according to Table 1 and Figure 3, it can be seen that the occurrence of cracks is reduced in an insulating material having K of 20 or more in the TC index 2. It can be seen that the occurrence of cracks is significantly reduced in an insulating material having K of 40 or more in the TC index 2.

[0071] When selecting an insulating material based on K according to the TC index 2, it is concluded that it is preferable to use a negative photosensitive PI. That is, the negative photosensitive PI is a material constituting each of the first redistribution insulating layer 310 and the second redistribution insulating layer 410, and is found to have high reliability.

[0072] In this manner, K according to the TC index (hereinafter referred to as TC index 1 and 2) can be obtained through quantified values ​​related to various materials constituting the first redistribution structure 300 and the second redistribution structure 400.

[0073] Ultimately, the semiconductor package 1000 according to the technical concept of the present invention has the effect of improving reliability by forming the first redistribution insulating layer 310 included in the first redistribution structure 300 and the second redistribution insulating layer 410 included in the second redistribution structure 400 from an optimal insulating material that can prevent physical damage by taking into account various physical properties due to the TC index.

[0074] 4 to 6 are graphs showing the degree of crack occurrence depending on various physical properties of insulating materials constituting an insulating layer included in a redistribution structure.

[0075] 4 to 6 show the crack occurrence ratio according to elongation, the crack occurrence ratio according to resistance to fracture, and the crack occurrence ratio according to the TC index of the present invention, respectively.

[0076] In Figure 4, the elongation rate was measured when the insulating material was at about -55°C (the lowest temperature under severe conditions). Looking at the crack occurrence rate according to the elongation rate, it can be seen that the crack occurrence rate significantly decreases as the elongation rate, which is a physical property of the insulating material, increases. That is, the crack occurrence frequency (unit: %) was measured to be about 100%, about 0% to 8%, and about 0% at elongation rates (unit: %) of about 38%, about 18%, and about 40%.

[0077] In FIG. 5, the measurement of the fracture resistance was carried out when the insulating material was at about -55°C (the lowest temperature under severe conditions). Looking at the crack occurrence rate due to the fracture resistance, it can be seen that the crack occurrence rate is significantly reduced as the fracture resistance, which is a physical property of the insulating material, increases. In other words, the fracture resistance (unit: mJ / mm 3 ) is about 0 mJ / mm 3 point, approximately 200,000mJ / mm 3 point, and approximately 1,080,000 mJ / mm 3 The crack occurrence frequency (unit: %) at the points was measured to be about 100%, about 0% to 10%, and about 0%. Here, the fracture resistance can be applied as a physical property substantially the same as the toughness.

[0078] In Fig. 6, the TC index of the present invention was measured under the condition that the insulating material was at about -55°C (the lowest temperature of the severe conditions). Looking at the crack occurrence rate according to the TC index of the present invention, it can be seen that the crack occurrence rate is significantly reduced as the TC index of the present invention increases in the insulating material. That is, the crack occurrence frequency (unit: %) was measured to be about 0% to 6%, about 0% to 8%, and about 0% at about 8 points, about 19 points, and about 39 points of the TC index of the present invention (unit: arbitrary unit).

[0079] In other words, the TC index of the present invention provides the probability that the first redistribution insulating layer 310 included in the first redistribution structure 300 and the second redistribution insulating layer 410 included in the second redistribution structure 400 can be constructed of an optimal insulating material that can prevent physical damage by taking into account various physical properties, thereby improving the reliability of the semiconductor package 1000 (see FIG. 1).

[0080] Fig. 7 is a cross-sectional view showing the main structure of a semiconductor package according to another embodiment of the technical concept of the present invention, and Fig. 8 is an enlarged cross-sectional view showing a portion BB in Fig. 7.

[0081] Most of the components and materials constituting the semiconductor package 1100 described below are substantially the same as or similar to those previously described with reference to Figures 1 to 3. Therefore, for ease of explanation, the following description will focus on the differences from the integrated circuit semiconductor package 1000 described above.

[0082] Referring to both Figures 7 and 8, a semiconductor package 1100 may include a first semiconductor chip 100, a first redistribution structure 300 disposed under the first semiconductor chip 100, and an encapsulant 250 surrounding the first semiconductor chip 100 on the top surface of the first redistribution structure 300.

[0083] The semiconductor package 1100 may also be a fan-out semiconductor package in which the horizontal width and horizontal area of ​​the first redistribution structure 300 are greater than the horizontal width and horizontal area of ​​the first semiconductor chip 100. In some embodiments, the semiconductor package 1100 may also be a fan-out wafer-level package or a fan-out panel-level package.

[0084] The first redistribution structure 300 may include a first redistribution insulating layer 310 and a plurality of first redistribution patterns 330. The first redistribution insulating layer 310 may surround the plurality of first redistribution patterns 330. In some embodiments, the first redistribution structure 300 may include a plurality of stacked first redistribution insulating layers 310. For example, the plurality of first redistribution insulating layers 310 may include, but are not limited to, a first insulating layer 312, a second insulating layer 314, and a third insulating layer 316 in sequence. The first redistribution insulating layer 310 may be made of, for example, a PID material.

[0085] The plurality of first redistribution patterns 330 may include a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334. The plurality of first redistribution line patterns 332 may be disposed on at least one of an upper surface and a lower surface of the first redistribution insulating layer 310. The plurality of first redistribution vias 334 may be connected to some of the plurality of first redistribution line patterns 332 by penetrating the first redistribution insulating layer 310.

[0086] Among the first redistribution patterns 330, a portion disposed adjacent to the lower surface of the first redistribution structure 300 is referred to as a plurality of first lower surface connection pads 330P1, and a portion disposed adjacent to the upper surface of the first redistribution structure 300 is referred to as a plurality of first upper surface connection pads 330P2.

[0087] A plurality of external connection terminals 600 may be attached to the first lower connection pads 330P1. The plurality of external connection terminals 600 may connect the semiconductor package 1100 to the outside.

[0088] In some embodiments, a plurality of under bump metals UBM may be disposed between the first lower connection pads 330P1 and the external connection terminals 600. That is, a plurality of under bump metals UBM may be disposed under the first lower connection pads 330P1, and a plurality of external connection terminals 600 may be disposed under the plurality of under bump metals UBM.

[0089] In some embodiments, a plurality of external connection terminals 600 may be attached to some of the first lower connection pads 330P1, and a passive element 610 may be attached to another of the first lower connection pads 330P1.

[0090] At least one first semiconductor chip 100 may be mounted on the first redistribution structure 300. That is, the first semiconductor chip 100 may be a single chip or a plurality of chip pads 120. The first semiconductor chip 100 may include a semiconductor substrate 110 having an active surface and a non-active surface facing each other, a semiconductor element 112 formed on the active surface of the semiconductor substrate 110, and a plurality of chip pads 120 disposed on a first surface of the first semiconductor chip 100.

[0091] A plurality of chip connecting members 130 may be interposed between the plurality of chip pads 120 of the first semiconductor chip 100 and some of the plurality of first top connection pads 330P2 of the first redistribution structure 300. The plurality of chip connecting members 130 may include bump layers 132 disposed on the plurality of chip pads 120 and internal connection terminals 134 covering the bump layers 132.

[0092] The encapsulant 250 may surround the first semiconductor chip 100 on the top surface of the first redistribution structure 300. The encapsulant 250 may form the exterior of the semiconductor package 1100. For example, the encapsulant 250 may be a molding member containing an epoxy molding compound. The encapsulant 250 may further include a filler.

[0093] In some embodiments, an internal underfill layer 150 surrounding the plurality of chip connecting members 130 may be interposed between the first semiconductor chip 100 and the first redistribution structure 300. In some embodiments, the internal underfill layer 150 may fill a space between the first semiconductor chip 100 and the first redistribution structure 300 and cover a lower portion of a side surface of the first semiconductor chip 100.

[0094] In some embodiments, the first redistribution insulating layer 310 may include an insulating material having K of 20 or more in the following TC index 1: [TC Index 1]

number

[0095] The inventors have found that when the first redistribution insulating layer 310 is made of the insulating material and the first redistribution pattern 330 is made of the conductive material, the TC index of 1 results in a significant reduction in cracks.

[0096] Here, the insulating material may be, for example, a PID material or a photosensitive polyimide. The PID material may be, for example, any one selected from PHS, PBO, and PI. The PI may be a negative photosensitive insulating material or a positive photosensitive insulating material. However, the insulating material is not limited to the above-listed materials.

[0097] Here, the conductive material constituting the first redistribution pattern 330 may be, but is not limited to, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy of the metals. In general, the first redistribution pattern 330 may include copper (Cu).

[0098] Here, U T is about 1 mJ / mm 3 ~110mJ / mm 3and the α 1 is about 40 ppm / ℃ to 70 ppm / ℃, and the α 2 is the thermal expansion coefficient of copper (Cu), which is about 16.7 ppm / ° C., the ΔT is 175° C. or 215° C., and the E is about 2 Gpa to 4 Gpa.

[0099] In another embodiment, the first redistribution insulating layer 310 may include an insulating material in which K satisfies 20 or more in the following TC index 2. [TC Index 2]

number

[0100] Specifically, in FIG. 1 indicates the vertical distance from the bottom surface of the first semiconductor chip 100 to the top surface of the external connection terminal 600, and d 2 indicates the vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the first insulating layer 312, and d 3 indicates the vertical distance from the bottom surface of the first semiconductor chip 100 to the bottom surface of the second insulating layer 314. That is, d 2 Instead of d 3 can be substituted.

[0101] Ultimately, the semiconductor package 1100 according to the technical concept of the present invention has an effect of improving reliability by forming the first redistribution insulating layer 310 included in the first redistribution structure 300 from an optimal insulating material that can prevent physical damage by taking into account various physical properties due to the TC index.

[0102] FIG. 9 is a flow chart showing a method for manufacturing a semiconductor package according to an embodiment of the technical concept of the present invention.

[0103] Referring to FIG. 9, a method for manufacturing a semiconductor package (S1000) may include a process sequence of first to seventh steps (S110 to S170).

[0104] When an embodiment is implemented differently, the order of certain steps may be performed differently than that described. For example, two steps described in succession may be performed substantially simultaneously or may be performed in the reverse order from that described.

[0105] A method for manufacturing a semiconductor package according to the technical concept of the present invention (S1000) may include a first step (S110) of selecting an insulating material using a TC index, a second step (S120) of forming a first redistribution structure including the selected insulating material, a third step (S130) of mounting a first semiconductor chip on the first redistribution structure, a fourth step (S140) of forming an encapsulant to cover the first semiconductor chip, a fifth step (S150) of forming a second redistribution structure including the selected insulating material on the encapsulant, a sixth step (S160) of mounting a second semiconductor chip on the second redistribution structure, and a seventh step (S170) of cutting a substrate structure including a plurality of first and second semiconductor chips to form respective semiconductor packages.

[0106] The technical features relating to each of the first to seventh steps (S110 to S170) will be described in detail below with reference to FIGS.

[0107] 10 to 22 are cross-sectional views showing a method for manufacturing a semiconductor package according to an embodiment of the technical concept of the present invention in a process sequence.

[0108] Referring to FIG. 10, a first redistribution insulating layer 310 and a first redistribution structure 300 including a plurality of first redistribution patterns 330 consisting of a plurality of first redistribution line patterns 332 and a plurality of first redistribution vias 334 are formed on a carrier substrate CS.

[0109] The insulating material constituting the first redistribution insulating layer 310 may be selected as an optimal insulating material capable of preventing physical damage in consideration of various physical properties according to the TC index of the present invention.

[0110] The carrier substrate CS may be a semiconductor substrate, a glass substrate, a ceramic substrate, or a plastic substrate. In some embodiments, the first redistribution structure 300 may be formed by attaching a release film onto the carrier substrate CS.

[0111] A first redistribution line pattern 332 may be formed on the carrier substrate CS. The first redistribution line pattern 332 formed on the carrier substrate CS also includes a plurality of first lower surface connection pads 330P1.

[0112] Then, a first preliminary redistribution insulating layer covering the first redistribution line pattern 332 may be formed on the carrier substrate CS, and a portion of the first preliminary redistribution insulating layer may be removed by an exposure process and a development process to form a first insulating layer 312 having a plurality of first via holes. The plurality of first via holes may be formed to have a horizontal width that narrows from an upper surface to a lower surface of the first insulating layer 312. In some embodiments, the lower surfaces of the plurality of first lower surface connection pads 330P1 and the first insulating layer 312 may be formed to be coplanar.

[0113] Then, a first redistribution conductive layer may be formed on the second insulating layer 314, and the first redistribution conductive layer may be patterned to form a first redistribution pattern 330 including a first redistribution line pattern 332 and a first redistribution via 334. The first redistribution via 334 is also a portion of the first redistribution pattern 330 that fills the plurality of first via holes, and the first redistribution line pattern 332 is also a portion of the first redistribution pattern 330 that is above the upper surface of the second insulating layer 314.

[0114] Then, a third insulating layer 316 and a first redistribution pattern 330 may be formed to form a first redistribution structure 300. The first redistribution line pattern 332 disposed on the upper surface of the first redistribution structure 300 also serves as a plurality of first upper connection pads 330P2. In some embodiments, when the first redistribution insulating layer 310 is formed to sequentially include a first insulating layer 312, a second insulating layer 314, and a third insulating layer 316, the plurality of first upper connection pads 330P2 also serves as a first redistribution line pattern 332 formed to be disposed on an upper surface of the third insulating layer 316.

[0115] Referring to FIG. 11, a plurality of conductive posts 200 are formed to be electrically connected to a plurality of first upper connection pads 330P2 disposed in an outer region of a first redistribution structure 300. As shown in FIG.

[0116] The conductive posts 200 may be formed by electroplating. A single plating process using a photoresist (not shown) and an exposure process and a development process may form the conductive posts 200 having a desired shape. In some embodiments, the conductive material may include, but is not limited to, copper (Cu) or a copper (Cu) alloy.

[0117] Specifically, the first upper surface connection pads 330P2 function as a seed layer for forming the conductive posts 200. That is, when the conductive posts 200 are formed by an electroplating process, the first upper surface connection pads 330P2 provide a path through which current flows, so that the conductive posts 200 may be formed on the first upper surface connection pads 330P2.

[0118] Referring to FIG. 12, a first semiconductor chip 100 including a plurality of chip pads 120 is mounted on a first redistribution structure 300 .

[0119] The first semiconductor chip 100 may be mounted on the first redistribution structure 300 such that a plurality of chip connecting members 130 are interposed between the plurality of chip pads 120 and some of the plurality of first upper surface connecting pads 330P2 of the first redistribution structure 300.

[0120] The first semiconductor chip 100 may be mounted on the chip mounting region of the first redistribution structure 300 so as to be horizontally spaced apart from the plurality of conductive posts 200. Specifically, a plurality of chip connecting members 130 each including a bump layer 132 and an internal connecting terminal 134 covering the bump layer 132 may be formed on a plurality of chip pads 120 of the first semiconductor chip 100, and the first semiconductor chip 100 having the plurality of chip connecting members 130 formed thereon may be mounted on the first redistribution structure 300.

[0121] The inner underfill layer 150 may be formed to fill the space between the first semiconductor chip 100 and the first redistribution structure 300. The inner underfill layer 150 may be formed to surround the plurality of chip connecting members 130.

[0122] Referring to FIG. 13, an encapsulant 250 is formed to cover the first semiconductor chip 100 and the conductive posts 200 .

[0123] The encapsulant 250 may be formed to have an upper surface located at a vertical level higher than the uppermost ends of the conductive posts 200 so as to cover all of the upper surfaces of each of the conductive posts 200 .

[0124] Then, a portion of the encapsulant 250 is removed to expose the conductive posts 200. That is, a portion of the upper portion of the encapsulant 250 may be removed by a chemical mechanical polishing (CMP) process. The encapsulant 250 may be made of a molding material including an epoxy molding compound.

[0125] Referring to FIG. 14, a second redistribution insulating layer 410 is formed on the plurality of conductive posts 200 and the encapsulant 250, and a second redistribution structure 400 including a plurality of second redistribution patterns 430 consisting of a plurality of second redistribution line patterns 432 and a plurality of second redistribution vias 434 is formed.

[0126] The insulating material constituting the second redistribution insulating layer 410 may be selected as an optimal insulating material capable of preventing physical damage in consideration of various physical properties according to the TC index of the present invention.

[0127] After forming the second preliminary redistribution insulating layer on the conductive posts 200 and the encapsulant 250, a portion of the second preliminary redistribution insulating layer may be removed by an exposure process and a development process to form a fourth insulating layer 412 having a plurality of second via holes. In some embodiments, the lower surfaces of the plurality of second lower surface connection pads 430P1 and the lower surface of the fourth insulating layer 412 may be formed to be coplanar.

[0128] The plurality of second via holes may be formed to have a horizontal width that narrows from the upper surface to the lower surface of the fourth insulating layer 412. After a second redistribution conductive layer is formed on the fifth insulating layer 414, the second redistribution conductive layer may be patterned to form a second redistribution pattern 430 including a second redistribution line pattern 432 and a second redistribution via 434.

[0129] The second redistribution vias 434 formed on the conductive posts 200 also serve as the second lower surface connection pads 430P1. The second redistribution vias 434 also serve as a portion of the second redistribution pattern 430 that fills the second via holes, and the second redistribution line pattern 432 also serves as a portion of the second redistribution pattern 430 that is above the upper surface of the fifth insulating layer 414.

[0130] Then, a sixth insulating layer 416 and a second redistribution pattern 430 may be formed to form the second redistribution structure 400. The second redistribution line pattern 432 disposed on the upper surface of the second redistribution structure 400 also serves as a plurality of second upper connection pads 430P2. In some embodiments, when the second redistribution insulating layer 410 is formed to sequentially include a fourth insulating layer 412, a fifth insulating layer 414, and a sixth insulating layer 416, the second upper connection pads 430P2 also serve as the second redistribution line pattern 432 formed to be disposed on the upper surface of the sixth insulating layer 416.

[0131] Referring to FIG. 15, a substrate structure SS formed on a carrier substrate CS is provided.

[0132] For the sake of convenience, the manufacturing process for one first semiconductor chip 100 has been described above, but in reality, a substrate structure SS in which a plurality of first semiconductor chips 100 are arranged horizontally or in a matrix on a carrier substrate CS may be formed. That is, the manufacturing process has been described with reference to FIGS. 10 to 14, focusing on the CC portion of FIG. 15.

[0133] Therefore, in the following description of the manufacturing process, the process of manufacturing the substrate structures SS including the plurality of first semiconductor chips 100 as the respective semiconductor packages 1000 (see FIG. 22) will be mainly described.

[0134] Referring to FIG. 16, the exposed surface of the substrate structure SS may be attached to a dicing film 10 .

[0135] The dicing film 10 may include a base layer 11, an intermediate layer 13 on the base layer 11, and an adhesive layer 15 on the intermediate layer 13. Here, the dicing film 10 has a first diameter. The first diameter is greater than a second diameter of the substrate structure SS. The second diameter is the diameter of a wafer constituting the substrate structure SS, and corresponds to, for example, about 300 mm (12 inches) or about 450 mm (18 inches).

[0136] The exposed surface of the substrate structure SS to which the carrier substrate CS is attached may be mounted so as to be adhered onto the adhesive layer 15 of the dicing film 10. As shown in the figure, an edge of the adhesive layer 15 of the dicing film 10 may be fixed to a lower portion of a frame 20. The frame 20 has a circular ring shape, but is not limited thereto. When the substrate structure SS to which the carrier substrate CS is attached is attached onto the adhesive layer 15 of the dicing film 10, the second redistribution structure 400 formed on the substrate structure SS may be attached to face the adhesive layer 15.

[0137] Referring to FIG. 17, the carrier substrate CS can be separated from the substrate structure SS.

[0138] In order to separate and remove the carrier substrate CS, the carrier substrate CS can be irradiated with a laser P1, which weakens the bonding force between the substrate structure SS and the carrier substrate CS, so that the carrier substrate CS can be completely separated.

[0139] To facilitate the separation of the carrier substrate CS, an adhesive layer (not shown) may be disposed between the carrier substrate CS and the substrate structure SS, said adhesive layer also being in a liquid or gel form that is easily deformable by a predetermined heat due to irradiation with the laser P1.

[0140] 18, a plurality of external connection terminals 600 are attached to some of the first lower connection pads 330P1, and a passive element 610 is attached to another of the first lower connection pads 330P1.

[0141] A reflow process may be performed to attach the external connection terminals 600 and the passive elements 610 to the first lower connection pads 330P1. After the solder constituting the external connection terminals 600 melts through the reflow process, it is not broken down and may be arranged in a ball shape on the first lower connection pads 330P1 due to surface tension. In some embodiments, an intermetallic compound may be formed at the interface between the external connection terminals 600 and the first lower connection pads 330P1.

[0142] An outer underfill layer 650 may then be filled between the passive components 610 and the first redistribution structure 300. The outer underfill layer 650 may surround the sidewalls of the solder bumps 630 disposed under the passive components 610 and fill the gaps between adjacent solder bumps 630.

[0143] Referring to FIG. 19, various components including the first redistribution structure 300 of the substrate structure SS may be cut P2 along the dicing line DL.

[0144] Since the substrate structure SS is a fan-out wafer level package or a fan-out panel level package, various types of material films including the first redistribution structure 300 may be cut P2 by the dicing line DL to physically separate the substrate structure SS into individual semiconductor dies. Although only one dicing line DL is illustrated in the drawings, the present invention is not limited thereto.

[0145] Referring to FIG. 20, a pressure P3 may be applied to the bottom of the dicing film 10 to expand the surface area of ​​the dicing film 10.

[0146] In some embodiments, a jig (not shown) may be attached under the dicing film 10 and the jig may be pushed up to expand the dicing film 10. That is, a mechanical pressure P3 may be applied to the lower portion of the dicing film 10.

[0147] By expanding the dicing film 10, the substrate structure SS (see FIG. 19) may be physically separated into the first and second semiconductor dies SD1 and SD2 along the dicing line DL (see FIG. 19). Although only the first and second semiconductor dies SD1 and SD2 are illustrated in the drawings, the number of semiconductor dies is not limited thereto.

[0148] Referring to FIG. 21, a first semiconductor die SD1 can be picked up P4 from the dicing film 10 using a pick-up device.

[0149] In some embodiments, a wet cleaning process may be performed to remove adhesive residue remaining on the exposed surface of the first semiconductor die SD1 after the dicing film 10 is removed. The wet cleaning process may be performed using an organic solvent or an inorganic solvent depending on the material of the adhesive layer 15 constituting the dicing film 10.

[0150] Referring to FIG. 22, a second semiconductor chip 500 may be mounted to be electrically connected to the second redistribution structure 400 of the first semiconductor die SD1.

[0151] The second semiconductor chip 500 may be mounted on the second redistribution structure 400 such that the second pads 530 face the second redistribution structure 400. The second semiconductor chip 500 may be electrically connected to the first redistribution patterns 330 of the first redistribution structure 300 via the internal connection terminals 550 attached to the second pads 530, the second redistribution patterns 430, and the conductive posts 200. In this manner, the semiconductor package 1000 may be completed.

[0152] FIG. 23 is a schematic diagram showing the configuration of a semiconductor package according to an embodiment of the technical concept of the present invention.

[0153] Referring to FIG. 23, a semiconductor package 1200 may include a microprocessing unit 1210, a memory 1220, an interface 1230, a graphics processing unit 1240, a functional block 1250, and a bus 1260 connecting them.

[0154] The semiconductor package 1200 may include both a microprocessing unit 1210 and a graphics processing unit 1240, or may include only one of them.

[0155] The microprocessing unit 1210 may include a core and a cache. For example, the microprocessing unit 1210 may include multiple cores. The performance of each core of the multiple cores may be the same or different from each other. In addition, each core of the multiple cores may be activated simultaneously or may have different activation times.

[0156] The memory 1220 may store results of processing by the functional blocks 1250 under the control of the microprocessing unit 1210. The interface 1230 may transmit and receive information and signals to and from an external device. The graphic processing unit 1240 may perform a graphic function. For example, the graphic processing unit 1240 may perform a video codec or process 3D graphics. The functional blocks 1250 may perform various functions. For example, if the semiconductor package 1200 is an application processor used in a mobile device, some of the functional blocks 1250 may perform a communication function.

[0157] The semiconductor package 1200 may include the semiconductor package 1000 illustrated in FIG. 1 and / or the semiconductor package 1100 illustrated in FIG.

[0158] Although the embodiments of the technical concept of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0159] 100 First semiconductor chip 110 Semiconductor substrate 120 Chip Pad 130 Chip connecting member 150 Inner Underfill Layer 200 Conductive Post 250 Encapsulating material 300 1st wiring structure 310 First redistribution insulating layer 330 First rewiring pattern 400 2nd wiring structure 410 Second redistribution insulating layer 430 Second rewiring pattern 500 Second Semiconductor Chip 550 Internal connection terminal 600 External connection terminal 1000, 1100 Semiconductor Package

Claims

1. a first redistribution structure including a plurality of first redistribution patterns having a plurality of first lower surface connection pads and a plurality of first upper surface connection pads, and a first redistribution insulating layer surrounding the plurality of first redistribution patterns; a first semiconductor chip mounted in a first chip mounting area on the first rewiring structure; a plurality of first solder bumps attached to the plurality of first lower connection pads at a lower portion of the first redistribution structure; a second redistribution structure disposed on the first semiconductor chip and the first redistribution structure, the second redistribution structure including a plurality of second redistribution patterns having a plurality of second lower surface connection pads and a plurality of second upper surface connection pads, and a second redistribution insulating layer surrounding the plurality of second redistribution patterns; a second semiconductor chip mounted in a second chip mounting area on the second rewiring structure; a plurality of second solder bumps attached to the plurality of second upper surface connection pads between the second redistribution structure and the second semiconductor chip; a plurality of conductive posts connecting a portion of the plurality of first upper surface connecting pads and a portion of the plurality of second lower surface connecting pads and disposed around the first semiconductor chip; an encapsulant that fills a gap between the first redistribution structure and the second redistribution structure and surrounds the conductive posts and the first semiconductor chip; each of the first redistribution patterns and the second redistribution patterns is made of a conductive material; The semiconductor package, wherein the first redistribution insulating layer and the second redistribution insulating layer are each made of an insulating material having a TC index of 20 or more: [TC Index] [0010] Where: U Ｔ means the toughness of the insulating material, α １ means the coefficient of thermal expansion of the insulating material, α ２ means the thermal expansion coefficient of a conductive material surrounded by an insulating material; ΔT means the change in temperature, E denotes the elastic modulus of the insulating material.

2. 2. The semiconductor package of claim 1, wherein each of the first redistribution insulating layer and the second redistribution insulating layer includes a plurality of insulating layers, and each of the plurality of insulating layers has a thickness along a vertical direction of about 3 μm to 10 μm.

3. 2. The semiconductor package of claim 1, wherein the insulating material is a photo imageable dielectric (PID) material.

4. 4. The semiconductor package of claim 3, wherein the PID material is any one selected from the group consisting of polyhydroxystyrene (PHS), polybenzoxazole (PBO), and polyimide (PI).

5. 5. The semiconductor package of claim 4, wherein the PI (Polyimide) is a negative photosensitive insulating material or a positive photosensitive insulating material.

6. 2 . The semiconductor package according to claim 1 , wherein the conductive material constituting each of the first rewiring patterns and the second rewiring patterns is copper (Cu).

7. In the temperature cycling test of the semiconductor package, the temperature change is Approximately -55°C to 120°C, or 2. The semiconductor package according to claim 1, wherein the temperature is about -65°C to 150°C.

8. 8. The semiconductor package according to claim 7, wherein the ΔT in the insulating material is 175° C. or 215° C.

9. 2. The semiconductor package of claim 1, wherein in the insulating material, E is about 2 Gpa to 4 Gpa.

10. Each of the first redistribution insulating layer and the second redistribution insulating layer includes a plurality of insulating layers stacked in a vertical direction, The semiconductor package of claim 1 , wherein at least some of the insulating layers include insulating materials having different K values ​​in the TC index.

11. a redistribution layer including copper (Cu) and an insulating layer surrounding the redistribution layer; a semiconductor chip mounted on the rewiring structure and including connection pads; an internal connection terminal disposed between the redistribution structure and the semiconductor chip, electrically connecting the redistribution layer and the connection pad; an external connection terminal attached to a lower portion of the redistribution structure and electrically connected to the redistribution layer; an encapsulant surrounding the semiconductor chip and the internal connection terminals on the redistribution structure; The semiconductor package, wherein the insulating layer is made of an insulating material that satisfies the following TC index, K being 20 or more. [TC Index] [0025] Where: U Ｔ means the toughness of the insulating material, α １ means the thermal expansion coefficient of the insulating material, α ２ means the thermal expansion coefficient of copper (Cu), ΔT means the change in temperature, E denotes the elastic modulus of the insulating material.

12. Said U Ｔ is about 1 mJ / mm ３ ~110mJ / mm ３ and The a １ is about 40 ppm / °C to 70 ppm / °C, The a ２ is about 16.7 ppm / ° C., The ΔT is 175° C. or 215° C., 12. The semiconductor package of claim 11, wherein E is about 2 Gpa to 4 Gpa.

13. 13. The semiconductor package according to claim 12, wherein the insulating layer is made up of a plurality of layers, each of which has a thickness in a vertical direction of about 3 μm to 10 μm.

14. 12. The semiconductor package of claim 11, wherein the insulating material is a PID material selected from the group consisting of polyhydroxystyrene (PHS), polybenzoxazole (PBO), and polyimide (PI).

15. the insulating layer includes a plurality of vertically stacked layers; The semiconductor package of claim 11 , wherein at least some of the layers include insulating materials having different K values ​​in the TC index.

16. a redistribution structure including a first insulating layer, at least one second insulating layer on the first insulating layer, and a plurality of redistribution layers disposed on the first insulating layer and the at least one second insulating layer, respectively, and electrically connected to each other; a semiconductor chip mounted on the rewiring structure and including connection pads; an internal connection terminal disposed between the redistribution structure and the semiconductor chip, electrically connecting the redistribution layers and the connection pads; an external connection terminal attached to a lower portion of the redistribution structure and electrically connected to the plurality of redistribution layers; an encapsulant surrounding the semiconductor chip and the internal connection terminals on the redistribution structure; The semiconductor package, wherein each of the first insulating layer and the at least one second insulating layer is made of an insulating material having a TC index K of 20 or more. [TC Index] [0030] Where: U Ｔ means the toughness of the insulating material, α １ means the thermal expansion coefficient of the insulating material, α ２ means the thermal expansion coefficient of a conductive material surrounded by an insulating material; ΔT means the change in temperature, E is the elastic modulus of the insulating material; d １ means the vertical distance from the bottom surface of the semiconductor chip to the top surface of the external connection terminal, d ２ means the vertical distance from the bottom surface of the semiconductor chip to the bottom surface of the first insulating layer or the second insulating layer.

17. 17. The semiconductor package of claim 16, wherein an under bump metal is disposed on a lowermost redistribution layer among the plurality of redistribution layers, and the external connection terminal is attached to the under bump metal.

18. The above d １ is the above d ２ 20. The semiconductor package of claim 17, wherein the semiconductor package is equal to or larger than the

19. 17. The semiconductor package of claim 16, wherein the first insulating layer and the at least one second insulating layer each have a thickness in a vertical direction of about 3 μm to 10 μm.

20. The insulating material is a PID material including any one selected from the group consisting of PHS (Polyhydroxystyrene), PBO (Polybenzoxazole), and PI (Polyimide), 20. The semiconductor package of claim 19, wherein the first insulating layer and the at least one second insulating layer are made of different insulating materials.

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