Semiconductor element including bit line

Abstract

To provide a semiconductor device including a bit line.SOLUTION: A semiconductor device includes: a substrate including a first active region defined by a first element separation film; a bit line contact arranged on the first active region of the substrate; and a bit line that extends in a first direction on the substrate. The bit line includes a lower conductive layer arranged on the substrate and surrounding a sidewall of the bit line contact, and a metal line stack arranged on the lower conductive layer. The metal line stack includes a first conductive layer arranged on the lower conductive layer and the bit line contact and including a first metal material, a first intermediate layer arranged on the first conductive layer and including graphene, and a second conductive layer arranged on the first intermediate layer and including the first metal material.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including bit lines. [Background technology]

[0002] Due to downscaling of semiconductor devices, the size of individual fine circuit patterns for implementing semiconductor devices is further reduced. In addition, as integrated circuit devices become more highly integrated, the line width of bit lines is reduced and the spacing between bit lines is also reduced. Therefore, there is a problem that defects occur in the process of forming bit lines having reduced line widths. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the problems of the conventional technology described above, and an object of the present invention is to provide a semiconductor device that can prevent defects from occurring in the process of forming bit lines having a reduced line width. [Means for solving the problem]

[0004] In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a substrate including a first active region defined by a first element isolation film, a bit line contact disposed on the first active region of the substrate, and a bit line extending in a first direction on the substrate, the bit line including a lower conductive layer disposed on the substrate and surrounding a sidewall of the bit line contact, and a metal line stack disposed on the lower conductive layer, the metal line stack including a first conductive layer including a first metal material disposed on the lower conductive layer and the bit line contact, a first intermediate layer disposed on the first conductive layer and including graphene, and a second conductive layer disposed on the first intermediate layer and including the first metal material.

[0005] According to another aspect of the present invention, a semiconductor device is provided that includes a substrate including a first active region defined by a first element isolation film and a second active region defined by a second element isolation film, a bit line contact disposed on the first active region of the substrate, a bit line extending in a first direction on the substrate, and a peripheral circuit gate stack disposed on the second active region, the bit line including a lower conductive layer disposed on the substrate and surrounding a sidewall of the bit line contact, and a metal line stack disposed on the lower conductive layer, the metal line stack including a first conductive layer disposed on the lower conductive layer and on the bit line contact, a first intermediate layer disposed on the first conductive layer and including graphene, and a second conductive layer disposed on the first intermediate layer and including the first metal material.

[0006] According to yet another aspect of the present invention, a semiconductor device includes a substrate including a first active region defined by a first element isolation film, a bit line contact disposed in a bit line contact hole extending into the substrate and connected to the first active region of the substrate, a bit line extending in a first direction on the substrate, the bit line contact including a lower conductive layer disposed on the substrate, surrounding a sidewall of the bit line contact and extending in the first direction, a metal silicide film disposed on the lower conductive layer and extending in the first direction, and a metal silicide film disposed on the metal silicide film. the first conductive layer includes a first conductive layer, a second conductive layer, and a first intermediate layer, the first conductive layer including a first metallic material, the second conductive layer including the first metallic material, and the first intermediate layer including a metal line stack sandwiched between the first conductive layer and the second conductive layer, the metal line stack including graphene; bitline spacers disposed on sidewalls of the bitline and extending in the first direction; and wordlines disposed in wordline trenches extending in a second direction intersecting the first direction to intersect the first active region within the substrate. Effect of the Invention

[0007] According to the present invention, it is possible to suppress and prevent grain aggregation and / or grain overgrowth that may occur in bit lines due to heat treatment during the manufacturing process, thereby preventing localized defects in bit lines having reduced line widths. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a layout diagram showing a semiconductor device according to an exemplary embodiment. [Diagram 2] FIG. 2 is an enlarged layout diagram of part II in FIG. [Diagram 3] 3 is a cross-sectional view taken along line AA' in FIG. 2. [Figure 4] 3 is a cross-sectional view taken along line BB' in FIG. 2. [Diagram 5] 3 is a cross-sectional view taken along line CC' in FIG. 2. [Figure 6] FIG. 4 is an enlarged view of a portion CX1 in FIG. [Figure 7] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 8] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 9] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 10] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 11] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 12] 1 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment; [Figure 13A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 13B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 15A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 15B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 16A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 16B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 17A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 17B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 18A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 18B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 19A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 19B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 20A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 20B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 21A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 21B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 22A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 22B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Diagram 23] 1 is a graph illustrating X-ray photoelectron spectroscopy measurements of a metal line stack according to an example embodiment. [Figure 24]1 is a graph showing Raman spectra of a metal line stack according to an example embodiment. [Diagram 25] 1 is a graph showing the change in roughness before and after annealing of a metal line according to a comparative example and a metal line stack according to an embodiment. [Figure 26] 11 is a graph showing the change in resistivity before and after annealing of a metal line according to a comparative example and a metal line stack according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0010] FIG. 1 is a layout diagram showing a semiconductor device according to an exemplary embodiment. FIG. 2 is an enlarged layout diagram of a portion II in FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2. FIG. 4 is a cross-sectional view taken along line B-B' in FIG. 2. FIG. 5 is a cross-sectional view taken along line C-C' in FIG. 2. FIG. 6 is an enlarged view of a portion CX1 in FIG. 3.

[0011] 1 to 6, the semiconductor device 100 includes a substrate 110 including a cell array region MCA and a peripheral circuit region PCA. The cell array region MCA is a memory cell region of a DRAM device, and the peripheral circuit region PCA is a core region or a peripheral circuit region of the DRAM device. For example, the cell array region MCA includes a cell transistor and a capacitor structure CAP connected thereto, and the peripheral circuit region PCA includes a peripheral circuit transistor PTR for transmitting a signal and / or a power source to the cell transistor included in the cell array region MCA. In an exemplary embodiment, the peripheral circuit transistor PTR forms various circuits such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0012] An isolation trench 112T is formed in the substrate 110, and a first isolation film 112 and a second isolation film 112P are formed in the isolation trench 112T. A plurality of first active regions AC1 are defined in the cell array region MCA of the substrate 110 by the first isolation film 112, and a plurality of second active regions AC2 are defined in the peripheral circuit region PCA by the second isolation film 112P.

[0013] 2, in the cell array region MCA, a plurality of first active regions AC1 are arranged with their major axes in a first diagonal direction D1 inclined with respect to a first horizontal direction X and a second horizontal direction Y. A plurality of word lines WL extend parallel to each other along the first horizontal direction X across the first active regions AC1. A plurality of bit lines BL extend parallel to each other along the second horizontal direction Y on the plurality of word lines WL. The plurality of bit lines BL are connected to the plurality of first active regions AC1 via bit line contacts DC.

[0014] A plurality of buried contacts BC are formed between two adjacent bit lines BL among the plurality of bit lines BL. A plurality of landing pads LP are formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP serve to connect a lower electrode 182 of a capacitor structure CAP formed on the plurality of bit lines BL to the first active region AC1. The plurality of landing pads LP are arranged to partially overlap the buried contacts BC and the bit lines BL, respectively.

[0015] The substrate 110 includes silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 includes at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 110 includes a conductive region, such as an impurity doped well or impurity doped structure.

[0016] The first element isolation film 112 includes an oxide film, a nitride film, or a combination thereof. A first buffer insulating layer 114 and a second buffer insulating layer 116 are sequentially disposed on the upper surface of the substrate 110. Each of the first buffer insulating layer 114 and the second buffer insulating layer 116 includes silicon oxide, silicon oxynitride, or silicon nitride.

[0017] A plurality of word line trenches 120T extending in a first horizontal direction X are disposed in the substrate 110, and a buried gate structure 120 is disposed in the plurality of word line trenches 120T. The buried gate structure 120 includes a gate dielectric film 122, a gate electrode 124, and a word line capping layer 126 disposed in each of the plurality of word line trenches 120T. The plurality of gate electrodes 124 correspond to the plurality of word lines WL illustrated in FIG.

[0018] The gate dielectric films 122 include silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a higher dielectric constant than silicon oxide. The gate electrodes 124 include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The word line capping layers 126 include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0019] A plurality of bit line contact holes DCH extend into the substrate 110 through the first buffer insulating layer 114 and the second buffer insulating layer 116, and a plurality of bit line contacts DC are formed in the plurality of bit line contact holes DCH. The plurality of bit line contacts DC are coupled to the plurality of first active regions AC1. The plurality of bit line contacts DC include TiN, TiSiN, W, tungsten silicide, doped polysilicon, or a combination thereof. Bit line contact spacers DCS cover the underside of the bit line contacts DC within the bit line contact holes DCH.

[0020] A plurality of bit lines BL extend along a second horizontal direction Y on the substrate 110 and the plurality of bit line contacts DC. The plurality of bit lines BL are connected to the first active regions AC1 through the bit line contacts DC, respectively.

[0021] Each of the multiple bit lines BL includes a lower conductive layer 132 , a metal silicide film 134 , and a metal line stack 136 .

[0022] The lower conductive layer 132 extends in the second horizontal direction Y on the second buffer insulating layer 116, and the lower conductive layer 132 covers both side walls of the bit line contact DC. For example, as shown in Fig. 3, the upper surface of the lower conductive layer 132 is disposed flush with the upper surface of the bit line contact DC, and both side walls of the bit line contact DC contact the lower conductive layer 132. The lower conductive layer 132 includes Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0023] In an exemplary embodiment, in the process for forming the bit line contact hole DCH, a part of the lower conductive layer 132, a part of the second buffer insulating layer 116, a part of the first buffer insulating layer 114, and a part of the substrate 110 are removed to form a bit line contact DC in the bit line contact hole DCH, so that an upper side of the bit line contact DC contacts the lower conductive layer 132 and a lower side of the bit line contact DC contacts the substrate 110 (e.g., the first active region AC1).

[0024] The metal silicide film 134 is disposed on the upper surface of the lower conductive layer 132 and on the upper surface of the bit line contact DC, and extends in the second horizontal direction Y. In an exemplary embodiment, the lower conductive layer 132 includes polysilicon, and the metal silicide film 134 includes at least one of cobalt silicide, nickel silicide, and tungsten silicide. In some embodiments, a conductive barrier film of at least one of titanium, titanium nitride, and tantalum nitride is selectively further disposed on the metal silicide film 134.

[0025] The metal line stack 136 includes a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B, which are sequentially disposed on the metal silicide film 134. For example, the metal line stack 136 has a structure in which the first intermediate layer 138A is sandwiched between the first conductive layer 136A and the second conductive layer 136B.

[0026] In an example embodiment, the first conductive layer 136A includes a first metallic material, the first metallic material including any one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or alloys thereof. In some example embodiments, the first conductive layer 136A includes ruthenium.

[0027] In an exemplary embodiment, the first intermediate layer 138A includes graphene. In an exemplary embodiment, the graphene constituting the first intermediate layer 138A includes a plurality of grains having a two-dimensional structure. For example, each grain of the first intermediate layer 138A has a two-dimensional structure in which 1 to 15 layers of two-dimensional carbon sheets are stacked layer-by-layer. In an exemplary embodiment, the first intermediate layer 138A has a nanocrystalline structure, and the plurality of grains have a grain size of about 2 nm to 200 nm. In some exemplary embodiments, the first intermediate layer 138A has an average grain size of 10 nm or more.

[0028] In an exemplary embodiment, in terms of the bonding energy of carbon atoms contained in graphene, the first intermediate layer 138A has a bonding energy of 100%. 2 The graphene includes carbon atoms having bonds at a ratio of 50% to 99%. The bond energy of the carbon atoms included in the first intermediate layer 138A is measured using an analytical device such as X-ray photoelectron spectroscopy (XPS).

[0029] In an exemplary embodiment, the first intermediate layer 138A exhibits a carbon atomic D peak, a 2D peak, a D' peak, and a G peak, as measured by Raman spectroscopy, with the ratio of the D peak to the carbon atomic G peak being 3.0 or less, the ratio of the 2D peak to the G peak being 0.1 or more, and the ratio of the D' peak to the G peak being 1.0 or less, where the G peak is at about 1580 cm -1 The peak corresponds to a Raman shift value of about 1350 cm -1 The 2D peak corresponds to a Raman shift value of about 2700 cm -1 This peak corresponds to a Raman shift value of

[0030] In some exemplary embodiments, the second conductive layer 136B includes a first metallic material, the first metallic material including any one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or alloys thereof. In some exemplary embodiments, the second conductive layer 136B includes ruthenium.

[0031] In an exemplary embodiment, the first intermediate layer 138A is interposed between the first conductive layer 136A and the second conductive layer 136B and functions as an anti-agglomeration layer that inhibits grain coarsening or grain merging of the first metal material contained within the first conductive layer 136A and the second conductive layer 136B.

[0032] For example, in the case of a bit line BL according to a comparative example including a single layer of a metal material such as ruthenium, when the bit line BL has a reduced line width (e.g., when the bit line BL has a relatively thin line width, such as a line width narrower than 10 nm), the metal material such as ruthenium included in the bit line BL may undergo grain coarsening or grain merging during a subsequent process at high temperature. The bit line BL according to the comparative example is formed in a line pattern extending in the second horizontal direction Y, but after a subsequent process at high temperature, a portion of the bit line BL has a locally increased line width due to grain coarsening, and as a result, another portion of the bit line BL has a locally decreased line width or a region where the bit line BL is discontinuously disconnected is formed.

[0033] However, according to an exemplary embodiment, the first intermediate layer 138A is interposed between the first conductive layer 136A and the second conductive layer 136B and functions as an anti-agglomeration layer that suppresses grain coarsening or grain merging of the first metal material contained in the first conductive layer 136A and the second conductive layer 136B, thereby preventing grain coarsening of the first metal material contained in the first conductive layer 136A and the second conductive layer 136B even if the bit line BL has a reduced line width (or a relatively thin line width).

[0034] In an exemplary embodiment, the metal line stack 136 has a first thickness t10 in the vertical direction. The first conductive layer 136A has a second thickness t11 in the vertical direction Z, the first intermediate layer 138A has a third thickness t12 in the vertical direction Z, and the second conductive layer 136B has a fourth thickness t13 in the vertical direction Z. The second thickness t11 of the first conductive layer 136A corresponds to about 20% to 80% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fourth thickness t13 of the second conductive layer 136B corresponds to about 20% to 80% of the first thickness t10 of the metal line stack 136 in the vertical direction Z.

[0035] The third thickness t12 of the first intermediate layer 138A corresponds to about 5% to 50% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. For example, if the third thickness t12 of the first intermediate layer 138A is less than 5% of the first thickness t10, it is insufficient to suppress grain coarsening, and if the third thickness t12 of the first intermediate layer 138A is greater than 50% of the first thickness t10, the resistivity of the entire metal line stack 136 increases, degrading the electrical performance of the semiconductor device 100. In some exemplary embodiments, the third thickness t12 of the first intermediate layer 138A is 50 Å (angstroms) or less. In some exemplary embodiments, the third thickness t12 of the first intermediate layer 138A is 5 Å or more.

[0036] A plurality of bit line capping layers 140 are disposed on each of the plurality of bit lines BL. Each of the bit line capping layers 140 includes a first capping layer 142, a second capping layer 144, and a third capping layer 146 sequentially disposed on an upper surface of the plurality of bit lines BL. The first capping layer 142, the second capping layer 144, and the third capping layer 146 include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0037] A bit line spacer 150 is disposed on both side walls of each of the bit lines BL. The bit line spacer 150 includes a first spacer layer 152, a second spacer layer 154, and a third spacer layer 156. In an exemplary embodiment, the first spacer layer 152 and the third spacer layer 156 include silicon nitride, and the second spacer layer 154 includes silicon oxide. The first spacer layer 152, the second spacer layer 154, and the third spacer layer 156 are sequentially disposed on the side walls of the bit lines BL and the side walls of the bit line capping layer 140.

[0038] For example, the bit line spacer 150 is disposed on the sidewall of the bit line BL such that the first spacer layer 152 of the bit line spacer 150 contacts the metal line stack 136 of the bit line BL, and for example, the first spacer layer 152 extends in the vertical direction Z along the sidewalls of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B on the sidewalls of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B of the metal line stack 136.

[0039] A plurality of buried contacts BC are disposed between each of the plurality of bit lines BL. For example, the bottoms of the plurality of buried contacts BC are disposed in buried contact holes BCH extending into the substrate 110 between two adjacent bit lines BL, and the bottoms of the buried contacts BC contact the first active regions AC1. In an exemplary embodiment, the plurality of buried contacts BC include doped polysilicon.

[0040] Between two adjacent bit lines BL, a plurality of insulating fences (not shown) are arranged along the second horizontal direction Y. The plurality of insulating fences are arranged at positions vertically overlapping with the plurality of word line trenches 120T. In a plan view, a plurality of buried contacts BC and a plurality of insulating fences are mutually arranged between the two bit lines BL extending in the second horizontal direction Y.

[0041] A plurality of landing pads LP are disposed on the plurality of buried contacts BC. Each of the plurality of landing pads LP includes a conductive barrier film (not shown) and a landing pad conductive layer (not shown). The conductive barrier film includes Ti, TiN, or a combination thereof. The landing pad conductive layer includes a metal, a metal nitride, a conductive polysilicon, or a combination thereof. For example, the landing pad conductive layer includes W. The plurality of landing pads LP have a plurality of island-type pattern shapes in a plan view.

[0042] The landing pads LP are electrically insulated from one another by an insulating pattern 160 surrounding the landing pads LP. The insulating pattern 160 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0043] An etch stop layer 180 is disposed on the insulating pattern 160, and the etch stop layer 180 has an opening 180H. The opening 180H is disposed at a position corresponding to the landing pad LP, and the upper surface of the landing pad LP is disposed at the bottom of the opening 180H.

[0044] A capacitor structure CAP is disposed on the etching stop film 180. The capacitor structure CAP includes a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186. The lower electrode 182 is disposed such that a bottom of the lower electrode 182 is disposed in the opening 180H of the etching stop film 180 and the bottom of the lower electrode 182 is placed on the landing pad LP. The capacitor dielectric layer 184 is disposed to a thin thickness so as to conformally cover the lower electrode 182, and the upper electrode 186 is disposed on the capacitor dielectric layer 184.

[0045] A peripheral circuit transistor PTR is disposed on the second active region AC2 in the peripheral circuit area PCA. The peripheral circuit transistor PTR includes a gate dielectric layer 118, a peripheral circuit gate stack PGS, and a gate capping pattern 142P, which are sequentially stacked on the second active region AC2.

[0046] The gate dielectric layer 118 is disposed on the upper surface of the substrate 110. The gate dielectric layer 118 is at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an ONO (oxide / nitride / oxide), or a dielectric film having a higher dielectric constant than a silicon oxide film. The gate capping pattern 142P is disposed to cover an upper surface of the peripheral circuit gate stack PGS. In an exemplary embodiment, the gate capping pattern 142P includes a silicon nitride film.

[0047] The peripheral circuit gate stack PGS includes a peripheral lower conductive layer 132P, a peripheral metal silicide film 134P, and a peripheral metal line stack 136P.

[0048] The peripheral lower conductive layer 132P is disposed on the gate dielectric layer 118 and includes Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. The peripheral metal silicide film 134P is disposed on an upper surface of the peripheral lower conductive layer 132P. In an exemplary embodiment, the peripheral metal silicide film 134P includes at least one of cobalt silicide, nickel silicide, and tungsten silicide. In some embodiments, a conductive barrier film of at least one of titanium, titanium nitride, and tantalum nitride is further disposed on the peripheral metal silicide film 134P.

[0049] The peripheral metal line stack 136P includes a first peripheral conductive layer 136AP, a first peripheral intermediate layer 138AP, and a second peripheral conductive layer 136BP, which are sequentially disposed on the peripheral metal silicide film 134P. For example, the peripheral metal line stack 136P has a structure in which the first peripheral intermediate layer 138AP is sandwiched between the first peripheral conductive layer 136AP and the second peripheral conductive layer 136BP.

[0050] In an example embodiment, the first peripheral conductive layer 136AP includes a first metallic material, the first metallic material including any one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or alloys thereof. In some example embodiments, the first peripheral conductive layer 136AP includes ruthenium.

[0051] In an exemplary embodiment, the first peripheral intermediate layer 138AP includes graphene. In an exemplary embodiment, the graphene constituting the first peripheral intermediate layer 138AP includes a plurality of grains having a two-dimensional structure. For example, each grain of the first peripheral intermediate layer 138AP has a two-dimensional structure in which 1 to 15 layers of two-dimensional carbon sheets are stacked layer-by-layer. In an exemplary embodiment, the first peripheral intermediate layer 138AP has a nanocrystalline structure, and the plurality of grains have a grain size of about 2 nm to 200 nm. In some exemplary embodiments, the first peripheral intermediate layer 138AP has an average grain size of 10 nm or more.

[0052] In an exemplary embodiment, in terms of the bonding energy of carbon atoms contained in graphene, the first peripheral intermediate layer 138AP has a bonding energy of 100% of all carbon atoms. 2 The graphene includes carbon atoms having bonds at a ratio of 50% to 99%. The bond energy of the carbon atoms included in the first peripheral intermediate layer 138AP is measured using an analytical device such as X-ray photoelectron spectroscopy (XPS).

[0053] In an exemplary embodiment, the first peripheral intermediate layer 138AP exhibits a carbon atomic D peak, a 2D peak, a D' peak, and a G peak, as measured by Raman spectroscopy, with the ratio of the D peak to the carbon atomic G peak being 3.0 or less, the ratio of the 2D peak to the G peak being 0.1 or more, and the ratio of the D' peak to the G peak being 1.0 or less, where the G peak is at about 1580 cm -1 The peak corresponds to a Raman shift value of about 1350 cm -1 The 2D peak corresponds to a Raman shift value of about 2700 cm -1 This peak corresponds to a Raman shift value of

[0054] In some exemplary embodiments, the second peripheral conductive layer 136BP includes a first metallic material, the first metallic material including any one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or alloys thereof. In some exemplary embodiments, the second peripheral conductive layer 136BP includes ruthenium.

[0055] In an exemplary embodiment, the peripheral metal line stack 136P has a first thickness t20 in the vertical direction. The first peripheral conductive layer 136AP has a second thickness t21 in the vertical direction Z, the first peripheral intermediate layer 138AP has a third thickness t22 in the vertical direction Z, and the second peripheral conductive layer 136BP has a fourth thickness t23 in the vertical direction Z. The second thickness t21 of the first peripheral conductive layer 136AP corresponds to about 20% to 80% of the first thickness t20 of the peripheral metal line stack 136P in the vertical direction Z. The fourth thickness t23 of the second peripheral conductive layer 136BP corresponds to about 20% to 80% of the first thickness t20 of the peripheral metal line stack 136P in the vertical direction Z.

[0056] The third thickness t22 of the first peripheral intermediate layer 138AP corresponds to about 5% to 50% of the first thickness t20 of the peripheral metal line stack 136P in the vertical direction Z. For example, if the third thickness t22 of the first peripheral intermediate layer 138AP is less than 5% of the first thickness t20, it is not thick enough to suppress grain coarsening, and if the third thickness t22 of the first peripheral intermediate layer 138AP is thicker than 50% of the first thickness t20, the resistivity of the entire peripheral metal line stack 136P increases, degrading the electrical performance of the semiconductor device 100. In some exemplary embodiments, the third thickness t22 of the first peripheral intermediate layer 138AP is 50 Å or less. In some exemplary embodiments, the third thickness t22 of the first peripheral intermediate layer 138AP is 5 Å or more.

[0057] In an exemplary embodiment, the constituent materials of the peripheral lower conductive layer 132P, the peripheral metal silicide film 134P, the first peripheral conductive layer 136AP, the first peripheral intermediate layer 138AP, and the second peripheral conductive layer 136BP are the same as the constituent materials of the lower conductive layer 132, the metal silicide film 134, the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B included in the bit line BL in the cell array region MCA. For example, the peripheral circuit gate stack PGS is formed simultaneously with the process of forming the bit line BL, but the technical idea of ​​the present invention is not limited thereto.

[0058] Both side walls of the peripheral circuit gate stack PGS and the gate capping pattern 142P are covered with an insulating spacer 150P. The insulating spacer 150P includes an oxide film, a nitride film, or a combination thereof. The peripheral circuit transistor PTR and the insulating spacer 150P are covered by a protective layer 144P, and a first interlayer insulating film 148 is disposed on the protective layer 144P to fill the space between two adjacent peripheral circuit transistors PTR. A capping insulating layer 146P is disposed on the first interlayer insulating film 148 and the protective layer 144P.

[0059] In the peripheral circuit region PCA, contact plugs PCT are formed in contact holes PCTH vertically penetrating the first interlayer insulating film 148 and the capping insulating layer 146P. The contact plugs PCT include a conductive barrier film and a landing pad conductive layer, the same as the landing pads LP formed in the cell array region MCA. A metal silicide film (not shown) is interposed between the second active region AC2 and the contact plugs PCT. An upper interlayer insulating film 190 is disposed on the capping insulating layer 146P to cover the contact plugs PCT.

[0060] Generally, since there is a problem that the resistance of the bit lines BL increases as the line width of the bit lines BL decreases, a technology is being attempted in which a metal material with low resistivity, for example, a metal material such as ruthenium, is used as the bit lines BL. However, when a metal material such as ruthenium is patterned to have a relatively narrow line width, grain coarsening or grain merging occurs in a subsequent high temperature process, causing a significant increase in roughness of the metal material layer, resulting in localized areas of increased line width, areas of decreased line width, and / or disconnected regions.

[0061] However, according to an exemplary embodiment, the metal line stack 136 includes a first intermediate layer 138A including graphene interposed between the first conductive layer 136A and the second conductive layer 136B, and the first intermediate layer 138A prevents grains of the metal material in the first conductive layer 136A and the second conductive layer 136B from coarsening, and therefore the bit line BL has low resistance, while preventing the occurrence of localized line width increase regions, line width decrease regions, and / or line cut regions in the bit line BL during the formation process of the semiconductor device 100, and therefore the semiconductor device 100 has excellent electrical characteristics.

[0062] The crystallinity and physical properties of the metal line stacks contained within the bit lines will now be described in detail with reference to FIGS.

[0063] FIG. 23 is a graph illustrating X-ray photoelectron spectroscopy measurements of a metal line stack in accordance with an example embodiment.

[0064] Referring to FIG. 23, the metal line stack according to the embodiment has a laminated structure of a first conductive layer made of a first metal material, a first intermediate layer made of graphene, and a second conductive layer made of the first metal material. In the metal line stack according to the embodiment, the first intermediate layer is formed to a thickness corresponding to about 10% of the total thickness of the metal line stack. In FIG. 23, an intermediate structure is formed in which a first conductive layer is formed using ruthenium as the first metal material, and a first intermediate layer is formed on the first conductive layer using graphene, and the binding energy between carbon atoms and ruthenium metal atoms of the intermediate structure is measured by X-ray photoelectron spectroscopy. As shown in FIG. 23, the sp 2 It can be seen that the peaks were measured at relatively high intensity, and it can be seen that the graphene layer formed on the metal material layer such as ruthenium has a layered structure.

[0065] FIG. 23 illustrates the binding energy of the first intermediate layer including graphene using X-ray photoelectron spectroscopy as an example. However, in addition to X-ray photoelectron spectroscopy, the atomic binding energy of a structure in which the first intermediate layer is interposed between the first conductive layer and the second conductive layer can be analyzed using an analytical device such as a transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS).

[0066] FIG. 24 is a graph illustrating a Raman spectrum of a metal line stack in accordance with an example embodiment.

[0067] Referring to FIG. 24, a first conductive layer was formed using ruthenium as a first metal material, and a first intermediate layer was formed on the first conductive layer using graphene to form an intermediate structure. The Raman spectrum of graphene in the intermediate structure was measured using Raman spectroscopy.

[0068] Graphene exhibits the D, 2D, D', and G peaks of carbon atoms, with the G peak at approximately 1580 cm -1 The peak corresponds to a Raman shift value of about 1350 cm -1 The 2D peak corresponds to a Raman shift value of about 2700 cm -1 The ratio of the D peak to the G peak of the carbon atoms was 1.01 (i.e., D / G=1.01), the ratio of the 2D peak to the G peak was 0.10 (i.e., 2D / G=0.10), and the ratio of the D' peak to the G peak was 0.30 (i.e., D' / G=0.30). From the Raman spectrum shown in FIG. 24, it can be seen that graphene is made of a nanocrystalline structure having a layered structure with relatively high crystallinity.

[0069] FIG. 25 is a graph showing the change in roughness before and after annealing of a metal line CO11 according to a comparative example and a metal line stack EX11 according to an embodiment.

[0070] 25, the metal line CO11 according to the comparative example has a single layer structure made of a first metal material, and the metal line stack EX11 according to the embodiment has a laminated structure of a first conductive layer made of a first metal material, a first intermediate layer made of graphene, and a second conductive layer made of the first metal material. In the metal line stack EX11 according to the embodiment, the first intermediate layer is formed to a thickness corresponding to about 10% of the total thickness of the metal line stack EX11, and the total thickness of the metal line CO11 according to the comparative example is the same as the total thickness of the metal line stack EX11 according to the embodiment. In addition, the metal line CO11 according to the comparative example and the metal line stack EX11 according to the embodiment were annealed at a temperature of about 600° C. for several minutes, and the surface rms roughness (root mean square roughness) was measured by an atomic force microscope before and after the annealing process.

[0071] The metal line CO11 according to the comparative example had an average roughness of 0.795 nm before the annealing treatment, but had an average roughness of 1.832 after the annealing treatment. The average roughness of the metal line CO11 according to the comparative example increased by about 130% after the annealing treatment compared to the initial value before the annealing treatment, which is presumably because the grains of the first metal material were exposed to high temperatures during the annealing treatment, causing grain aggregation or coarsening, and the surface morphology changed to a roughened surface.

[0072] Meanwhile, the metal line stack EX11 according to the embodiment had an average roughness of 0.564 nm before the annealing treatment, but had an average roughness of 0.586 after the annealing treatment. The average roughness of the metal line stack EX11 according to the embodiment hardly increased or only slightly increased after the annealing treatment compared to the initial value before the annealing treatment. It was confirmed that the metal line stack EX11 according to the embodiment had almost no change in surface morphology even after the annealing treatment. This is presumably because, even if the grains of the first metal material are exposed to high temperatures during the annealing treatment, the grains of the first metal material contained in the first conductive layer and the second conductive layer do not undergo grain aggregation or coarsening due to the presence of the first intermediate layer including graphene sandwiched between the first conductive layer and the second conductive layer.

[0073] FIG. 26 is a graph showing the change in resistivity before and after annealing of a metal line CO11 according to a comparative example and a metal line stack EX11 according to an embodiment.

[0074] 26, the metal line CO11 according to the comparative example had a resistivity of 14.50 μΩ·cm before the annealing treatment and had a resistivity of 10.62 μΩ·cm after the annealing treatment. The resistivity of the metal line CO11 according to the comparative example was reduced by about 26.8% of the initial resistivity after the annealing treatment compared to the initial value before the annealing treatment.

[0075] The metal line stack EX11 according to the embodiment had a resistivity of 16.91 μΩ·cm before the annealing treatment, and had a resistivity of 12.69 μΩ·cm after the annealing treatment. The resistivity of the metal line stack EX11 according to the embodiment was reduced by about 25.0% of the initial resistivity after the annealing treatment compared to the initial value before the annealing treatment. It can be seen that the metal line stack EX11 according to the embodiment has a slightly higher resistivity value than the metal line CO11 according to the comparative example, but on the other hand, the resistivity reduction rate after the annealing treatment has a similar value to that of the metal line CO11 according to the comparative example.

[0076] 25 and 26, the metal line CO11 according to the comparative example has a roughened surface morphology after the annealing process, while the metal line stack EX11 according to the embodiment maintains almost the same initial surface morphology after the annealing process. Also, the metal line stack EX11 according to the embodiment has a resistivity reduced to a similar level as the metal line CO11 according to the comparative example after the annealing process. Thus, the bit line including the metal line stack EX11 according to the embodiment has low resistance, while the occurrence of localized line width increased areas, line width decreased areas, and / or line cut areas in the bit line due to high temperature processes is prevented.

[0077] 7 and 8 are cross-sectional views showing a semiconductor device 100A according to an example embodiment.

[0078] 7 and 8, the metal line stack 136 includes a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B, and the second thickness t11 of the first conductive layer 136A in the vertical direction Z is thicker than the fourth thickness t13 of the second conductive layer 136B in the vertical direction Z.

[0079] In an exemplary embodiment, the second thickness t11 of the first conductive layer 136A corresponds to about 40% to 80% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fourth thickness t13 of the second conductive layer 136B corresponds to about 10% to 30% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The third thickness t12 of the first intermediate layer 138A corresponds to about 5% to 20% of the first thickness t10 of the metal line stack 136 in the vertical direction Z.

[0080] It will be understood that the embodiment described based on Figures 7 and 8 is not mutually exclusive with the embodiment described based on Figures 1 to 6, and that the respective thicknesses of first conductive layer 136A, first intermediate layer 138A, and second conductive layer 136B in the embodiment described based on Figures 7 and 8 partially overlap with the respective thicknesses of first conductive layer 136A, first intermediate layer 138A, and second conductive layer 136B in the embodiment described based on Figures 1 to 6.

[0081] 9 and 10 are cross-sectional views illustrating a semiconductor device 100B according to an exemplary embodiment.

[0082] 9 and 10, the metal line stack 136 includes a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B, and the second thickness t11 of the first conductive layer 136A in the vertical direction Z is thinner than the fourth thickness t13 of the second conductive layer 136B in the vertical direction Z.

[0083] In an exemplary embodiment, the second thickness t11 of the first conductive layer 136A corresponds to about 10% to 30% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fourth thickness t13 of the second conductive layer 136B corresponds to about 40% to 80% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The third thickness t12 of the first intermediate layer 138A corresponds to about 5% to 20% of the first thickness t10 of the metal line stack 136 in the vertical direction Z.

[0084] It will be understood that the embodiment described based on Figures 9 and 10 is not mutually exclusive with the embodiment described based on Figures 1 to 6, and that the respective thicknesses of first conductive layer 136A, first intermediate layer 138A, and second conductive layer 136B in the embodiment described based on Figures 9 and 10 partially overlap with the respective thicknesses of first conductive layer 136A, first intermediate layer 138A, and second conductive layer 136B in the embodiment described based on Figures 1 to 6.

[0085] 11 and 12 are cross-sectional views illustrating a semiconductor device 100C according to an example embodiment.

[0086] 11 and 12, the metal line stack 136 includes a first conductive layer 136A, a first intermediate layer 138A, a second conductive layer 136B, and a second intermediate layer 138B, which are sequentially disposed on the metal silicide film 134. The second intermediate layer 138B includes graphene, for example, the graphene constituting the second intermediate layer 138B includes a plurality of grains having a two-dimensional structure.

[0087] In an exemplary embodiment, the metal line stack 136 has a first thickness t10 in the vertical direction, the first conductive layer 136A has a second thickness t11 in the vertical direction Z, the first intermediate layer 138A has a third thickness t12 in the vertical direction Z, the second conductive layer 136B has a fourth thickness t13 in the vertical direction Z, and the second intermediate layer 138B has a fifth thickness t14 in the vertical direction Z. The second thickness t11 of the first conductive layer 136A corresponds to about 20% to 60% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fourth thickness t13 of the second conductive layer 136B corresponds to about 20% to 60% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The third thickness t12 of the first intermediate layer 138A corresponds to about 5% to 30% of the first thickness t10 of the metal line stack 136 in the vertical direction Z. The fifth thickness t14 of the second intermediate layer 138B corresponds to about 5% to 30% of the first thickness t10 of the metal line stack 136 in the vertical direction Z.

[0088] 11 and 12, a metal line stack 136 consisting of four layers, a first conductive layer 136A, a first intermediate layer 138A, a second conductive layer 136B, and a second intermediate layer 138B, is illustrated, however, in other embodiments, the metal line stack 136 may further include an additional conductive layer including a first metal material and an additional intermediate layer including graphene.

[0089] 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, and 22B are cross-sectional views showing a manufacturing method of the semiconductor device 100 according to an exemplary embodiment. Specifically, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A are cross-sectional views corresponding to the A-A' cross section in FIG. 2, and 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B are cross-sectional views corresponding to the B-B' cross section in FIG. 2.

[0090] 13A and 13B, a plurality of isolation trenches 112T are formed in a substrate 110. As shown in FIG.

[0091] Next, a first isolation film 112 is formed to fill the plurality of isolation trenches 112T. A plurality of first active regions AC1 are defined in the substrate 110 by the formation of the first isolation film 112. In a plan view, the plurality of first active regions AC1 extend along a first oblique direction D1 (see FIG. 2) inclined at a predetermined angle with the first horizontal direction X and the second horizontal direction Y.

[0092] In an exemplary embodiment, the first isolation layer 112 is formed using silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some examples, the first isolation layer 112 is formed of a double layer structure of a silicon oxide layer and a silicon nitride layer, but is not limited thereto.

[0093] A mask pattern (not shown) is formed on the substrate 110, and a portion of the substrate 110 is removed using the mask pattern as an etching mask to form the word line trenches 120T. For example, the mask pattern for forming the word line trenches 120T may be formed using a double patterning technique (DPT) or a quadruple patterning technique (QPT), but is not limited thereto.

[0094] Thereafter, a gate dielectric layer 122, a gate electrode 124, and a word line capping layer 126 are sequentially formed in the word line trench 120T.

[0095] For example, the gate dielectric layer 122 is conformally disposed on the inner walls of the wordline trenches 120T. The gate electrodes 124 are formed by filling the wordline trenches 120T with a conductive layer (not shown) and then etching back the top of the conductive layer to re-expose a portion of the upper side of the wordline trenches 120T. A wordline capping layer 126 is formed in the exposed portions of the wordline trenches 120T.

[0096] 14A and 14B, a first buffer insulating layer 114 and a second buffer insulating layer 116 are formed on the first active region AC1 and the first device isolation layer 112. Then, a lower conductive layer 132 is formed on the first and second buffer insulating layers 114 and 116. A bit line contact hole DCH is formed by removing a portion of the lower conductive layer 132, the first and second buffer insulating layers 114 and 116, and the substrate 110. Then, a bit line contact DC is formed in the bit line contact hole DCH using a conductive material.

[0097] In an exemplary embodiment, the lower conductive layer 132 is formed using Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. In an exemplary embodiment, the bit line contacts DC are formed using TiN, TiSiN, W, tungsten silicide, doped polysilicon, or a combination thereof.

[0098] 15A and 15B, a metal silicide film 134 is formed on the bit line contact DC and the lower conductive layer 132. The metal silicide film 134 is formed using at least one of cobalt silicide, nickel silicide, and tungsten silicide. Optionally, a conductive barrier film may be further formed on the metal silicide film 134 using at least one of titanium, titanium nitride, and tantalum nitride.

[0099] Thereafter, a first conductive layer 136A, a first intermediate layer 138A, and a second conductive layer 136B are formed on the metal silicide film 134 in this order.

[0100] In an exemplary embodiment, the first conductive layer 136A includes a first metal material, which is formed using any one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or an alloy thereof. The first conductive layer 136A is formed using at least one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process.

[0101] The first intermediate layer 138A includes graphene and is formed using at least one of a plasma-based CVD process, a thermal CVD process, and an ALD process. For example, the plasma-based CVD process includes at least one of a microwave plasma CVD process, an inductively coupled plasma (ICP) CVD process, a capacitively coupled plasma (CCP) CVD process, and a pulsed plasma CVD process.

[0102] In an exemplary embodiment, the second conductive layer 136B includes a first metallic material, and the first metallic material is formed using any one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or alloys thereof. The first conductive layer 136A is formed using at least one of a PVD process, a CVD process, and an ALD process.

[0103] Here, the stacked structure of the first conductive layer 136A, the first intermediate layer 138A, and the second conductive layer 136B is referred to as a metal line stack layer 136L. Then, a bit line capping layer 140 is formed on the metal line stack layer 136L. The bit line capping layer 140 includes a first capping layer 142, a second capping layer 144, and a third capping layer 146, which are sequentially arranged on the upper surface of the metal line stack layer 136L. The first capping layer 142, the second capping layer 144, and the third capping layer 146 are formed using at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0104] 16A and 16B, the metal line stack layer 136L (see FIG. 15A), the metal silicide layer 134, and the lower conductive layer 132 are patterned using the bit line capping layer 140 as an etch mask to form a plurality of bit lines BL.

[0105] In the patterning process for forming the plurality of bit lines BL, a portion of the bit line contact DC disposed in the bit line contact hole DCH is also removed, so that the sidewalls of the bit line contact DC are aligned with the sidewalls of the bit lines BL, and the inner walls of the bit line contact hole DCH are exposed again on both sides of the bit line contact DC, as shown in FIG.

[0106] Then, a first spacer layer 152 is formed on the sidewalls of the bit lines BL, the bit line capping layer 140, and the bit line contacts DC. The first spacer layer 152 is also conformally disposed on the inner walls of the bit line contact holes DCH. In an exemplary embodiment, the first spacer layer 152 is formed using silicon nitride.

[0107] 17A and 17B, bit line contact spacers DCS are formed by filling the remaining portions of the bit line contact holes DCH on the first spacer layer 152. For example, the bit line contact spacers DCS are formed using silicon nitride or silicon oxide.

[0108] Next, a second spacer layer 154 is formed on the sidewalls of the bitlines BL and the bitline capping layer 140. In an exemplary embodiment, the second spacer layer 154 is formed using silicon oxide.

[0109] Then, an anisotropic etching process is performed on the second spacer layer 154 to remove the first and second buffer insulating layers 114 and 116 disposed between the bit lines BL, thereby exposing the top surface of the substrate 110.

[0110] A third spacer layer 156 is then conformally formed over the second spacer layer 154 and the upper surface of the substrate 110. In an exemplary embodiment, the third spacer layer 156 is formed using silicon nitride.

[0111] 18A and 18B, the upper portion of the substrate 110 exposed in the spaces between the bit lines BL is further removed to form buried contact holes BCH. In an exemplary embodiment, the process of forming the buried contact holes BCH includes a wet etching process, a dry etching process, or a combination thereof.

[0112] During the etching process for forming the buried contact hole BCH, an upper portion of the bit line capping layer 140 is also removed, so that the upper surface level of the bit line capping layer 140 is lowered.

[0113] 19A and 19B, a buried contact BC is formed to fill the inside of the buried contact hole BCH. In an exemplary embodiment, the buried contact BC is formed using doped polysilicon.

[0114] In an exemplary embodiment, the buried contact holes BCH are formed to have a line-type planar shape disposed between adjacent bit lines BL, and then a preliminary contact layer having a line-type planar shape is formed in the buried contact holes BCH, and the preliminary contact layer is patterned to form buried contacts BC. Thereafter, an insulating fence is formed using an insulating material in a space between the buried contacts BC (e.g., a space where a portion of the preliminary contact layer is removed).

[0115] In another embodiment, before forming the buried contact hole BCH, a plurality of insulating fences are formed using an insulating material between two adjacent bit lines BL and at the intersection of the word line trench 120T, a portion of the substrate 110 disposed between the plurality of bit lines BL and between the plurality of insulating fences is removed to form the buried contact hole BCH, and then a buried contact BC is formed in the buried contact hole BCH.

[0116] 20A and 20B, a landing pad conductive layer LPL is formed on the upper surfaces of the buried contacts BC. The landing pad conductive layer LPL is formed to a sufficient thickness to contact the buried contacts BC and cover the upper surface of the bit line capping layer 140.

[0117] 21A and 21B, a mask pattern is formed on the landing pad conductive layer LPL, and the landing pad conductive layer LPL is patterned using the mask pattern as an etching mask to form landing pad openings LPH, which form a plurality of landing pads LP disposed on the plurality of buried contacts BC, respectively.

[0118] 22A and 22B, an insulating pattern 160 is formed in the landing pad opening LPH using an insulating material. The insulating pattern 160 is disposed to cover sidewalls of the landing pads LP.

[0119] 3 and 4, a plurality of lower electrodes 182 connected to the landing pads LP are formed, and a capacitor dielectric layer 184 and an upper electrode 186 are sequentially formed on sidewalls of the plurality of lower electrodes 182.

[0120] The semiconductor device 100 is completed by carrying out the above-mentioned method.

[0121] According to an exemplary embodiment, the bit line includes a metal line stack having a structure in which a first conductive layer including a first metal material such as ruthenium, a first intermediate layer including graphene, and a second conductive layer including the first metal material are sequentially stacked. The first intermediate layer suppresses and prevents grain agglomeration and / or grain overgrowth of the first and second conductive layers during a heat treatment step in a manufacturing process, thereby preventing localized disconnection of the bit line.

[0122] As above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the description of the embodiments, these terms are merely used for the purpose of describing the technical idea of ​​the present invention, and are not used to limit the meaning or the scope of the present invention. Therefore, a person having ordinary knowledge in the art will understand that various modifications and equivalent other embodiments are possible. [Explanation of symbols]

[0123] 100 Semiconductor device 110 Substrate 112 First element isolation film 112P Second element isolation film 112T Element isolation trench 114 First buffer insulating layer 116 Second buffer insulating layer 118 Gate Dielectric Layer 120 Buried Gate Structure 120T Word Line Trench 122 Gate dielectric film 124 Gate electrode 126 Word Line Capping Layer 132 Lower conductive layer 132P Peripheral lower conductive layer 134P Peripheral metal silicide film 136P Peripheral metal line stack 134 Metal silicide film 136 Metal Line Stack 136A 1st conductive layer 136B Second conductive layer 138A 1st middle layer 140-bit line capping layer 142 First Capping Layer 142P Gate Capping Pattern 144 Second Capping Layer 146 Third Capping Layer 150 Bit Line Spacer 152 First spacer layer 154 Second spacer layer 156 Third Spacer Layer 160 Insulation Pattern 180 Etching stop film 180H opening 182 Lower Electrode 184 Capacitor Dielectric Layer 186 Upper electrode t10 1st thickness t11 2nd thickness t12 3rd thickness t13 4th thickness BL Bit Line DC Bit Line Contact DCS Bit Line Contact Spacer DCH Bit Line Contact Hole MCA cell array region PCA peripheral circuit area PTR peripheral circuit transistor PGS Peripheral circuit gate stack WL Word Line

Claims

1. a substrate including a first active region defined by a first isolation layer; a bit line contact disposed on the first active region of the substrate; a bit line extending in a first direction on the substrate; The bit line is a lower conductive layer disposed on the substrate and disposed on sidewalls of the bit line contact; a metal line stack disposed on the lower conductive layer; The metal line stack comprises: a first conductive layer including a first metal material disposed on the lower conductive layer and the bit line contact; a first intermediate layer disposed on the first conductive layer and including graphene; a second conductive layer disposed on the first intermediate layer, the second conductive layer including the first metallic material.

2. the metal line stack has a first thickness in a vertical direction; the first intermediate layer has a second thickness in the vertical direction; 2. The semiconductor device according to claim 1, wherein the second thickness is 5% to 50% of the first thickness.

3. 3. The semiconductor device according to claim 2, wherein the second thickness of the first intermediate layer is in the range of 5 Å to 50 Å.

4. 2. The semiconductor device of claim 1, wherein the first metallic material comprises at least one of ruthenium (Ru), molybdenum (Mo), rhodium (Rh), iridium (Ir), or an alloy thereof.

5. The semiconductor device of claim 1 , wherein the first metallic material comprises ruthenium (Ru).

6. When the first intermediate layer is analyzed by X-ray photoelectron spectroscopy, it has a structure of sp ２ 2. The semiconductor device according to claim 1, wherein the content of carbon atoms having bonds is 50% to 99%.

7. 2. The semiconductor device according to claim 1, wherein, in the first intermediate layer, a ratio of a D peak to a G peak of carbon atoms is 3.0 or less, a ratio of a 2D peak to the G peak is 0.1 or more, and a ratio of a D' peak to the G peak is 1.0 or less, as measured by Raman spectroscopy.

8. further comprising a bit line spacer disposed on a sidewall of the bit line; 2. The device of claim 1, wherein the bitline spacer contacts a sidewall of the lower conductive layer and a sidewall of the metal line stack.

9. The semiconductor device of claim 8 , wherein a sidewall of the first intermediate layer contacts the bit line spacer.

10. 2. The device of claim 1, wherein the bit line further comprises a metal silicide layer disposed on the lower conductive layer and on the metal line stack.

11. 11. The semiconductor device of claim 10, wherein the metal silicide film is interposed between the lower conductive layer and the first conductive layer and between the bit line contact and the first conductive layer.

12. The metal line stack comprises: The semiconductor device according to claim 1 , further comprising a second intermediate layer disposed on the second conductive layer and including graphene.

13. the substrate further includes a second active region defined by a second isolation layer; The semiconductor device further includes a peripheral circuitry gate stack disposed on the second active area; The peripheral circuit gate stack comprises: a peripheral lower conductive layer; a peripheral metal line stack disposed on the peripheral lower conductive layer; The peripheral metal line stack comprises: a first peripheral conductive layer disposed on the peripheral lower conductive layer and including the first metallic material; a first peripheral intermediate layer disposed on the first peripheral conductive layer and including graphene; 2. The semiconductor device according to claim 1, further comprising: a second peripheral conductive layer disposed on the first peripheral intermediate layer, the second peripheral conductive layer including the first metallic material.

14. the peripheral metal line stack having a third thickness in a vertical direction; the first peripheral interlayer has a fourth thickness in the vertical direction; 14. The semiconductor device according to claim 13, wherein the fourth thickness is 5% to 50% of the third thickness.

15. 15. The semiconductor device according to claim 14, wherein the fourth thickness of the first peripheral intermediate layer is in the range of 5 Å to 50 Å.

16. a substrate including a first active region defined by a first isolation layer and a second active region defined by a second isolation layer; a bit line contact disposed on the first active region of the substrate; a bit line extending in a first direction on the substrate; a peripheral circuitry gate stack disposed on the second active area; The bit line is a lower conductive layer disposed on the substrate and surrounding a sidewall of the bit line contact; a metal line stack disposed on the lower conductive layer; The metal line stack comprises: a first conductive layer including a first metal material disposed on the lower conductive layer and on the bit line contact; a first intermediate layer disposed on the first conductive layer and including graphene; a second conductive layer disposed on the first intermediate layer, the second conductive layer including the first metallic material.

17. The peripheral circuit gate stack comprises: a peripheral lower conductive layer; a peripheral metal line stack disposed on the peripheral lower conductive layer; The peripheral metal line stack comprises: a first peripheral conductive layer disposed on the peripheral lower conductive layer and including the first metallic material; a first peripheral intermediate layer disposed on the first peripheral conductive layer and including graphene; 17. The semiconductor device of claim 16, further comprising: a second peripheral conductive layer disposed on the first peripheral intermediate layer, the second peripheral conductive layer including the first metallic material.

18. the metal line stack has a first thickness in a vertical direction; the first intermediate layer has a second thickness in the vertical direction; the second thickness is between 5% and 50% of the first thickness; the peripheral metal line stack has a third thickness in the vertical direction; the first peripheral interlayer has a fourth thickness in the vertical direction; 18. The semiconductor device according to claim 17, wherein the fourth thickness is 5% to 50% of the third thickness.

19. a substrate including a first active region defined by a first isolation layer; a bit line contact disposed in a bit line contact hole extending into the substrate and connected to the first active region of the substrate; a bit line extending in a first direction on the substrate, a lower conductive layer disposed on the substrate, surrounding a sidewall of the bit line contact and extending in the first direction; a metal silicide film disposed on the lower conductive layer and extending in the first direction; a bit line including a metal line stack disposed on the metal silicide film, extending in the first direction, the metal line stack including a first conductive layer, a second conductive layer, and a first intermediate layer, the first conductive layer including a first metal material, the second conductive layer including the first metal material, the first intermediate layer sandwiched between the first conductive layer and the second conductive layer, the metal line stack including graphene; a bit line spacer disposed on a sidewall of the bit line and extending in the first direction; a word line disposed in a word line trench extending in a second direction intersecting the first direction so as to intersect the first active region within the substrate.

20. the first metallic material includes ruthenium (Ru); The first intermediate layer, when analyzed using X-ray photoelectron spectroscopy, has a sp ２ 20. The semiconductor device according to claim 19, wherein the content of carbon atoms having bonds is 50% to 99%.

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