Bridge chip and semiconductor integrated module

Abstract

To provide a bridge chip and a semiconductor integrated module capable of improving the robustness of electrical connections between a plurality of elements.SOLUTION: A bridge chip has a substrate having a first surface and a second surface opposite the first surface, a first resin film that is flexible and formed on the first surface of the substrate, and a metal film formed on the first resin film. The metal film has a connection for electrical connection with the element. The substrate has a buffer section that runs through the substrate between the first and second surfaces. The connection is located inside the buffer in the plan view of the substrate.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a bridge chip and a semiconductor integrated module. [Background technology]

[0002] Patent Document 1 describes an optical transmitter. The optical transmitter includes a Mach-Zehnder modulator, a driver IC, and a wiring board. The wiring board connects the Mach-Zehnder modulator and the driver IC to each other by flip-chip mounting. The wiring board is a flexible board made of silicon dioxide (SiO2) or resin. In this optical transmitter, the inclination of the wiring board with respect to the Mach-Zehnder modulator and the driver IC is set to within ±3°.

[0003] Patent Document 2 describes an optical transmitter having an interconnect bridge assembly including a substrate. The substrate of the interconnect bridge assembly electrically connects the modulator driver and the control IC to each other. The substrate is made of a material having flexibility or elasticity. This allows the substrate to absorb the difference in height between the modulator driver and the control IC. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-189699 A [Patent Document 2] US Patent Application Publication No. 2015 / 0180580 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, multiple elements such as a driver IC and optical circuit elements may be subject to stress due to expansion or contraction caused by temperature changes while housed in a housing. Therefore, it is necessary to protect the elements from the effects of stress while enabling signal transmission between multiple elements.

[0006] An object of the present disclosure is to provide a bridge chip and a semiconductor integrated module that can improve the robustness of electrical connections between multiple elements. [Means for solving the problem]

[0007] The bridge chip according to the present disclosure includes a substrate having a first surface and a second surface opposite to the first surface, a first flexible resin film formed on the first surface of the substrate, and a metal film formed on the first resin film. The metal film has a connection portion for electrical connection with an element. The substrate has a buffer portion penetrating the substrate between the first surface and the second surface. The connection portion is disposed inside the buffer portion in a plan view of the substrate. Effect of the Invention

[0008] According to the present disclosure, it is possible to improve the robustness of electrical connections between multiple elements. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing the internal structure of a semiconductor integrated module according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor integrated module according to the embodiment. [Diagram 3] FIG. 3 is a bottom view showing the bridge chip according to the embodiment. [Figure 4] FIG. 4 is a plan view showing the bridge chip according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view taken along line AA in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line BB in FIG. [Figure 7]FIG. 7 is a diagram showing steps of a method for manufacturing a bridge chip according to the embodiment. [Figure 8] FIG. 8 is a diagram showing steps of a method for manufacturing a bridge chip according to the embodiment. [Figure 9] FIG. 9 is a diagram showing steps of a method for manufacturing a semiconductor integrated module according to the embodiment. [Figure 10] FIG. 10 is a diagram for explaining deformation of the buffer portion and the support portion of the substrate of the bridge chip according to the embodiment. [Figure 11] FIG. 11 is a plan view showing the internal structure of a semiconductor integrated module according to a first modified example. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor integrated module according to a first modification. [Figure 13] FIG. 13 is a plan view showing a bridge chip according to a second modified example. [Figure 14] FIG. 14 is a cross-sectional view taken along line CC in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along line DD in FIG. [Figure 16] FIG. 16 is a diagram showing steps of a method for manufacturing a semiconductor integrated module including a bridge chip according to the second modified example. [Figure 17] FIG. 17 is a plan view showing a bridge chip according to a third modified example. [Figure 18] FIG. 18 is a cross-sectional view taken along line EE in FIG. [Figure 19] FIG. 19 is a plan view showing a bridge chip according to the fourth modified example. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor integrated module according to a fifth modification. [Figure 21] FIG. 21 is a cross-sectional view showing a semiconductor integrated module according to a sixth modified example. [Figure 22] FIG. 22 is a diagram showing steps of a method for manufacturing a bridge chip according to the seventh modified example. [Figure 23] FIG. 23 is a diagram showing steps of a method for manufacturing a bridge chip according to the seventh modified example. [Figure 24] FIG. 24 is a diagram showing steps of a method for manufacturing a bridge chip according to the eighth modified example. [Diagram 25] FIG. 25 is a diagram showing steps of a method for manufacturing a bridge chip according to the eighth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the bridge chip and semiconductor integrated module according to the present disclosure will be listed and described. (1) A bridge chip according to one embodiment includes a substrate having a first surface and a second surface opposite to the first surface, a first flexible resin film formed on the first surface of the substrate, and a metal film formed on the first resin film. The metal film has a connection portion for electrical connection with an element. The substrate has a buffer portion penetrating the substrate between the first surface and the second surface. The connection portion is disposed inside the buffer portion when viewed from above the substrate.

[0011] In this bridge chip, a first resin film having flexibility is formed between the substrate and the metal film. The metal film has a connection portion for electrical connection with the element. The substrate has a buffer portion penetrating the substrate, and the connection portion is disposed inside the buffer portion in plan view of the substrate. Thus, the connection portion, the first resin film having flexibility, and the buffer portion are arranged in this order along the stacking direction of the substrate, the first resin film, and the metal film. The portion where the connection portion is located in plan view of the substrate is made to be a portion that is more easily deformed than other portions because the buffer portion is located below the connection portion. Therefore, since the connection portion electrically connected to the element is more easily displaced than other portions, even if a temperature change or the like occurs, the portion of the first resin film aligned with the connection portion along the stacking direction is deformed, thereby reducing the effect of stress on the element. Therefore, the element can be protected from the effect of stress to improve robustness between a plurality of elements.

[0012] (2) In the above (1), the bridge chip may include a second flexible resin film, which may be formed on the first resin film and the metal film and have an opening on the metal film. In this case, the second flexible resin film may cover a part of the first resin film and a part of the metal film.

[0013] (3) In the above (1) or (2), the substrate may further have a support portion inside the buffer portion in a plan view of the substrate. The connection portion may be connected to the second surface of the substrate via the first resin film and the support portion. In this case, the connection portion, the flexible first resin film, and the support portion are arranged in this order along the stacking direction of the substrate, the first resin film, and the metal film. Therefore, the first resin film and the connection portion can be supported by the support portion while deforming a portion of the first resin film arranged along the stacking direction with the connection portion.

[0014] (4) In any of the above (1) to (3), the bridge chip may further have solder bumps formed on the connection parts. In this case, the connection parts can be connected to the elements by melting the solder bumps by heating, so that the connection parts can be easily connected to the elements without having to strongly press the connection parts against the elements.

[0015] (5) In any one of the above (1) to (4), the first resin film may be made of polyimide. In this case, the first resin film can be a resin film having excellent flexibility and stretchability.

[0016] (6) In any one of the above (1) to (5), the metal film may be made of any one of copper, gold, and aluminum.

[0017] (7) In any of the above (1) to (6), the metal film may include a wiring having a first pad formed as a connection part at a first end and a second pad formed as a connection part at a second end. The first pad may be configured to be electrically connectable to a first element, and the second pad may be configured to be electrically connectable to a second element separated from the first element. In this case, the first pad of the wiring of the metal film may be electrically connected to the first element, and the second pad of the wiring of the metal film may be electrically connected to the second element.

[0018] (8) In any of the above (1) to (6), the metal film may include a plurality of wirings each extending in a first direction, and each of the plurality of wirings may have a first pad at a first end and a second pad at a second end. The first pads of the plurality of wirings may be arranged along a second direction intersecting the first direction, and the second pads of the plurality of wirings may be arranged along the second direction. The buffer section may include a first buffer section including a plurality of first pads therein when viewed from above the substrate, and a second buffer section including a plurality of second pads therein when viewed from above the substrate. In this case, it is possible to make the portions of the first resin film aligned with the first pads and the second pads in the stacking direction more easily deformable than the other portions.

[0019] (9) In any of the above (1) to (8), the substrate may be made of silicon, which makes it easier to heat the substrate during mounting, etc.

[0020] (10) In any one of the above (1) to (8), the substrate may be made of glass. In this case, the heat insulating property of the substrate can be further improved.

[0021] (11) In any of the above (1) to (8), the support portion of the substrate may be made of silicon.

[0022] (12) A semiconductor integrated module according to an embodiment includes a base having a reference surface, a first element mounted on the reference surface and transmitting an electric signal, a second element mounted on the reference surface and receiving an electric signal, and the aforementioned bridge chip connected to the first element and the second element and transmitting an electric signal. Since this semiconductor integrated module includes the aforementioned bridge chip, the same effect as described above can be obtained. That is, since the connection parts electrically connected to the first element and the second element are more easily displaced than other parts, even if a temperature change or the like occurs, the influence of stress on the first element and the second element can be reduced by deforming the parts of the first resin film aligned with the connection parts in the stacking direction. Therefore, the first element and the second element can be protected from the influence of stress to improve robustness between a plurality of elements.

[0023] [Details of the embodiment of the present disclosure] Various examples of the bridge chip and the semiconductor integrated module according to the embodiment will be described below with reference to the drawings. Note that the present invention is not limited to the following examples, but is intended to include all modifications within the scope of the claims and equivalents thereto. In the description of the drawings, the same or corresponding elements are given the same reference numerals, and duplicated descriptions are omitted as appropriate. The drawings may be partially simplified or exaggerated for ease of understanding, and the dimensional ratios and the like are not limited to those shown in the drawings. In other words, the dimensions in the drawings may differ from the actual dimensions.

[0024] FIG. 1 is a plan view showing an internal structure of a semiconductor integrated module 1 according to this embodiment. FIG. 2 is a vertical cross-sectional view showing the semiconductor integrated module 1. In this embodiment, the semiconductor integrated module 1 is an optical module. As shown in FIGS. 1 and 2, the semiconductor integrated module 1 is, for example, an optical transmission module (TOSA: Transmitter Optical Sub Assembly) including a rectangular parallelepiped package 2, an optical connector 3, and a terminal 4. The semiconductor integrated module 1 may be, for example, a transmission module (CDM: Coherent Driver Module) for coherent optical communication. The package 2 is made of, for example, ceramic. The package 2 extends in a first direction D1 which is the longitudinal direction of the package 2, a second direction D2 which is the width direction of the package 2, and a third direction D3 which is the height direction of the package 2. The first direction D1, the second direction D2, and the third direction D3 are, for example, perpendicular to each other.

[0025] The package 2 has a pair of first side walls 2b located at an end in the first direction D1, a pair of second side walls 2c located at an end in the second direction D2, and a bottom wall 2h located at one end in the third direction D3. An internal space 2A of the package 2 is defined by the pair of first side walls 2b, the pair of second side walls 2c, and the bottom wall 2h. Components of the semiconductor integrated module 1 are accommodated in the internal space 2A. The semiconductor integrated module 1 further includes a lid 6 that seals the internal space 2A. The lid 6 is made of, for example, metal. FIG. 1 shows the internal space 2A of the package 2 in a plan view from the third direction D3 with the lid 6 omitted.

[0026] In the internal space 2A, for example, a driver IC 11 as a first element, an optical circuit element 12 as a second element, and an optical component 20 are provided. For example, the optical circuit element 12 is an optical modulator. The driver IC 11 is, for example, an electric circuit formed on a silicon (Si) substrate using a SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process, and amplifies an electric signal supplied from a terminal 4 and supplies the amplified signal to the optical circuit element 12.

[0027] The driver IC 11 transmits an electrical signal, and the optical circuit element 12 receives the electrical signal. In this embodiment, the driver IC 11 supplies the electrical signal to the optical circuit element 12. The optical circuit element 12 is, for example, an indium phosphide (InP) substrate on which a Mach-Zehnder interferometer is formed, and modulates and outputs an optical signal supplied from the outside based on the electrical signal supplied from the driver IC 11. The modulation rate of the optical signal is, for example, 200 GBd.

[0028] The electrical signal supplied from the driver IC 11 to the optical circuit element 12 passes through, for example, a transmission line formed in an electrical signal output section of the driver IC 11 and an electrical signal input section of the optical circuit element 12. It is desirable that these transmission lines have approximately equal characteristic impedances, and the characteristic impedance is, for example, 60Ω differential. The length of the driver IC 11 in the first direction D1 and the length of the optical circuit element 12 in the first direction D1 are, for example, 2 mm. The length of the driver IC 11 in the second direction D2 and the length of the optical circuit element 12 in the second direction D2 are, for example, 4 mm.

[0029] The package 2 has a heat sink (heat dissipation member). For example, the bottom wall 2h is made of the heat sink. The heat sink is made of, for example, copper tungsten (CuW). The heat sink may be made of, for example, a metal material other than CuW. Hereinafter, the bottom wall 2h is also referred to as the heat sink. The driver IC 11 is mounted on the heat sink (heat dissipation member) via a heat sink block 13. The heat sink block 13 is bonded to the first surface 2f of the package 2.

[0030] The driver IC 11 is attached to the heat dissipation block 13 by, for example, a thermally conductive adhesive (not shown) such as silver paste. An alloy solder such as gold-tin (AuSn) solder or tin-silver-copper (SnAgCu) solder may be used instead of the thermally conductive adhesive. The heat dissipation block 13 is attached to the first surface 2f of the package 2 by, for example, a thermally conductive adhesive. The heat dissipation block 13 may be made of, for example, a metal or ceramic. The heat dissipation block 13 may also be made of aluminum nitride.

[0031] The optical circuit element 12 is mounted on the bottom wall 2h via, for example, a TEC (ThermoElectric Cooler) 15, which is a temperature adjustment element. The TEC 15 is bonded to the second surface 2g of the package 2. For example, the first surface 2f and the second surface 2g are formed on the bottom wall 2h. The second surface 2g is a surface parallel to the first surface 2f. For example, the second surface 2g is located on the same plane as the first surface 2f. A spacer 14 is provided between the optical circuit element 12 and the TEC 15.

[0032] The optical circuit element 12 is bonded to the spacer 14 by, for example, a thermally conductive adhesive. The spacer 14 is bonded to the TEC 15 by, for example, a thermally conductive adhesive. The TEC 15 is bonded to the second surface 2g of the package 2 by, for example, a thermally conductive adhesive. The spacer 14 may be provided between the TEC 15 and the bottom wall 2h, not between the optical circuit element 12 and the TEC 15. A plurality of spacers 14 may be provided. The spacer 14 may be made of, for example, a metal or ceramic. The spacer 14 may be made of aluminum nitride. For example, an optical component other than the optical circuit element 12 may be mounted on the spacer 14. The spacer 14 may be omitted.

[0033] For example, the optical component 20 includes at least one of a lens, a mirror, a beam splitter, and an optical filter. The optical component 20 performs input and output of an optical signal to and from the optical circuit element 12. The optical connector 3 is provided on the first side wall 2b. The optical connector 3 performs input and output of an optical signal to and from the optical component 20. Regarding the direction, the direction in which light is output from the optical connector 3 to the outside of the package 2 may be referred to as the front, front side, or forward, and the opposite direction of the front, front side, or forward may be referred to as the rear, rear side, or rear. For example, light output from the optical connector 3 to the rear, rear side, or rear is input to the optical component 20. However, these directions are for convenience of explanation and do not limit the direction in which the components are arranged.

[0034] For example, the package 2 has an electric wiring 2B. The electric wiring 2B is, for example, a feed-through electric wiring that penetrates a first side wall 2b (rear wall) on the rear side of the package 2 while maintaining the hermeticity (airtightness) of the internal space 2A. The electric wiring 2B has two ends. One end (first end) of the electric wiring 2B is exposed to the outside of the package 2. At the outer end of each of the electric wirings 2B of the package 2, a plurality of terminals 4 for electrical connection with an external device are arranged so as to be aligned along the second direction D2. The other end (second end) of the electric wiring 2B is provided facing the internal space 2A. At the inner end of each of the electric wirings 2B of the package 2, a plurality of terminals 5 for electrical connection with the driver IC 11 are arranged so as to be aligned along the second direction D2.

[0035] The package 2 has a fifth surface 2j on which an electric wiring 2B is formed, and a terminal 4 and a terminal 5 are further provided on the fifth surface 2j. The terminal 4 and the terminal 5 are electrically connected to each other via the electric wiring 2B. Therefore, electric signals can be exchanged between the outside and the inside (internal space 2A) of the package 2 via the electric wiring 2B. The electric signals include, for example, analog signals and digital signals as well as a power supply voltage and a ground voltage (ground potential). The fifth surface 2j is a surface parallel to the first surface 2f.

[0036] In the internal space 2A, each of the multiple terminals 5 is electrically connected to a pad 11b of the driver IC 11 via a bonding wire 8b. The driver IC 11 has a third surface 11d on the opposite side of the heat dissipation block 13, and the pads 11b are provided on the third surface 11d. In addition, a circuit (not shown) of the driver IC 11 is also formed on the third surface 11d. In the package 2, the multiple terminals 5 are lined up along the second direction D2. In the driver IC 11, the multiple pads 11b are lined up along the second direction D2. A plurality of bonding wires 8b are lined up along the second direction D2, and each bonding wire 8b electrically connects the terminals 5 and the pads 11b to each other.

[0037] The semiconductor integrated module 1 has a plurality of terminals 9b and a plurality of terminals 9c that extend along the second direction D2 and are exposed to the outside of the package 2. One end of each of the terminals 9b and 9c is exposed to the outside of the package 2 at each of the pair of second side walls 2c. The other end of each of the plurality of terminals 9b is electrically connected to a pad 11c of the driver IC 11 via a bonding wire 8c. The pad 11c is provided on a third surface 11d of the driver IC 11. The terminals 9b and 9c may be provided on only one of the pair of second side walls 2c.

[0038] The other end of each of the multiple terminals 9c is electrically connected to a pad 12b of the optical circuit element 12 via a bonding wire 8d. The optical circuit element 12 has a fourth surface 12d on the opposite side to the TEC 15, and the pad 12b is provided on the fourth surface 12d of the optical circuit element 12. A circuit (not shown) of the optical circuit element 12 is formed on the fourth surface 12d. As described above, an electrical signal is supplied to the semiconductor integrated module 1 via at least one of the terminal 4 and the terminals 9b and 9c, and the electrical signal is supplied to the driver IC 11 or the optical circuit element 12 via the bonding wires 8b, 8c, and 8d.

[0039] The optical circuit element 12 is formed, for example, using an InP compound semiconductor, and the linear expansion coefficient of the optical circuit element 12 is, for example, 4.5 ppm / °C. The temperature of the optical circuit element 12 is controlled to be constant by the TEC 15. The driver IC 11 is formed, for example, on a Si substrate, and the linear expansion coefficient of the driver IC 11 is, for example, 3 to 4 ppm / °C. The temperature of the driver IC 11 varies depending on the external temperature of the semiconductor integrated module 1, the power consumption of the driver IC 11, and the thermal resistance of the heat dissipation block 13 and the bottom wall 2h. The bottom wall 2h is made of, for example, copper tungsten (CuW), and has a linear expansion coefficient of 6 to 7 ppm / °C. In this way, since the linear expansion coefficients and temperatures of the multiple components constituting the semiconductor integrated module 1 are different from each other, the positions of the driver IC 11 and the optical circuit element 12 in the first direction D1, the second direction D2, and the third direction D3 can vary depending on the external temperature.

[0040] The semiconductor integrated module 1 has a bridge chip 30 that electrically connects the driver IC 11 and the optical circuit elements 12 to each other. Hereinafter, the direction in which the bridge chip 30 is viewed from the driver IC 11 and the optical circuit elements 12 may be referred to as top, upper side, or upward, and the direction in which the driver IC 11 and the optical circuit elements 12 are viewed from the bridge chip 30 may be referred to as bottom, lower side, or downward. However, these directions are provided for convenience of explanation and do not limit the positions and directions of components.

[0041] Fig. 3 is a bottom view showing the bridge chip 30. Fig. 4 is a plan view showing the bridge chip 30. As shown in Figs. 2, 3 and 4, the pad 11f of the driver IC 11 is electrically connected to the pad 12c of the optical circuit element 12 via the bridge chip 30. The bridge chip 30 is connected to the driver IC 11 and the optical circuit element 12 and transmits an electrical signal. The electrical signal transmitted by the bridge chip 30 has a band of, for example, 100 GHz or more.

[0042] For example, the bridge chip 30 has a rectangular plate shape. For example, the length in the second direction D2 of the bridge chip 30 is greater than the length in the first direction D1 of the bridge chip 30, and the length in the first direction D1 of the bridge chip 30 is greater than the length in the third direction D3 of the bridge chip 30. As an example, the length in the second direction D2 of the bridge chip 30 is 2 mm or more and 4 mm or less, the length (width) of the bridge chip 30 in the first direction D1 is 0.5 mm or more and 2 mm or less, and the length (thickness) of the bridge chip 30 in the third direction D3 is 0.1 mm or more and 0.5 mm or less.

[0043] The bridge chip 30 has a substrate 31, a first resin film 32, and a metal film 33. For example, when viewed along the third direction D3, the shape and size of the substrate 31 are the same as those of the first resin film 32. FIG. 5 is a cross-sectional view taken along the line AA in FIG. 4. As shown in FIGS. 3, 4, and 5, the substrate 31 has a first surface 31b and a second surface 31c opposite to the first surface 31b. The substrate 31 is made of silicon (Si). The substrate 31 has, for example, a rectangular plate shape. The length (thickness) of the substrate 31 in the third direction D3 is, for example, 0.2 mm.

[0044] The first resin film 32 has flexibility. For example, the flexibility of the first resin film 32 is higher than that of the substrate 31 and higher than that of the metal film 33. The first resin film 32 is formed on the first surface 31b. The first resin film 32 is interposed between the first surface 31b of the substrate 31 and the metal film 33. The first resin film 32 has a third surface 32b with which the first surface 31b of the substrate 31 contacts, and a fourth surface 32c opposite to the third surface 32b. The metal film 33 contacts the fourth surface 32c. The first resin film 32 has, for example, a rectangular plate shape. As an example, the length (thickness) of the first resin film 32 in the third direction D3 is 7 μm. For example, the first resin film 32 is made of polyimide. However, the first resin film 32 may be made of a material other than polyimide. For example, the first resin film 32 may be made of modified polyimide or polybenzoxazole.

[0045] The metal film 33 is formed on the first resin film 32. The metal film 33 is conductive. The metal film 33 is in contact with the fourth surface 32c of the first resin film 32. As an example, the length (thickness) of the metal film 33 in the third direction D3 is 3 μm. In this case, since the metal film 33 is thin, the flexibility of the metal film 33 is enhanced. The metal film 33 has a connection portion 33b for electrical connection with an element (e.g., the driver IC 11 or the optical circuit element 12). For example, the connection portion 33b is a pad.

[0046] For example, the bridge chip 30 has a plurality of metal films 33. In this case, the plurality of metal films 33 are arranged along the second direction D2. For example, the metal film 33 is made of copper (Cu). In this case, fine patterning is possible by plating, which will be described later. However, the metal film 33 may be made of a material other than copper. For example, the metal film 33 may be made of gold (Au) or aluminum (Al). The connection portion 33b of the metal film 33 is plated with, for example, Au. However, the connection portion 33b may have an intermediate layer containing nickel (Ni) or palladium (Pd) between Au and Cu. The plurality of metal films 33 are in contact with the first resin film 32. The first resin film 32 has insulating properties. The plurality of metal films 33 are electrically insulated from each other.

[0047] For example, the bridge chip 30 has a second resin film 34 formed on the first resin film 32 and the metal film 33. The second resin film 34 has flexibility. For example, the flexibility of the second resin film 34 is higher than that of the substrate 31 and higher than that of the metal film 33. The second resin film 34 is in contact with the fourth surface 32c of the first resin film 32. The second resin film 34 has an opening 34b on the metal film 33. For example, a part of the metal film 33 is exposed in the opening 34b, and the part of the metal film 33 exposed in the opening 34b is used as the connection portion 33b.

[0048] The second resin film 34 has, for example, a rectangular plate shape. The second resin film 34 has a plurality of openings 34b. The plurality of openings 34b are aligned along the second direction D2. For example, two openings 34b are aligned along the first direction D1. As an example, the openings 34b have a rectangular shape. For example, the second resin film 34 is made of polyimide. The material of the second resin film 34 may be the same as the material of the first resin film 32, or may be different from the material of the first resin film 32. The second resin film 34 may be made of a material other than polyimide. For example, the second resin film 34 may be made of modified polyimide or polybenzoxazole. The second resin film 34 is in contact with the plurality of metal films 33. The second resin film 34 has insulating properties. The plurality of metal films 33 are electrically insulated from each other. The second resin film 34 functions as a protective film that protects the plurality of metal films 33. The second resin film 34 can be omitted.

[0049] The metal film 33 includes a wiring 33A. The wiring 33A extends along a first direction D1. The wiring 33A has two ends. The wiring 33A has a first pad 33c formed as a connection portion 33b at one end (first end) and a second pad 33d formed as a connection portion 33b at the other end (second end). For example, the first pad 33c and the second pad 33d are disposed at both ends of the wiring 33A in the first direction D1.

[0050] For example, the first pad 33c is configured to be electrically connectable to the driver IC 11, and the second pad 33d is configured to be electrically connectable to the optical circuit element 12. In this case, the first pad 33c is connected to the pad 11f of the driver IC 11, and the second pad 33d is connected to the pad 12c of the optical circuit element 12. In the following, the portion where the first pad 33c is connected to the pad 11f of the driver IC 11 and the portion where the second pad 33d is connected to the pad 12c of the optical circuit element 12 are referred to as a joint portion. The joint portion includes, for example, either a stud bump 46 or a solder bump 62, which will be described later. For example, the metal film 33 includes a plurality of wirings 33A each extending in the first direction D1. The plurality of wirings 33A are arranged along the second direction D2. Thus, the plurality of first pads 33c are arranged along the second direction D2, and the plurality of second pads 33d are arranged along the second direction D2.

[0051] The bridge chip 30 has a set C consisting of a plurality of wirings 33A arranged along the second direction D2, and the plurality of sets C are arranged along the second direction D2. As an example, the number of wirings 33A constituting the set C is four. For example, in the set C, a single-layer coplanar line having a GSSG (ground-signal-signal-ground) configuration is formed. In the bridge chip 30, for example, four channels of the single-layer coplanar line having the above-mentioned GSSG configuration are formed. Since each channel has two signals, it is possible to transmit a differential signal. Note that the configuration of the transmission line is not limited to GSSG, and may be, for example, GSGSG (ground-signal-ground-signal-ground), SS (signal-signal), or SGS (signal-ground-signal). Furthermore, in the bridge chip 30, two layers of microstrip lines may be formed instead of one layer of coplanar lines.

[0052] For example, the thickness (length in the second direction D2) of the ground wiring 33A is larger than the thickness of the signal wiring 33A, for example, twice as large as that of the signal wiring 33A. For example, the ground wiring 33A has two first pads 33c aligned along the second direction D2 and two second pads 33d aligned along the second direction D2. For example, the signal wiring 33A has one first pad 33c at an end in the first direction D1 and one second pad 33d at an end opposite to the first pad 33c.

[0053] The substrate 31 has a buffer portion 31d penetrating the substrate 31 between the first surface 31b and the second surface 31c. FIG. 6 is a cross-sectional view taken along the line BB in FIG. 4. As shown in FIGS. 4, 5, and 6, the buffer portion 31d is, for example, a through hole penetrating the substrate 31 in the third direction D3. The inside of the through hole is hollow. For example, the buffer portion 31d has a rectangular shape in a plan view of the substrate 31 (when viewed along the third direction D3). The length of the buffer portion 31d in the second direction D2 is greater than the length of the buffer portion 31d in the first direction D1.

[0054] The connection parts 33b are disposed inside the buffer part 31d in a plan view of the substrate 31. That is, when viewed along the third direction D3, the multiple connection parts 33b are located inside the buffer part 31d. The buffer part 31d has, for example, a first inner surface 31q extending in both the second direction D2 and the third direction D3, and a second inner surface 31r extending in both the first direction D1 and the third direction D3. The buffer part 31d is defined by a pair of first inner surfaces 31q aligned along the first direction D1 and a pair of second inner surfaces 31r aligned along the second direction D2.

[0055] For example, the buffer section 31d includes a first buffer section 31h and a second buffer section 31j aligned along the first direction D1. In a plan view of the substrate 31, the first buffer section 31h includes a plurality of first pads 33c therein, and the second buffer section 31j includes a plurality of second pads 33d therein. In a plan view of the substrate 31, for example, each of the first buffer section 31h and the second buffer section 31j has a rectangular shape.

[0056] The substrate 31 has a support portion 31f located inside the buffer portion 31d in a plan view of the substrate 31, and a general portion 31w which is a portion of the substrate 31 other than the support portion 31f. The support portion 31f is made of, for example, silicon. The support portion 31f is provided inside the buffer portion 31d and is separated from the general portion 31w. That is, when viewed in a plan view along the third direction D3, the support portion 31f is surrounded by the buffer portion 31d. The connection portion 33b is connected to the second surface 31c of the substrate 31 via the first resin film 32 and the support portion 31f. The support portion 31f has a first outer surface 31k extending in both the second direction D2 and the third direction D3, and a second outer surface 31p extending in both the first direction D1 and the third direction D3. The support portion 31f has a pair of first outer surfaces 31k aligned along the first direction D1 and a pair of second outer surfaces 31p aligned along the second direction D2.

[0057] For example, the substrate 31 has a support portion 31f and a groove 31s surrounding the support portion 31f in the buffer portion 31d in a plan view of the substrate 31. As an example, the width of the groove 31s is 50 μm. The groove 31s is recessed from the second surface 31c along the third direction D3. The groove 31s penetrates the substrate 31 in the third direction D3. The groove 31s has a rectangular frame shape in a plan view of the substrate 31. The groove 31s includes a first groove 31t formed between the first inner surface 31q and the first outer surface 31k, and a second groove 31v formed between the second inner surface 31r and the second outer surface 31p. The groove 31s includes a pair of first grooves 31t aligned along the first direction D1 and a pair of second grooves 31v aligned along the second direction D2.

[0058] The groove 31s separates the support portion 31f from the general portion 31w. That is, the support portion 31f is separated from the general portion 31w. For example, the support portion 31f is an island independent from the general portion 31w. The connection portion 33b of the metal film 33 is connected to the support portion 31f, which is independent from the general portion 31w, inside the buffer portion 31d through the first resin film 32. Therefore, the portion of the substrate 31 and the first resin film 32 where the connection portion 33b is provided (the portion of the substrate 31 and the first resin film 32 that overlaps with the connection portion 33b when viewed in a plan view along the third direction D3) is easily displaced relative to the surrounding general portion 31w because the first resin film 32, the metal film 33, and the second resin film 34 have flexibility. The second resin film 34 may have a portion that overlaps with the groove 31s when viewed in a plan view of the substrate 31 removed. By removing the second resin film 34 from the portion overlapping the groove 31s in a plan view of the substrate 31, the portion of the substrate 31 and the first resin film 32 where the connection portion 33b is provided becomes more likely to be displaced relative to the surrounding general portion 31w.

[0059] The portion of the substrate 31 and the first resin film 32 where the first pad 33c is provided (the portion of the substrate 31 and the first resin film 32 overlapping with the first pad 33c when viewed in a plan view along the third direction D3) is surrounded by the first buffer portion 31h and the second buffer portion 31j and separated from the portion of the substrate 31 and the first resin film 32 where the second pad 33d is provided (the portion of the substrate 31 and the first resin film 32 overlapping with the second pad 33d when viewed in a plan view along the third direction D3). Thus, the portion of the substrate 31 and the first resin film 32 where the first pad 33c is provided and the portion of the substrate 31 and the first resin film 32 where the second pad 33d is provided can be displaced independently of each other. Therefore, even if the driver IC 11 or the heat dissipation block 13 connected to the first pad 33c, the optical circuit element 12, the spacer 14 or the TEC 15 connected to the second pad 33d, or the bottom wall 2h deform (for example, expand or contract) due to a temperature change or the like, the portion where the first pad 33c is provided and the portion where the second pad 33d is provided are flexibly displaced in response to the deformation. For example, when the distance between the first pad 33c and the second pad 33d is shortened due to the deformation, the distance between the portion where the first pad 33c is provided on the substrate 31 and the first resin film 32 and the portion where the second pad 33d is provided on the substrate 31 and the first resin film 32 is also shortened. In addition, when the distance between the first pad 33c and the second pad 33d is lengthened due to the deformation, the distance between the portion where the first pad 33c is provided on the substrate 31 and the first resin film 32 and the portion where the second pad 33d is provided on the substrate 31 and the first resin film 32 is also lengthened. Therefore, the joint between the driver IC 11 and the bridge chip 30, and the joint between the optical circuit element 12 and the bridge chip 30, etc. can be protected from the effects of stress.

[0060] Next, an example of a manufacturing method of the bridge chip 30 will be described with reference to Figs. 7 and 8. First, a Si substrate 41 that is the base of the substrate 31 is prepared (a process of preparing a Si substrate). For example, the Si substrate 41 is in the form of a wafer (for example, an 8-inch wafer). Next, a first resin film 32 is formed on the Si substrate 41 (a process of forming a first resin film). When forming the first resin film 32, a baking process may be performed.

[0061] After the first resin film 32 is formed, the seed layer 43 is formed (step of forming a seed layer). The seed layer 43 is made of, for example, copper (Cu). The seed layer 43 is formed by sputtering. Then, a resist 44 is formed on the seed layer 43 and patterned (step of patterning the resist). After patterning the resist 44, electroplating is performed to grow plating in the seed layer 43 where there is no resist 44, thereby forming a metal film 33 (step of forming a metal film). Then, the resist 44 is removed, and the seed layer 43 covered with the resist 44 is etched (for example, Cu etching).

[0062] Next, a second resin film 34 is formed on the first resin film 32 and the metal film 33 (step of forming a second resin film). At this time, the second resin film 34 is patterned by exposure and development to form a plurality of openings 34b through which the metal film 33 is exposed (step of forming openings). Then, a surface treatment is performed on the parts of the metal film 33 exposed from the openings 34b. More specifically, plating made of gold (Au), nickel (Ni) or palladium (Pd) is formed on the parts of the metal film 33 exposed from the openings 34b (step of forming plating). This forms the connection parts 33b.

[0063] Then, a resist 45 is formed on the surface 41b of the Si substrate 41 opposite to the first resin film 32, and patterned. After patterning the resist 45, etching (e.g., Si etching) is performed to form the grooves 31s (groove forming step). For example, deep etching using Deep RIE is performed to form the grooves 31s. The buffer portion 31d and the support portion 31f are formed by forming the grooves 31s. Then, the resist 45 is removed, dicing is performed, and the series of steps for manufacturing the bridge chip 30 is completed.

[0064] Next, an example of a method for manufacturing the semiconductor integrated module 1 will be described with reference to FIG. 9. First, in a package having a bottom wall 2h, a first side wall 2b, and a second side wall 2c, a heat dissipation block 13, a driver IC 11, a TEC 15, a spacer 14, an optical circuit element 12, and an optical component 20 are mounted on the bottom wall 2h. Stud bumps 46 are formed on the pads 11f of the driver IC 11 and the pads 12c of the optical circuit element 12 (step of forming stud bumps). For example, the stud bumps 46 are Au stud bumps. Note that in the package, the bottom wall 2h, the first side wall 2b, and the second side wall 2c may be integrally formed.

[0065] For example, the bridge chip 30 is held by the collet 47 with the connection parts 33b of the metal film 33 facing downward. Then, each connection part 33b is brought into contact with each stud bump 46, and the bridge chip 30 is flip-chip mounted on the driver IC 11 and the optical circuit element 12 by thermocompression bonding. At this time, since the connection parts 33b are supported by the tip of the collet 47 via the support parts 31f, it is possible to apply a load and heat to each stud bump 46. Note that instead of the above-mentioned thermocompression bonding, the bridge chip 30 may be mounted on the driver IC 11 and the optical circuit element 12 by ultrasonic bonding. After mounting the bridge chip 30, the lid 6 is placed on the first side wall 2b and the second side wall 2c to seal the internal space 2A, and then a series of steps for manufacturing the semiconductor integrated module 1 is completed. Note that before sealing the internal space 2A with the lid 6, the optical components 20 are mounted and the bonding wires 8b are wired.

[0066] Next, the effects obtained from the bridge chip 30 and the semiconductor integrated module 1 according to this embodiment will be described. The bridge chip 30 has a flexible first resin film 32 between the substrate 31 and the metal film 33. The metal film 33 has a connection portion 33b for electrical connection with the driver IC 11 and the optical circuit element 12, respectively. The substrate 31 has a buffer portion 31d penetrating the substrate 31, and the connection portion 33b is disposed inside the buffer portion 31d in a plan view of the substrate 31. Thus, the connection portion 33b, the flexible first resin film 32, and the buffer portion 31d are arranged in this order along the third direction D3, which is the stacking direction of the substrate 31, the first resin film 32, and the metal film 33. The portion where the connection portion 33b is located in the plan view of the substrate 31 is displaceable with respect to other portions of the bridge chip 30 because the connection portion 33b is separated from the surrounding substrate 31 (general portion 31w) by the buffer portion 31d.

[0067] FIG. 10 is a diagram showing a schematic diagram of displacement of a portion of the buffer portion 31d where the connecting portion 33b connected to the pad 12c of the optical circuit element 12 is located. As shown in FIG. 10, the portion of the substrate 31 (supporting portion 31f) and the first resin film 32 aligned with the connecting portion 33b along the third direction D3 is independent of the general portion 31w of the substrate 31, and therefore is a portion that can be displaced relative to the surrounding general portion 31w inside the buffer portion 31d by deformation of the first resin film 32, the metal film 33, and the second resin film 34. As an example, when the thickness (width) of the groove 31s is 50 μm, the portion aligned with the connecting portion 33b along the third direction D3 can be displaced by about 10 μm. FIG. 10 shows the displacement of the portion where the second pad 33d connected to the pad 12c of the optical circuit element 12 is located, but the portion where the first pad 33c connected to the pad 11f of the driver IC 11 is located can also be displaced in the same manner.

[0068] Since the connection portion 33b electrically connected to each of the driver IC 11 and the optical circuit element 12 can be displaced relative to other portions of the bridge chip 30, even if the pad 11f of the driver IC 11 and the pad 11f of the optical circuit element 12 are displaced due to temperature changes or the like, the effect of stress on the joint between the driver IC 11 and the bridge chip 30 and the joint between the optical circuit element 12 and the bridge chip 30 can be reduced. Therefore, the robustness of the electrical connection between the driver IC 11 and the optical circuit element 12 can be improved. For example, in the absence of the buffer portion 31d, the relative positions of the connection portion 33b connected to the driver IC 11 and the connection portion 33b connected to the optical circuit element 12 are fixed, so that the joint between the driver IC 11 and the bridge chip 30 and the joint between the optical circuit element 12 and the bridge chip 30 are subjected to stress in response to the displacement of the pad 11f of the driver IC 11 and the pad 11f of the optical circuit element 12.

[0069] Furthermore, in this embodiment, the portion of the substrate 31 and the first resin film 32 where the first pad 33c is provided and the portion of the substrate 31 and the first resin film 32 where the second pad 33d is provided are separated from the general portion 31w by the formation of the groove 31s. Therefore, it is possible to improve the heat insulation for the first pad 33c and the second pad 33d. As a result of performing a thermal analysis on a bridge chip 30 having a substrate 31 in which a groove 31s having a width of 50 μm is formed and a bridge chip having a substrate in which the groove 31s is not formed, the thermal resistance between the first pad 33c and the second pad 33d in the bridge chip in which the groove 31s is not formed was 104.4 [K / W], whereas the thermal resistance in the bridge chip 30 in which the groove 31s is formed was 202.6 [K / W].

[0070] The bridge chip 30 may include a flexible second resin film 34 that is formed on the first resin film 32 and the metal film 33 and has an opening 34b on the metal film 33. In this case, the flexible second resin film 34 can cover a part of the first resin film 32 and a part of the metal film 33. The second resin film 34 functions as a protective film for the metal film 33.

[0071] The substrate 31 may further have a support portion 31f on the inner side of the buffer portion 31d in a plan view of the substrate 31. The connection portion 33b may be connected to the second surface 31c of the substrate 31 via the first resin film 32 and the support portion 31f. In this case, the connection portion 33b, the first resin film 32 having flexibility, and the support portion 31f are arranged in this order along the third direction D3. Therefore, the first resin film 32 and the connection portion 33b can be supported by the support portion 31f while deforming the portion of the first resin film 32 arranged along the third direction D3 with the connection portion 33b. This allows, for example, when the bridge chip 30 is gripped by the collet 47 and mounted on the driver IC 11 and the optical circuit element 12, a load and heat can be effectively applied to bond the connection portion 33b to the pad 11f.

[0072] The first resin film 32 may be made of polyimide, in which case the first resin film 32 can be a resin film with excellent flexibility and stretchability.

[0073] The metal film 33 may be made of any of copper (Cu), gold (Au) and aluminum (Al).

[0074] The metal film 33 may include a wiring 33A having a shape extending in the first direction D1 and having two ends. One end (first end) of the wiring 33A has a first pad 33c formed as a connection portion 33b, and the other end (second end) of the wiring 33A has a second pad 33d formed as a connection portion 33b. The first pad 33c may be configured to be electrically connectable to the driver IC 11, and the second pad 33d may be configured to be electrically connectable to the optical circuit element 12 separated from the driver IC 11. In this case, the first pad 33c of the wiring 33A of the metal film 33 can be electrically connected to the driver IC 11, and the second pad 33d of the wiring 33A of the metal film 33 can be electrically connected to the optical circuit element 12. This allows an electrical signal to be transmitted from the driver IC 11 to the optical circuit element 12 via the wiring 33A.

[0075] The metal film 33 may include a plurality of wirings 33A each extending in the first direction D1, and each of the plurality of wirings 33A has two ends. Each of the wirings 33A may have a first pad 33c at one end (first end) and a second pad 33d at the other end (second end) of the wiring 33A. The first pads 33c of the plurality of wirings 33A may be arranged along the second direction D2, and the second pads 33d of the plurality of wirings 33A may be arranged along the second direction D2. The plurality of wirings 33A are insulated from each other. The buffer section 31d may include a first buffer section 31h including a plurality of first pads 33c on the inside in a plan view of the substrate 31, and a second buffer section 31j including a plurality of second pads 33d on the inside in a plan view of the substrate 31. In this case, the first pad 33c and the portion of the first resin film 32 aligned on the first pad 33c along the third direction D3, and the second pad 33d and the portion of the first resin film 32 aligned on the second pad 33d along the third direction D3 can be made displaceable from each other.

[0076] The substrate 31 may be made of silicon. Also, the support portion 31f of the substrate 31 may be made of silicon. In this case, the substrate 31 can be easily heated during mounting, etc. Also, the grooves 31s can be easily formed by etching.

[0077] Next, the bridge chip according to the modified example will be described. The configuration of a part of the bridge chip according to the various modified examples described later is the same as the configuration of a part of the bridge chip 30 described above. Therefore, in the following description, the same reference numerals will be used to denote parts that overlap with the configuration of the bridge chip 30, and the description will be omitted as appropriate.

[0078] Fig. 11 is a plan view showing an internal structure of a semiconductor integrated module including a bridge chip 50 according to a first modified example. Fig. 12 is a cross-sectional view of the semiconductor integrated module of Fig. 11 taken along a plane extending along both the first direction D1 and the third direction D3. As shown in Figs. 11 and 12, the bridge chip 50 extends from the optical circuit element 12, past the driver IC 11, to the package 2.

[0079] The bridge chip 50 has a substrate 51, a first resin film 52, and a metal film 53. The first resin film 52 is the same as the first resin film 32, except for the length in the first direction D1, for example. The metal film 53 includes a wiring 53A, and the wiring 53A has a first pad 33c, a second pad 33d, a third pad 53c, and a fourth pad 53d as a connection portion 53b. The third pad 53c is configured to be electrically connectable to the driver IC 11, and the fourth pad 53d is configured to be electrically connectable to the package 2. More specifically, the third pad 53c is connected to the pad 11b of the driver IC 11, and the fourth pad 53d is connected to the terminal 5 formed on the fifth surface 2j of the package 2.

[0080] The substrate 51 has a buffer section 51d and a support section 51f. For example, the shape and size of the buffer section 51d are the same as those of the buffer section 31d described above, and the shape and size of the support section 51f are the same as those of the support section 31f described above. The buffer section 51d includes a first buffer section 31h, a second buffer section 31j, a third buffer section 51h, and a fourth buffer section 51j. In a plan view of the substrate 51, the third buffer section 51h includes a plurality of third pads 53c therein, and the fourth buffer section 51j includes a plurality of fourth pads 53d therein.

[0081] As described above, in the bridge chip 50 according to the first modification, the substrate 51 has the buffer portion 51d penetrating the substrate 51, and the connection portion 53b is disposed inside the buffer portion 51d in a plan view of the substrate 51. Therefore, the portion where the connection portion 53b is located in a plan view of the substrate 51 can be displaced relative to other portions of the bridge chip 50 by the deformation of the first resin film 32 around the portion. Since the connection portions 53b electrically connected to the driver IC 11, the optical circuit element 12, and the package 2 are configured to be displaceable relative to each other, the influence of stress on the joint between the package 2 and the bridge chip 50, the joint between the driver IC 11 and the bridge chip 50, and the joint between the optical circuit element 12 and the bridge chip 50 can be reduced. Therefore, the bridge chip 50 can obtain the same effect as the bridge chip 30. Furthermore, since the bridge chip 50 extends from the optical circuit element 12 to the package 2 over the driver IC 11, the bonding wire 8b connecting the package 2 and the driver IC 11 to each other can be eliminated.

[0082] FIG. 13 is a plan view showing a bridge chip 60 according to a second modified example. FIG. 14 is a cross-sectional view taken along the line CC in FIG. 13. FIG. 15 is a cross-sectional view taken along the line DD in FIG. 13. As shown in FIG. 13, FIG. 14, and FIG. 15, the bridge chip 60 includes a substrate 61 that does not have a support portion 31f. Therefore, in a portion along the third direction D3 from the connection portion 33b, the first resin film 32 is provided but the substrate 61 is not provided. Therefore, in the bridge chip 60, the portion of the first resin film 32 where the connection portion 33b is provided (the portion of the first resin film 32 that overlaps with the connection portion 33b when viewed in plan along the third direction D3) is more easily displaced relative to the surrounding general portion 31w than in the case of the bridge chip 30.

[0083] FIG. 16 is a diagram for explaining mounting of the bridge chip 60 on the driver IC 11 and the optical circuit element 12. As shown in FIG. 16, the bridge chip 60 has solder bumps 62 formed on the connection parts 33b. The solder bumps 62 are made of, for example, tin-silver-copper (SnAgCu) or gold-tin (AuSn). For example, the bridge chip 60 is held by a collet 47 with the solder bumps 62 facing downward. Then, each solder bump 62 is brought into contact with the stud bumps 46, and the solder bumps 62 are melted by heating to flip-chip mount the bridge chip 60 on the driver IC 11 and the optical circuit element 12.

[0084] As described above, in the bridge chip 60 according to the second modification, the first resin film 32 is provided at a position along the third direction D3 from the connection portion 33b, but the substrate 61 (support portion 31f) is not provided. Therefore, the portion of the first resin film 32 where the connection portion 33b is provided can be more easily deformed, so that the influence of stress on the joint between the driver IC 11 and the bridge chip 60 and the joint between the optical circuit element 12 and the bridge chip 60 can be more reliably reduced even if a temperature change occurs. Furthermore, the bridge chip 60 has solder bumps 62 formed on the connection portions 33b. In this case, the solder bumps 62 can be melted by heating to connect the connection portions 33b to the driver IC 11 and the optical circuit element 12, respectively. Therefore, the connection portions 33b can be connected to the driver IC 11 and the optical circuit element 12 without pressing the connection portions 33b against the driver IC 11 and the optical circuit element 12 via the support portion 31f during connection.

[0085] FIG. 17 is a plan view showing a bridge chip 70 according to a third modified example. FIG. 18 is a cross-sectional view taken along the line EE in FIG. 17. As shown in FIG. 17 and FIG. 18, the bridge chip 70 includes a substrate 71 having a plurality of support portions 71f formed inside each of the first buffer portion 31h and the second buffer portion 31j, a first resin film 32, and a metal film 73. In the bridge chip 70, for example, one layer of coplanar lines having a GSSG configuration is formed with four channels. The metal film 73 includes a ground wiring 73A and a signal wiring 73B, and for example, the thickness of the ground wiring 73A is approximately the same as the thickness of the signal wiring 73B.

[0086] The substrate 71 has a plurality of support portions 71f aligned along the second direction D2. The support portions 71f are provided, for example, for each channel. The bridge chip 70 has a set C made up of a plurality of GSSG wirings aligned along the second direction D2, and a support portion 71f is provided for each set C. In a plan view of the substrate 71, a groove 71s is formed between two sets C aligned along the second direction D2. The groove 71s separates the plurality of support portions 71f from one another.

[0087] As described above, in the bridge chip 70 according to the third modification, the substrate 71 has a plurality of support parts 71f separated from each other, and the support parts 71f are provided for each channel. Therefore, the part where the connection part 33b is located in the plan view of the substrate 71 can be displaced independently for each channel. In the third modification, an example in which a divided support part 71f is provided for each channel has been described. However, the support part 71f does not have to be provided for each channel, and the manner of separation of the support part 71f is not particularly limited. That is, in the third modification, the plurality of support parts 71f are configured by dividing one support part 31f into four for each channel, but the plurality of support parts 71f may be configured by dividing one support part 31f into two or three, and the number of divisions for dividing one support part 31f into the plurality of support parts 71f may be five or more.

[0088] FIG. 19 is a plan view showing a bridge chip 80 according to a fourth modified example. The bridge chip 80 has a substrate 81 in which a hole 82 is formed, which is located between the first buffer section 31h and the second buffer section 31j and recessed from the second surface 31c along the third direction D3. The substrate 81 has a plurality of holes 82, and for example, the holes 82 penetrate the substrate 81 in the third direction D3. In a plan view of the substrate 81, for example, the plurality of holes 82 are arranged in a staggered manner. However, the arrangement of the plurality of holes 82 is not particularly limited. In this bridge chip 80, the hole 82 is formed between the first buffer section 31h and the second buffer section 31j in a plan view of the substrate 81. Therefore, it is possible to improve the thermal insulation between the connection section 33b (first pad 33c) in the first buffer section 31h and the connection section 33b (second pad 33d) in the second buffer section 31j. This makes it possible to reduce, for example, the flow of heat from the driver IC 11 to the optical circuit element 12 via the bridge chip 80 (such a phenomenon is called thermal crosstalk).

[0089] Fig. 20 is a cross-sectional view showing a semiconductor integrated module 91 according to a fifth modified example. As shown in Fig. 20, the semiconductor integrated module 91 includes a base 92 having a reference surface 92b, a first element 93 and a second element 94 mounted on the reference surface 92b, and the bridge chip 30 described above. For example, the first element 93 is an element that transmits an electric signal, and the second element 94 is an element that receives an electric signal. For example, the semiconductor integrated module 91 is not an optical module, and the semiconductor integrated module 91 does not require impedance control as in the semiconductor integrated module 1 described above.

[0090] The base 92 is, for example, a package substrate made of an organic material. The first element 93 has a first pad 93b and a second pad 93c formed on a surface facing away from the base 92. The second element 94 has a third pad 94b and a fourth pad 94c formed on a surface facing away from the base 92. The first element 93 and the second element 94 are face-up mounted on the base 92. For example, the semiconductor integrated module 91 has a first bonding wire 95b and a second bonding wire 95c. The first bonding wire 95b electrically connects a pad (not shown) of the base 92 and the first pad 93b to each other, and the second bonding wire 95c electrically connects a pad (not shown) of the base 92 and the fourth pad 94c to each other. The second pad 93c is connected to the connection portion 33b (first pad 33c) of the bridge chip 30 via a stud bump 96b, and the third pad 94b is connected to the connection portion 33b (second pad 33d) of the bridge chip 30 via a stud bump 96c.

[0091] As described above, the semiconductor integrated module 91 according to the fifth modification includes the bridge chip 30 described above, and therefore has the same effects as those described above. That is, the connection portion 33b connected to the first element 93 and the connection portion 33b connected to the second element 94 can be displaced relative to each other. Therefore, even if a temperature change or the like occurs, the connection portion 33b and the portion of the first resin film 32 aligned along the third direction D3 are displaced, thereby reducing the effect of stress on the joint between the first element 93 and the bridge chip 30 and the joint between the second element 94 and the bridge chip 30. Therefore, the robustness of the electrical connection between the first element 93 and the second element 94 can be improved.

[0092] Fig. 21 is a cross-sectional view showing a semiconductor integrated module 101 according to a sixth modified example. As shown in Fig. 21, the semiconductor integrated module 101 includes a base 102 having a reference surface 102b, a first element 103 and a second element 104 mounted on the reference surface 102b, and the bridge chip 30 described above. For example, the first element 103 is an element that transmits an electric signal, and the second element 104 is an element that receives an electric signal. When viewed along the third direction D3, the bridge chip 30 is disposed between the first element 103 and the second element 104.

[0093] The base 102 is, for example, a package substrate made of an organic material. The base 102 has a pad 102c arranged at a position facing the first element 103 on the reference surface 102b, and a pad 102d arranged at a position facing the second element 104 on the reference surface 102b. For example, the base 102 has a plurality of pads 102c and a plurality of pads 102d. The plurality of pads 102c and the plurality of pads 102d are lined up along the reference surface 102b.

[0094] The first element 103 has a first pad 103b and a second pad 103c formed on a surface facing the base 102. The second element 104 has a third pad 104b and a fourth pad 104c formed on a surface facing the base 102. The semiconductor integrated module 101 has a first terminal 105b and a second terminal 105c for surface mounting provided on the pads 102c and 102d of the base 102, respectively. The first terminal 105b electrically connects the pads 102c and the first pad 103b to each other, and the second terminal 105c electrically connects the pads 102d and the third pad 104b to each other. That is, the first element 103 and the second element 104 are mounted face-down on the base 102. Note that face-down mounting is also called flip-chip mounting.

[0095] In the semiconductor integrated module 101, the bridge chip 30 is disposed so that the substrate 31 faces the base 102 and the connection portion 33b faces the first element 103 and the second element 104. That is, the bridge chip 30 is disposed so that the connection portion 33b faces upward and the substrate 31 faces downward. The substrate 31 faces the base 102. The bridge chip 30 extends in both the first direction D1 and the second direction D2 between the first element 103 and the second element 104 and the base 102. The connection portion 33b (first pad 33c) is connected to the second pad 103c via, for example, a stud bump 106b, and the connection portion 33b (second pad 33d) is connected to the fourth pad 104c via, for example, a stud bump 106c. Solder bumps may be used instead of the stud bumps 106c. Bridge chip 30 is connected, for example, by face-down mounting to first element 103 and second element 104 arranged in a face-up state on a table of an assembly jig. First element 103 and second element 104 to which bridge chip 30 is connected are mounted upside down on base 102.

[0096] Next, the bridge chip according to the seventh modification will be described. The shape and size of the bridge chip according to the seventh modification are the same as those of the bridge chip 30 shown in Figures 2, 3, and 4. The bridge chip according to the seventh modification is different from the bridge chip 30 in that the substrate 31 is made of glass.

[0097] A method for manufacturing a bridge chip according to the seventh modified example will be described with reference to Fig. 22 and Fig. 23. In the following, descriptions overlapping with the method for manufacturing the bridge chip 30 shown in Fig. 7 and Fig. 8 will be omitted as appropriate. First, a Si glass integrated substrate 111 is prepared (a process for preparing a Si glass integrated substrate). In the Si glass integrated substrate 111, a portion where the groove 31s is to be formed is made of silicon 112 in advance, and a portion where the groove 31s is not to be formed is made of glass 113.

[0098] The first resin film 32 is formed, the seed layer 43 is formed, the resist 44 is patterned, the metal film 33 is formed, the second resin film 34 is formed, and the metal film 33 is surface-treated. After the surface treatment is performed on the part of the metal film 33 exposed from the opening 34b of the second resin film 34, Si etching (for example, dry etching of the silicon 112) is performed to form the groove 31s. Then, after dicing, the bridge chip according to the seventh modification is completed. As described above, in the bridge chip according to the seventh modification, since the substrate 31 is made of glass, the heat insulation of the substrate 31 can be further improved and the thermal crosstalk can be reduced. Furthermore, even in the bridge chip made of glass 113, which is difficult to etch, the groove 31s can be easily manufactured by using the Si-glass integrated substrate 111 as described above. When etching Si in FIG. 23, the etching rate of glass is smaller than that of Si, so no resist is used. However, Si may be etched using the resist 45 as in FIG. 8.

[0099] Next, the bridge chip according to the eighth modification will be described. The shape and size of the bridge chip according to the eighth modification are the same as those of the bridge chip 30 shown in Figures 2, 3, and 4. In the bridge chip according to the eighth modification, the support portion 31f of the substrate 31 is made of silicon, and the portions of the substrate 31 other than the support portion 31f are made of glass.

[0100] A method for manufacturing a bridge chip according to the eighth modified example will be described with reference to Fig. 24 and Fig. 25. First, a Si glass integrated substrate 121 is prepared (a process for preparing a Si glass integrated substrate). In the Si glass integrated substrate 121, the portions where the grooves 31s and the supporting portions 31f are to be formed are made of silicon 122 in advance, and the portions where neither the grooves 31s nor the supporting portions 31f are to be formed are made of glass 123. As in the seventh modified example described above, the first resin film 32 is formed, the seed layer 43 is formed, the resist 44 is patterned, the metal film 33 is formed, the second resin film 34 is formed, and the metal film 33 is surface-treated.

[0101] After performing surface treatment on the portion of the metal film 33 exposed from the opening 34b of the second resin film 34, a resist 45 is patterned on the portion where the support portion 31f of the silicon 112 is to be formed. After patterning the resist 45, a groove 31s is formed by performing Si etching. The silicon 122 in the portion not etched by Si is formed as the support portion 31f. Then, after removing the resist 45 and performing dicing, the bridge chip according to the eighth modification is completed. As described above, in the bridge chip according to the eighth modification, the portion between the first buffer portion 31h and the second buffer portion 31j in the substrate 31 is made of glass. Therefore, in the bridge chip according to the eighth modification, the heat insulation of the substrate 31 can be further improved, and the same effect as that of the seventh modification can be obtained. When etching Si in FIG. 25, the etching rate of glass is smaller than that of Si, so the resist 45 is not formed on the glass. However, the resist 45 may also be formed on the glass.

[0102] The embodiment and various modified examples of the bridge chip and semiconductor integrated module according to the present disclosure have been described above. However, the present invention is not limited to the above-mentioned embodiment or various modified examples, and can be modified as appropriate within the scope of the gist described in the claims. In addition, the bridge chip and semiconductor integrated module according to the present disclosure may be a combination of multiple examples of the above-mentioned embodiment and the first to eighth modified examples. For example, the configuration, shape, size, material, number, and arrangement of each part of the bridge chip and semiconductor integrated module according to the present disclosure are not limited to the above-mentioned embodiment or modified examples, and can be modified as appropriate. For example, in the above-mentioned embodiment, the bridge chip 30 having the second resin film 34 has been described. However, the bridge chip may not have the second resin film 34. [Explanation of symbols]

[0103] 1. Semiconductor integrated module 2. Package 2A…Internal space 2b…First side wall 2B…Electrical wiring 2c…Second side wall 2f...Front page 2g…Second side 2h…Bottom wall 2j...Side 5 3...Optical connector 4,5…Terminal 6. Lid 8b, 8c, 8d...Bonding wire 9b, 9c...Terminals 11...Driver IC (first element) 11b, 11c...Pad 11d…Side 3 11f…Pad 12...Optical circuit element (second element) 12b, 12c...Pad 12d…Side 4 13…Heat dissipation block 14…Spacer 15…TEC 20...Optical components 30…Bridge tip 31...Substrate 31b…First page 31c…Second side 31d…Buffer section 31f…Support part 31h...1st buffer section 31j…Second buffer section 31k…1st outer surface 31p…Second outer surface 31q…First inner surface 31r…Second inner surface 31s…Groove 31t…1st groove 31v…2nd groove 31w…General section 32…First resin film 32b...Third side 32c…Side 4 33...Metal film 33A…Wiring 33b…Connection 33c…First pad 33d…Second pad 34…Second resin film 34b…Aperture 41...Si substrate 41b...side 43…Seed layer 44,45…Resist 46…Stud bump 47…Colette 50…Bridge tip 51... Circuit board 51d...Buffer section 51f…Support part 51h...Third buffer section 51j…4th buffer section 52…First resin film 53...Metal film 53A…Wiring 53b…Connection 53c…3rd pad 53d…4th pad 60…Bridge tip 60Ω…Differential 61...Substrate 62...Solder bump 70…Bridge tip 71...Substrate 71f…Support part 71s…Groove 73...Metal film 73A, 73B…Wiring 80…Bridge tip 81...Substrate 82…hole 91...Semiconductor integrated module 92…Bass 92b…Reference plane 93...First element 93b…First pad 93c…Second pad 94…Second element 94b…3rd pad 94c…4th pad 95b…First bonding wire 95c…Second bonding wire 96b, 96c…Stud bump 101...Semiconductor integrated module 102...Bass 102b…Reference plane 102c, 102d…Pad 103...First element 103b…First pad 103c…Second pad 104...Second element 104b…3rd pad 104c…4th pad 105b…First terminal 105c…2nd terminal 106b, 106c…Stud bump 111...Si glass integrated substrate 112...Silicon 113…Glass 121...Si glass integrated substrate 122...Silicon 123…Glass C...group D1…first direction D2…Second direction D3…Third direction

Claims

1. a substrate having a first surface and a second surface opposite the first surface; a first resin film having flexibility and formed on the first surface of the substrate; a metal film formed on the first resin film; Equipped with the metal film has a connection portion for electrical connection with an element; the substrate has a buffer portion penetrating the substrate between the first surface and the second surface, The connection portion is disposed on the inner side of the buffer portion in a plan view of the substrate. Bridge chip.

2. a second resin film having flexibility, formed on the first resin film and the metal film, and having an opening on the metal film; The bridge chip of claim 1 .

3. the substrate further includes a support portion on an inner side of the buffer portion in a plan view of the substrate, the connecting portion is connected to the second surface of the substrate via the first resin film and the supporting portion.

3. The bridge chip according to claim 1 or 2.

4. Further comprising a solder bump formed on the connection portion.

3. The bridge chip according to claim 1 or 2.

5. The first resin film is made of polyimide.

3. The bridge chip according to claim 1 or 2.

6. The metal film is made of any one of copper, gold, and aluminum.

3. The bridge chip according to claim 1 or 2.

7. the metal film includes a wiring having a first pad formed as the connection portion at a first end and a second pad formed as the connection portion at a second end, the first pad is configured to be electrically connectable to a first element; The second pad is configured to be electrically connectable to a second element spaced apart from the first element.

3. The bridge chip according to claim 1 or 2.

8. the metal film includes a plurality of wirings each extending in a first direction; Each of the plurality of wirings has a first pad at a first end and a second pad at a second end; the first pads of the plurality of wirings are arranged along a second direction intersecting the first direction; The second pads of the plurality of wirings are arranged along the second direction, the buffer section includes a first buffer section including a plurality of the first pads therein when viewed in a plane of the substrate, and a second buffer section including a plurality of the second pads therein when viewed in a plane of the substrate, 3. The bridge chip according to claim 1 or 2.

9. The substrate is made of silicon.

3. The bridge chip according to claim 1 or 2.

10. The substrate is made of glass.

3. The bridge chip according to claim 1 or 2.

11. The support portion of the substrate is made of silicon. The bridge chip according to claim 3 .

12. a base having a reference surface; a first element mounted to the reference surface and transmitting an electrical signal; a second element mounted to the reference surface and receiving the electrical signal; a bridge chip according to claim 1 or 2, connected to the first element and the second element and transmitting the electrical signal; Equipped with Semiconductor integrated module.

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