Slave device, communication system, imaging apparatus, master device, and data communication method

Abstract

To provide a system with which, while suppressing the pressure of communication bands, it is possible for some of a plurality of slave devices having the same common address and a master device to communicate data.SOLUTION: In a slave device 32 for communicating data to a master device via a bus, a communication unit communicates data to the master device on the basis of a control signal including address information that indicates an address common to a plurality of slave devices, designation information that designates at least one slave device to which data is to be communicated among the plurality of slave devices, and data length information that indicates the data length that the slave device designed by designation information receives or transmits in a prescribed order, in order to read from a register of the slave device or write to the register the data having the data length indicated by the data length information, in accordance with the predetermined order and the designation information.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a slave device, a communication system, an imaging apparatus, a master device, and a data communication method. [Background technology]

[0002] Patent Document 1 discloses an I2C communication device with a changeable address. Patent Document 2 discloses a communication device in which a plug-in module manages slaves added to a platform. Patent Document 3 discloses a method in which multiple integrated circuits that communicate with a host provide registers for storing unique slave addresses, global addresses, and sequence numbers. Patent Document 4 discloses a method of communication by assigning virtual device addresses to multiple devices as global devices. [Prior art document] [Patent documents] [Patent Document 1] Special Publication No. 2004-510228 [Patent Document 2] International Publication No. 2014 / 083707 [Patent Document 3] Chinese Patent Application Publication No. 112148656 [Patent Document 4] U.S. Patent Application Publication No. 2016 / 0314087 Summary of the Invention [Problem to be solved by the invention]

[0003] There is a demand for a system that enables data communication between a master device and some of a plurality of slave devices having the same common address while minimizing pressure on the communication band. [Means for solving the problem]

[0004] A first aspect of the present invention provides a slave device that performs data communication with a master device via a bus, the slave device including a communication unit that performs data communication with the master device based on a control signal including address information indicating an address common to a plurality of slave devices, designation information designating at least one slave device among the plurality of slave devices as a target of data communication, and data length information indicating a data length received or transmitted in a predetermined order by the slave device designated by the designation information, so as to read data of a data length indicated in the data length information from a register of the slave device or write data to the register of the slave device in accordance with the predetermined order and the designation information.

[0005] In the slave device, each of the plurality of slave devices may have an ID to which a predetermined order is uniquely assigned, and the communication unit may determine an order of reading or writing the data from or to the slave device itself based on the ID and the designation information.

[0006] In any of the slave devices, each of the plurality of slave devices may be uniquely assigned a predetermined order. The designation information may have a first bit sequence in which at least one slave device to be a target of data communication among the plurality of slave devices is assigned to each bit. When the slave device is assigned to a bit having a first value in the first bit sequence, the communication unit may receive or transmit data of a data length indicated in the data length information in accordance with the predetermined order and the designation information. When the slave device is assigned to a bit having a second value in the first bit sequence, the communication unit may determine that the slave device is not a target of data communication.

[0007] In any of the slave devices, the address information may include a first bit indicating whether the slave device is to read or write data, and the communication unit may determine whether the slave device is to read or write data based on the first bit.

[0008] In any of the slave devices, the data length information may have a second bit sequence corresponding to a register address and data length of the slave device from which the slave device is to read or write data. The communication unit may identify a register address and data length of the slave device from which the slave device is to read or write data, which corresponds to the second bit sequence included in the data length information, by referring to a map indicating a relationship between the second bit sequence and the register address and data length of the slave device from which the slave device is to read or write data. When the slave device is a target of data communication, the communication unit may receive or transmit data of the data length indicated in the data length information in accordance with the predetermined order and the designation information by accessing the register address of the slave device from which the slave device is to read or write data.

[0009] In any of the slave devices, a predetermined order may be uniquely assigned to each of the plurality of slave devices. The address information may include a first bit indicating whether the slave device should read or write data. The designation information may have a first bit sequence in which at least one slave device among the plurality of slave devices that is a target of data communication is assigned to each bit. The data length information may have a second bit sequence corresponding to a register address of the slave device from which the slave device should read or write data and a data length. The communication unit may determine whether the slave device should read data from the register or write data to the register based on the first bit. When the address information indicates the common address and the slave device is assigned to a bit having a first value in the first bit sequence, the communication unit may determine that the slave device is a target of data communication. When the address information indicates the common address and the slave device is assigned to a bit having a second value in the first bit sequence, the communication unit may determine that the slave device is not a target of data communication. When the slave device is a target of data communication, the communication unit may identify a register address of the slave device from which the slave device is to read or write data and a data length corresponding to the second bit sequence included in the data length information, by referring to a map indicating a relationship between a second bit sequence and a register address of the slave device from which the slave device is to read or write data and the data length. When the slave device is a target of data communication, the communication unit may receive or transmit data of the data length indicated in the data length information in accordance with the predetermined order and the designation information, by accessing the register address of the slave device from which the slave device is to read or write data.

[0010] In any of the slave devices, the address information may indicate the common address or an individual address that uniquely identifies each of the multiple slave devices. When the address information indicates the individual address, the control signal may include, instead of the designation information and the data length information, register information indicating a register address of the slave device from which the slave device corresponding to the individual address, which is the target of data communication, should read or write data. When the address information indicates an individual address of the slave device, the communication unit may perform data communication with the master device to read or write data by accessing the register address of the slave device indicated in the register information.

[0011] In any of the slave devices, the slave device may communicate data with the master device using an I2C communication method.

[0012] In any of the slave devices, the slave device may be an IC chip.

[0013] In a second aspect of the present invention, there is provided a communication system including any one of the slave devices and the master device that transmits the control signal to the plurality of slave devices via the bus.

[0014] In a third aspect of the present invention, there is provided an imaging device comprising the communication system, an optical system, a plurality of imaging units each having an imaging element that captures an image formed through the optical system, and a driving unit that drives at least one of the optical system and the imaging element, and each of the plurality of slave devices drives at least one of the optical system and the imaging element by controlling the respective driving unit in accordance with the respective data.

[0015] In a fourth aspect of the present invention, there is provided an imaging device comprising: the communication system; an optical system; an imaging unit having an imaging element that captures an image formed through the optical system; and a driving unit that drives at least one of the optical system and the imaging element, and each of the plurality of slave devices drives at least one of the optical system and the imaging element by controlling the driving unit in accordance with the respective data.

[0016] In a fifth aspect of the present invention, there is provided a master device that performs data communication with a plurality of slave devices via a bus, the master device including a communication unit that performs data communication with at least one slave device among the plurality of slave devices that is the target of data communication by transmitting, to the plurality of slave devices via the bus, a control signal including address information indicating an address common to the plurality of slave devices, designation information designating at least one slave device among the plurality of slave devices that is the target of data communication, and data length information indicating a data length to be received or transmitted in a predetermined order by the slave device designated by the designation information.

[0017] In a sixth aspect of the present invention, there is provided a data communication method for performing data communication between a master device and a plurality of slave devices via a bus, the data communication method comprising the steps of: receiving, from the master device, a control signal by a slave device among the plurality of slave devices, the control signal including address information indicating an address common to the plurality of slave devices, designation information designating at least one slave device among the plurality of slave devices as a target of data communication, and data length information indicating a data length to be received or transmitted in a predetermined order by the slave device designated by the designation information; and, when the slave device is designated as a target of data communication by the designation information, performing data communication with the master device based on the control signal to read data of the data length indicated in the data length information from a register of the slave device or write data to the register of the slave device in accordance with the predetermined order and the designation information.

[0018] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a diagram showing an example of a schematic diagram of a user terminal 100 having an imaging device 10 including a plurality of cameras 12a to 12c. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of cameras 12a to 12c. [Diagram 3] FIG. 1 is a diagram showing an example of the configuration of substrates 16 and 26. [Figure 4] FIG. 1 is a diagram showing an example of a master-slave configuration for controlling a conventional IC chip. [Diagram 5] FIG. 1 shows an example of a control signal transmitted by the master device 20 to control six slave devices 22a to 22f. [Figure 6]FIG. 11 is a diagram showing another example of the control signal transmitted by the master device 20 to control the six slave devices 22a to 22f. [Figure 7] FIG. 1 is a diagram illustrating an example of a configuration of a communication system according to an embodiment of the present invention. [Figure 8] FIG. 2 illustrates an example of the configuration of a slave device 32. [Figure 9] FIG. 4 is a diagram showing an example of a control signal 90 according to the embodiment. [Figure 10] A diagram showing an example of the structure of ADRS bit 94. [Figure 11] FIG. 4 is a diagram showing an example of a reference table showing combinations of control targets of a slave device 32 (IC chip) according to the embodiment. [Figure 12] FIG. 4 is a diagram illustrating an example of a control map according to the embodiment. [Figure 13] 11 is a diagram showing an example of a control signal 130 when performing a 1-byte write according to the embodiment. FIG. [Figure 14] FIG. 11 is a diagram showing an example of a control signal 140 when performing a 2-byte write according to the embodiment. [Figure 15] FIG. 11 is a diagram showing an example of a control signal 150 when performing a 2-byte write according to the embodiment. [Figure 16] 13 is a diagram showing an example of a control signal 160 when performing a 1-byte read according to the embodiment. FIG. [Figure 17] FIG. 11 is a diagram showing an example of a control signal 170 when performing a 2-byte read according to the embodiment. [Figure 18] FIG. 4 is a diagram showing an example of a flowchart of the operation of an IC recognition unit 64 according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] 1 is a diagram showing an example of a schematic diagram of a user terminal 100 having an imaging device 10 including multiple cameras 12a to 12c. Note that in this specification, the multiple cameras 12a to 12c, etc. may be collectively referred to as multiple cameras 12, or cameras 12, etc.

[0022] As an example, the user terminal 100 is a device including an imaging device 10 built into a smartphone, a tablet, a laptop computer, a small personal computer, etc. As another example, the user terminal 100 may be a device including an imaging device 10 for capturing moving images, such as a digital camera, a web camera, or a video camera.

[0023] The multiple cameras 12 have optical systems with different focal lengths and angles of view. The imaging ranges of the multiple cameras 12 overlap. Here, the camera 12a is, for example, an ultra-wide-angle camera having an optical system with a focal length of 13 mm or more and less than 16 mm, an f-number of 2.2 or more and less than 2.6, and an angle of view of 110 degrees or more and less than 130 degrees. The camera 12b is, for example, a wide-angle camera (main camera) having an optical system with a focal length of 22 mm or more and less than 30 mm, and an f-number of 1.5 or more and less than 2.0. The camera 12c is, for example, a telephoto camera having an optical system with a focal length of 50 mm or more and less than 150 mm, and an f-number of 2.2 or more and less than 4.0.

[0024] The imaging device 10 may output one image by combining images captured by at least two of the multiple cameras 12.

[0025] The camera 12 has an image stabilization function. The camera 12 may have an optical image stabilization (OIS) function. Control of the optical system of the camera 12 in the OIS function will be described in detail with reference to FIG.

[0026] 1 is an example, and the number of cameras 12 is not limited to three, and may be less than three, or may be four or more. In this case, for example, the imaging ranges of two or more cameras 12 may overlap, the imaging ranges of three cameras 12 may overlap, or the imaging ranges of four or more cameras 12 may overlap. The imaging device 10 may include one or more cameras 12.

[0027] Here, the X-axis may be a direction along a plane perpendicular to the optical axis (Z-axis) of each optical system of the multiple cameras 12, and may be taken as a direction in which one of the edges of the user terminal 100 extends. The Y-axis may be a direction along a plane perpendicular to the optical axis on the front or back of the user terminal 100, and may be taken as a direction perpendicular to the X-axis and forming a right-handed system with respect to the positive direction of the X-axis. The Z-axis may be taken as a direction that intersects the XY plane and forms a right-handed system with the XYZ axes.

[0028] 2 is a diagram showing an example of the configuration of the cameras 12a to 12c. The camera 12a includes an optical system 120a, voice coil motors 121a and 123a, and IC chips 127a and 128a. The camera 12b includes an optical system 120b, voice coil motors 121b and 123b, and IC chips 127b and 128b. The camera 12c includes an optical system 120c, voice coil motors 121c and 123c, and IC chips 127c and 128c. The optical systems 120a to 120c include a plurality of lenses. The plurality of lenses may function as at least one of a zoom lens, a varifocal lens, and a focus lens.

[0029] The voice coil motors 121a-121c, 123a-123c are driving mechanisms for driving the optical systems 120a-120c along two orthogonal axes, the X-axis and the Y-axis, on a plane perpendicular to the optical axis, in order to realize the OIS. The voice coil motors 121a-121c, 123a-123c include air core coils 122a-122c and 124a-124c, and magnets paired with the respective air core coils. The IC chips 127a-127c and IC chips 128a-128c may be disposed in the air core portions of the air core coils 122a-122c and 124a-124c, respectively. In this specification, voice coil motors 121a-121c and 123a-123c may be collectively referred to as multiple voice coil motors 121, 123, or voice coil motors 121, 123, etc. Furthermore, air core coils 122a-122c and air core coils 124a-124c may be collectively referred to as multiple air core coils 122, 124, or air core coils 122, 124, etc. IC chips 127a-127c and IC chips 128a-128c may be collectively referred to as multiple IC chips 127, 128, or IC chips 127, 128, etc.

[0030] For example, magnets are provided on a holding frame that holds optical systems 120a-120c, and air core coils 122a-122c, 124a-124c are provided on bases 14a-14c (sometimes collectively referred to as base 14) that support the holding frame so that it can move on the XY plane. When IC chips 127, 128 pass a current through air core coils 122, 124, a force is generated in air core coils 122, 124 in a direction perpendicular to the magnetic field, and the holding frame moves relative to base 14. This realizes OIS.

[0031] In the cameras 12a to 12c, at least one of the voice coil motors 121 and 123 is driven to move the optical systems 120a to 120c in a direction that cancels the image shake.

[0032] As described above, each of the multiple cameras 12 includes IC chips 127, 128 that control the voice coil motors 121, 123. Therefore, as the number of cameras 12 included in the imaging device 10 increases, the number of IC chips 127, 128 increases.

[0033] Here, the imaging device 10 generates one image with a pseudo-deep depth of field by synthesizing two images captured by two cameras with different focus positions (for example, a combination of cameras 12a and 12b, cameras 12b and 12c, or cameras 12c and 12a). In this case, the two cameras 12 control voice coil motors 121 and 123 via IC chips 127 and 128 to drive the optical system 120, thereby performing OIS.

[0034] Specifically, within the control range under the first imaging condition, the ultra-wide-angle camera 12a and the wide-angle camera 12b execute OIS by passing currents through the voice coil motors 121 and 123 via the respective IC chips 127 and 129 to drive the respective optical systems 120a and 120b. Also, within the control range under the second imaging condition, the wide-angle camera 12b and the telephoto camera 12c execute OIS by passing currents through the voice coil motors 121 and 123 via the respective IC chips 127 and 128 to drive the respective optical systems 120b and 120c. In other words, since two IC chips 127 and 128 control two voice coil motors 121 and 123 for one camera 12, in this example, four IC chips 127 and 128 may be controlled at once.

[0035] 3 is a diagram showing an example of the configuration of the boards 16 and 26. The board 16 may be supported by the board 26 via an elastic body such as a spring, or a ball and a rail, so as to be movable or rotatable along the XY plane with respect to the board 26. Meanwhile, the board 26 may be fixed to the housing of the imaging device 10. The board 16 has an imaging element 18 and air-core coils 122d, 124d, and 126d that constitute voice coil motors 121d, 123d, and 125d for implementing in-body image shake correction (BIS), in other words, sensor-shift optical image shake correction. The board 16 also includes a position sensor for detecting the position of the board 16. The imaging device 10 includes an imaging element 18 that forms an image via an optical system 120.

[0036] The substrate 26 is a substrate arranged in the Z-axis direction (depth direction) in the XYZ space with respect to the substrate 16. The magnets 260d, 263d, and 266d are arranged on the substrate 26. The voice coil motors 121d, 123d, and 125d are configured by the air-core coils 122d, 124d, and 126d and the magnets 260d, 263d, and 266d. The substrate 26 includes the magnets 260d, 263d, and 266d at positions facing the air-core coils 122d, 124d, and 126d. In this embodiment, the substrate 16 has the air-core coils 122d, 124d, and 126d, and the substrate 26 has the magnets 260d, 263d, and 266d. However, this is merely an example, and the substrate 16 may have the magnets 260d, 263d, and 266d, and the substrate 26 may have the air core coils 122d, 124d, and 126d.

[0037] The substrate 16 includes an air core coil 122d, an air core coil 124d, an air core coil 126d, an IC chip 127d, an IC chip 128d, and an IC chip 129d on one surface (the surface on the negative side in the Z-axis direction in the example shown in the figure). The IC chips 127d, 128d, and 129d may be disposed in the air core portions of the air core coils 122d, 124d, and 126d, respectively.

[0038] Voice coil motors 123d and 125d are drive mechanisms that apply a force along the Y-axis direction to substrate 16. Voice coil motor 121d is a drive mechanism that applies a force along the X-axis direction to substrate 16. When voice coil motors 123d and 125d are driven to apply a force in the opposite direction along the Y-axis direction to substrate 16 (the combination of white arrows or the combination of black arrows in the figure), substrate 16 is rotated.

[0039] Therefore, by driving the voice coil motors 123d, 125d, and 121d, at least one of rotation and translation (shift) of the substrate 16 is performed relative to the optical system 120, thereby realizing the BIS. That is, in order to control the BIS by the substrate 16, three IC chips 127d, 128d, and 129d are controlled.

[0040] At least one of the cameras 12a to 12c may include such a substrate 16, 26. This allows at least one camera to have both the OIS and BIS functions.

[0041] Alternatively, at least one of cameras 12a-12c may not have voice coil motor 121, 123 (any of corresponding voice coil motors 121a-121c, 123a-123c) that drives optical system 120, but may have board 16, 26. Therefore, it may have voice coil motor 123d, 125d, 121d that drives board 16 on which imaging element 18 is mounted. In other words, at least one camera may have only BIS function without OIS function.

[0042] The OIS or BIS may be realized by further moving the optical systems 120a to 120c or the image sensor 18 disposed on the substrate 16 along the Z-axis direction. In this case, a further driving mechanism such as a voice coil motor will be provided, but in this specification, a detailed description of the control in the Z-axis direction will be omitted for the sake of simplicity.

[0043] 4 shows an example of a communication system 200 for controlling a conventional IC chip configured in a master-slave configuration. The communication system 200 includes a master device 20 and a plurality of slave devices 22a to 22c. The master device 20 and the plurality of slave devices 22a to 22c are each an IC chip.

[0044] The master device 20 transmits control signals for controlling each of the slave devices 22a to 22c. For example, an I2C communication method (I 2 Control signals are transmitted as data using the I.C. protocol. 2 In the C protocol, the master device 20 controls the slave devices 22a to 22c by transmitting a serial clock (SCL) signal and a serial data (SDA) signal.

[0045] The slave devices 22a to 22c are IC chips provided in the voice coil motors 121, 123, and 125, respectively, to control the operations of the voice coil motors 121, 123, and 125. The slave devices 22a to 22c each have a different individual address so that the master device 20 can distinguish and control each IC chip. In the example shown in the figure, the slave device 22a has an individual address AAh, the slave device 22b has an individual address BBh, and the slave device 22c has an individual address CCh.

[0046] In the control signal, the master device 20 designates one of the slave devices 22a-22c to be processed using the individual addresses AAh-CCh, and then designates a register address to which the processing is to be written. Furthermore, in the control signal, the master device 20 designates data to be written to the subsequently designated register address. The specific content of the control signal transmitted by the master device 20 will be described in detail with reference to Figs. 5 and 6.

[0047] In the figure, three slave devices 22a to 22c are shown as slave devices 22 included in communication system 200, but the number of slave devices 22a to 22c is not limited to three and may be less than three or may be four or more. In the example in Fig. 2, two IC chips are provided for each of cameras 12a to 12c, so communication system 200 has six slave devices 22, i.e., slave devices 22a to 22f. On the other hand, when one camera 12 in Fig. 2 is used in combination with board 16 in Fig. 3, communication system 200 has five slave devices 22, i.e., slave devices 22a to 22e.

[0048] Fig. 5 shows an example of a control signal transmitted by the master device 20 to control the six slave devices 22a to 22f. As already explained, in the example of Fig. 2, the master device 20 transmits a control signal for controlling the six slave devices 22a to 22f. The control signal shown in the figure includes bit strings 24a to 24f. The control signal in the example shown in the figure is a control signal for instructing the slave devices 22a to 22f to write data having a length of 1 byte (8 bits).

[0049] The bit string 24a is a portion of the control signal for the first slave device 22a. In the bit string 24a, the first 8 bits specify an individual address of which slave device is to be controlled. The bit string 24a includes 1-bit data for the master device 20 to receive an acknowledgement (ACK) from the slave device 22 to which the specified individual address is assigned.

[0050] Next, the bit string 24a includes a register addressing bit that specifies a write position in a register of the slave device 22a. After the register addressing bit, the bit string 24a includes one-bit data for transmitting an acknowledgement (ACK) from the slave device 22 to the master device 20.

[0051] Next, the bit string 24a includes an 8-bit data string that specifies the contents of the data to be written to a 1-byte (8-bit) register of the slave device 22a. After the 8-bit data string, the bit string 24a again includes 1-bit data for an acknowledgement (ACK).

[0052] As a result, the bit string 24a includes data with a total data length of 27 bits. When six slave devices 22 are controlled, the bit string 24a is followed by a bit string 24b for controlling the second slave device 22, a bit string 24c for controlling the third slave device 22, and so on, followed by bit strings 24b to 24f. The bit strings 24b to 24f have the same length as the bit string 24a. Therefore, the control signal for an instruction to write data of 1 byte (8 bits) length to the slave devices 22a to 22f has a data length of 27×6=162 bits.

[0053] When the slave devices 22a to 22f process such control signals, the slave devices 22a to 22f may start processing in the order in which communication from the master device 20 to the slave devices 22a to 22f ends. Therefore, for example, when controlling the movement of the optical system 120 or the image sensor 18 from a current position to a target position in the XY plane, the actuators controlled by the slave devices 22a to 22f may be driven at different timings. In such a case, the actuators that drive the optical system 120 or the image sensor 18 in the X direction and the actuators that drive the optical system 120 or the image sensor 18 in the Y direction are controlled at different timings. As a result, the movement of the optical system 120 or the image sensor 18 from the current position to the target position may not be a linear movement connecting the current position and the target position, but may be a broken line movement, resulting in an unsmooth operation.

[0054] Fig. 6 shows another example of a control signal transmitted by the master device 20 to control the six slave devices 22a to 22f. In the example of Fig. 2, the master device 20 transmits a control signal for controlling the six slave devices 22a to 22f. The control signal shown in the figure includes bit strings 28a to 28f. The control signal in the example shown in the figure is a control signal for instructing the slave devices 22a to 22f to write data having a length of 2 bytes (16 bits).

[0055] The bit string 28a is a portion of the control signal for the first slave device 22a. In the control signal bit string 28a, the first 8 bits specify an individual address indicating the slave device to be controlled. The bit string 28a includes 1-bit data for the master device 20 to receive an acknowledgement (ACK) from the slave device 22 to which the specified individual address is assigned.

[0056] Next, the bit string 28a includes a register addressing bit that specifies a write position of a bit in a register of the slave device 22a. The bit string 24a includes, after the register addressing bit, one bit of data for transmitting an acknowledgement (ACK) from the slave device 22 to the master device 20.

[0057] Next, the bit string 28a includes an 8-bit data string that specifies the contents of the data to be written to the register of the slave device 22a. After the 8-bit data string, the bit string 28a again includes 1-bit data for an acknowledgement (ACK).

[0058] 6, the bit string 28a further includes an 8-bit data string to be written to a register in the slave device 22a, followed by another 1-bit data for an acknowledgement (ACK).

[0059] As a result, bit string 28a includes data with a total data length of 36 bits. Bit strings 28b to 28f have the same length as bit string 28a. Therefore, the control signal for instructing slave devices 22a to 22f to write 2-byte (16-bit) data has a data length of 36×6=216 bits.

[0060] In this way, in the conventional communication system 200, when 1 byte of data is communicated using the I2C protocol, a 162-bit control signal is communicated, and when 2 bytes of data is communicated, a 216-bit control signal is communicated. Such communication puts a strain on the communication bandwidth of the I2C communication line.

[0061] 5, in the control signal of this example, the slave device 32 designated by the individual address individually performs the read / write operation of the bit designated by the register address designation bit. In the control signal, the bit strings 24a-24f or the bit strings 28a-28f are transmitted consecutively, and the individual slave devices 22 may start their operation independently in the order in which the communication from the master device to the slave device 22 ends. Therefore, a time difference may occur in the drive timing of the actuator, and the operation of the slave devices 22a-22c and the optical system 120 or the image sensor 18 controlled by the slave devices 22a-22c may not be smooth.

[0062] 7 is a diagram showing an example of the configuration of a communication system for controlling the cameras 12a to 12c according to this embodiment. The system shown includes a master device 30, the cameras 12a to 12c, and another slave device .

[0063] The camera 12a includes slave devices 32a and 32b and an imaging unit 40a. The operation of the imaging unit 40a is controlled by the slave devices 32a and 32b.

[0064] Furthermore, the imaging unit 40a includes an imaging element 44a that captures an image formed via the optical system 42a, and a driving unit 46a that drives at least one of the optical system 42a and the imaging element 44a. The driving unit 46a includes a voice coil motor formed by a combination of air-core coils 460, 464 and magnets 462, 466. The optical system 42, the imaging element 44, the air-core coils 460, 464, and the magnets 462, 466, etc. may be elements corresponding to the elements described with reference to FIGS. 2 and 3.

[0065] The air core coil 460 and magnet 462 of the drive unit 46 correspond to one of the directions (X direction or Y direction) in which the drive unit 46 drives the optical system 42 or the image sensor 44. The air core coil 464 and magnet 466 correspond to the other direction (X direction or Y direction) in which the drive unit 46 drives the optical system 42 or the image sensor 44.

[0066] Similarly, camera 12b includes slave devices 32c and 32d and imaging unit 40b. Camera 12c includes slave devices 32e and 32f and imaging unit 40c. Imaging units 40b and 40c have the same configuration as imaging unit 40a.

[0067] In this way, the slave device 32 is provided in each of the multiple image capturing units 40. However, the slave device 32 may be provided in any position within the communication system as long as the slave device 32 is located in a position where it can control the driving of either the optical system 42 or the image capturing element 44.

[0068] 2, when performing OIS control of two of the cameras 12a to 12c at a time, that is, the cameras 12a and 12b, the cameras 12b and 12c, or the cameras 12c and 12a, four slave devices 32 are controlled. In this embodiment, such an embodiment will be described.

[0069] 3, in the embodiment of Fig. 7, a board 16 may be provided for one camera 12 to perform OIS and BIS control. In this case, two slave devices 32 (IC chips) for OIS control of the camera 12 are provided, and three slave devices 32 (IC chips) for BIS control are provided on the board 16. In this way, a total of five slave devices 32 are controlled by the control signal of the master device 30.

[0070] The master device 30 controls the slave devices 32a to 32f and the other slave devices 34. Specifically, the master device 30 controls device operation by communicating control signals based on a serial clock (SCL) signal and a serial data (SDA) signal to the slave devices 32a to 32f and the other slave devices 34 via a bus. The master device 30 includes a communication unit 31 for performing data communication to transmit such control signals to the slave device 32 via the bus. In this manner, a "communication system" is configured that includes the master device 30, the slave devices 32a to 32f, and the other slave devices 34.

[0071] The slave devices 32a to 32f are devices that perform data communication with the master device 30 via a bus and are controlled based on a common address and an individual address based on a control signal output from the master device 30. In particular, the slave devices 32a and 32b control the electromagnetic actuator in the driving unit 46a, i.e., the voice coil motor. In order to perform such control, each of the slave devices 32 is assigned a common address that is a "common address" for the multiple slave devices 32 and an individual address that uniquely identifies each of the multiple slave devices 32. The master device 30 can set the ID and individual settings of the slave devices 32 via the individual address. The ID may be an index that can identify all slave devices 32 having the same common address in ascending order. For example, if the same common address is assigned to six slave devices 32, the ID assigned to each of the six slave devices 32 may be any one of "ID1", "ID2", "ID3", "ID4", "ID5", and "ID6".

[0072] As in the communication system 200, in this embodiment, the slave devices 32a to 32f communicate data with the master device 30 by the I2C communication method. Also, the slave devices 32a to 32f are IC chips connected to the driving units 46a to 46c to control the operations of the driving units 46a to 46c.

[0073] The other slave devices 34 are devices to which the common address assigned to the slave devices 32a to 32f by the master device 30 is not assigned. The other slave devices 34 may have a common address (not shown) different from the slave devices 32a to 32f. The other slave devices 34 may have individual addresses so that they are individually controlled by control signals from the master device 30. In this embodiment, the other slave devices 34 have an individual address: RRh.

[0074] Next, the internal configuration of each slave device 32 will be described with reference to Fig. 8. Fig. 8 is a diagram showing an example of the configuration of the slave device 32. The slave device 32 includes input terminals 50, 52, a communication unit 60, a position sensor 70, an amplifier unit 72, an ADC 74 (ADC: Analog to Digital converter), an actuator driver 80, and output terminals 54, 56. Each of the slave devices 32a to 32f shown in Fig. 7 has the internal configuration of the slave device 32 shown in Fig. 8.

[0075] The slave device 32 performs control to move the optical system 42 or the image sensor 44 to a target position based on the SCL signal input from the input terminal 50, the SDA signal input from the input terminal 52, and position information of the magnet 462 or 466. To this end, the slave device 32 outputs a current of a desired magnitude from the output terminals 54, 56 to the air-core coil 460 or 464.

[0076] The communication unit 60 communicates data with the master device 30 to read or write data of a data length indicated by data length information included in the control signal based on the control signal received from the master device 30. Furthermore, each slave device 32 may be uniquely assigned an ID indicating a predetermined order so that the communication unit 60 receives or transmits data from or to the master device 30 in the predetermined order assigned to the slave devices 32a to 32f. The communication unit 60 includes a transmission / reception unit 62, an IC recognition unit 64, an internal register 66, and a non-volatile memory 68.

[0077] The transmitting / receiving unit 62 receives the SCL signal input from the input terminal 50 and the SDA signal input from the input terminal 52, and transmits a portion of the control signal that allows the slave device 32 to recognize the common address or the individual address to the IC recognition unit 64. Furthermore, the transmitting / receiving unit 62 transmits data to be read from or written to each internal register 66 to the internal register 66.

[0078] The IC recognition unit 64 recognizes whether the slave device 32 on which the IC recognition unit 64 is mounted is a control target as the slave device 32 to be controlled indicated by the control signal. Specifically, the IC recognition unit 64 recognizes whether a group of slave devices 32 having a common address can be a control target based on a portion of the control signal transmitted by the transmission / reception unit 62 for the slave device 32 to recognize a common address or an individual address. Alternatively, the IC recognition unit 64 recognizes whether a slave device 32 having an individual address is a control target. When the IC recognition unit 64 recognizes that a group of slave devices 32 having a common address can be a control target, the IC recognition unit 64 recognizes whether the slave device 32 is a control target based on the ID indicated in the common address register 664 and the designation information included in the control signal communicated from the master device 30. Furthermore, the IC recognition unit 64 recognizes the register address of the slave device 32 from which data should be read or written, the data length of the data, and the timing for accessing to read or write the data based on the ID indicated in the common address register 664 and the data length information included in the control signal. The designation information and data length information contained in the control signal will be described in detail later.

[0079] The internal register 66 is a register in which the actuator driver 80 records control information for controlling the electromagnetic actuator. The internal register 66 includes a target position register 660, an operation mode register 662, and a common address register 664.

[0080] The target position register 660 is a register that stores information about a target position to which the actuator driving unit 80 drives the optical system 42 or the image sensor 44. The operation mode register 662 is a register that stores information about an operation mode in which the actuator driving unit 80 controls driving the optical system 42 or the image sensor 44.

[0081] The common address register 664 is a register indicating a common address and ID of the slave device 32. Therefore, the IC recognition unit 64 can compare the common address bit indicated in the control signal with the value indicating the common address indicated in the common address register 664 to determine whether the slave device 32 belongs to a group of slave devices 32 that can be controlled by the control signal. The IC recognition unit 64 also refers to the designation information indicated in the control signal, specifically, the upper bits of the ADRS bits described later, and compares it with the ID in the common address register 664 to recognize the slave device 32 to be controlled that will communicate with the master device 30 this time. When the IC recognition unit 64 recognizes that it is the slave device 32 to be controlled that will communicate with the master device 30 this time, it further recognizes the timing of communication with the master device 30 according to the value indicating the ID indicated in the common address register 664 and data length information, specifically, the information indicated in the lower bits of the ADRS bits described later.

[0082] The non-volatile memory 68 is a memory for storing control information for the actuator driving unit 80 to control the electromagnetic actuator, such as data having a larger capacity than the data stored in the internal register 66 or data to be stored for a longer period of time. The non-volatile memory 68 is mounted in the slave device 32. The non-volatile memory 68 may be a non-volatile memory such as a flash memory.

[0083] The position sensor 70 detects the position of the magnet 462 or 466 based on the magnetic field around the magnet 462 or 466. For example, the position sensor 70 detects the position of the optical system 42 by detecting the position of the magnet 462 or 466, particularly when the magnet 462 or 466 is provided on a holding frame of the optical system 42. The position sensor 70 is a magnetic sensor using a magnetic sensor element such as a Hall element, a TMR element using a tunnel magnetoresistance effect, or a GMR element using giant magnetoresistance. The position sensor 70 outputs a voltage or current based on the detected magnetic field to the amplifier 72.

[0084] The amplifier 72 amplifies the voltage or current output from the position sensor 70 and outputs the amplified voltage or current to the ADC 74. The ADC 74 converts the voltage or current output from the amplifier 72 into a digital signal indicating position information of the optical system 42 and outputs the digital signal to the actuator driver 80.

[0085] The actuator driving unit 80 supplies a voltage or current output from the output terminals 54, 56 to control the current flowing through the air-core coil 460 or 464 constituting the electromagnetic actuator, thereby driving the electromagnetic actuator. Each of the voice coil motors mentioned in Figures 2 and 3 is an example of an electromagnetic actuator. The actuator driving unit 80 includes a control unit 82, a DAC (Digital to Analog converter) 84, a first driver 86, and a second driver 88.

[0086] The control unit 82 controls the current flowing through the air-core coil 460 or 464 constituting the electromagnetic actuator, based on the control information indicated in the internal register 66 and the digital signal indicating the position information of the optical system 42 output from the ADC 74. The control unit 82 outputs a digital signal regarding the control information in order to control the current flowing through the air-core coil 460 or 464. The DAC 84 converts the digital signal output by the control unit 82 into an analog signal and outputs it to the first driver 86 or the second driver 88.

[0087] The first driver 86 and the second driver 88 supply a voltage, a current, or power to be output from the output terminals 54, 56 to the electromagnetic actuator in response to the analog signal output from the DAC 84. The first driver 86 and the second driver 88 may be drivers for supplying currents of opposite polarity to the air core coils 460 and 464.

[0088] 9 and subsequent figures will be used to explain a case where the address information indicating the slave device 32 to be controlled has a common address in a control signal when the master device 30 controls the slave device 32. However, the address information may have individual address bits as in the conventional control signals explained with reference to Figures 5 and 6.

[0089] In this way, when the address information indicates an individual address, the control signal generated by the master device 30 may include register information indicating the register address of the slave device 32 from which the slave device 32, which is the target of data communication corresponding to the individual address bit, should read (read) or write (write) data, as in the examples of Figures 5 and 6.

[0090] When the address information indicates an individual address of the slave device 32, the communication unit 60 accesses the register address of the slave device 32 indicated in the register information, thereby performing data communication with the master device 30 to read or write data. Therefore, in this case, the indicated master device 30 and slave device 32 perform the same processes as the master device 20 and slave device 22 indicated in the communication system 200 of FIGS. 4 to 6.

[0091] In this way, the master device 30 and the slave device 32 of this embodiment can perform both the process using common address bits, which will be described with reference to Fig. 9 onwards, and the conventional process described with reference to Fig. 4 to Fig. 6. The master device 30 and the slave device 32 of this embodiment may also perform such a process when it is desired to process an individual slave device 32. To implement such a process, the master device 30 is capable of generating and communicating a corresponding control signal.

[0092] 9 shows an example of a control signal 90 according to the embodiment. The control signal 90 includes a common address bit 92, an ADRS bit 94, and data 96a to 96h.

[0093] The common address bits 92 are bits for specifying multiple slave devices 32 that can be targets for communication with the master device 30 using one control signal. The common address bits 92 may be bits for specifying multiple slave devices 32 that control the same control target, such as the image capture device 10. Furthermore, a one-bit portion before the common address bits 92 indicates whether the slave device 32 should read or write data. This one-bit portion corresponds to the "first bit."

[0094] The communication unit 60 determines whether the slave device 32 should read or write data based on the value of the first bit. The common address bit 92 indicates an address common to multiple slave devices. Address information is configured to include the first bit and the common address bit 92. The communication unit 60 determines whether it belongs to a group of slave devices 32 that can be controlled based on a comparison between the address information of the common address bit 92 and the common address stored in the common address register 664.

[0095] The ADRS bits 94 specify at least one slave device 32 that is to be the target of data communication among the multiple slave devices 32. Among the information indicated in the ADRS bits 94, the information specifying at least one slave device 32 corresponds to "specification information." The communication unit 60 may determine the order in which to read or write its own data based on the IDs assigned to the multiple slave devices 32 and the specification information.

[0096] Furthermore, in the portion other than the bits containing the designation information, the ADRS bits 94 contain “data length information” that indicates the register address of the internal register 66 to be accessed and the data length to be received or transmitted by the slave device 32 specified by the designation information.

[0097] When the communication unit 60 determines that it is a group of slave devices 32 that can be controlled based on the address information of the common address bits 92, it determines whether it is a slave device 32 to be controlled based on the designation information and its own ID indicated in the ADRS bits 94. When the communication unit 60 determines that it is a slave device 32 to be controlled, it communicates with the master device 30 to read or write data (any of data 96a to 96h) at a timing corresponding to the designation information, data length information, and its own ID. When the communication unit 60 determines that it is not a slave device 32 to be controlled, it ignores the data 96a to 96h. This allows a single control signal 90 to operate several specific slave devices 32 out of a plurality of slave devices 32 having the same common address as control targets at the same time. Moreover, even if a slave device 32 that is not a control target exists among a plurality of slave devices 32 having the same common address, the control signal 90 of this embodiment does not need to include dummy data for the slave device 32 that is not a control target. The ADRS bits 94 will be described later with reference to FIG. 10.

[0098] In this way, the address information and the designation information designate the control target for a combination of multiple slave devices 32, and the data length information specifies the data position to be read from or written to the internal register 66. Each of the common address bits 92 and the ADRS bits 94 includes a single acknowledgement (ACK) bit, followed by data 96a to 96h.

[0099] The data 96a-96h may be data for reading out internal data and setting operations in the internal register 66 in each of the multiple slave devices 32. Or, the data 96a-96h may be data for controlling the actuator driving unit 80. In other words, the data 96a-96h may be data for each of the multiple slave devices 32 to drive at least one of the optical system 42 and the image sensor 44 by controlling the driving unit 46 connected to each of the multiple slave devices 32 in accordance with the respective data 96a-96h.

[0100] In this embodiment, six slave devices 32 in Fig. 7 are provided. Here, of the six IC chips, there are 15 combinations for operating two IC chips, 30 combinations for operating three IC chips, 15 combinations for operating four IC chips, 6 combinations for operating five IC chips, and 1 combination for operating six IC chips. Therefore, when controlling two to six IC chips, there are 57 combinations. Therefore, a 6-bit value is required to express all of these.

[0101] Here, for example, six IC chips are designated as IC1, IC2, IC3, IC4, IC5, and IC6. When IC3=IC4 and IC5=IC6, and two or more ICs are controlled among IC1 to IC6, the number of combinations is 11. In this case, all patterns for controlling two or more ICs can be covered by a four-bit value. In this embodiment, two pairs are formed for four IC chips among the six IC chips, and the IC chips included in the pairs are controlled in the same manner, thereby enabling the control of six IC chips by the upper bits of the four-bit ADRS bit 94.

[0102] 10 is a diagram showing an example of the structure of the ADRS bit 94. The 8-bit ADRS bit 94 includes, for example, 4 most significant bits 942 and 4 least significant bits 944.

[0103] At least one slave device 32 that is a target of data communication among the multiple slave devices 32 is assigned to each bit of the upper bits 942, which include the four bits ADRS[7] to ADRS[4]. The upper bits 942 correspond to a "first bit string."

[0104] When the upper bits 942 have a predetermined first value (e.g., 1), the communication unit 60 of the slave device 32 assigned to that bit determines that the slave device 32 is a target for data communication. On the other hand, when the upper bits 942 have a predetermined second value (e.g., 0), the communication unit 60 of the slave device 32 assigned to that bit determines that the slave device 32 is not a target for data communication.

[0105] The lower bits 944 of ADRS[3] to ADRS[0] include data length information corresponding to the register address and data length of the slave device 32 from which the slave device 32 should read or write data. The lower bits 944 correspond to a “second bit string.”

[0106] Each of the four bits ADRS[3] to ADRS[0] can take a value of 1 or 0. Therefore, the pattern indicated by the four bits ADRS[3] to ADRS[0] can indicate 16 different states by each bit taking a different value. With these 16 different values, the lower bit 944 can indicate 16 different commands for the register address and data length of the slave device 32 from which data is to be read or written. These 16 different commands will be described later with reference to the control map of FIG. 12.

[0107] 11 shows an example of a look-up table showing combinations of control targets of the slave device 32 (IC chip) according to the embodiment. The slave device 32 to be controlled is selected based on the value of the upper bits 942 of the ADRS bits, i.e., the four bits ADRS[7] to ADRS[4].

[0108] In this embodiment, IC1 is a control target when ADRS[7] indicates a value of 1, and IC1 is not a control target when ADRS[7] indicates a value of 0. Similarly, IC1 is a control target when ADRS[6] indicates a value of 1, and IC1 is not a control target when ADRS[6] indicates a value of 0.

[0109] As already described with reference to Fig. 9, control is performed by regarding the pair of IC3 and IC4, and IC5 and IC6 as the same. When ADRS[5] indicates a value of 1, the pair of IC3 and IC4 is the control target, and when ADRS[5] indicates a value of 0, the pair of IC3 and IC4 is not the control target. Similarly, when ADRS[4] indicates a value of 1, the pair of IC5 and IC6 is the control target, and when ADRS[4] indicates a value of 0, the pair of IC5 and IC6 is not the control target.

[0110] 11 is merely an example of a combination of IC chips to be controlled for a given value in the upper bits 942 of the ADRS bits, and other combinations may be used. For example, when IC1=IC2 and IC3=IC4, a bit for controlling IC1 and IC2, a bit for controlling IC3 and IC4, a bit for controlling IC5, and a bit for controlling IC6 may be used. As a reference table for realizing the control of this embodiment, other reference tables may be used as long as they are combinations that allow six ICs to be controlled with four bits.

[0111] 12 shows an example of a control map according to an embodiment. ADRS[3:0], which is the lower bits 944 of the ADRS bits, can take values ​​from 0 to 15. In the control map, the control performed on the internal register 66 of the slave device 32 and the data length are indicated according to the value of ADRS[3:0].

[0112] When ADRS[3:0] has a value of 0, one byte communication is performed at position 0 of the target position register 660 of the slave device 32. When ADRS[3:0] has a value of 1, one byte communication is performed at position 1 of the target position register 660 of the slave device 32. Position 1 in the target position register 660 may be a consecutive position from position 0, or may be a position moved one byte from the position indicated by position 0. When ADRS[3:0] has a value of 2, one byte communication is performed at each of positions 0 and 1 of the consecutive target position register 660 of the slave device 32, that is, two bytes are communicated.

[0113] When ADRS[3:0] has a value of 3, one byte communication is performed at a first position in the operation mode register 662 of the slave device 32. When ADRS[3:0] has a value of 4, one byte communication is performed at a second position different from the first position. The second position may be a position consecutive to the first position, or may be a position shifted by one byte from the first position. When ADRS[3:0] has a value of 5, one byte communication is performed at each of the first and second positions in the operation mode register 662 of the slave device 32, i.e., two bytes are communicated.

[0114] When ADRS[3:0] has a value of 6, a predetermined operation command is executed in the register at the third position in the operation mode register 662 of the slave device 32. The operation performed in accordance with this operation command is a one-byte communication. Other predetermined operation commands may also be defined when ADRS[3:0] has a value of 7 to 15. For these cases, the control map may indicate the register to be accessed in the internal register 66 of the slave device 32, the register address, and the data length.

[0115] The communication unit 60 refers to such a control map indicating the relationship between the data length information of the lower bits 944, which are the second bit string, and the register address and data length of the slave device 32 from which the slave device 32 should read or write data. In this way, the IC recognition unit 64 specifies the register address and data length of the slave device 32 from which the slave device 32 should read or write data. When the slave device 32 is the target of data communication, the slave device 32 receives or transmits data of a data length specified based on the data length information according to the ID indicating a predetermined order and the designation information by accessing the register address of the slave device 32 from which the slave device 32 should read or write data. The control map shown in FIG. 12 is an example of a "map" indicating the relationship between the register address and data length of the slave device 32 from which the slave device 32 should read or write data.

[0116] 13 shows an example of a control signal 130 when performing a 1-byte write according to the embodiment. In the control signal 130, the first 8 common address bits 132 specify a group of slave devices 32 to be controlled.

[0117] Next, the control signal 130 includes the next 8-bit ADRS bits 134 after the common address bits 132, with one acknowledgement (ACK) bit in between. The common address bits 132 specify a group of slave devices 32 that can be controlled. Furthermore, the ADRS bits 134 select the slave devices 32 to be enabled as the control targets, specify the register address of the internal register 66 to be read / written, read / write data according to the command, and specify the data length to be read / written according to the command. In the example of FIG. 5, the control signal includes 8 individual address bits for specifying the slave devices 32 and 8 register address bits for each of the six slave devices 32. In the control signal 130, the 8-bit common address bits 132 and the 8-bit ADRS bits 134 can specify the slave devices 32 and register addresses to be processed by the command all at once, so that the bit string for specifying the slave devices 32 and the register addresses is shortened.

[0118] Then, the control signal 130 includes 8 bits of data to be read / written from / to the slave devices 32 with IDs 1 to 6, each with a 1-bit acknowledgement (ACK) bit between them. The total length of the bit string included in the control signal 130 is 72 bits.

[0119] In this way, by including the common address bit 132 and the ADRS bit 134, the process of selecting the slave device 32 and the control signal 130 indicating the length of data to be read or written are simplified for the slave devices 32 with IDs 1 to 6. As a result, the total length of the bit string included in the control signal 130 is a shorter control signal than the 162-bit control signal for 1-byte write described with reference to Fig. 5. Therefore, the amount of communication of control content is reduced in the control signal 130.

[0120] A unique ID indicating a predetermined order is assigned to each slave device 32 to be controlled among the slave devices 32a to 32f so that the slave device 32 can recognize the order in which data is received from or transmitted to the master device 30. Using the ID indicating the predetermined order and the designation information, the slave device 32 can determine whether it is a slave device 32 to be controlled and the timing of receiving or transmitting data from or to the master device 30.

[0121] Furthermore, each slave device 32 of this embodiment starts operating all at once (for example, simultaneously) when the communication of the control signal 130 is completed. Therefore, in the example of control for moving the optical system 42 or the image sensor 44 from the current position to the target position in the XY plane described with reference to FIG. 5, the actuators controlled by the slave devices 32a to 32f of this embodiment are controlled with the same drive timing. That is, in such a case, the control of the actuator for driving the optical system 42 or the image sensor 44 in the X direction and the actuator for driving the optical system 42 or the image sensor 44 in the Y direction can be started simultaneously. This makes it possible to move the optical system 42 or the image sensor 44 from the current position to the target position along a straight line connecting the current position and the target position, for example. In this way, the operation of the drive target such as one optical system 42 or the image sensor 44 controlled by multiple slave devices 32 becomes smoother than when a common address is not used.

[0122] 14 shows an example of a control signal 140 when performing a 2-byte write according to the embodiment. Like the control signal 130, the control signal 140 also includes a common address bit 142, an ADRS bit 144, and an associated acknowledgement (ACK) bit.

[0123] In the control signal 140, 2 bytes of data are written to the slave devices 32 with IDs 1 to 6. In comparison with the example of Fig. 6, when 2 bytes of data are written to the six slave devices 32 with IDs 1 to 6, the slave device 32 to which data is to be written and the target register address are specified by six 8-bit individual address bits and 8-bit register address bits in the example of Fig. 6.

[0124] On the other hand, in the control signal 140, in order to execute a command for a plurality of slave devices 32, a group of slave devices 32 indicated by the common address bits 142 can be the target of data write. Furthermore, in the upper bits 942 of the ADRS bits 144, whether the slave device 32 is the target of communication with the master device 30 (whether it is enabled) and the order of communication with the master device 30 are specified. The communication unit 60 recognizes the target of communication and the order of communication by referring to the ADRS bits 144. In addition, in the data length information in the lower bits 944 of the ADRS bits 144, a register address and a data length that are predetermined for the command are specified. As a result, data is written to the internal register 66. In this way, in the control signal 140, by using the common address bits 142 and the ADRS bits 144, each of which is 8 bits, it is not necessary to provide individual address bits and register address bits for each slave device 32.

[0125] In addition to these common address bits 142 and ADRS bits 144, the control signal 140 includes 2 bytes of data for writing to the slave devices 32 with IDs 1 to 6. Therefore, the total length of the bit string included in the control signal 140 is 126 bits.

[0126] In this way, by including the common address bit 142 and the ADRS bit 144, the control signal 140 indicating the process of selecting the slave device 32 and the data length to be read or written for the slave devices 32 of ID1 to ID6 is shorter and simpler than the 216-bit control signal shown in FIG. 6. Furthermore, in each slave device 32 using the control signal 140, the slave device 32 to be controlled and the order of data processing are determined among the multiple slave devices 32 that can be controlled based on the ID read from the common address register 664 and the designation information and data length information indicating the slave device 32 to be controlled that are shown in the ADRS bit 144. Furthermore, similar to the control signal 130, the slave devices 32 start operating all at once (for example, simultaneously) at the point in time when the communication of the control signal 140 is completed. This allows the operation of the drive target such as the optical system 42 or the image sensor 44 controlled by the multiple slave devices 32 to be smoother than the example of FIG. 6.

[0127] 15 shows an example of a control signal 150 when performing a 2-byte write according to the embodiment. Like the control signals 130 and 140, the control signal 150 also includes a common address bit 152, an ADRS bit 154, and an associated acknowledgement (ACK) bit.

[0128] In the control signal 150, 2 bytes of data are written to the slave devices 32 with IDs 1, 2, 5, and 6. The control signal 150 is an example of a control signal based on the control when IC3=IC4 and IC5 and IC6, as described with reference to FIGS.

[0129] This example is an example in which the upper bits ADRS[7]-[4] of the ADRS bits 154 are ADRS[7]=1, ADRS[6]=1, ADRS[5]=0, and ADRS[4]=1 in the reference table corresponding to the ADRS bits in Fig. 11. In this way, an example in which the upper bits ADRS[7:4] of the ADRS bits 154 are set to 1101b is shown as the control signal 150. In this way, data communication can be realized between the master device 30 and some of the slave devices 32 among the multiple slave devices 32 to which the same common address is assigned, using one control signal 130.

[0130] Following the common address bits 152, the ADRS bits 154, and their corresponding acknowledgement (ACK) bits, the control signal 150 includes two bytes of data (and an acknowledgement (ACK) bit) for writing to the slave devices 32 with IDs 1, 2, 5, and 6. The total length of the bit string included in the control signal 150 is 90 bits.

[0131] In this way, the inclusion of common address bits 152 and ADRS bits 154 simplifies the process of selecting a slave device 32 for the slave devices 32 with IDs 1 to 6, and the control signal 150 indicating the length of data to be read or written, etc. In this case, the total length of the bit string included in control signal 150 is even shorter than that of control signal 140, compared to the 216-bit 2-byte write control signal described with reference to FIG.

[0132] The communication unit 60 judges whether or not it belongs to a group of slave devices 32 that can be controlled, based on the common address indicated by the common address bits 152. Furthermore, the communication unit 60 recognizes the slave device 32 to be controlled this time by comparing the value indicated by the upper bits ADRS[7] to [4] of the ADRS bits 154 with the ID of the common address register 664. In addition, the communication unit 60 recognizes the order of data processing between the slave devices 32 to be controlled, based on the recognition result of the slave device 32 to be controlled this time, its own ID read from the common address register 664, and the data length specified by the value indicated by the lower bits ADRS[3] to [0] of the ADRS bits 154. Due to the correspondence relationship between the common address bits 152 and the common address, target positions and the like can be set for multiple slave devices 32 by the control signal 150 that is shorter than when individual addresses are used.

[0133] Furthermore, similarly to the control signals 130 and 140, when communication of the control signal 150 ends, the slave devices 32 start operating all at once (for example, simultaneously). This allows the control signal 150 to also smoothly control the targets to be driven, such as the optical system 42 or the image sensor 44, by the slave device 32.

[0134] The IDs of the slave devices 32 enabled as the slaves to be controlled, indicated by the ADRS bit 154, do not have to be all IDs having the same common address. In the slave devices 32 of this embodiment, the slave devices 32 with IDs 1, 2, 5, and 6 are enabled. When the communication unit 60 determines that it is not a slave device 32 to be controlled based on the ID stored in the common address register 664 and the designation information of the ADRS bit 154, it ignores the data following the acknowledgement bit following the ADRS bit 154. In this way, by using a combination of the common address, the ID, and the designation information, the degree of freedom of the slave devices 32 that can be designated is increased compared to the case where only the common address is used. In addition, when the communication unit 60 determines that it is not a slave device 32 to be controlled, it ignores the data following the acknowledgement bit following the ADRS bit 154, so that the control signal 150 does not need to include dummy data for the slave devices 32 that are not selected. Therefore, in this embodiment, it is possible to avoid the dummy data from squeezing the communication band in the I2C communication method.

[0135] Furthermore, in the control signal 150 of this embodiment, the timing and data length of accessing the internal register 66 of the target slave device 32 are determined based on the ID stored in the common address register 664 and the designation information and data length information indicated in the ADRS bit 154. As in this embodiment, when the slave devices 32 with IDs 1, 2, 5, and 6 are enabled, the communication units 60 of the slave devices 32 with IDs 1, 2, 5, and 6 can recognize the timing and data length of accessing the internal register 66 to communicate data with the master device 30 based on the ID, designation information, and data length information. When the communication unit 60 is the slave device 32 to be controlled, it waits until it is time to communicate data with the master device 30. Therefore, in the control signal 150, the communication unit 60 of the slave device 32 to be controlled can access the internal register 66 at an appropriate timing and communicate data of an appropriate data length with the master device 30. As described above, in this embodiment, the slave device 32 can recognize the timing and data length for communicating with the master device 30 and communicate with the master device 30, so the amount and time of communication between the master device 30 and the slave device 32 can be reduced.

[0136] 16 shows an example of a control signal 160 when performing a 1-byte read according to the embodiment. The first bit included in the control signal 160 is a bit that indicates writing or reading, and even when reading, the first bit specifies writing.

[0137] Next, the control signal 160 includes eight common address bits 162. The control signal 160 includes an ADRS bit 164, sandwiched between an acknowledgement (ACK) bit.

[0138] In the control signal 160, similarly to the example of FIG. 15, in the reference table corresponding to the ADRS bits in FIG. 11, the upper bits ADRS[7] to [4] are ADRS[7]=1, ADRS[6]=1, ADRS[5]=0, and ADRS[4]=1. In this manner, an example in which the upper bits ADRS[7:4]=1101b of the ADRS bits 164 are set is shown as the control signal 160. Therefore, in the control signal 160, one byte is read from the slave devices 32 with IDs 1, 2, 5, and 6. When reading data, the control signal 160 includes a common address bit 166 after including a bit indicating a read in the bits indicating a write or read. The control signal 160 includes an acknowledgement (ACK) bit after the common address bit 166, and then includes a bit string indicating data 168a to 168d for data 1 to data 6 to be actually read.

[0139] Similar to the control signal for writing data, the overall length of the control signal 160 in this embodiment is shorter than the data length of the control signal for reading data in the conventional communication system 200 of FIG.

[0140] 17 shows an example of a control signal 170 when performing a 2-byte read according to the embodiment. The first bit included in the control signal 170 is a bit that indicates writing or reading, and the first bit specifies writing.

[0141] Next, the control signal 170 includes eight common address bits 172. The control signal 170 includes an ADRS bit 174, sandwiched between an acknowledgement (ACK) bit.

[0142] In the control signal 170, similarly to the examples of FIG. 15 and FIG. 16, in the reference table corresponding to the ADRS bits in FIG. 11, the upper bits ADRS[7]-[4] are ADRS[7]=1, ADRS[6]=1, ADRS[5]=0, and ADRS[4]=1. In this manner, an example in which the upper bits ADRS[7:4]=1101b of the ADRS bits 174 are set is shown as the control signal 170. Therefore, in the control signal 170, two bytes are read from the slave devices 32 with IDs 1, 2, 5, and 6. When reading data, the control signal 170 includes a common address bit 176 after including a bit indicating a read in the bits indicating a write or read. The common address bit 176 includes an acknowledgement (ACK) bit, and then includes a bit string indicating data 178a-178g for data 1-data 8 to be actually read.

[0143] Similar to the control signal for writing data, the overall length of the control signal 170 of this embodiment is shorter than the data length of the control signal for reading data in the conventional communication system 200 of FIG.

[0144] According to the slave device 32 configured as above, the communication unit 60 confirms that the common address of the address information matches the common address register 664 set in the internal register 66, and determines whether the communication unit 60 should read or write data based on the first bit indicated in the address information. The communication unit 60 determines whether the communication unit 60 is assigned to the bit having "1" among the upper bits 942 by referring to the upper bits 942 of the ADRS bits 94 and a reference table as shown in FIG. 11. Then, when the common address is indicated in the address information and the bit having "1" among the upper bits 942 is assigned to a slave device, the communication unit 60 determines that the communication unit 60 is the target of data communication. Furthermore, the communication unit 60 specifies the register address and data length of the slave device 32 from which the communication unit 60 should read or write data, which corresponds to the data length information of the lower bits 944, by referring to the lower bits 944 of the ADRS bits 94 and a control map as shown in FIG. 12.

[0145] On the other hand, when the communication unit 60 itself is assigned to a bit having "0" among the upper bits 942, the communication unit 60 determines that it is not a target of data communication. Next, when the communication unit 60 itself is a target of data communication, it receives or transmits data of a data length specified based on the correspondence between the data length information indicated in the lower bits 944 and the control map, in accordance with an order determined by the ID read from the common address register 664 and the designation information indicating the slave device 32 to be controlled, which is indicated in the ADRS bits 94.

[0146] 18 shows an example of a flowchart of the operation of the IC recognition unit 64 according to the embodiment. The operation performed by the IC recognition unit 64 includes steps S100 to S134.

[0147] The slave device 32 receives communication data including a control signal from the master device 30 (step S100). Specifically, the communication data may be received by the transmitting / receiving unit 62 in the communication unit 60 from the input terminals 50, 52. The transmitting / receiving unit 62 then transmits to the IC recognition unit 64 a portion of the control signal indicating whether the slave device 32 is a control target.

[0148] Next, in this embodiment, processing steps S110 to S134 performed by the IC recognition unit 64 will be described. The IC recognition unit 64 reads the common address and ID of the slave device 32 from the internal register 66. The IC recognition unit 64 compares the common address bit from the portion of the control signal indicating whether the slave device 32 is a control target or not with the common address read from the common address register 664 (step S110). If the comparison result shows that the contents match, the process proceeds to step S112, and if the contents do not match, the process proceeds to step S118.

[0149] Next, the IC recognition unit 64 determines whether to perform a read process or a write process on the internal register 66 in the slave device 32 based on the bit indicating whether a read (R) process or a write (W) process is to be performed, which is indicated before the common address bit (step S112). Next, the IC recognition unit 64 compares the bit (corresponding to an enable signal) indicating the IC to be controlled, which is indicated in the ADRS bit, with the ID indicated in the common address register 664 to verify whether they match (step S114). If the comparison result indicates that the contents match, the process proceeds to step S116, and if the contents do not match, the process proceeds to step S118.

[0150] If the comparison result is no match (NO) in step S110 or step S114, the IC recognition unit 64 returns a negative acknowledgement (NACK) in recognizing whether the slave device 32 is the control target (step S118). Together with the negative acknowledgement (NACK) from the IC recognition unit 64, the processing of the slave device 32 in the control signal of the communication data communicated in step S100 ends.

[0151] 11, the IC recognition unit 64 identifies the IDs of all slave devices 32 that are targets of data communication by the current control signal. The IC recognition unit 64 arranges all identified IDs in ascending order and identifies the order of its own IDs shown in the internal register 66, thereby determining the order in which the slave devices 32 perform control (step S116). Meanwhile, the IC recognition unit 64 reads data length information from the lower bits of the ADRS bits, and compares the contents of the data length information with the control map (step S120).

[0152] As a result, the IC recognition unit 64 determines the register address to be accessed in the register (step S122). Information on the register address to be accessed in the register is used in step S134. Furthermore, the IC recognition unit 64 determines the data length to be processed in the register in the register address to be accessed (step S124). Information on the data length is used in step S126.

[0153] The IC recognition unit 64 additively adds up the order in which the slave device 32 performs control and the data length to be processed in the register (step S126). If the order of the slave device 32 is N, the IC recognition unit 64 calculates (N-1) x data length (data order). For example, if the order of the slave device 32 is "3", the IC recognition unit 64 adds two to the data length (calculates 2 x data length). This allows the IC recognition unit 64 to determine the timing at which the slave device 32 performs data processing in the clock indicated by the clock signal, that is, the order of data processing (data order) (step S128). In the case of a read process, the IC recognition unit 64 recognizes that after the ACK following the ADRS bit 94, the IC recognition unit 64 waits for (N-1) x data length (data order) and accesses the designated register in the slave device 32 to read the data. In the case of a write process, the IC recognition unit 64 waits for (N-1) x data length (data order) after the ACK following the common address bits 166, 176, whose first bit is specified to be written, and then accesses the specified register in the slave device 32 to write the data.

[0154] The IC recognition unit 64 counts the number of data in the clock by a counter (not shown) and compares whether the number of data matches the data order (step S130). If the number of data reaches the data order to be processed, the process proceeds to step S134, and if the number of data does not reach the data order to be processed, the process proceeds to step S132.

[0155] If the number of data items has not reached the data order to be processed, the IC recognition unit 64 waits (step S132) and then proceeds to a process of comparing again whether the number of data items matches the data order (step S130).

[0156] When the number of data reaches the data order to be processed, the IC recognition unit 64 accesses the register of the target register address of the slave device 32 based on the information of the register address to be accessed in the register, and performs a read or write process of data of the byte length specified by the data length determined in step S124 (step S134). This allows the control information used by the actuator drive unit 80 to be processed.

[0157] The above process implements the operation of the IC recognition unit 64. This implements the data communication method in this embodiment. Therefore, the operation of the IC recognition unit 64 is implemented, which can simultaneously control multiple ICs and can handle control signals that can reduce the signal length of the control signal and prevent the communication band from being overloaded.

[0158] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0159] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0160] 10. Imaging device 12 Camera 14 Base (substrate) 16,26 PCB 18,44 Image sensor 20,30 Master device 22,32 Slave Device 24,28 bit string 31,60 Communications Department 34 Other Slave Devices 40 Imaging unit 42,120 Optical system 46 Drive unit 50,52 Input terminal 54,56 Output terminal 62 Transmitter / receiver 64 IC recognition section 66 Internal Registers 68 Non-volatile memory 70 Position Sensor 72 Amplification section 74 ADC 80 Actuator drive unit 82 Control section 84DAC 86 1st Driver 88 2nd Driver 90,130,140,150,160,170 Control signal 92,132,142,152,162,166,172,176 common address bits 94,134,144,154,164,174 ADRS bits 96,168,178 Data 100 user terminals 121,123,125 Voice coil motor 122,124,126,460,464 Air core coil 127,128,129 IC chip 200 Communication Systems 260,263,266,462,466 Magnets 660 Target Position Register 662 Operation Mode Register 664 Common Address Register 942 high order bits 944 low bits

Claims

1. A slave device that communicates data with a master device via a bus, A slave device comprising: a communication unit that performs data communication with the master device based on a control signal including address information indicating an address common to a plurality of slave devices, designation information that designates at least one slave device among the plurality of slave devices as the target of data communication, and data length information indicating the data length received or transmitted in a predetermined order by the slave device designated by the designation information, to read data of the data length indicated in the data length information from a register of the slave device or write data to the register of the slave device in accordance with the predetermined order and the designation information.

2. Each of the plurality of slave devices has an ID to which a predetermined order is uniquely assigned, the communication unit determines an order of reading or writing the data based on the ID and the designation information; 2. The slave device of claim 1.

3. a predetermined order is uniquely assigned to each of the plurality of slave devices; the designation information has a first bit sequence in which at least one slave device to be a target of data communication among the plurality of slave devices is assigned to each bit; The communication unit is receiving or transmitting data having a data length indicated in the data length information in accordance with the predetermined order and the designation information when the slave device is assigned to a bit having a first value in the first bit sequence; The slave device according to claim 1 , wherein when the slave device is assigned to a bit having a second value in the first bit sequence, the slave device is determined to be not a target for data communication.

4. the address information includes a first bit indicating whether the slave device is to read or write data; The communication unit is 2. The slave device of claim 1, wherein the slave device determines whether to read or write data based on the first bit.

5. the data length information has a second bit string corresponding to a register address and a data length of the slave device from which the slave device reads or writes data; The communication unit is by referring to a map indicating a relationship between a second bit string and a register address and a data length of the slave device from which the slave device is to read or write data, the register address and the data length of the slave device corresponding to the second bit string included in the data length information are identified; 2. The slave device of claim 1, wherein when the slave device is a target for data communication, the slave device receives or transmits data of a data length indicated in the data length information in accordance with the predetermined order and the designation information by accessing the register address of the slave device from which the slave device is to read or write data.

6. a predetermined order is uniquely assigned to each of the plurality of slave devices; the address information includes a first bit indicating whether the slave device is to read or write data; the designation information has a first bit sequence in which at least one slave device to be a target of data communication among the plurality of slave devices is assigned to each bit; the data length information has a second bit string corresponding to a register address and a data length of the slave device from which the slave device reads or writes data; The communication unit is determining whether the slave device should read data from or write data to the register based on the first bit; If the common address is indicated in the address information and the slave device is assigned to a bit having a first value in the first bit string, the slave device is determined to be a target for data communication; If the common address is indicated in the address information and the slave device is assigned to a bit having a second value in the first bit string, the slave device is determined to be not a target for data communication; When the slave device is a target of data communication, by referring to a map showing a relationship between a second bit sequence and a register address and a data length of the slave device from which the slave device is to read or write data, the register address and the data length of the slave device corresponding to the second bit sequence included in the data length information are identified; 2. The slave device of claim 1, wherein when the slave device is a target for data communication, the slave device receives or transmits data of a data length indicated in the data length information in accordance with the predetermined order and the designation information by accessing the register address of the slave device from which the slave device is to read or write data.

7. the address information indicates the common address or an individual address that uniquely identifies each of the plurality of slave devices; When the address information indicates the individual address, the control signal includes, instead of the designation information and the data length information, register information indicating a register address of the slave device from which data is to be read or written by the slave device corresponding to the individual address and which is the target of data communication, and 2. The slave device according to claim 1, wherein when the address information indicates an individual address of the slave device, the communication unit performs data communication with the master device to read or write data by accessing the register address of the slave device indicated in the register information.

8. The slave device according to claim 1 , wherein the slave device performs data communication with the master device using an I2C communication method.

9. The slave device of claim 1 , wherein the slave device is an IC chip.

10. A plurality of slave devices according to any one of claims 1 to 9; the master device transmitting the control signal to the plurality of slave devices via the bus; A communication system comprising:

11. A communication system according to claim 10; a plurality of imaging units each having an optical system, an imaging element for capturing an image formed through the optical system, and a driving unit for driving at least one of the optical system and the imaging element; Equipped with an imaging device, wherein each of the plurality of slave devices drives at least one of the optical system and the imaging element by controlling the corresponding driving unit in accordance with the corresponding data;

12. A communication system according to claim 10; an imaging unit including an optical system, an imaging element that captures an image formed through the optical system, and a driving unit that drives at least one of the optical system and the imaging element; Equipped with each of the plurality of slave devices drives at least one of the optical system and the image sensor by controlling the driving unit in accordance with the respective data.

13. A master device that communicates data with a plurality of slave devices via a bus, A master device comprising a communication unit that performs data communication with at least one slave device among the plurality of slave devices that is the target of data communication by transmitting a control signal to the plurality of slave devices via the bus, the control signal including address information indicating an address common to the plurality of slave devices, designation information that designates at least one slave device among the plurality of slave devices that is the target of data communication, and data length information that indicates the data length received or transmitted in a predetermined order by the slave device designated by the designation information.

14. 1. A data communication method for communicating data between a master device and a plurality of slave devices via a bus, comprising: a step of a slave device among the plurality of slave devices receiving from the master device a control signal including address information indicating an address common to the plurality of slave devices, designation information designating at least one slave device among the plurality of slave devices as a target of data communication, and data length information indicating a data length to be received or transmitted in a predetermined order by the slave device designated by the designation information; a step of performing data communication between the slave device and the master device, when the slave device is designated as a target of data communication by the designation information, so as to read data of a data length indicated in the data length information from a register of the slave device or write data to the register of the slave device in accordance with the predetermined order and the designation information, based on the control signal; A data communication method comprising:

Images