Display device

Abstract

To provide a display device capable of suppressing reduction of a frame rate while attaining high definition of display.SOLUTION: A display device comprises: a substrate including a display region; a plurality of pixels provided in the display region and arrayed in a first direction and a second direction which crosses the first direction; a plurality of gate lines extending in the first direction and arrayed in the second direction; and a first gate driver and a second gate driver for supplying gate drive signals to the plurality of gate lines. The first gate driver and the second gate driver are provided in the second direction and disposed side by side in the first direction. The first gate driver and the second gate driver successively scan the plurality of gate lines in a first region of the display region and simultaneously scan the plurality of gate lines adjacent in the second direction in a second region different from the first region of the display region.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Patent Document 1 describes a display device capable of simultaneously driving a set of multiple adjacent gate lines (scanning lines). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-271366 A Summary of the Invention [Problem to be solved by the invention]

[0004] In such a display device, there is a demand for suppressing a decrease in frame rate while achieving high-definition display. In Patent Document 1, it may be difficult to achieve both high-definition display and a high frame rate.

[0005] An object of the present invention is to provide a display device capable of suppressing a decrease in frame rate while achieving high-definition display. [Means for solving the problem]

[0006] A display device according to one embodiment of the present disclosure includes a substrate having a display area, a plurality of pixels provided in the display area and arranged in a first direction and a second direction intersecting the first direction, a plurality of gate lines extending in the first direction and arranged in the second direction, and a first gate driver and a second gate driver that supply gate drive signals to the plurality of gate lines, the first gate driver and the second gate driver each being provided along the second direction and arranged side by side in the first direction, the first gate driver and the second gate driver sequentially scanning the plurality of gate lines in a first region of the display area, and simultaneously scanning the plurality of gate lines adjacent to each other in the second direction in a second region of the display area different from the first region. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view that illustrates a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a pixel array of the display device according to the embodiment. [Diagram 3] FIG. 3 is a diagram illustrating an example of the configuration of the display device according to the embodiment. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of the host and driver IC according to the embodiment. [Diagram 5] FIG. 5 is an explanatory diagram illustrating a method for scanning a plurality of gate lines in the display device according to the embodiment. [Figure 6] FIG. 6 is a block diagram showing a schematic configuration of the gate driver. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of the first gate driver. [Figure 8] FIG. 8 is a timing chart for explaining a method of scanning a plurality of gate lines in the first region. [Figure 9] FIG. 9 is a timing chart for explaining a method of scanning a plurality of gate lines in the second region. [Figure 10]FIG. 10 is a timing chart for explaining a method of scanning a plurality of gate lines in the second region in a display device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The form (embodiment) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited by the contents described in the following embodiments. In addition, the components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the present disclosure are naturally included in the scope of the present disclosure. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present disclosure. In addition, in this disclosure and each figure, elements similar to those described above with respect to the previously mentioned figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] (Embodiment) 1 is a cross-sectional view showing a display device according to an embodiment. The display device 1 according to the embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In the embodiment, the display device 1 can adopt, for example, a column inversion driving method or a frame inversion method as a driving method. The driving method in the display device 1 is not limited to the column inversion driving method or the frame inversion method.

[0010] As shown in Fig. 1, the display device 1 includes an array substrate 2, a counter substrate 3, and a liquid crystal layer 6. The array substrate 2 includes a first substrate 21 made of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX and the common electrode COML. The plurality of pixel electrodes PX are disposed, for example, in a matrix above the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0011] The pixel electrodes PX and the common electrode COML are made of a conductive material having light-transmitting properties, such as ITO (Indium Tin Oxide), etc. A polarizing plate 35B is provided on the lower side of the first substrate 21 via an adhesive layer (not shown).

[0012] The array substrate 2 includes wiring such as pixel transistors Tr (see FIG. 2) of each pixel Pix, signal lines SL (see FIG. 2) that supply pixel signals SIG to each pixel electrode PX, and gate lines GL (see FIG. 2) that supply gate drive signals GATE that drive each pixel transistor Tr. The signal lines SL and the gate lines GL extend in a plane parallel to the surface of the first substrate 21.

[0013] The counter substrate 3 includes a second substrate 31 made of glass or transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. In addition, a polarizing plate 35A is provided on the upper side of the second substrate 31 via an adhesive layer (not shown).

[0014] The array substrate 2 and the counter substrate 3 are disposed opposite to each other with a predetermined gap (cell gap) provided. A liquid crystal layer 6 is provided as a display function layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 modulates light passing through the liquid crystal layer 6 by changing the alignment state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML. In this embodiment, for example, a liquid crystal suitable for a lateral electric field mode such as IPS (in-plane switching) including FFS (fringe field switching) is used.

[0015] The display device 1 has a light source device (backlight) (not shown) that illuminates the display area AA from behind. The backlight is disposed opposite the array substrate 2, and the opposing substrate 3 is located on the display surface side. The backlight has, for example, a plurality of LEDs as light-emitting elements. Various types of backlights are applicable, but detailed explanations of their structures will be omitted.

[0016] Fig. 2 is a diagram showing an example of a pixel arrangement of a display device according to an embodiment. As shown in Fig. 2, the display device 1 includes a plurality of pixels Pix, a plurality of gate lines GL, and a plurality of signal lines SL provided on an array substrate 2. The plurality of pixels Pix are arranged in a matrix in a display area AA of the array substrate 2. That is, the plurality of pixels Pix are arranged in a first direction Dx and also in a second direction Dy intersecting the first direction Dx.

[0017] In the following description, the first direction Dx is a direction in a plane parallel to the array substrate 2. The second direction Dy is a direction in a plane parallel to the array substrate 2, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the main surface of the array substrate 2. In addition, "planar view" refers to the positional relationship when viewed from a direction perpendicular to the array substrate 2.

[0018] The gate lines GL each extend in a first direction Dx and are arranged in a second direction Dy. The gate lines GL are each connected to the pixels Pix arranged in the first direction Dx. The gate lines GL supply a gate driving signal GATE to the pixels Pix.

[0019] The signal lines SL each extend in the second direction Dy and are arranged in the first direction Dx. The signal lines SL are each connected to the pixels Pix arranged in the second direction Dy. The signal lines SL supply pixel signals SIG to the pixels Pix.

[0020] Each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is configured with a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to a signal line SL, the gate is connected to a gate line GL, and the drain is connected to the pixel electrode PX. A storage capacitance CS is formed between the pixel electrode PX and a common electrode COML.

[0021] A gate driving signal GATE is supplied to the gates of the pixel transistors Tr of the pixels Pix aligned in the first direction Dx via the gate line GL. A pixel signal SIG is supplied to the sources of the pixel transistors Tr of the pixels Pix aligned in the second direction Dy via the signal line SL. FIG. 2 shows an example in which N pixels Pix are aligned in the first direction Dx and M pixels Pix are aligned in the second direction Dy, but this is not limiting. Hereinafter, a row in which the pixels Pix are aligned in the first direction Dx is also referred to as a pixel row. A column in which the pixels Pix are aligned in the second direction Dy is also referred to as a pixel column.

[0022] The pixels Pix include, for example, red pixels for displaying red (R), green pixels for displaying green (G), and blue pixels for displaying blue (B). An example of the pixel arrangement is a stripe arrangement in which the R, G, and B pixels are arranged in a first direction Dx. However, the pixel arrangement is not limited to the R, G, and B stripe arrangement. Specifically, for example, the pixels Pix may be white pixels for displaying white (W), or may be a diagonal stripe arrangement having a predetermined angle with respect to the first direction Dx and the second direction Dy, or an arrangement in which a plurality of pixel groups displaying different colors are periodically arranged in both the first direction Dx and the second direction Dy.

[0023] Fig. 3 is a diagram showing an example of the configuration of a display device according to an embodiment. As shown in Fig. 3, the display device 1 further includes a drive circuit 40, a power supply device 12, and a host 13 (control device).

[0024] The host 13 transmits a video signal, which is an original signal of a video to be displayed in the display area AA, to the driver IC 41. The host 13 also transmits a control signal for controlling the drive circuit 40 to the display device 1. The host 13 also transmits a control signal for controlling the power supply from the power supply device 12 to the drive circuit 40 to the power supply device 12.

[0025] The host 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. The host 13 executes a program using these hardware resources such as the CPU and the storage device, thereby realizing the display function of the display device 1. The host 13 controls the image to be displayed on the display device 1 so that the driver IC 41 can handle the image as image input gradation information according to the execution result of the program.

[0026] The power supply device 12 supplies power to a drive circuit 40 provided on the array substrate 2 based on a control signal from the host 13. Specifically, the power supply device 12 generates a first power supply voltage signal PSIG1 of a positive value and a second power supply voltage signal PSIG2 of a negative value to be supplied to the drive circuit 40. The first power supply voltage signal PSIG1 is controlled to a first potential (VGH). The second power supply voltage signal PSIG2 is controlled to a second potential (VGL) that is lower than the first potential (VGH). The power supply device 12 also supplies power to a driver IC 41 included in the drive circuit 40.

[0027] The driving circuit 40 is provided in the peripheral region of the display area AA. The driving circuit 40 includes a driver IC 41 (display control circuit), a gate driver 42, and a signal line selection circuit 43. The driver IC 41 is mounted in the peripheral region of the display area AA. The driver IC 41 is connected to the host 13 via a relay board such as a flexible printed circuit board (FPC). The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral region of the display area AA.

[0028] The driver IC 41 controls the gate driver 42 and the signal line selection circuit 43. Specifically, the driver IC 41 supplies control signals such as a start signal ST, a shift clock signal SCK, and an output control signal GCK to the gate driver 42. The driver IC 41 also supplies a selection control signal MUX to the signal line selection circuit 43. The driver IC 41 also converts a video signal from the host 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing a pixel signal SIG corresponding to an RGB pixel arrangement. The driver IC 41 also supplies a common potential VCOM to the common electrode COML.

[0029] The gate driver 42 is a circuit that generates a gate drive signal GATE based on the start signal ST, the shift clock signal SCK, and the output control signal GCK output from the driver IC 41.

[0030] The signal line selection circuit 43 supplies pixel signals SIG to pixels Pix included in a pixel row selected by the gate driver 42. The signal line selection circuit 43 includes a switch circuit that selects a signal line SL that supplies the pixel signal SIG. The signal line selection circuit 43 selectively outputs the pixel signal SIG corresponding to each pixel Pix based on the image signal Vsig from the driver IC 41.

[0031] 4 is a block diagram showing a configuration example of a host and a driver IC according to the embodiment. In the display device 1 according to the embodiment, the driver IC 41 controls a gate driver 42, a signal line selection circuit 43, and a backlight (not shown) based on a control signal and various information from the host 13 (control device).

[0032] As shown in FIG. 4, the driver IC 41 includes a register 44, a memory 45, an image signal generating circuit 46, a timing control circuit 47, a control signal generating circuit 48, and a light source driving circuit 49.

[0033] Based on a control signal and various information from the host 13, the timing control circuit 47 controls the memory 45, the image signal generating circuit 46, the control signal generating circuit 48, and the light source driving circuit 49 so that they operate in synchronization with each other.

[0034] The register 44 is a circuit that receives and temporarily stores driving information from the host 13. The driving information includes information on the number of gate lines GN (see FIG. 5) to be grouped together when the gate driver 42 scans the gate lines GL, the divided areas of the display area AA (the first area AA1, the second area AA2, and the third area AA3 (see FIG. 5)), and the like.

[0035] The memory 45 is a circuit that receives a video signal from the host 13 and temporarily stores the video signal. The image signal generation circuit 46 generates an image signal Vsig based on the video signal acquired from the memory 45. The image signal generation circuit 46 outputs the generated image signal Vsig to the signal line selection circuit 43 (see FIG. 3).

[0036] The control signal generation circuit 48 is a circuit that generates control signals such as a start signal ST, a shift clock signal SCK, and an output control signal GCK based on drive information from the host 13. The control signal generation circuit 48 supplies control signals such as the start signal ST, the shift clock signal SCK, and the output control signal GCK to the gate driver 42. This causes the gate driver 42 to scan a plurality of gate lines GL sequentially or simultaneously in accordance with the drive information. The control signal generation circuit 48 also generates a selection control signal MUX (see FIG. 3) and outputs it to the signal line selection circuit 43 (see FIG. 3).

[0037] The light source drive circuit 49 is a circuit that outputs a drive signal VLED to a light emitting element of a backlight (not shown) based on drive information from the host 13. Various forms of backlight drive are applicable depending on the configuration of the pixels Pix of the display area AA, but detailed description thereof will be omitted.

[0038] In the display device 1 of this embodiment, the gate driver 42 sequentially or simultaneously scans a plurality of gate lines GL for each region during a period in which one frame of an image is displayed (one frame period). That is, the gate driver 42 scans the plurality of gate lines GL by changing the number of gate lines GL grouped together for each region. Hereinafter, a detailed configuration of the gate driver 42 and a method of scanning the gate lines GL will be described with reference to Figs. 5 to 10.

[0039] 5 is an explanatory diagram illustrating a method for scanning a plurality of gate lines in a display device according to an embodiment. As shown in FIG. 5, a display area AA includes a first area AA1, a second area AA2, and a third area AA3. The first area AA1, the second area AA2, and the third area AA3 are areas provided corresponding to a plurality of pixel rows, respectively.

[0040] The first region AA1 is located in the center of the display region AA in the second direction Dy. The second region AA2 is disposed adjacent to the first region AA1 on one side of the second direction Dy (upper side in FIG. 5). The third region AA3 is disposed adjacent to the first region AA1 on the other side of the second direction Dy (lower side in FIG. 5). In other words, the first region AA1 is disposed between the second region AA2 and the third region AA3 in the second direction Dy.

[0041] The gate driver 42 sequentially scans the gate lines GL in the first area AA1 (gate line group number GN=1). In other words, the gate driver 42 sequentially supplies the gate driving signal GATE to each gate line GL in the first area AA1.

[0042] The gate driver 42 simultaneously scans a plurality of gate lines GL arranged in the second direction Dy in the second area AA2 and the third area AA3 (for example, the number of gate lines GN=4). In other words, the gate driver 42 simultaneously supplies a gate driving signal GATE to a plurality of gate lines GL (for example, four gate lines GL) in the second area AA2 and the third area AA3.

[0043] As a result, the display device 1 can perform a higher-definition display in the first area AA1 located in the center of the display area AA compared to the second area AA2 and the third area AA3. Meanwhile, the display device 1 can shorten the period required for scanning the gate lines GL (hereinafter referred to as the drive period) in the second area AA2 and the third area AA3 located on the periphery of the display area AA to 1 / 4 of the period required when the gate drive signal GATE is supplied sequentially. Therefore, the display device 1 can suppress a decrease in the frame rate while achieving a high-definition display. The frame rate refers to the number of frame images displayed in a given time (for example, one second).

[0044] Fig. 6 is a block diagram showing a gate driver. As shown in Fig. 6, the gate driver 42 has a first gate driver 42A and a second gate driver 42B. The gate driver 42 further has a buffer circuit 50. The first gate driver 42A and the second gate driver 42B are connected to ends of the same side of the multiple gate lines GL. The first gate driver 42A and the second gate driver 42B are each provided along the second direction Dy and are arranged side by side in the extension direction (first direction Dx) of the multiple gate lines GL.

[0045] The first gate driver 42A and the second gate driver 42B are controlled independently of each other by inputting different start signals ST1, ST2 (input signals), shift clock signals SCK1, SCK2, and output control signals GCK1, GCK2, GCK3, GCK4. The first gate driver 42A and the second gate driver 42B output gate control signals G (G1, G2, ...), which are the logical values ​​of the gate drive signal GATE, based on various control signals.

[0046] The buffer circuit 50 is a circuit that receives gate control signals G (G1, G2, . . . ) generated as logical values ​​and generates a gate drive signal GATE having a first potential VGH and a second potential VGL. The buffer circuit 50 supplies the gate drive signal GATE corresponding to the gate control signals G to the gate line GL.

[0047] More specifically, the first gate driver 42A includes a plurality of first register circuits SR1-1, SR1-2, SR1-3, SR1-4, ... arranged in the second direction Dy, and a plurality of first output circuits OC1-1, OC1-2, OC1-3, OC1-4, ... provided corresponding to each of the plurality of first register circuits SR1-1, SR1-2, SR1-3, SR1-4, ....

[0048] The second gate driver 42B is arranged in parallel with the first gate driver 42A. The second gate driver 42B includes a plurality of second register circuits SR2-1, SR2-2, SR2-3, SR2-4, ... arranged in the second direction Dy, and a plurality of second output circuits OC2-1, OC2-2, OC2-3, OC2-4, ... provided corresponding to the plurality of second register circuits SR2-1, SR2-2, SR2-3, SR2-4, ..., respectively.

[0049] In the following description, when there is no need to distinguish between the first register circuits SR1-1, SR1-2, SR1-3, SR1-4, etc., they will simply be referred to as the first register circuit SR1. Also, when there is no need to distinguish between the first output circuits OC1-1, OC1-2, OC1-3, OC1-4, etc., they will simply be referred to as the first output circuit OC1.

[0050] When it is not necessary to distinguish between the second register circuits SR2-1, SR2-2, SR2-3, SR2-4, etc., they will be simply referred to as the second register circuit SR2. Furthermore, when it is not necessary to distinguish between the second output circuits OC2-1, OC2-2, OC2-3, OC2-4, etc., they will be simply referred to as the second output circuit OC2.

[0051] The gate lines GL are arranged in the second direction Dy, and every P gate lines GL (P is a natural number) are alternately connected to a first gate driver 42A and a second gate driver 42B. In the example shown in FIG. 6, P=2.

[0052] The gate lines GL1 and GL2 are connected to the first register circuit SR1-1 and the first output circuit OC1-1 of the first gate driver 42A. The gate lines GL3 and GL4 are connected to the second register circuit SR2-1 and the second output circuit OC2-1 of the second gate driver 42B. The gate lines GL5 and GL6 are connected to the first register circuit SR1-2 and the first output circuit OC1-2 of the first gate driver 42A. The gate lines GL7 and GL8 are connected to the second register circuit SR2-2 and the second output circuit OC2-2 of the second gate driver 42B. Similarly, the gate lines GL9, GL10, ... are alternately connected to the first gate driver 42A and the second gate driver 42B.

[0053] A total of four (=P×2) gate lines GL are connected to a set of a first register circuit SR1 and a first output circuit OC1, and a set of a second register circuit SR2 and a second output circuit OC2 provided correspondingly thereto.

[0054] Fig. 7 is a circuit diagram showing a configuration example of the first gate driver. In Fig. 7, the first register circuit SR1 and the first output circuit OC1 of the first gate driver 42A will be described. However, the second gate driver 42B has the same configuration as the first gate driver 42A. The description of the first register circuit SR1 and the first output circuit OC1 in Fig. 7 can also be applied to the second register circuit SR2 and the second output circuit OC2.

[0055] 7, the first register circuit SR1 includes clocked inverters 51 and 53, and an inverter 52. When the shift clock signal SCK1 becomes high potential (hereinafter, represented as H), the clocked inverter 51 of the first register circuit SR1-1 turns on, and an inverted signal of the start signal ST1 is output to the inverter 52. Since the signal is inverted by the inverter 52, the output signal Q of the first register circuit SR1-1 becomes a signal of high potential (H) like the start signal ST1 of high potential (H).

[0056] An inverted signal of the shift clock signal SCK1 is input by the inverter 56 to the clocked inverter 53 of the first register circuit SR1-1 and the clocked inverter 51 of the first register circuit SR1-2 in the next stage. Therefore, when the shift clock signal SCK1 is at high potential (H), the clocked inverter 53 of the first register circuit SR1-1 and the clocked inverter 51 of the first register circuit SR1-2 in the next stage are turned off. In other words, while the shift clock signal SCK1 maintains high potential (H), the output signal Q of the first register circuit SR1-1 is not transferred to the first register circuit SR1-2.

[0057] When the shift clock signal SCK1 becomes a low potential (hereinafter, represented as L), the clocked inverter 51 of the first register circuit SR1-1 is turned off, and the clocked inverter 51 of the first register circuit SR1-2 of the next stage is turned on. As a result, the output signal Q of the first register circuit SR1-1 is transferred to the first register circuit SR1-2. At this time, the clocked inverter 53 of the first register circuit SR1-1 is turned on, and the output signal Q is held by the inverter 52 and the clocked inverter 53. As a result, a change in the output signal Q is suppressed from when the clocked inverter 51 of the first register circuit SR1-1 is turned off until the clocked inverter 51 of the first register circuit SR1-2 of the next stage is turned on.

[0058] In this way, the first register circuit SR outputs an output signal Q according to the start signal ST1 (input signal) of high potential (H) at the timing of the rise or fall of the shift clock signal SCK1. Then, at the timing of the rise or fall of the shift clock signal SCK1, the output signal Q is sequentially transferred to the next-stage first register circuit SR.

[0059] 7, the first output circuit OC1 includes AND circuits 54 and 55. P (P=2 in this embodiment) AND circuits 54 and 55 are provided corresponding to the number of gate lines GL connected to one set of the first register circuit SR1 and the first output circuit OC1. The AND circuit 54 generates a logical product value of the output signal Q of the first register circuit SR1 and the output control signal GCK1. The AND circuit 55 generates a logical product value of the output signal Q of the first register circuit SR1 and the output control signal GCK2.

[0060] As described above, the second register circuit SR2 and the second output circuit OC2 of the second gate driver 42B have the same configuration as the first register circuit SR and the first output circuit OC1. As shown in Fig. 6, the second register circuit SR2 and the second output circuit OC2 operate based on the start signal ST2, the shift clock signal SCK2, and the output control signals GCK3 and GCK4. In other words, the second gate driver 42B (the second register circuit SR2 and the second output circuit OC2) operates based on signals different from those of the first gate driver 42A (the first register circuit SR and the first output circuit OC1).

[0061] In this embodiment, the first gate driver 42A and the second gate driver 42B may operate synchronously or asynchronously. Therefore, the first gate driver 42A and the second gate driver 42B can improve the degree of freedom in scanning the gate lines GL compared to the case where only one of them is provided.

[0062] 8 is a timing chart for explaining a method of scanning a plurality of gate lines in the first region. As shown in FIG. 8, in the first gate driver 42A, the start signal ST1 goes to high potential (H) at time t1. The shift clock signal SCK1 goes from low potential (L) to high potential (H) at time t2. At time t2, that is, at the rising edge of the shift clock signal SCK1, the output signal Q is output from the first register circuit SR1.

[0063] During a period when the shift clock signal SCK1 is at a high potential (H), the output control signals GCK1 and GCK2 are at a high potential (H) in a time-division manner. More specifically, the output control signal GCK1 is at a high potential (H) at time t2. The output control signal GCK2 is at a high potential (H) at time t3. In response to the output control signals GCK1 and GCK2, the gate control signals G1 and G2 are at a high potential (H) in a time-division manner.

[0064] In the first area AA1, the second gate driver 42B operates out of synchronization with the first gate driver 42A. In the second gate driver 42B, the start signal ST2 goes to high potential (H) at time t3. At time t4, the shift clock signal SCK2 goes from low potential (L) to high potential (H). At time t4, that is, at the rising edge of the shift clock signal SCK2, the output signal Q is output from the second register circuit SR2.

[0065] During a period when the shift clock signal SCK2 is at a high potential (H), the output control signals GCK3 and GCK4 go to a high potential (H) in a time-division manner. More specifically, the output control signal GCK3 goes to a high potential (H) at time t4. The output control signal GCK4 goes to a high potential (H) at time t5. In response to the output control signals GCK3 and GCK4, the gate control signals G3 and G4 go to a high potential (H) in a time-division manner.

[0066] Next, in the first gate driver 42A, the shift clock signal SCK1 changes from high potential (H) to low potential (L) at time t6. At time t6, that is, at the falling edge of the shift clock signal SCK1, the output signal Q is output from the first register circuit SR1.

[0067] The output control signal GCK1 goes to high potential (H) at time t6. The output control signal GCK2 goes to high potential (H) at time t7. In response to the output control signals GCK1 and GCK2, the gate control signals G5 and G6 go to high potential (H) in a time-division manner.

[0068] Next, in the second gate driver 42B, the shift clock signal SCK2 changes from high potential (H) to low potential (L) at time t8. At time t8, that is, at the falling edge of the shift clock signal SCK2, the output signal Q is output from the second register circuit SR2.

[0069] While the shift clock signal SCK2 is at low potential (L), the output control signal GCK3 goes to high potential (H) at time t8. The output control signal GCK4 goes to high potential (H) at time t9. In response to the output control signals GCK3 and GCK4, the gate control signals G7 and G8 go to high potential (H) in a time-division manner.

[0070] After time t10, by repeatedly performing the operations shown from time t2 to time t9, the first register circuit SR1 of the first gate driver 42A and the second register circuit SR2 of the second gate driver 42B operate to alternately output the output signal Q. The first output circuit OC1 and the second output circuit OC2 sequentially output the gate control signals G1, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, and G12 of high potential (H) in a time-division manner.

[0071] The buffer circuit 50 generates a gate drive signal GATE based on the gate control signals G1, G2, . . . , G12 generated as logical values. The gate drive signal GATE is generated to have a waveform corresponding to the gate control signal G shown in FIG. 8. That is, the gate drive signal GATE has a first potential VGH corresponding to the gate control signal G of high potential (H), and has a second potential VGL lower than the first potential VGH corresponding to the gate control signal G of low potential (L). The gate drive signal GATE is sequentially supplied to the gate lines GL1 to GL12. By the above-mentioned operation, the first gate driver 42A and the second gate driver 42B sequentially scan the multiple gate lines GL in the first area AA1.

[0072] In addition, in FIG. 8, the start signal ST2 input to the second gate driver 42B is a signal different from the start signal ST1 input to the first gate driver 42A, and changes from low potential (L) to high potential (H) at a different timing from the start signal ST1. However, without being limited thereto, the start signal ST2 input to the second gate driver 42B may be a signal common to the start signal ST1. By configuring the first gate driver 42A and the second gate driver 42B to receive a common start signal ST1, at least one wiring can be omitted. Also, in the timing charts shown in FIG. 9 and FIG. 10 described later, the start signal ST1 and the start signal ST2 may be different signals or may be a common signal.

[0073] Fig. 9 is a timing chart for explaining a method of scanning a plurality of gate lines in the second region. As shown in Fig. 9, the first gate driver 42A and the second gate driver 42B simultaneously scan two gate lines GL (gate line group number GN = 2) in the period from time t21 to time t24, and simultaneously scan three gate lines GL (gate line group number GN = 3) in the period from time t24 to time t28.

[0074] In the first gate driver 42A, the start signal ST1 goes to high potential (H) at time t21. The shift clock signal SCK1 goes from low potential (L) to high potential (H) at time t22. At the timing of time t22, the output signal Q is output from the first register circuit SR1.

[0075] While the shift clock signal SCK1 is at high potential (H), the output control signals GCK1 and GCK2 go to high potential (H) at timing t22. In response to the output control signals GCK1 and GCK2, the gate control signals G1 and G2 go to high potential (H).

[0076] Next, in the second gate driver 42B, the start signal ST2 goes to high potential (H) at a timing before time t23. The shift clock signal SCK2 goes from low potential (L) to high potential (H) at time t23. At the timing of time t23, the output signal Q is output from the second register circuit SR2.

[0077] While the shift clock signal SCK2 is at high potential (H), the output control signals GCK3 and GCK4 go to high potential (H) at timing t23. In response to the output control signals GCK3 and GCK4, the gate control signals G3 and G4 go to high potential (H).

[0078] As a result, in each period from time t21 to time t24, the gate drive signal GATE is supplied simultaneously to two gate lines GL, and the two gate lines GL are scanned together. Note that, although the period in which the two gate lines GL are scanned together is shown repeated twice in FIG. 9, it may be repeated three or more times.

[0079] Next, at time t24, the shift clock signals SCK1 and SCK2 change from high potential (H) to low potential (L). At the timing of time t24, the output signals Q are output from the first register circuit SR1-2 and the second register circuit SR2-2.

[0080] During a period in which the shift clock signals SCK1 and SCK2 are at low potential (L), the output control signals GCK1, GCK2, and GCK3 go to high potential (H) at timing t24. The output control signal GCK4 maintains low potential (L). In response to the output control signals GCK1, GCK2, and GCK3, the gate control signals G5, G6, and G7 go to high potential (H).

[0081] Next, at time t25, the shift clock signal SCK1 goes from low potential (L) to high potential (H). The shift clock signal SCK2 maintains the low potential (L). At the timing of time t25, the output signal Q is output from the first register circuit SR1-3.

[0082] While the shift clock signal SCK1 is at high potential (H) and the shift clock signal SCK2 is at low potential (L), the output control signals GCK1, GCK2, and GCK4 go to high potential (H) at the timing of time t25. In response to the output control signals GCK1, GCK2, and GCK4, the gate control signals G8, G9, and G10 go to high potential (H).

[0083] Similarly, from time t26 onwards, the first register circuit SR1 of the first gate driver 42A and the second register circuit SR2 of the second gate driver 42B output output signals Q sequentially, either synchronously or asynchronously, so that the three gate control signals G are at high potential (H).

[0084] That is, during the same period, one of the first gate driver 42A and the second gate driver 42B sets the gate control signal G corresponding to P (P=2) gate lines GL to a high potential (H), and the other of the first gate driver 42A and the second gate driver 42B sets the gate control signal G corresponding to one gate line GL to a high potential (H).

[0085] As a result, in each period from time t24 to time t28, the gate drive signal GATE is simultaneously supplied to the three gate lines GL, and the three gate lines GL are scanned collectively. That is, in the first gate driver 42A, P (e.g., P=2) gate lines GL are connected to a pair of a first register circuit SR1 and a first output circuit OC1. In the second gate driver 42B, P (e.g., P=2) gate lines GL are connected to a pair of a second register circuit SR2 and a second output circuit OC2. In this embodiment, the first gate driver 42A and the second gate driver 42B simultaneously scan (P+1) gate lines GL adjacent to each other in the second direction Dy in the second region AA2. In other words, the first gate driver 42A and the second gate driver 42B simultaneously scan P gate lines GL connected to one of the first gate driver 42A and the second gate driver 42B, and one gate line GL connected to the other of the first gate driver 42A and the second gate driver 42B and adjacent to the P gate lines GL. Note that, in the second region AA2, the number of gate lines GL simultaneously scanned by the first gate driver 42A and the second gate driver 42B is a maximum of (P+1) gate lines GL adjacent to each other in the second direction Dy, and the first gate driver 42A and the second gate driver 42B may simultaneously scan less than (P+1) gate lines GL.

[0086] In addition, in FIG. 9, the period from time t24 to time t28 during which the three gate lines GL are scanned collectively is shown repeated four times, but it may be repeated three or less times or five or more times.

[0087] As described above, in this embodiment, the gate lines GL are alternately connected to the first gate driver 42A and the second gate driver 42B for every P (e.g., P=2) adjacent gate lines GL. The first gate driver 42A and the second gate driver 42B are respectively input with different shift clock signals SCK and output control signals GCK and are controlled independently of each other. The first gate driver 42A and the second gate driver 42B operate synchronously or asynchronously during one frame period.

[0088] As a result, the first gate driver 42A and the second gate driver 42B sequentially scan the multiple gate lines GL in the first area AA1, and simultaneously scan the multiple gate lines GL adjacent in the second direction Dy in the second area AA2. In other words, the first gate driver 42A and the second gate driver 42B have a period during one frame period during which they sequentially scan the multiple gate lines GL (e.g., from time t1 to time t14) and a period during which they simultaneously scan the multiple gate lines GL adjacent in the second direction Dy (e.g., from time t21 to time t28).

[0089] As a result, the display device 1 of the present embodiment can improve the degree of freedom of scanning the gate lines GL in one frame period, compared to the case where the gate lines GL are scanned by one gate driver 42. More specifically, the display device 1 can reduce the period required for scanning in the second area AA2 to 1 / 2 or 1 / 3, compared to the case where the gate driving signal GATE is sequentially supplied to the gate lines GL of each pixel row in the entire display area AA, for example, and can shorten the drive period in one frame period. Furthermore, the display device 1 can maintain high-definition display in the first area AA1, compared to the case where a plurality of gate lines GL are simultaneously scanned in the entire display area AA. As a result, the display device 1 can suppress a decrease in frame rate while achieving high-definition display.

[0090] 8 and 9 are merely examples, and can be modified as appropriate as long as the (P+1) gate lines GL are scanned simultaneously. For example, in FIG. 9, the first gate driver 42A and the second gate driver 42B change the gate line grouping number GN (the number of gate lines GL to which the gate driving signal GATE is simultaneously supplied) from GN=2 to GN=3 in the second area AA2, but the present invention is not limited to this. The first gate driver 42A and the second gate driver 42B may simultaneously scan the gate lines GL with the gate line grouping number GN=2 across the second area AA2, or may scan the gate lines GL with the gate line grouping number GN=3 across the second area AA2. In addition, although FIG. 9 shows a method of scanning the gate lines GL in the second area AA2, the scanning method shown in FIG. 9 can also be applied to the gate lines GL in the third area AA3 (see FIG. 5).

[0091] (Modification) Fig. 10 is a timing chart for explaining a method of scanning a plurality of gate lines in the second region of a display device according to a modified example. As shown in Fig. 10, in the modified example, the first gate driver 42A and the second gate driver 42B simultaneously scan (P x 2) gate lines GL in the second region AA2 (P = 2 in this modified example). That is, the first gate driver 42A and the second gate driver 42B operate in synchronization with each other to simultaneously scan the P gate lines GL connected to the first gate driver 42A and the P gate lines GL connected to the second gate driver 42B.

[0092] More specifically, in the first gate driver 42A and the second gate driver 42B, the start signals ST1 and ST2 go to high potential (H) at time t31. At time t32, the shift clock signals SCK1 and SCK2 go from low potential (L) to high potential (H). At the rising edges of the shift clock signals SCK1 and SCK2, the output signals Q are output from the first register circuit SR1 and the second register circuit SR2, respectively.

[0093] During the period when the shift clock signals SCK1 and SCK2 are at high potential (H), the output control signals GCK1, GCK2, GCK3, and GCK4 are at high potential (H). In response to the output control signals GCK1, GCK2, GCK3, and GCK4, the gate control signals G1, G2, G3, and G4 are at high potential (H).

[0094] At time t33, the shift clock signals SCK1 and SCK2 change from high potential (H) to low potential (L). At the falling edges of the shift clock signals SCK1 and SCK2, the output signals Q are output from the first register circuit SR1 and the second register circuit SR2, respectively.

[0095] While the shift clock signals SCK1 and SCK2 are at low potential (L), the output control signals GCK1, GCK2, GCK3, and GCK4 are at high potential (H). In response to the output control signals GCK1, GCK2, GCK3, and GCK4, the gate control signals G5, G6, G7, and G8 are at high potential (H).

[0096] At time t34, the first gate driver 42A and the second gate driver 42B perform the same operation as in the period from time t32 to time t33 described above, and the gate control signals G9, G10, G11, and G12 become high potential (H).

[0097] As described above, the first gate driver 42A and the second gate driver 42B simultaneously supply the gate drive signal GATE to the four gate lines GL. In this modified example, the combination of the four gate lines GL to which the gate drive signal GATE is simultaneously supplied is P (P=2) gate lines GL connected to a pair of a first register circuit SR1 and a first output circuit OC1, and P (P=2) gate lines GL connected to a pair of a second register circuit SR2 and a second output circuit OC2.

[0098] After time t35, the first gate driver 42A and the second gate driver 42B simultaneously scan three gate lines GL, similar to the scanning method described in FIG. 9. That is, this modified example can be combined with the above-mentioned embodiment. For example, without being limited to the example shown in FIG. 10, two gate lines GL may be simultaneously scanned after a period in which four gate lines GL are simultaneously scanned. Alternatively, one frame period may have a period in which four gate lines GL are simultaneously scanned, a period in which three gate lines GL are simultaneously scanned, and a period in which two gate lines GL are simultaneously scanned, and the number of gate lines GL scanned simultaneously may be sequentially changed.

[0099] In the above-described embodiment and modified example, the gate lines GL are alternately connected to the first gate driver 42A and the second gate driver 42B for every P (P=2) gate lines GL arranged in the second direction Dy, but the present invention is not limited to this. For example, when P=4, that is, four (P=4) gate lines GL may be connected to a set of a first register circuit SR1 and a first output circuit OC1 in the first gate driver 42A, and four (P=4) gate lines GL may be connected to a set of a second register circuit SR2 and a second output circuit OC2 in the second gate driver 42B.

[0100] In this case, the first gate driver 42A and the second gate driver 42B may simultaneously scan three gate lines GL out of the four gate lines GL connected to the first gate driver 42A, and two gate lines GL adjacent to the above three gate lines GL out of the four gate lines GL connected to the second gate driver 42B (i.e., P+1=5 gate lines).

[0101] In other words, in the second region AA2, the first gate driver 42A and the second gate driver 42B simultaneously scan m gate lines GL (m is a natural number and m < P + 1) connected to one of the first gate driver 42A and the second gate driver 42B, and (P + 1 - m) gate lines GL adjacent to the m gate lines GL and connected to the other of the first gate driver 42A and the second gate driver 42B. Thereby, the display device 1 can improve the degree of freedom of the gate lines GL to be scanned simultaneously.

[0102] As described above, the preferred embodiments of the present disclosure have been described, but the present disclosure is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications are possible without departing from the spirit of the present disclosure. Appropriate modifications made without departing from the spirit of the present disclosure also naturally belong to the technical scope of the present disclosure. At least one of various omissions, substitutions, and changes of components can be made without departing from the gist of each of the above-described embodiments and each modification example.

Explanation of Reference Numerals

[0103] 1 Display device 2 Array substrate 3 Counter substrate 6 Liquid crystal layer 12 Power supply circuit 13 Host 21 First substrate 24 Insulating layer 31 Second substrate 32 Color filter 35A, 35B Polarizing plate 40 Driving circuit 41 Driver IC 42 Gate driver 42A First gate driver 42B Second gate driver 43 Signal line selection circuit 44 Register 45 Memory 46 Image signal generation circuit 47 Timing control circuit 48 Control signal generation circuit 49 Light source driving circuit 50 Buffer circuit 51, 53 Clocked inverter 52, 56 Inverter 54, 55 AND circuit AA display area AA1 1st area AA2 2nd area AA3 Third area G, G1, G2, ..., G12 Gate control signals GCK, GCK1, GCK2, GCK3, GCK4 output control signals GATE Gate drive signal GL Gate line SCK, SCK1, SCK2 Shift clock signals SL signal line ST, ST1, ST2 Start signal SR1 First resistor circuit SR2 Second register circuit OC1 First output circuit OC2 Second output circuit

Claims

1. a substrate having a display area; A plurality of pixels provided in the display area and arranged in a first direction and a second direction intersecting the first direction; a plurality of gate lines extending in the first direction and arranged in the second direction; a first gate driver and a second gate driver for supplying gate drive signals to the gate lines; the first gate driver and the second gate driver are provided along the second direction and are arranged side by side in the first direction; The first gate driver and the second gate driver Sequentially scanning the gate lines in a first region of the display region; In a second region of the display region different from the first region, the gate lines adjacent to each other in the second direction are simultaneously scanned. Display device.

2. The plurality of gate lines are alternately connected to the first gate driver and the second gate driver for every P (P is a natural number) gate lines adjacent to each other in the second direction. The display device according to claim 1 .

3. The first gate driver and the second gate driver simultaneously scan a maximum of (P+1) gate lines adjacent to each other in the second direction in the second region. The display device according to claim 2 .

4. In the second region, the first gate driver and the second gate driver simultaneously scan the P gate lines connected to one of the first gate driver and the second gate driver, and one gate line connected to the other of the first gate driver and the second gate driver and adjacent to the P gate lines. The display device according to claim 3 .

5. In the second region, the first gate driver and the second gate driver simultaneously scan m (m is a natural number and m<P+1) gate lines connected to one of the first gate driver and the second gate driver, and (P+1-m) gate lines connected to the other of the first gate driver and the second gate driver and adjacent to the m gate lines. The display device according to claim 2 .

6. The first gate driver and the second gate driver simultaneously scan the P gate lines connected to the first gate driver and the P gate lines connected to the second gate driver in the second region. The display device according to claim 2 .

7. the first gate driver includes a plurality of first register circuits arranged in the second direction, and a plurality of first output circuits provided corresponding to the plurality of first register circuits, respectively; The second gate driver includes a plurality of second register circuits arranged in the second direction, and a plurality of second output circuits provided corresponding to the plurality of second register circuits, respectively. The display device according to claim 1 .

8. the first register circuit includes a clocked inverter and an inverter, and outputs an output signal corresponding to a high potential input signal at a timing based on a shift clock signal; The first output circuit includes P (P is a natural number) AND circuits that generate a logical product of the output signal of the first register circuit and P independent output control signals as a logical value of the gate drive signal and drive P gate lines. The display device according to claim 7.

9. the second register circuit and the second output circuit of the second gate driver have the same configuration as the first register circuit and the first output circuit of the first gate driver, The first gate driver generates a logic value of the gate driving signal based on a shift clock signal and an output control signal different from those of the first gate driver. The display device according to claim 8.

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