Panel level fan-out package structure and manufacturing method

Abstract

To provide a panel level fan-out package structure that meets the fan-out demands of dense I / O devices, solves the heat dissipation problem of high frequency devices, and significantly improves the efficiency of a manufacturing process, and a manufacturing method.SOLUTION: A method includes preparing a frame 400 having a first dielectric layer 301 and a through cavity surrounded by the first dielectric layer. The frame includes a first surface, a second surface, and a heat dissipation copper post 202 that penetrates the first dielectric layer and is exposed to the first surface. An element 500 having a terminal surface flush with the second surface and including a first terminal and a second terminal is mounted in the through cavity, a second dielectric layer 601 is formed on the first surface to cover the element, a first redistribution layer 701 is formed on the second surface to fan out the first terminal, a third dielectric layer 801 is formed on the first redistribution layer, a second redistribution layer 702 is formed on the third dielectric layer to fan out the second terminal, and the second redistribution layer is conductively connected to the first redistribution layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to the field of electronic device technology, and more particularly to a panel level fan-out package structure and manufacturing method. [Background technology]

[0002] With the continuous development of electronic information technology, multi-functionality and miniaturization are the main driving forces of electronic product renewal. In order to realize the multi-functionality of electronic products, the design of main component integrated circuits and package modules becomes more and more complex, and in order to realize the portability of electronic products, the size and thickness of electronic products are required to become smaller and smaller. In view of this, high density integration is an important development trend of semiconductor packages in the future, and fan-out packaging technology is currently a very important advanced packaging technology.

[0003] The currently mature fan-out packaging technology is the wafer-level fan-out package (FOWLP), whose package size is often 6 inches or 8 inches. Although the size of silicon wafers is increasing, expensive materials and manufacturing processes still limit the diameter size to 12 inches, which also limits the number of fan-out units that can be placed on a wafer. 18-inch wafers are attracting wide attention, but the necessary investment, materials and related equipment are still unknown. In addition, the unit cost of FOWLP increases due to the limitation on the number of chip support structures that can be processed simultaneously, making it too expensive for markets that require a competitive list price (e.g. wireless communication, consumer electronics and automotive markets).

[0004] Therefore, there is a need to provide a solution called Fan-Out Panel Level Package (FOPLP), which uses a panel level packaging substrate to realize chip packaging and fan-out, improve packaging efficiency, and reduce processing costs. However, typical panel level packaging substrates lack an effective heat dissipation solution for the panel because they use a substrate mainly made of polymer, and FOPLP lacks the multi-layer manufacturing process capability equivalent to FOWLP, making it difficult to realize fan-out for high-density I / O chips. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of this, it is an object of the present disclosure to provide a panel level fan-out package structure and manufacturing method. [Means for solving the problem]

[0006] Based on the above objective, in a first aspect, the present disclosure provides a method for manufacturing a panel level fan-out package structure, comprising: (a) providing a panel level frame having a first dielectric layer and a through cavity surrounded by the first dielectric layer, the frame including a first surface and a second surface, and a heat dissipating copper post penetrating the first dielectric layer and exposed at the first surface; (b) mounting an element in the through cavity, a terminal surface of the element being flush with the second surface, the terminal surface including a first terminal and a second terminal, and forming a second dielectric layer on the first surface to cover the element; (c) forming a first redistribution layer on the second surface to fan out the first terminals; The method is characterized by including a step (d) of forming a third dielectric layer on the first redistribution layer, forming a second redistribution layer on the third dielectric layer that fans out the second terminal, and the second redistribution layer being conductively connected to the first redistribution layer.

[0007] In some implementations, (f) opening a window in the second dielectric layer to expose the heat dissipation copper post and a backside of the device; The method further includes a step (g) of forming a fourth line layer including a heat dissipation copper surface on the second dielectric layer, the heat dissipation copper surface being conductively connected to the heat dissipation copper post and a rear surface of the element.

[0008] In some implementations, the frame further includes a conductive copper post, and two end surfaces of the conductive copper post are exposed on the first surface and the second surface, respectively; Among them, the manufacturing method is (f') opening a window in the second dielectric layer to expose the conductive copper post, the heat dissipation copper post and the back surface of the element; The method further includes a step (g) of manufacturing a fourth line layer including a functional circuit terminal and a heat dissipation copper surface on the second dielectric layer, wherein the functional circuit terminal is conductively connected to the conductive copper post, and the heat dissipation copper surface is conductively connected to the heat dissipation copper post and a back surface of the element.

[0009] In some implementations, the conductive copper post is further conductively connected to the functional circuit terminal and the first redistribution layer.

[0010] In some implementations, step (a) comprises: a sub-step (a1) of preparing a panel level mounting plate and forming a heat dissipation copper post and an annular sacrificial copper post on the mounting plate, the heat dissipation copper post having a height smaller than that of the sacrificial copper post; a sub-step (a2) of forming the first dielectric layer on the support plate to expose the sacrificial copper post to the first dielectric layer; a sub-step (a3) ​​of removing the support plate; and substep (a4) of etching away the sacrificial copper post to remove the first dielectric layer surrounded by the sacrificial copper post to form a frame having a heat dissipation copper post and a through cavity, the frame having a first surface and a second surface, the heat dissipation copper post being exposed on the first surface.

[0011] In some implementations, step (a) comprises: a sub-step (a1') of preparing a panel level mounting plate and forming a conductive copper post, a heat dissipation copper post and an annular sacrificial copper post on the mounting plate, the heat dissipation copper post having a height smaller than that of the sacrificial copper post and the conductive copper post; a sub-step (a2') of forming the first dielectric layer on the support plate to expose the sacrificial copper post to the first dielectric layer; a sub-step (a3') of removing the support plate; and (a4') a substep of etching and removing the sacrificial copper post to remove the first dielectric layer surrounded by the sacrificial copper post to form a frame having a conductive copper post, a heat dissipation copper post and a through cavity, the frame having a first surface and a second surface, the heat dissipation copper post being exposed on the first surface, and the conductive copper post being exposed on the first surface and the second surface.

[0012] In some implementations, the difference in height between the heat dissipation copper post and the sacrificial copper post is 20 to 50 μm.

[0013] In some implementations, the sacrificial copper post and the conductive copper post are flush with the second surface.

[0014] In some implementations, step (d) comprises: A sub-step (d1) of opening a window in the third dielectric layer by exposure and development to expose the second terminal of the element and the first redistribution layer; (d2) forming a third metal seed layer on a surface of the third dielectric layer; (d3) applying a third photoresist layer to the third metal seed layer and patterning the third photoresist layer to form a third feature pattern; (d4) forming a second redistribution layer by electroplating the third feature pattern to fan out the second terminals and electrically connect them to the first redistribution layer; and (d5) removing the third photoresist layer and etching the exposed third metal seed layer.

[0015] In some implementations, the manufacturing method includes: The method further includes a step (e) of forming a fourth dielectric layer on the second redistribution layer, fabricating a third redistribution layer on the fourth dielectric layer, and the third redistribution layer being conductively connected to the second redistribution layer.

[0016] In some implementations, the heat dissipating copper post comprises all of the frame except the cavity and is separated from the cavity by the first dielectric layer, and the heat dissipating copper plane covers a second surface of the frame.

[0017] In some implementations, the heat dissipating copper post forms a frame for all but the cavity and the conductive copper post and is separated from the cavity and the conductive copper post by the first dielectric layer, and the heat dissipating copper surface covers the second surface other than the functional circuit terminals.

[0018] In a second aspect, an embodiment of the present disclosure provides a panel level fan-out package structure, comprising: a frame; and an element embedded in the frame, the frame comprising a heat dissipation copper post and a first dielectric layer separating the heat dissipation copper post and the element, wherein the frame has opposing first and second surfaces, and a first redistribution layer, a third dielectric layer and a second redistribution layer are disposed on the second surface, in that order, the first redistribution layer and the second redistribution layer are conductively connected to each other to fan out a first terminal and a second terminal of the element, and the first redistribution layer is conductively connected to the second redistribution layer.

[0019] In some implementations, the method further includes a fourth dielectric layer in the second redistribution layer and a third redistribution layer in the fourth dielectric layer, the third redistribution layer being conductively connected to the second redistribution layer.

[0020] In some implementations, the frame further includes a second dielectric layer installed on a first surface of the frame and a fourth line layer in the second dielectric layer, wherein the fourth line layer includes a heat dissipation copper surface, the heat dissipation copper surface is conductively connected to the heat dissipation copper post and the rear surface of the element, and the heat dissipation copper surface covers the first surface.

[0021] In some implementations, the frame further includes a conductive copper post separated from the heat dissipation copper post by the first dielectric layer, a second dielectric layer disposed on a first surface of the frame, and a fourth line layer in the second dielectric layer, the fourth line layer including a functional circuit terminal and a heat dissipation copper surface, wherein the heat dissipation copper surface is conductively connected to the heat dissipation copper post and a rear surface of the element, the heat dissipation copper surface covers the first surface except for the functional circuit terminal, and both ends of the conductive copper post are conductively connected to the functional circuit terminal and the first redistribution layer, respectively. Effect of the Invention

[0022] As can be seen from the above, the panel level fan-out package structure and manufacturing method provided in the embodiments of the present disclosure realizes fan-out and epitaxial growth of dense I / O of devices by fanning out multiple terminals of a device embedded in a metal frame in several times, solving the problem that the traditional panel level fan-out package manufacturing process capacity cannot meet the fan-out demand of dense I / O devices, and by installing a large-area heat dissipation copper post and a heat dissipation copper surface that are conductively connected to the back surface of the device, the heat dissipation problem of high frequency devices is solved, and by forming a height difference between the heat dissipation copper post, the conductive copper post and the sacrificial copper post, there is no need to polish the heat dissipation copper post after etching and removing the sacrificial copper post, which saves technology in the manufacturing process and significantly improves the efficiency of the manufacturing process. [Brief description of the drawings]

[0023] In order to more clearly describe the technical solutions in the present disclosure or related technologies, the following briefly introduces drawings that need to be used in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only embodiments of the present disclosure, and those skilled in the art can further obtain other drawings based on these drawings without making any creative efforts. [Figure 1(a)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(aa)] FIG. 1(b) is a plan view of FIG. [Figure 1(b)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(c)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(d)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(e)]1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(f)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(g)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(h)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(i)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 1(j)] 1A-1D show schematic cross-sectional views of intermediate structures at various steps in a manufacturing method of a panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Diagram 2] 1 shows a schematic diagram of a panel level fan-out package structure provided in an embodiment of the present disclosure. [Figure 3(a)] 1A-1C show schematic cross-sectional views of intermediate structures at some steps of a manufacturing method for another panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 3(b)] 1A-1C show schematic cross-sectional views of intermediate structures at some steps of a manufacturing method for another panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 3(c)] 1A-1C show schematic cross-sectional views of intermediate structures at some steps of a manufacturing method for another panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 3(d)] 1A-1C show schematic cross-sectional views of intermediate structures at some steps of a manufacturing method for another panel level fan-out packaging structure provided in an embodiment of the present disclosure. [Figure 4] 1 shows a schematic diagram of another panel level fan-out package structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail hereinafter in conjunction with specific embodiments and with reference to the drawings.

[0025] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the common meaning understood by a person of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate order, number, or importance, but are used to distinguish different components. Similar words such as "include" or "include" mean that the part or item appearing before the word covers the part or item listed after the word and the like, and does not exclude other parts or items. Similar words such as "connect" or "connect" are not limited to physical or mechanical connections, but can include electrical connections, which may be direct or indirect. "Top", "bottom", "left", "right", etc. are intended to indicate relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0026] An exemplary embodiment of the present disclosure provides a method for manufacturing a panel level fan-out packaging structure. Figures 1(a)-1(j) show schematic cross-sectional views of intermediate structures in each step of a method for manufacturing a panel level fan-out packaging structure according to one embodiment of the present invention. Specifically, the method includes the following steps:

[0027] As shown in FIG. 1(a), a panel level support plate 100 is prepared, and a conductive copper post 201, a heat dissipation copper post 202, and a sacrificial copper post 203 are formed on the support plate 100--step (a). The panel level support plate 100 may be circular or rectangular, for example, rectangular or square. The dimensions of the panel level support plate 100 can be selected according to actual requirements, for example, 300 mm×300 mm, 510 mm×515 mm, or 600 mm×600 mm. Here, a first metal seed layer 101 can be formed on the support plate 100 in advance, for example, the first metal seed layer 101 can be manufactured on the support plate 100 by using a metal sputtering method. The material of the first metal seed layer 101 can be copper, titanium, or a combination thereof, and a combination of copper and titanium is preferred.

[0028] In some embodiments, the specific steps of forming the conductive copper post 201, the heat dissipation copper post 202, and the sacrificial copper post 203 may be to first fabricate a circuit pattern on the first metal seed layer 101, then electroplate the circuit pattern, and finally peel off the film.

[0029] Optionally, the sacrificial copper post 203 is selected from a ring structure or a continuous columnar wall structure. FIG. 1(aa) is a plan view of the structure shown in FIG. 1(a). FIG. 1(aa) exemplarily shows that the sacrificial copper post 203 has a continuous columnar wall structure. Here, in a subsequent step, the sacrificial copper post 203 is etched and removed, so that the first dielectric layer surrounded by the sacrificial copper post 203 is removed to form a through cavity, and it is easy to install an element in the subsequent through cavity.

[0030] It should be noted that the number of sacrificial copper posts 203 is not limited to one, but can be limited based on the number of packaged elements (eg, chips) required and the panel area, and the present disclosure does not limit this.

[0031] The conventional FOPLP solution lacks an effective heat dissipation solution. In view of this, in the embodiment of the present disclosure, a large-area heat dissipation copper post (heat dissipation block) 202 is provided. Note that, in general, after avoiding the sacrificial copper post 203 and the conductive copper post 201, the heat dissipation copper post 202 with the largest area can be provided to improve the heat dissipation effect. It should be understood that if the heat dissipation function is not considered, the heat dissipation copper post 202 does not need to be manufactured.

[0032] Optionally, the thickness (corresponding height) of the heat dissipating copper post 202 is controlled to be smaller than the thicknesses (corresponding heights) of the conductive copper post 201 and the sacrificial copper post 203 during electroplating. For example, the height of the heat dissipating copper post 202 can be 20 to 50 μm smaller than the heights of the conductive copper post 201 and the sacrificial copper post 203. Optionally, the conductive copper post 201 and the sacrificial copper post 203 have approximately the same height, thereby exposing the conductive copper post 201 to the first surface and the second surface of the frame.

[0033] Here, the conductive copper posts 201 are used to make a conductive connection to the flip-chip device 1001 when packaging the device 1001 on the surface of the panel level fan-out packaging structure 1000 (see FIG. 1(j)). It should be understood that if the panel level fan-out packaging structure 1000 does not require the flip-chip device 1001, the conductive copper posts 201 can be omitted (as shown in FIG. 4).

[0034] 1(b), a first dielectric material is applied to form a first dielectric layer 301, and the first dielectric layer 301 exposes the end faces of the sacrificial copper post 203 and the conductive copper post 201--step (b). Here, the height of the heat dissipation copper post 202 is smaller than that of the sacrificial copper post 203 and the conductive copper post 201, so that the heat dissipation copper post 202 is still covered by the first dielectric layer 301.

[0035] In some embodiments, the manner of applying the first dielectric material may be a process such as conventional pressure welding, vacuum high speed pressure welding, painting, etc., until the first dielectric material completely covers the conductive copper post 201, the heat dissipation copper post 202, and the sacrificial copper post 203. Then, the first dielectric material is thinned to form the first dielectric layer 301. Here, the thinning process may adopt a process such as a polishing plate, plasma etching, etc., to expose the end faces of the sacrificial copper post 203 and the conductive copper post 201. The height of the heat dissipation copper post 202 is smaller than the height of the conductive copper post 201 and the sacrificial copper post 203, so that the heat dissipation copper post 202 does not need to be thinned by a polishing plate, which greatly improves the processing efficiency.

[0036] Optionally, the first dielectric material may be a polymer dielectric material containing glass fiber, which contributes to ensuring the strength and rigidity of the substrate. Exemplarily, the polymer dielectric material containing glass fiber is selected from one of the group consisting of liquid crystal polymer, BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, and polyimide resin, but the present invention is not limited thereto.

[0037] 1(c), the mounting plate is removed—step (c), where the mounting plate removal includes removing the mounting plate 100 and etching the exposed metal seed layer 101.

[0038] Next, as shown in FIG. 1(d), the sacrificial copper post 203 is etched away to remove the dielectric material surrounded by the sacrificial copper post 203, thereby forming a frame 400 having a conductive copper post 201, a heat dissipation copper post 202 and a through cavity 401 - step (d).

[0039] In some embodiments, the frame 400 includes a first surface 402 and a second surface 403 , and the heat dissipating copper posts 202 are exposed on the first surface 402 and not exposed on the second surface 403 .

[0040] The specific form of etching and removing the sacrificial copper posts 203 is described in the exemplary embodiment of the present disclosure as follows: First, a first photoresist layer is applied to fabricate a first feature pattern of the sacrificial copper posts 203, then etching is performed, and after etching and removing the sacrificial copper posts 203, the film is peeled off to remove the photoresist, and the frame 400 shown in FIG.

[0041] Next, as shown in FIG. 1(e), the element 500 is mounted in the through cavity, with the terminal surface of the element being flush with the second surface 403, and a second dielectric material is applied to the first surface 402 of the packaged element 500 to form a second dielectric layer 601 - step (e).

[0042] The element 500 may be an IC chip, a logic circuit component, a power amplifier, a capacitor, an inductor, a resistor, etc., and the present disclosure is not limited thereto. The terminal surface of the element 500 includes at least a first terminal 501 and a second terminal 502.

[0043] In some embodiments, an adhesive dielectric layer can be formed on the second surface 403, which has adhesiveness at room temperature or when heated, and can adhere the device. The adhesive dielectric layer can be formed by pressing a dielectric material having a dry film type coating function. The element 500 is then placed in the through cavity and bonded to the adhesive dielectric layer. Whether or not to heat the adhesive dielectric layer during bonding can be selected based on the adhesiveness of the adhesive dielectric layer, for example, the element can be heated when the adhesiveness is low. The adhesive dielectric layer can be removed after the second dielectric layer 601 is formed.

[0044] Optionally, the second dielectric material may be the same as or different from the first dielectric material.

[0045] Next, as shown in FIG. 1(f), a first redistribution layer 701 is fabricated on the second surface 403 and fanned out to the first terminal 501 of the element 500 - step (f).

[0046] In some embodiments, the steps of manufacturing the first redistribution layer 701 may include: first, forming a second metal seed layer on the second surface 403, then applying a second photoresist layer to the second metal seed layer, patterning the second photoresist layer to form a second feature pattern, then electroplating the second feature pattern to form a first redistribution layer that fans out the first terminal, and finally removing the second photoresist layer and etching the exposed second metal seed layer. Here, the material of the second metal seed layer is similar to the material of the first metal seed layer, so the description is omitted. Optionally, the material of the first redistribution layer may be copper.

[0047] 1(g), a third dielectric material is applied to the first redistribution layer to form a third dielectric layer 801, and a second redistribution layer 702 is fabricated on the third dielectric layer, and the second redistribution layer 702 fans out the second terminal 502 of the element and connects it to the first redistribution layer 701 - step (g). Note that the second redistribution layer 702 can simultaneously play the role of epitaxially growing the first redistribution layer.

[0048] In some embodiments, the third dielectric material may be a photosensitive dielectric material with high resolution capability, which aids in the subsequent opening of micro-vias.

[0049] In some embodiments, a third dielectric material is applied to the first redistribution layer by a process such as pressing, coating, etc., and then the third dielectric material is locally removed by exposure and development to expose the second terminal of the element and a part of the first redistribution layer, and finally the third dielectric layer 801 is hardened to form.

[0050] In some embodiments, the step of fabricating the second redistribution layer 702 may include: forming a third metal seed layer on the surface of the third dielectric layer 801, applying a third photoresist layer to the third metal seed layer, patterning the third photoresist layer to form a third feature pattern, electroplating the third feature pattern to form a second redistribution layer that fans out the second terminals and connects to the first redistribution layer, removing the third photoresist layer, and etching the exposed third metal seed layer.

[0051] As can be seen from the above, the technical solution of the embodiment of the present disclosure adopts a technology of fanning out element terminals in several stages, which can realize rational wiring of highly dense I / O element fan-out, effectively reduce the horizontal wiring space, and solve the technical problem that the traditional FOPLP has difficulty in realizing highly dense I / O element fan-out.

[0052] 1(h), a fourth dielectric material is applied to the second redistribution layer 702 to form a fourth dielectric layer 802, and a third redistribution layer 703 is fabricated on the fourth dielectric layer 802, and the third redistribution layer 703 is connected to the second redistribution layer 702 - step (h). Note that the third redistribution layer 703 can be epitaxially formed on the second redistribution layer 702.

[0053] The manufacturing processes of the fourth dielectric layer 802 and the third redistribution layer 703 refer to the third dielectric layer 801 and the second redistribution layer 702, and the description thereof will be omitted.

[0054] 1(i), a window is opened in the second dielectric layer 601 (i.e., the package layer of the element 500) to expose the conductive copper post 201, the heat dissipation copper post 202, and the back surface of the element 500, and a fourth line layer 901 including a functional circuit terminal 9011 and a heat dissipation copper surface 9012 is manufactured in the second dielectric layer 601 after the window is opened, thereby obtaining an element fan-out package structure 1000 - step (i). Note that the heat dissipation copper surface 9012 is connected to the heat dissipation copper post 202 and the back surface of the element 500, and the functional circuit terminal 9011 is connected to the conductive copper post 201. The heat dissipation copper surface 9012 can cover almost the entire first surface of the frame, and if there is a conductive copper post 201, it is only necessary to expose the functional circuit terminal 9011. The large-area heat dissipation copper posts 202 and the heat dissipation copper plane 9012 help to realize large-area direct heat dissipation, and significantly improve the heat dissipation capability of the package structure 1000 .

[0055] The manufacturing process of the fourth line layer 901 can refer to the third redistribution layer, and the description will be omitted.

[0056] 1(j), the functional circuit terminals 9011 can be realized as upper pads in the package to realize conductive connection to another element or the package body 1001, and the third redistribution layer 703 can be realized as lower pads to realize conductive connection to the substrate or PCB board 1002--step (j). Note that the other element 1001 may be an IC chip.

[0057] An exemplary embodiment of the present disclosure provides a method for manufacturing another panel level fan-out package structure. Figures 3(a)-3(d) show schematic cross-sectional views of intermediate structures in some steps of the method for manufacturing another panel level fan-out package structure in one embodiment of the present disclosure. The difference between the package structures manufactured in Figures 3(a)-(d) and Figures 1(a)-(j) is that they do not include a conductive copper post 201. Specifically, the manufacturing method includes the following steps:

[0058] As shown in FIG. 3(a), a frame 400' having a heat dissipation copper post 202' and a through cavity 401' is prepared--step (a'). For the specific process of step (a'), refer to steps (a) to (d). Since the frame 400' does not include the conductive copper post 201, the heat dissipation copper post 202' can have a larger area, which is more advantageous for heat dissipation. The frame 400' is similar to the frame 400, and includes a first surface 402' and a second surface 403'. Among them, the heat dissipation copper post 202' is exposed to the first surface 402' and is enclosed within the second surface 403'.

[0059] Next, as shown in Fig. 3(b), referring to the process of steps (d) to (h), a first redistribution layer, a third dielectric layer, a second redistribution layer, a fourth dielectric layer and a third redistribution layer are manufactured (step (b'). Step (b') realizes fanning out the element terminals in several steps.

[0060] 3(c), referring to step (j), a fourth line layer 901' is manufactured to obtain a panel level fan-out package structure 1000'--step (c'). The fourth line layer 901' includes a heat dissipation copper post and a heat dissipation copper surface covering almost the entire first surface connecting the back surface of the device, which can realize a large area of ​​direct heat dissipation. Since there is no conductive copper post, the area of ​​the heat dissipation copper post and the heat dissipation copper surface is larger, which is more helpful for heat dissipation.

[0061] Finally, as shown in Figure 3(d), the third redistribution layer 703 can be used to form pads to conductively connect the fan-out package structure 1000' to a substrate or PCB board 1002' - step (d'). Note that due to the absence of conductive copper posts, a double-sided package cannot be realized.

[0062] Based on a similar inventive concept, an embodiment of the present disclosure further provides a panel level fan-out packaging structure.Referring to FIG.2, a cross-sectional schematic diagram of a panel level fan-out packaging structure 1000 provided in an embodiment of the present disclosure is shown.

[0063] Specifically, the panel level fan-out package structure 1000 includes a frame 400, a device 500, a first redistribution layer 701, a third dielectric layer 801, a second redistribution layer 702, a fourth dielectric layer 802, and a third redistribution layer 703. The device 500 is installed on the frame 400, and the first redistribution layer 701, the third dielectric layer 801, the second redistribution layer 702, the fourth dielectric layer 802, and the third redistribution layer 703 are installed in order on a second surface of the frame 400, the first redistribution layer 701 and the second redistribution layer 702 are respectively connected to the first terminal and the second terminal of the device 500, the first redistribution layer 701 is connected to the second redistribution layer 702, and the second redistribution layer 702 is connected to the third redistribution layer 703. With this structure, the first terminal and the second terminal of the element 500 are fanned out in several stages, which realizes rational wiring for high-density I / O element terminal fan-out and reduces the horizontal wiring space.

[0064] In some embodiments, the second dielectric layer 601 and the fourth line layer 901 are disposed on the first surface of the frame 400, the fourth line layer 901 includes a functional circuit terminal 9011 and a heat dissipation copper surface 9012, the heat dissipation copper surface 9012 is connected to the rear surface of the element 500 and the heat dissipation copper post 202, and both ends of the conductive copper post 201 in the frame 400 are respectively connected to the functional circuit terminal 9011 and the first redistribution layer 701. As shown in FIG. 1(j), the heat dissipation copper surface 9012 can be used to realize large-area heat dissipation, and the conductive copper post 201 and the functional circuit terminal 9011 can be used to electrically connect to another element or the package body.

[0065] An embodiment of the present disclosure provides yet another panel level fan-out packaging structure.Referring to FIG.4, a cross-sectional schematic diagram of another panel level fan-out packaging structure 1000' provided in an embodiment of the present disclosure is shown.

[0066] Similar to the panel level fan-out package structure 1000, the panel level fan-out package structure 1000' also uses a first redistribution layer 701', a second redistribution layer 702' and a third redistribution layer 703' to realize fanning out the device terminals in several stages. The difference between the panel level fan-out package structure 1000' and the panel level fan-out package structure 1000 is that the frame does not include the conductive copper post 201, so the fourth line layer 901' includes a heat dissipation copper surface connecting the back surface of the device 500 and the heat dissipation copper post 202, but does not include a functional circuit terminal.

[0067] The panel level fan-out package structure of the above embodiment has beneficial effects of the corresponding method embodiment, and the description is omitted here.

[0068] As will be understood by those skilled in the art, the discussion of any of the above embodiments is merely illustrative, and does not imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, combinations can be made between the technical features of the above embodiments or different embodiments, steps can be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure described above, which will not be described in detail for clarity.

[0069] The embodiments of the present disclosure are intended to embrace all such replacements, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the protection scope of the present disclosure. [Explanation of symbols]

[0070] 100 mounting plate, panel level mounting plate, 101 first metal seed layer, metal seed layer, 201 conductive copper post, 202 heat dissipation copper post, 202' heat dissipation copper post, 203 sacrificial copper post, 301 first dielectric layer, 400 frame, 400' frame, 401 through cavity, 401' through cavity, 402 first surface, 402' first surface, 403 second surface, 403' second surface, 500 second dielectric material package element, element, 501 first terminal, 502 second terminal, 601 second dielectric layer, 701 first redistribution layer, 701' first redistribution layer, 702 second redistribution layer, 702' second redistribution layer, 703 third redistribution layer, 703' third redistribution layer, 801 third dielectric layer, 802 Fourth dielectric layer, 901 Fourth line layer, 901' Fourth line layer, 1000 Panel level fan-out package structure, element fan-out package structure, package structure, 1000' Panel level fan-out package structure, fan-out package structure, 1001 Package body, flip chip element, element, 1002 PCB board, 1002' PCB board, 9011 Functional circuit terminal, 9012 Heat dissipation copper surface

Claims

1. (a) providing a panel level frame having a first dielectric layer and a through cavity surrounded by the first dielectric layer, the frame including a first surface and a second surface, and a heat dissipating copper post passing through the first dielectric layer and exposed at the first surface; (b) mounting an element in the through cavity, a terminal surface of the element being flush with the second surface, the terminal surface including a first terminal and a second terminal, and forming a second dielectric layer on the first surface to cover the element; (c) forming a first redistribution layer on the second surface to fan out the first terminals; and (d) forming a third dielectric layer on the first redistribution layer, and forming a second redistribution layer on the third dielectric layer to fan out the second terminal, the second redistribution layer being conductively connected to the first redistribution layer.

2. (f) opening a window in the second dielectric layer to expose the heat dissipation copper post and a backside of the device; 2. The manufacturing method according to claim 1, further comprising: a step (g) of forming a fourth line layer including a heat dissipation copper surface on the second dielectric layer, the heat dissipation copper surface being conductively connected to the heat dissipation copper post and a rear surface of the element.

3. The frame further includes a conductive copper post, and two end surfaces of the conductive copper post are exposed on the first surface and the second surface, respectively; Among them, the manufacturing method is (f') opening a window in the second dielectric layer to expose the conductive copper post, the heat dissipation copper post and the back surface of the element; 2. The manufacturing method according to claim 1, further comprising: a step (g') of manufacturing a fourth line layer including a functional circuit terminal and a heat dissipation copper surface on the second dielectric layer, the functional circuit terminal being conductively connected to the conductive copper post, and the heat dissipation copper surface being conductively connected to the heat dissipation copper post and a rear surface of the element.

4. 4. The method according to claim 3, wherein the conductive copper post is further conductively connected to the functional circuit terminal and the first rewiring layer.

5. Step (a) a sub-step (a1) of preparing a panel level mounting plate and forming a heat dissipation copper post and an annular sacrificial copper post on the mounting plate, the heat dissipation copper post having a height smaller than that of the sacrificial copper post; a sub-step (a2) of forming the first dielectric layer on the support plate to expose the sacrificial copper post to the first dielectric layer; a sub-step (a3) ​​of removing the support plate; and (a4) a sub-step of etching away the sacrificial copper post to remove a first dielectric layer surrounded by the sacrificial copper post to form a frame having a heat dissipation copper post and a through cavity, the frame including a first surface and a second surface, the heat dissipation copper post being exposed at the first surface.

6. Step (a) a sub-step (a1') of preparing a panel level mounting plate and forming a conductive copper post, a heat dissipation copper post and an annular sacrificial copper post on the mounting plate, the heat dissipation copper post having a height smaller than that of the sacrificial copper post and the conductive copper post; a sub-step (a2′) of forming the first dielectric layer on the support plate to expose the sacrificial copper post to the first dielectric layer; a sub-step (a3′) of removing the support plate; and a sub-step (a4') of etching and removing the sacrificial copper post to remove a first dielectric layer surrounded by the sacrificial copper post to form a frame having a conductive copper post, a heat dissipation copper post and a through cavity, the frame having a first surface and a second surface, the heat dissipation copper post being exposed on the first surface, and the conductive copper post being exposed on the first surface and the second surface.

7. 7. The method according to claim 5, wherein the difference in height between the heat dissipation copper post and the sacrificial copper post is 20 to 50 μm.

8. The method of claim 6 , wherein the sacrificial copper post and the conductive copper post are flush with the second surface.

9. Step (d) A sub-step (d1) of opening a window in the third dielectric layer by exposure and development to expose the second terminal of the element and the first redistribution layer; a substep (d2) of forming a third metal seed layer on a surface of the third dielectric layer; (d3) applying a third photoresist layer to the third metal seed layer and patterning the third photoresist layer to form a third feature pattern; a sub-step (d4) of electroplating the third feature pattern to form a second redistribution layer that fans out the second terminals and electrically connects them to the first redistribution layer; 2. The method of claim 1, further comprising the substep (d5) of removing the third photoresist layer and etching the exposed third metal seed layer.

10. 2. The method of claim 1, further comprising the step (e) of forming a fourth dielectric layer on the second redistribution layer, and fabricating a third redistribution layer on the fourth dielectric layer, the third redistribution layer being conductively connected to the second redistribution layer.

11. 3. The method of claim 2, wherein the heat dissipating copper post constitutes the entire frame except for the cavity and is separated from the cavity by the first dielectric layer, and the heat dissipating copper plane covers a second surface of the frame.

12. 4. The manufacturing method according to claim 3, wherein the heat dissipation copper post constitutes a frame for all parts other than the cavity and the conductive copper post, and is separated from the cavity and the conductive copper post by the first dielectric layer, and the heat dissipation copper surface covers the second surface other than the functional circuit terminals.

13. 1. A panel level fan-out package structure comprising: a frame; and a device embedded in the frame, the frame including a heat dissipation copper post and a first dielectric layer separating the heat dissipation copper post and the device, wherein the frame has opposing first and second surfaces, a first redistribution layer, a third dielectric layer and a second redistribution layer are disposed on the second surface in that order, the first redistribution layer and the second redistribution layer are conductively connected to each other to fan out a first terminal and a second terminal of the device, and the first redistribution layer is conductively connected to the second redistribution layer.

14. 14. The package structure of claim 13, further comprising a fourth dielectric layer in the second redistribution layer and a third redistribution layer in the fourth dielectric layer, the third redistribution layer being conductively connected to the second redistribution layer.

15. 14. The package structure of claim 13, further comprising a second dielectric layer disposed on a first surface of the frame and a fourth line layer in the second dielectric layer, wherein the fourth line layer includes a heat dissipation copper surface, the heat dissipation copper surface is conductively connected to the heat dissipation copper post and a rear surface of the element, and the heat dissipation copper surface covers the first surface.

16. 14. The package structure of claim 13, wherein the frame further includes a conductive copper post separated from the heat dissipation copper post by the first dielectric layer, a second dielectric layer disposed on a first surface of the frame, and a fourth line layer in the second dielectric layer, the fourth line layer including a functional circuit terminal and a heat dissipation copper surface, the heat dissipation copper surface being conductively connected to the heat dissipation copper post and a rear surface of the element, the heat dissipation copper surface covering the first surface except for the functional circuit terminal, and both ends of the conductive copper post being conductively connected to the functional circuit terminal and the first redistribution layer, respectively.

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