Semiconductor device

Abstract

To provide a semiconductor device with adjustable height of semiconductor elements and excellent electrical characteristics.SOLUTION: A semiconductor device comprises a support layer, a first semiconductor element provided above the support layer, a second semiconductor element provided above the support layer, and an insulator provided above the support layer and in which at least a portion of the first semiconductor element and at least a portion of the second semiconductor element are embedded, and the support layer has a first convex portion at least partially embedded in the insulator below the first semiconductor element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device in which at least a portion of a semiconductor element is embedded in an insulator. [Background technology]

[0002] In recent years, modules in which semiconductor elements are embedded in an insulating layer around a printed circuit board as a core have been considered.

[0003] Patent document 1 describes a multilayer wiring board having a wiring board in which wiring layers and insulating layers are laminated, an electronic component having a plurality of electrodes arranged at a predetermined pitch and bumps formed on the plurality of electrodes, and lands for connecting the bumps to wiring of an upper layer circuit, wherein each of the plurality of bumps has a flat surface on the upper part, and each flat surface is directly connected to a plurality of lands.

[0004] Patent document 2 describes an electronic component-embedded substrate comprising a resin substrate, a semiconductor device placed on the surface of the resin substrate with its back surface facing the resin substrate, an insulating layer covering the semiconductor device, at least one via conductor embedded inside the insulating layer, and a wiring pattern electrically connected to any of the via conductors, the semiconductor device having an electric circuit and at least one terminal exposed on its main surface and electrically connected to the electric circuit, and both a non-terminal region of the main surface where the at least one first terminal is not exposed and the back surface are roughened.

[0005] It should be noted that the Background section is provided to provide embodiments of the present disclosure in a technical or operational context to aid those skilled in the art in understanding the scope and usefulness of the present disclosure. Unless expressly specified, no statement in this specification is admitted to be prior art merely by being included in the Background section. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-124260 A [Patent Document 2] Patent No. 5903973 Summary of the Invention

[0007] The following presents a simplified summary of the present disclosure to provide a basic understanding to those skilled in the art. This summary is not intended to identify key elements of the embodiments of the present disclosure or to delineate the scope of the present disclosure. The purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description presented later. [Problem to be solved by the invention]

[0008] An object of the present disclosure is to provide a semiconductor device that is capable of adjusting the height of a semiconductor element and has excellent electrical characteristics. [Means for solving the problem]

[0009] In order to solve the above problems, a semiconductor device according to one embodiment of the present disclosure comprises a support layer, a first semiconductor element provided above the support layer, a second semiconductor element provided above the support layer, and an insulator provided above the support layer and in which at least a portion of the first semiconductor element and at least a portion of the second semiconductor element are embedded, wherein the support layer has a first convex portion, at least a portion of which is embedded in the insulator below the first semiconductor element. Effect of the Invention

[0010] In the semiconductor device according to the embodiment of the present disclosure, the height of the semiconductor element can be adjusted, and electrical characteristics can be improved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 2A] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 2B] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 2C] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 2D] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 2E] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 2F] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 2G] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Diagram 3] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 4] 2C for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. FIG. [Diagram 5] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 6] 2C for explaining a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. FIG. [Figure 7] 1 is a block diagram illustrating an example of a control system that employs a semiconductor device according to an embodiment of the present disclosure. [Figure 8] 1 is a circuit diagram illustrating an example of a control system that employs a semiconductor device according to an embodiment of the present disclosure. [Figure 9] FIG. 11 is a block diagram showing another example of a control system employing the semiconductor device according to the embodiment of the present disclosure. [Figure 10] FIG. 11 is a circuit diagram illustrating another example of a control system employing the semiconductor device according to the embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The embodiments of the present disclosure and various features and advantageous details thereof are described and / or illustrated with the drawings and are more particularly described with reference to the non-limiting embodiments and examples described herein below. As will be apparent to one skilled in the art, features shown in the drawings are not necessarily drawn to scale, even if not described herein. It should also be noted that a feature in one embodiment may be used alone or in combination with other features in another embodiment. Descriptions of well-known elements and processing techniques may be omitted so as not to unnecessarily obscure the embodiments of the present disclosure. The examples used herein are merely intended to aid in the understanding of the present disclosure and further enable those skilled in the art to practice the embodiments of the present disclosure. Thus, the embodiments and examples herein should not be construed as limiting the scope of the present disclosure, which is defined only by the claims and applicable law. Moreover, in the drawings of the present disclosure, like reference numerals represent like parts.

[0013] Terms such as "first", "second" and "third" are used to describe various elements used herein, but the elements are not limited by these terms. Terms such as "first", "second" and "third" are used only to distinguish one element from another element. For example, a first element can be referred to as a second element and a second element can be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any or all combinations of one or more of the listed items.

[0014] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used in this specification, "comprises" and "includes" refer to the presence of the described elements but do not exclude the presence of one or more other elements.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein are interpreted to have a meaning that is not inconsistent with the meaning in the context of this specification and the related art. In addition, unless defined herein, it should be understood that terms used herein should not be interpreted in an idealized or overly formal sense.

[0016] (First embodiment) FIG. 1 is a cross-sectional view showing a schematic diagram of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 includes a support layer 2, a first semiconductor element 3, a second semiconductor element 4, and an insulator 5. In the present disclosure, the thickness direction of the support layer 2 is defined as the "vertical direction". The direction from the support layer 2 toward the first semiconductor element 3 is defined as the "upper direction". The direction from the support layer 2 toward the opposite side of the first semiconductor element 3 is defined as the "lower direction". The surface of an element facing upward or diagonally upward is defined as the "upper surface". The surface of an element facing downward or diagonally downward is referred to as the "lower surface". These "upper" and "lower" directions do not limit the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0017] Each of the first semiconductor element 3, the second semiconductor element 4, and the insulator 5 is provided above the support layer 2. Each of the first semiconductor element 3, the second semiconductor element 4, and the insulator 5 is supported by the support layer 2. At least a part of the first semiconductor element 3 and at least a part of the second semiconductor element 4 are embedded in the insulator 5. The semiconductor device 100 may further include a first wiring layer 1 located above the insulator 5. The semiconductor device 100 may further include a first connection portion 7a and a second connection portion 7b that electrically connect the first wiring layer 1 and the first semiconductor element 3. The semiconductor device 100 may further include a metal block 10 that electrically connects the first wiring layer 1 and the support layer 2. The semiconductor device 100 may further include a first insulating protection layer 9a that protects the first wiring layer 1. The semiconductor device 100 may further include a second insulating protection layer 9b that protects the support layer 2.

[0018] The support layer 2 has, for example, a second wiring layer 21. The second wiring layer 21 is an example of a wiring layer. The support layer 2 may further have a third connection portion 7c that electrically connects the second wiring layer 21 and the first semiconductor element 3. The third connection portion 7c is an example of a connection portion. The support layer 2 may further have a fourth connection portion 7d that electrically connects the second wiring layer 21 and the second semiconductor element 4.

[0019] Examples of the material of the second wiring layer 21 include Cu, Au, Al, Ag, Fe, Ti, Ni, Pt, Pd, and alloys of two or more of these metals (which may contain other metals). The material of the second wiring layer 21 is preferably Cu. The material of the second wiring layer 21 is not limited as long as it is a conductive material.

[0020] The constituent material of each of the third connection portion 7c and the fourth connection portion 7d may be the same as or different from the constituent material of the second wiring layer 21. Examples of the constituent material of each of the third connection portion 7c and the fourth connection portion 7d include Cu, Au, Al, Ag, Fe, Ti, Ni, Pt, Pd, or an alloy of two or more of these (which may contain other metals), or a conductive resin paste. Each of the third connection portion 7c and the fourth connection portion 7d is preferably Cu or a Cu alloy. The constituent material of each of the third connection portion 7c and the fourth connection portion 7d is not limited as long as it is a material having conductivity. Each of the third connection portion 7c and the fourth connection portion 7d may be formed integrally with the second wiring layer 21, or may be connected to the second wiring layer 21 via another member. In the present disclosure, "formed integrally" means that two members are directly connected without the intervention of another member such as an adhesive, and includes not only the case where the materials of the two members are the same, but also the case where the materials of the two members are different from each other. Each of the third connection portion 7c and the fourth connection portion 7d may have a multi-layer structure in order to increase the adhesive strength with the second wiring layer 21, the first semiconductor element 3, or the second semiconductor element 4.

[0021] The first semiconductor element 3 is disposed on the support layer 2. The first semiconductor element 3 is, for example, a transistor. In this example, the first semiconductor element 3 is an IGBT (insulated gate bipolar transistor). The first semiconductor element 3 may be a transistor other than an IGBT. The other transistor is, for example, a MOSFET (metal oxide semiconductor field effect transistor). The first semiconductor element 3 may be a semiconductor element other than a transistor. The other semiconductor element is, for example, a diode.

[0022] The first semiconductor element 3 has a semiconductor layer 3a and a plurality of electrodes. In this example, the first semiconductor element 3 has a first electrode 3b, a second electrode 3c, and a third electrode 3d as the plurality of electrodes. The number of electrodes that the first semiconductor element 3 has is not limited. The first semiconductor element 3 may further include an insulating film (passivation film) 3e that covers the outer ends of each of the first electrode 3b and the second electrode 3c. The insulating film 3e is optional.

[0023] The material of the semiconductor layer 3a preferably includes a power semiconductor material, and more preferably is a power semiconductor material. Examples of the power semiconductor material include gallium nitride, silicon carbide, and gallium oxide. When the semiconductor element 3 includes a power semiconductor material, the heat dissipation of the semiconductor device 100 can be suitably ensured. The material of the semiconductor layer 3a may include a material other than the power semiconductor material.

[0024] The first electrode 3b and the second electrode 3c are disposed on the upper surface of the semiconductor layer 3a, i.e., the surface of the semiconductor layer 3a opposite to the support layer 2. The third electrode 3d is disposed on the lower surface of the semiconductor layer 3a, i.e., the surface of the semiconductor layer 3a facing the support layer 2. For example, the first electrode 3b functions as an emitter electrode, the second electrode 3c functions as a gate electrode, and the third electrode 3d functions as a collector electrode. When the first semiconductor element 3 is a MOSFET, for example, the first electrode 3b functions as a source electrode, the second electrode 3c functions as a gate electrode, and the third electrode 3d functions as a drain electrode.

[0025] The upper surface of the first electrode 3b and the upper surface of the second electrode 3c are each flat. The upper surface of the first electrode 3b and the upper surface of the second electrode 3c are disposed at substantially the same position in the vertical direction. In the present disclosure, "substantially the same" includes both being strictly the same and being slightly different. "Substantially the same" may include a case where there is a manufacturing error within a range of ±5% of the thickness of the entire first semiconductor element 3. Furthermore, "substantially the same" may include a case where there is a manufacturing error within a range of ±10% of the thickness of the entire first semiconductor element 3. The upper surface of the first electrode 3b and the upper surface of the second electrode 3c may not be flat. The upper surface of the first electrode 3b and the upper surface of the second electrode 3c may not be disposed at substantially the same position. That is, the upper surface of the first electrode 3b and the upper surface of the second electrode 3c may be disposed at different positions in the vertical direction.

[0026] The lower surface of the third electrode 3d is flat. The third electrode 3d is electrically connected to the second wiring layer 21 via the third connection portion 7c. For example, when the third connection portion 7c is formed integrally with the second wiring layer 21 using the same metal or the like as the second wiring layer 21, the portion of the integrally formed portion from the connection surface with the third electrode 3d to a surface whose area changes in a planar view in the vertical direction (i.e., the same position in the vertical direction as the lower surface of the insulator 5) is defined as the third connection portion 7c.

[0027] The insulating film 3e is disposed on the semiconductor layer 3a, the first electrode 3b, and the second electrode 3c. The upper surface of the insulating film 3e, that is, the surface of the insulating film 3e opposite to the semiconductor layer 3a, is located higher than the upper surface of the first electrode 3b and higher than the upper surface of the second electrode 3c. The insulating film 3e covers the outer ends of the first electrode 3b and the second electrode 3c. Examples of the method for forming the insulating film 3e include a CVD method, an atmospheric pressure CVD method, a plasma CVD method, and a mist CVD method. The method for forming the insulating film 3e is not limited. Examples of the material for the insulating film 3e include a SiO2 film, a silicon nitride film, a polysilicon film, a phosphorus-added SiO2 film (PSG film), a boron-added SiO2 film, a phosphorus-boron-added SiO2 film (BPSG film), and a polyimide film. The material for the insulating film 3e is not limited. The thickness of the insulating film 3e is, for example, 10 μm or less, and preferably 5 μm or less. The thickness of the insulating film 3e is not limited.

[0028] The insulating film 3e has openings that expose the first electrode 3b and the second electrode 3c to the first wiring layer 1 side. Therefore, each of the first electrode 3b and the second electrode 3c has an exposed portion that is exposed in the opening of the insulating film 3e. A first connection portion 7a is disposed in the opening of the insulating film 3e that exposes the first electrode 3b. A second connection portion 7b is disposed in the opening of the insulating film 3e that exposes the second electrode 3c.

[0029] The first semiconductor element 3 has a thickness. The thickness of the first semiconductor element 3 is the vertical distance from the top to the bottom of the first semiconductor element 3. In this example, the thickness of the first semiconductor element 3 is the vertical distance from the top surface of the insulating film 3e to the bottom surface of the third electrode 3d.

[0030] The second semiconductor element 4 is disposed on the support layer 2. The second semiconductor element 4 is, for example, a diode. In this example, the second semiconductor element 4 is an SBD (Schottky barrier diode). The second semiconductor element 4 may be a diode other than an SBD. The other diode is, for example, a PiN diode. The second semiconductor element 4 may be a semiconductor element other than a diode. The other semiconductor element is, for example, a transistor.

[0031] The second semiconductor element 4 has a semiconductor layer 4a and a plurality of electrodes. The material of the semiconductor layer 4a preferably includes a power semiconductor material, and more preferably is a power semiconductor material. Examples of the power semiconductor material of the semiconductor layer 4a include gallium nitride, silicon carbide, or gallium oxide, which are the same as the power semiconductor material of the semiconductor layer 3a. The material of the semiconductor layer 4a may include a material other than the power semiconductor material.

[0032] In this example, the second semiconductor element 4 has a first electrode 4b and a second electrode 4c as a plurality of electrodes. The first electrode 4b is disposed on the upper surface of the semiconductor layer 4a, i.e., the surface opposite to the support layer 2. The second electrode 4c is disposed on the lower surface of the semiconductor layer 4a, i.e., the surface on the support layer 2 side. For example, the first electrode 4b functions as a Schottky electrode, and the second electrode 4c functions as an ohmic electrode.

[0033] The upper surface of the first electrode 4b is flat. The upper surface of the first electrode 4b and the upper surface of the first electrode 3b of the first semiconductor element 3 are disposed at substantially the same position in the vertical direction. The upper surface of the first electrode 4b does not have to be flat. The upper surface of the first electrode 4b and the upper surface of the first electrode 3b may be disposed at different positions in the vertical direction.

[0034] The lower surface of the second electrode 4c, i.e., the surface of the second electrode 4c facing the support layer 2, is flat. The lower surface of the second electrode 4c and the lower surface of the third electrode 3d of the first semiconductor element 3 may be disposed at substantially the same position in the vertical direction, or may be disposed at different positions in the vertical direction.

[0035] The second electrode 4c is electrically connected to the second wiring layer 21 via a fourth connection portion 7d. For example, when the fourth connection portion 7d is formed integrally with the second wiring layer 21 using the same metal or the like as the second wiring layer 21, the portion of the integrally formed portion from the connection surface with the second electrode 4c to a surface whose area changes in a planar view in the vertical direction (i.e., the same position in the vertical direction as the lower surface of the insulator 5) is defined as the fourth connection portion 7d.

[0036] The second semiconductor element 4 has a thickness. The thickness of the second semiconductor element 4 is the vertical distance from the top end to the bottom end of the second semiconductor element 4. In this example, the thickness of the second semiconductor element 4 is the vertical distance from the top surface of the first electrode 4b to the bottom surface of the second electrode 4c. The thickness of the second semiconductor element 4 may be smaller or larger than the thickness of the first semiconductor element 3, or may be substantially the same as the thickness of the first semiconductor element 3. In this example, the thickness of the second semiconductor element 4 is larger than the thickness of the first semiconductor element 3.

[0037] The metal block 10 is disposed on the support layer 2. Examples of materials constituting the metal block 10 include Cu, Au, Al, Ag, Fe, Ti, Ni, Pt, Pd, or alloys thereof (which may contain other metals). The material constituting the metal block 10 is not particularly limited. The metal block 10 is supported by the support layer 2. The metal block 10 may be in contact with the second wiring layer 21, or may be connected to the second wiring layer 21 via another member. In this example, the metal block 10 is in contact with the second wiring layer 21, and the lower surface of the metal block 10, i.e., the surface of the metal block 10 on the support layer 2 side, is covered by the second wiring layer 21. By directly contacting the second wiring layer 21 with the metal block 10, the electrical connectivity and heat dissipation between the first wiring layer 1 and the second wiring layer 21 can be improved.

[0038] The metal block 10 has a height. The height of the metal block 10 is the vertical distance from the top end to the bottom end of the metal block 10. The height of the metal block 10 may be larger or smaller than the thickness of the first semiconductor element 3, or may be substantially the same as the thickness of the first semiconductor element 3. The height of the metal block 10 may be larger or smaller than the thickness of the second semiconductor element 4, or may be substantially the same as the thickness of the second semiconductor element 4. In this example, the height of the metal block 10 is larger than the thickness of the first semiconductor element 3 and is larger than the thickness of the second semiconductor element 4. The lower surface of the metal block 10 is disposed below the first semiconductor element 3 and is disposed below the second semiconductor element 4. The upper surface of the metal block 10 is located above the upper surface of the first electrode 4b of the second semiconductor element 4.

[0039] The insulator 5 is disposed on the support layer 2. Examples of the material of the insulator 5 include epoxy resin, cyanate ester resin, acrylic resin, polyimide resin, and silicone resin. The material of the insulator 5 is not limited. Each of the surface of the insulator 5 facing the support layer 2 and the surface facing the first wiring layer 1 is flat.

[0040] The insulator 5 has a thickness. The thickness of the insulator 5 is the vertical distance from the top to the bottom of the insulator 5. The thickness of the insulator 5 may be larger or smaller than the thickness of the first semiconductor element 3, or may be substantially the same as the thickness of the first semiconductor element 3. The thickness of the insulator 5 may be larger or smaller than the thickness of the second semiconductor element 4, or may be substantially the same as the thickness of the second semiconductor element 4. The thickness of the insulator 5 is preferably 1.0 to 1.2 times the thickness of the first semiconductor element 3.

[0041] Only a portion of the first semiconductor element 3, the entirety of the second semiconductor element 4, and only a portion of the metal block 10 are embedded in the insulator 5. The entirety of the first semiconductor element 3 may be embedded in the insulator 5. Only a portion of the second semiconductor element 4 may be embedded in the insulator 5. The entirety of the metal block 10 may be embedded in the insulator 5.

[0042] The lower surface of the insulator 5, i.e., the surface of the insulator 5 facing the support layer 2, is disposed below the first semiconductor element 3 and the second semiconductor element 4. The lower surface of the insulator 5 is disposed at substantially the same position as the lower surface of the metal block 10 in the up-down direction.

[0043] The upper surface of the insulator 5, i.e., the surface of the insulator 5 opposite to the support layer 2, is flat. The upper surface of the insulator 5 is disposed at substantially the same position in the vertical direction as the upper surfaces of the first electrode 3b and the second electrode 3c of the first semiconductor element 3 and the upper surface of the first electrode 4b of the second semiconductor element 4. The upper surface of the insulator 5 may be disposed at a different position in the vertical direction from the upper surfaces of the first electrode 3b, the second electrode 3c, and the first electrode 4b. The upper surface of the insulator 5 is disposed lower than the upper surfaces of the insulating film 3e and the metal block 10.

[0044] The first wiring layer 1 is disposed on the insulator 5. That is, the insulator 5 is located between the support layer 2 and the first wiring layer 1. The material of the first wiring layer 1 may be the same as or different from the material of the second wiring layer 21. Examples of the material of the first wiring layer 1 include Cu, Au, Al, Ag, Fe, Ti, Ni, Pt, Pd, or an alloy of two or more of these (which may contain other metals). The material of the first wiring layer 1 is preferably Cu. The material of the first wiring layer 1 is not limited as long as it is a material having electrical conductivity. The first wiring layer 1 is in contact with the insulator 5 and the insulating film 3e. Therefore, the heat dissipation of the semiconductor device 100 can be improved. The first wiring layer 1 may be in non-contact with the insulator 5 or may be in non-contact with the insulating film 3e. For example, another layer such as an adhesive layer may be disposed between the first wiring layer 1 and the insulator 5. The first wiring layer 1 in this example is a wiring layer exposed to the outside of the semiconductor device 100. Therefore, it is possible to improve the heat dissipation performance of the semiconductor device 100. The first wiring layer 1 does not have to be exposed to the outside of the semiconductor device 100. The upper surface of the insulating film 3e is disposed higher than the upper surface of the insulator 5.

[0045] The first connection portion 7a and the second connection portion 7b are each disposed between the first semiconductor element 3 and the first wiring layer 1.

[0046] The constituent material of each of the first connection portion 7a and the second connection portion 7b may be the same as or different from the constituent material of the first wiring layer 1. Examples of the constituent material of each of the first connection portion 7a and the second connection portion 7b include Cu, Au, Al, Ag, Fe, Ti, Ni, Pt, Pd, or alloys thereof (which may contain other metals), or conductive resin paste. Each of the first connection portion 7a and the second connection portion 7b is preferably Cu or a Cu alloy. The constituent material of each of the first connection portion 7a and the second connection portion 7b is not limited as long as it is a material having conductivity.

[0047] The first electrode 3b of the first semiconductor element 3 and the first wiring layer 1 are electrically connected via a first connection portion 7a. The second electrode 3c of the first semiconductor element 3 and the first wiring layer 1 are electrically connected via a second connection portion 7b.

[0048] Each of the first connection portion 7a and the second connection portion 7b may be formed integrally with the first wiring layer 1, or may be connected to the first wiring layer 1 via another member. For example, when the first connection portion 7a is formed integrally with the first wiring layer 1 using the same metal as the first wiring layer 1, the portion of the integrally formed portion from the connection surface with the first electrode 3b to the surface whose area changes in a planar view in the vertical direction (i.e., the same position in the vertical direction as the upper surface of the insulating film 3e) is defined as the first connection portion 7a. For example, when the second connection portion 7b is formed integrally with the first wiring layer 1 using the same metal as the first wiring layer 1, the portion of the integrally formed portion from the connection surface with the second electrode 3c to the surface whose area changes in a planar view in the vertical direction (i.e., the same position in the vertical direction as the upper surface of the insulating film 3e) is defined as the second connection portion 7b. Each of the first connection portion 7a and the second connection portion 7b may have a multi-layer structure in order to increase the adhesive strength with the first wiring layer 1 or the first semiconductor element 3.

[0049] In this example, the upper surfaces of the first electrode 3b and the second electrode 3c of the first semiconductor element 3 and the insulator 5 are located substantially on the same plane. That is, the lower surface of the first connection portion 7a, the lower surface of the second connection portion 7b, and the upper surface of the insulator 5 are located substantially on the same plane. Therefore, the thickness of each of the first connection portion 7a and the second connection portion 7b can be reduced, and the heat dissipation of the semiconductor device 100 can be suitably ensured. For example, the thickness of each of the first connection portion 7a and the second connection portion 7b can be 10 μm or less, preferably 5 μm or less. Therefore, it is advantageous in terms of electrical connection and thermal connection with the first wiring layer 1 and the second wiring layer 21.

[0050] The upper surface of the first electrode 4b of the second semiconductor element 4 is flush with the upper surface of the insulator 5. That is, the upper surfaces of the first electrode 3b and the second electrode 3c of the first semiconductor element 3, the first electrode 4b of the second semiconductor element 4, and the insulator 5 are located substantially on the same plane. The first wiring layer 1 is in contact with the first electrode 4b. This electrically connects the first wiring layer 1 and the second semiconductor element 4. The upper surface of the first electrode 4b may be located below the upper surface of the insulator 5. In this case, the first wiring layer 1 and the second semiconductor element 4 may be electrically connected via a connection portion similar to the first connection portion 7a.

[0051] The upper surface of the metal block 10 (i.e., the surface on the first wiring layer 1 side) is located at substantially the same position in the up-down direction as the upper surface of the insulating film 3e. That is, the upper surface of the metal block 10 is located higher than the upper surface of the insulator 5. The first wiring layer 1 contacts the metal block 10 and covers the upper surface of the metal block 10. This electrically connects the first wiring layer 1 and the metal block 10. Note that the metal block 10 and the first wiring layer 1 may be electrically connected via another member.

[0052] The first insulating protective layer 9a covers a part of the first wiring layer 1. The first insulating protective layer 9a is disposed on the surface of the insulator 5 facing the first wiring layer 1 and on the surface of the first wiring layer 1 opposite the insulator 5, and is in contact with the first wiring layer 1 and the insulator 5. The first insulating protective layer 9a forms a housing wall of the semiconductor device 100 as a module. The first insulating protective layer 9a is formed of a material having electrical insulation properties, such as solder resist. For example, a control system (including a gate driver, etc.) of the semiconductor element 3, a higher-level system, or a controlled object is disposed on the surface of the first wiring layer 1 opposite the insulator 5 and the surface of the first insulating protective layer 9a opposite the insulator 5. The semiconductor device 100 exchanges signals and power with the control system, higher-level system, controlled object, etc. of the semiconductor element 3.

[0053] The second insulating protective layer 9b covers a part of the second wiring layer 21. The second insulating protective layer 9b is disposed on the surface of the second wiring layer 21 opposite to the insulator 5 and on the surface of the insulator 5 facing the second wiring layer 21, and is in contact with the second wiring layer 21 and the insulator 5. The second insulating protective layer 9b forms a housing wall of the semiconductor device 100. The second insulating protective layer 9b is formed of a material that allows heat dissipation while providing insulation from the outside of the module, such as a TIM (Thermal Interface Material). A heat sink, such as a heat dissipation fin, is connected to the surface of the second insulating protective layer 9b opposite to the second wiring layer 21. The heat sink effectively dissipates heat generated from the first semiconductor element 3 and the second semiconductor element 4 to the outside of the module.

[0054] The support layer 2 has a first convex portion at least a part of which is embedded in the insulator 5 below the first semiconductor element 3. The first convex portion protrudes upward from the second wiring layer 21. In this example, the first convex portion is the third connection portion 7c. That is, the first convex portion is located directly below the third electrode 3d of the first semiconductor element 3, and is entirely embedded in the insulator 5. The first convex portion is not limited to the third connection portion 7c. The first convex portion does not have to have the function of electrically connecting the first semiconductor element 3 and the second wiring layer 21.

[0055] The support layer 2 further has a second convex portion at least a part of which is embedded in the insulator 5 below the second semiconductor element 4. The second convex portion protrudes upward from the second wiring layer 21. In this example, the second convex portion is the fourth connection portion 7d. That is, the second convex portion is located directly below the second electrode 4c of the second semiconductor element 4, and is entirely embedded in the insulator 5. The second convex portion is not limited to the fourth connection portion 7d. The second convex portion does not have to have the function of electrically connecting the second semiconductor element 4 and the second wiring layer 21.

[0056] Next, the operation of the semiconductor device 100 will be described in detail. First, when a gate driver (not shown) outputs a control signal (switching signal), the first semiconductor element 3 operates and performs switching control. As a result, a desired pulse waveform is generated from the first semiconductor element 3 and output as a drive signal from the first electrode 3b. This drive signal is provided to a control target (not shown). For example, when the first semiconductor element 3 is an IGBT, the switching control of the IGBT is performed by supplying a control signal from a gate driver (not shown) to the second electrode 3c. In this case, the second semiconductor element 4 is, for example, an SBD, and functions as a high-voltage free wheeling diode (FWD) for returning the current of the third electrode 3d to the first electrode 3b.

[0057] When the first semiconductor element 3 and the second semiconductor element 4 operate, electrical signals and processing signals are collected through the electrical circuit formed in the first wiring layer 1 and sent to the control system through the electrical circuit of the second wiring layer 21. That is, the electrical signals and processing signals sent to the control system are transmitted and received through the second wiring layer 21. Therefore, electrical signals inputted and outputted from the second electrode 3c and the third electrode 3d of the first semiconductor element 3 and the second electrode 4c of the second semiconductor element 4 are also given to the electrical circuit of the first wiring layer 1, and are further conducted in a loop connected to the second wiring layer 21 via the metal block 10. In this way, the first wiring layer 1 and the second wiring layer 21 contribute to the electrical conduction of the semiconductor elements 3 and 4 connecting the first and second wiring layers 1 and 21 through the metal block 10.

[0058] Heat within the module, i.e., heat generated from the semiconductor elements 3 and 4, is dissipated above or below the semiconductor device 100 via the first connection portion 7a, the second connection portion 7b, the third connection portion 7c, the fourth connection portion 7d, and the metal block 10. In this embodiment, as described above, a heat dissipation mechanism such as a heat dissipation fin is attached to the underside of the second wiring layer 21, thereby enabling effective heat dissipation from the module.

[0059] Next, a specific manufacturing process of the semiconductor device 100 according to one embodiment of the present disclosure will be described in more detail with reference to the schematic cross-sectional views shown in Figures 2A to 2G. Note that a part or a combination of such manufacturing methods for the semiconductor device 100 is also novel and useful, and is included in the present disclosure.

[0060] The manufacturing method of the semiconductor device 100 includes a step of forming a third connection portion 7c (i.e., a first protrusion) on the third electrode 3d of the first semiconductor element 3 (hereinafter, this step is referred to as a "third connection portion forming step"), a step of embedding the first semiconductor element 3 and the second semiconductor element 4 in the insulator 5 so that the third connection portion 7c is exposed to the outside of the insulator 5 (hereinafter, this step is referred to as an "embedding step"), and a step of forming a second wiring layer 21 on the surface of the third connection portion 7c opposite to the third electrode 3d (hereinafter, this step is referred to as a "second wiring layer forming step"). The manufacturing method of the semiconductor device 100 may further include a first protective portion forming step, a fourth connecting portion forming step, a polishing step, a second protective portion forming step, a first protective portion removing step, a first connecting portion forming step, a second connecting portion forming step, a first wiring layer forming step, a second protective portion removing step, and an insulating protection layer forming step.

[0061] The first protective portion forming step is a step of forming a first protective portion 13 (see FIG. 2A) that protects the first electrode 3b and the second electrode 3c of the first semiconductor element 3 and the first electrode 4b of the second semiconductor element 4. The first protective portion 13 is, for example, a support substrate formed from a glass substrate. The first protective portion 13 may be a support substrate other than a glass substrate. The first protective portion 13 is not limited to a support substrate. In the first protective portion forming step, for example, as shown in FIG. 2A, the first semiconductor element 3, the second semiconductor element 4, and the metal block 10 are bonded to the first protective portion 13 directly or via another member. In this example, the first electrode 3b, the second electrode 3c, and the insulating film 3e of the first semiconductor element 3, and the first electrode 4b of the second semiconductor element 4 are bonded to the first protective portion 13 via a temporary adhesive layer 15 and a peeling layer 14.

[0062] The third connection part forming step and the fourth connection part forming step are performed on the structure obtained through the first protective part forming step. In the third connection part forming step, for example, a metal layer that becomes the third connection part 7c is formed on the third electrode 3d of the first semiconductor element 3 (see FIG. 2A). In the fourth connection part forming step, a fourth connection part 7d (i.e., a second convex part) is formed on the second electrode 4c of the second semiconductor element 4. In the fourth connection part forming step, for example, a metal layer that becomes the fourth connection part 7d is formed on the second electrode 4c (see FIG. 2A). In each of the third connection part forming step and the fourth connection part forming step, the metal layer is formed using a known method such as a plating method (electrolytic plating method or electroless plating method). In the third connection part forming step and the fourth connection part forming step, the third connection part forming step may be performed first, the fourth connection part forming step may be performed first, or they may be performed simultaneously.

[0063] The embedding step is performed on the structure obtained through the third connection part forming step and the fourth connection part forming step. In the embedding step, for example, as shown in FIG. 2B, a molding method using a release film 16 is used to inject a sealant as the insulator 5, thereby embedding the first semiconductor element 3, the second semiconductor element 4, and the metal block 10 in the insulator 5. In detail, only a part of the first semiconductor element 3, the whole of the second semiconductor element 4, and only a part of the metal block 10 are embedded in the insulator 5. For example, a silicone resin or an epoxy resin is used as the sealant. A known method is used as a molding method for injecting the sealant. For example, a transfer molding method or a compression molding method is preferable as the molding method.

[0064] The polishing step is performed on the structure obtained through the embedding step. The polishing step is a step of polishing the third connecting portion 7c and the fourth connecting portion 7d so that the surface of the third connecting portion 7c opposite to the third electrode 3d and the surface of the fourth connecting portion 7d opposite to the third electrode 3d are flush with each other. In the polishing step, in addition to the third connecting portion 7c and the fourth connecting portion 7d, the insulator 5 may also be polished.

[0065] Specifically, before the start of the polishing step, the release film 16 is removed as shown in Fig. 2C. Thereafter, as shown in Fig. 2D, the third connecting portion 7c and the fourth connecting portion 7d are polished so that the surface of the third connecting portion 7c opposite to the third electrode 3d, the surface of the fourth connecting portion 7d opposite to the second electrode 4c, the surface of the metal block 10 opposite to the protective portion 13, and the surface of the insulator 5 opposite to the protective portion 13 are flush with each other to form a flat surface. Examples of the polishing method used in the polishing step include known methods such as chemical mechanical polishing (CMP).

[0066] The second wiring layer forming step is performed on the structure obtained through the polishing step. In the second wiring layer forming step, for example, as shown in FIG. 2E, the metal layer that becomes the second wiring layer 21 is formed on the flat surface formed by the polishing step, that is, the surface of the third connecting portion 7c opposite to the third electrode 3d, the surface of the fourth connecting portion 7d opposite to the second electrode 4c, the surface of the metal block 10 opposite to the protective portion 13, and the surface of the insulator 5 opposite to the protective portion 13. In the second wiring layer forming step, for example, a metal layer that becomes the second wiring layer 21 is formed using a known method such as a plating method (electrolytic plating method or electroless plating method), and this metal layer is patterned using a known patterning method. In this example, the second wiring layer forming step is performed after the polishing step, but the polishing step may be omitted and the second wiring layer forming step may be performed after the embedding step. In this case, in the second wiring layer formation process, a second wiring layer 21 is formed which is electrically connected to the third connection portion 7c, the fourth connection portion 7d, and the metal block 10, with the surface of the third connection portion 7c opposite the third electrode 3d and the surface of the fourth connection portion 7d opposite the second electrode 4c being shifted in the vertical direction.

[0067] The second protective portion forming step is performed on the structure obtained through the second wiring layer forming step. The second protective portion forming step is a step of forming a second protective portion 20 that protects the second wiring layer 21. The second protective portion 20 is, for example, a support substrate formed from a glass substrate. The second protective portion 20 may be a support substrate other than a glass substrate. The second protective portion 20 is not limited to a support substrate. In the second protective portion forming step, for example, as shown in FIG. 2F, the second wiring layer 21 and the insulator 5 are bonded to the second protective portion 20 directly or via another member. In this example, the surface of the second wiring layer 21 opposite the insulator 5 and a part of the surface of the insulator 5 on the second wiring layer 21 side are bonded to the second protective portion 20 via the resist 17, the temporary adhesion layer 18, and the peeling layer 19.

[0068] The first protective portion removal step is performed on the structure obtained through the second protective portion formation step. The first protective portion removal step is a step of removing the first protective portion 13 (see FIG. 2G). In the first protective portion removal step, for example, the structure is irradiated with UV light, the first protective portion (support substrate) 13 is peeled off from the peeling layer 14, and further, the temporary adhesion layer 15 is removed by washing to expose the first electrode 3b and the second electrode 3c. At this time, the insulating film 3e is maintained in a state in which it covers at least the outer ends of the first electrode 3b and the second electrode 3c (in a state in which it can insulate between the first electrode 3b and the second electrode 3c).

[0069] The first connection portion forming step, the second connection portion forming step, and the first wiring layer forming step are performed on the structure obtained through the first protective portion removing step. The first connection portion forming step is a step of forming a first connection portion 7a on the first electrode 3b of the first semiconductor element 3 (see FIG. 2G). The second connection portion forming step is a step of forming a second connection portion 7b on the second electrode 3c of the first semiconductor element 3 (see FIG. 2G). The first wiring layer forming step is a step of forming a first wiring layer 1 on the surface of the first connection portion 7a opposite to the first electrode 3b and the surface of the second connection portion 7b opposite to the second electrode 3c (see FIG. 2G). The first connection portion forming step and the second connection portion forming step may be performed first, or may be performed first, or may be performed simultaneously. The first wiring layer forming step is performed following the first connection portion forming step and the second connection portion forming step. In the first wiring layer forming step, for example, as shown in FIG. 2G, the first wiring layer 1 is formed so as to contact the surface of the first connection portion 7a opposite to the first electrode 3b, the surface of the second connection portion 7b opposite to the second electrode 3c, the surface of the first electrode 4b of the second semiconductor element 4 opposite to the semiconductor layer 4a, and the surface of the metal block 10 opposite to the second wiring layer 21. In each of the first connection portion forming step, the second connection portion forming step, and the first wiring layer forming step, a metal layer to be the first connection portion 7a, the second connection portion 7b, or the first wiring layer 1 is formed using a known method such as a plating method (electrolytic plating method or electroless plating method). The formation of the metal layer in each of the first connection portion forming step, the second connection portion forming step, and the first wiring layer forming step may be performed continuously or intermittently. In the first wiring layer forming step, the formed metal layer is patterned using a known patterning method.

[0070] The second protective portion removal step is performed on the structure obtained through the first connection portion forming step, the second connection portion forming step, and the first wiring layer forming step. The second protective portion removal step is a step of removing the second protective portion 20. In the second protective portion removal step, for example, the second protective portion 20, the peeling layer 19, and the temporary adhesion layer 18 are removed by a process similar to that of the first protective portion removal step. That is, the structure is irradiated with UV light, the second protective portion 20 is peeled off from the peeling layer 19, and further the temporary adhesion layer 18 is removed by washing. The resist 17 is removed, for example, by a known dry process or wet process.

[0071] The insulating protection layer forming step is performed on the structure obtained through the second protective portion removing step. The insulating protection layer forming step is a step of forming a first insulating protection layer 9a and a second insulating protection layer 9b. In the insulating protection layer forming step, for example, the first insulating protection layer 9a and the second insulating protection layer 9b are formed by a known method. Through the insulating protection layer forming step, the semiconductor device 100 shown in FIG. 1 is obtained.

[0072] The support layer 2 in the above-described embodiment has a third connection portion 7c (first convex portion) at least a part of which is embedded in the insulator 5 below the first semiconductor element 3. Therefore, even if there is a difference between the thickness of the first semiconductor element 3 and the thickness of the second semiconductor element 4, the first semiconductor element 3 and the second semiconductor element 4 can be aligned in the vertical positions with respect to the first wiring layer 1 by adjusting the thickness of the third connection portion 7c according to the difference. Therefore, each of the first connection portion 7a and the second connection portion 7b can be made extremely thin, for example, several μm to 10 μm, which is about the thickness of the insulating film 3e, and the electrical connectivity between the first wiring layer 1 and the first electrode 3b and the electrical connectivity between the first wiring layer 1 and the second electrode 3c can be improved.

[0073] Moreover, by performing the polishing process, the semiconductor device 100 can be made thinner. Furthermore, in the third connection portion forming process and the fourth connection portion forming process, the metal layer that becomes the third connection portion 7c and the metal layer that becomes the fourth connection portion 7d are formed, so that the influence on the third electrode 3d can be reduced without strict control of accuracy in the polishing process. This further improves the accuracy of the thickness variation between lots of the first semiconductor element 3 and the second semiconductor element 4 and the accuracy of the height variation of the metal block 10. Furthermore, by performing the first protection portion forming process and the polishing process, the controllability of the height accuracy of the first semiconductor element 3 can be more easily improved while suppressing the influence on the first electrode 3b and the second electrode 3c. Moreover, according to the above-mentioned manufacturing method of the semiconductor device 100, it is not necessary to form vias for electrically connecting the first semiconductor element 3 and the second semiconductor element 4 to the first wiring layer 1 and the second wiring layer 21, and it is not necessary to perform hole processing in the insulator 5 to form the vias. Therefore, the first semiconductor element 3 and the second semiconductor element 4 can be electrically connected to the first wiring layer 1 and the second wiring layer 21 via the connection parts 7a, 7b, 7c, or 7d having a large contact area with the electrodes 3b, 3c, 3d, or 4c. This can improve the electrical characteristics of the semiconductor device 100, such as reducing the electrical resistance at the connection parts 7a, 7b, 7c, or 7d to allow current to flow efficiently. In addition, heat is easily transferred from the electrodes 3b, 3c, 3d, or 4c to the connection parts 7a, 7b, and 7c, so that the heat dissipation of the semiconductor device 100 can also be improved.

[0074] The semiconductor device 100 according to the present embodiment includes two semiconductor elements, but there is no restriction on the number of semiconductor elements, and may include three or more semiconductor elements. The semiconductor device 100 may also include only one semiconductor element, for example, the first semiconductor element 3 or the second semiconductor element 4. The first semiconductor element 3 and the second semiconductor element 4 shown in FIG. 1 are both vertical elements having electrodes on both sides, but they may also be horizontal elements having electrodes on only one side. That is, both the first semiconductor element 3 and the second semiconductor element 4 may be vertical elements, or one of the first semiconductor element 3 and the second semiconductor element 4 may be a vertical element and the other may be a horizontal element.

[0075] When a power semiconductor element is mounted as the first semiconductor element 3 or the second semiconductor element 4, it is particularly useful to use silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), etc. as the semiconductor material of the power semiconductor. In particular, it is extremely useful to include a semiconductor element 3 using gallium oxide (α-Ga2O3) with a high band gap corundum structure or gallium oxide (β-Ga2O3) with a β-gallium structure. Since these semiconductor materials generate a large amount of heat during operation, application of the present disclosure, which has excellent module miniaturization and heat dissipation characteristics, contributes to not only high density of the semiconductor device 100 but also improved reliability.

[0076] Second embodiment Next, a semiconductor device 200 according to a second embodiment will be described. Fig. 3 is a schematic cross-sectional view of the semiconductor device 200 according to the second embodiment. The semiconductor device 200 has elements in common with the semiconductor device 100 according to the first embodiment. Therefore, in the following description, the matters of the semiconductor device 200 that are in common with the semiconductor device 100 will not be described.

[0077] The semiconductor device 200 differs from the semiconductor device 100 of the first embodiment in that a part of the second semiconductor element 4 is located below the surface of the insulator 5 on the support layer 2 side. Specifically, the support layer 2 does not have a fourth connection portion (second convex portion) 7d. A recess 22 is formed in a portion of the surface of the second wiring layer 21 on the insulator 5 side that corresponds to the second semiconductor element 4. The surface of the second electrode 4c of the second semiconductor element 4 opposite to the semiconductor layer 4a is located below the surface of the insulator 5 on the second wiring layer 21 side. The lower end of the semiconductor layer 4a of the second semiconductor element 4 is also located below the surface of the insulator 5 on the second wiring layer 21 side. Only a part of the second semiconductor element 4, specifically, only the lower end of the semiconductor layer 4a and the second electrode 4c are arranged in the recess 22. The second electrode 4c and the second wiring layer 21 are in contact with each other. This electrically connects the second semiconductor element 4 and the second wiring layer 21.

[0078] 4 is a cross-sectional view for explaining the manufacturing method of the semiconductor device 200, and corresponds to FIG. 2C which is a cross-sectional view for explaining the manufacturing method of the semiconductor device 100 of the first embodiment. In the manufacturing method of the semiconductor device 200, the polishing step is not performed, and the second wiring layer forming step is performed after the embedding step. That is, the second wiring layer forming step is performed on the structure shown in FIG.

[0079] Third embodiment Next, a semiconductor device 300 according to a third embodiment will be described. Fig. 5 is a schematic cross-sectional view of the semiconductor device 300 according to the third embodiment. The semiconductor device 300 has elements in common with the semiconductor device 100 according to the first embodiment. Therefore, in the following description, the matters of the semiconductor device 300 that are in common with the semiconductor device 100 will not be described.

[0080] The semiconductor device 300 differs from the semiconductor device 100 of the first embodiment in that the surface of the second semiconductor element 4 on the support layer 2 side and the surface of the insulator 5 on the support layer 2 side are disposed at the same position in the vertical direction. Specifically, the support layer 2 does not have a fourth connection portion 7d (second convex portion). The portion of the surface of the second wiring layer 21 on the insulator 5 side that corresponds to the second semiconductor element 4 and its surrounding area are flat surfaces. The surface of the second electrode 4c of the second semiconductor element 4 opposite to the semiconductor layer 4a and the surface of the insulator 5 on the second wiring layer 21 side are disposed at the same position in the vertical direction and are flush with each other. The second electrode 4c and the second wiring layer 21 are in contact with each other. This electrically connects the second semiconductor element 4 and the second wiring layer 21.

[0081] 6 is a cross-sectional view for explaining the manufacturing method of the semiconductor device 300, and corresponds to FIG. 2C, which is a cross-sectional view for explaining the manufacturing method of the semiconductor device 100. In the manufacturing method of the semiconductor device 300, the polishing step is not performed, and the second wiring layer forming step is performed after the embedding step. That is, the second wiring layer forming step is performed on the structure shown in FIG.

[0082] The semiconductor device 100, 200 or 300 according to the embodiment of the present disclosure described above can be applied to a power conversion device such as an inverter or converter to achieve the above-mentioned functions.

[0083] FIG. 7 is a block diagram showing an example of a control system 500 using the semiconductor device 100, 200, or 300. FIG. 8 is a circuit diagram of the control system 500. The control system 500 is a system suitable for mounting on, for example, an electric vehicle. The control system 500 has a battery (power source) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (drive object) 505, and a drive control unit 506, which are mounted on the electric vehicle. The battery 501 is, for example, a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and can store power by charging at a power supply station or by regenerative energy during deceleration, and can output a DC voltage required for the operation of the driving system and electrical system of the electric vehicle. The boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit, and output the boosted voltage to the driving system such as the motor. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit, and by stepping down a DC voltage of, for example, 200 V supplied from the battery 501 to, for example, about 12 V, it can output the voltage to an electrical system including power windows, power steering, or in-vehicle electrical equipment.

[0084] Inverter 504 converts the DC voltage supplied from boost converter 502 into a three-phase AC voltage by switching operation and outputs it to motor 505. Motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission (not shown) or the like.

[0085] Meanwhile, using various sensors (not shown), actual values ​​such as the number of rotations of the wheels, torque, and the amount of depression of the accelerator pedal (acceleration amount) are measured from the electric vehicle while it is running, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory, and generates a control signal using the input measurement signal and outputs it to the inverter 504 as a feedback signal to control the switching operation by the switching element. As a result, the AC voltage that the inverter 504 gives to the motor 505 is instantly corrected, so that the driving control of the electric vehicle can be accurately performed, and the safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving a feedback signal from the drive control unit 506 to the boost converter 502.

[0086] 8 shows a circuit configuration excluding the step-down converter 503 in FIG. 7, that is, a circuit configuration showing only a configuration for driving a motor 505. The semiconductor device 100, 200, or 300 is used as, for example, a Schottky barrier diode in a step-up converter 502 and an inverter 504 to perform switching control. In the step-up converter 502, it is incorporated in a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated in a switching circuit including an IGBT to perform switching control. An inductor (such as a coil) is interposed in the output of the battery 501 to stabilize the current, and a capacitor (such as an electrolytic capacitor) is interposed between the battery 501, the step-up converter 502, and the inverter 504 to stabilize the voltage.

[0087] 8, the drive control unit 506 includes a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of a non-volatile memory. A signal input to the drive control unit 506 is provided to the calculation unit 507, which performs programmed calculations as necessary to generate feedback signals for each semiconductor element. The storage unit 508 also temporarily holds the results of calculations performed by the calculation unit 507, and accumulates physical constants and functions necessary for drive control in the form of a table and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can be configured as known in the art, and their processing capabilities can be selected as desired.

[0088] As shown in FIG. 7 and FIG. 8, in the control system 500, a thyristor, a power transistor, an IGBT, a MOSFET, etc., which are diodes or switching elements, are used for the switching operations of the boost converter 502, the buck converter 503, and the inverter 504. The switching characteristics are significantly improved by using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements. Furthermore, by applying the semiconductor device 100, 200, or 300, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, the boost converter 502, the buck converter 503, and the inverter 504 can each be expected to have the effect of the present disclosure, and the effect of the present disclosure can be expected in any one of them, any combination of two or more of them, or in any form including the drive control unit 506.

[0089] The above-mentioned control system 500 can be applied not only to the control system of an electric vehicle using the semiconductor device 100, 200, or 300, but also to control systems for various purposes such as stepping up / down the power from a DC power source, converting DC to AC, etc. Also, a power source such as a solar cell can be used as the battery.

[0090] FIG. 9 is a block diagram showing another example of a control system employing the semiconductor device 100, 200, or 300. FIG. 10 is a circuit diagram of the control system 600. The control system 600 is a system suitable for mounting on infrastructure equipment, home appliances, and the like that operate with power from an AC power source. The control system 600 receives power supplied from, for example, an external three-phase AC power source (power source) 601, and has an AC / DC converter 602, an inverter 604, a motor (drive target) 605, and a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.) of a power company, and its output is stepped down via a substation and supplied as an AC voltage. In addition, for example, a power source is installed in a building or a nearby facility in the form of a private generator, etc., and supplied with power via a power cable. The AC / DC converter 602 is a voltage conversion device that converts AC voltage to DC voltage, and converts the AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage is converted into a desired DC voltage that is generally used, such as 3.3V, 5V, or 12V. If the object to be driven is a motor, the voltage is converted to 12V. Note that a single-phase AC power supply can be used instead of the three-phase AC power supply, and in that case, a similar system configuration can be achieved by using an AC / DC converter with a single-phase input.

[0091] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The motor 605 has a different form depending on the controlled object, but is a three-phase AC motor for driving wheels when the controlled object is a train, pumps and various power sources when the controlled object is a factory facility, and compressors and the like when the controlled object is a home appliance, and is rotationally driven by the three-phase AC voltage output from the inverter 604 and transmits the rotational driving force to a driven object (not shown).

[0092] For example, in home appliances, there are many objects to be driven that can be supplied with the DC voltage output from AC / DC converter 602 as is (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.), in which case inverter 604 is not required in control system 600, and the DC voltage is supplied to the object to be driven from AC / DC converter 602. In this case, for example, a personal computer is supplied with a DC voltage of 3.3 V, and an LED lighting equipment is supplied with a DC voltage of 5 V.

[0093] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotation speed and torque of the object to be driven, or the temperature and flow rate of the surrounding environment of the object to be driven, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604 to control the switching operation of the switching element. As a result, the AC voltage provided by the inverter 604 to the motor 605 is instantly corrected, so that the operation control of the object to be driven can be performed accurately, and stable operation of the object to be driven is realized. In addition, as described above, when the object to be driven can be driven by a DC voltage, it is also possible to feedback control the AC / DC converter 602 instead of feedback to the inverter 604.

[0094] Fig. 10 shows the circuit configuration of Fig. 9. The semiconductor device 100, 200 or 300 is used as, for example, a Schottky barrier diode in an AC / DC converter 602 and an inverter 604 to perform switching control. The AC / DC converter 602 uses, for example, a Schottky barrier diode configured in a bridge circuit, and performs DC conversion by converting and rectifying the negative voltage of the input voltage into a positive voltage. In the inverter 604, the semiconductor device is incorporated in a switching circuit in an IGBT to perform switching control. Note that a capacitor (such as an electrolytic capacitor) is interposed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0095] 10, the drive control unit 606 includes a calculation unit 607 made up of a CPU and a storage unit 608 made up of a non-volatile memory. A signal input to the drive control unit 606 is provided to the calculation unit 607, which performs programmed calculations as necessary to generate feedback signals for each semiconductor element. The storage unit 608 also temporarily holds the results of calculations performed by the calculation unit 607, and accumulates physical constants and functions necessary for drive control in the form of a table and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can be configured as known units, and their processing capabilities can be selected as desired.

[0096] In the control system 600, as in the control system 500 shown in Figs. 7 and 8, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and the inverter 604. The switching characteristics are improved by using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements. Furthermore, by applying the semiconductor device 100, 200, or 300, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the effects of the present disclosure can be expected for each of the AC / DC converter 602 and the inverter 604, and the effects of the present disclosure can be expected for any one of them, a combination of them, or any form including the drive control unit 606.

[0097] 9 and 10, a motor 605 is shown as an example of a driven object, but the driven object is not necessarily limited to mechanically operated objects, and can be many devices that require AC voltage. The control system 600 can be applied as long as it inputs power from an AC power source to drive the driven object, and can be installed for drive control of infrastructure equipment (for example, power equipment in buildings and factories, communication equipment, traffic control equipment, water and sewage treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (for example, refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.).

[0098] [Note] The following additional notes will be given regarding the above-described embodiment.

[0099] (Appendix 1) A semiconductor device comprising: a support layer, a first semiconductor element provided above the support layer, a second semiconductor element provided above the support layer, and an insulator provided above the support layer and in which at least a portion of the first semiconductor element and at least a portion of the second semiconductor element are embedded, the support layer having a first convex portion at least a portion of which is embedded in the insulator below the first semiconductor element.

[0100] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the second semiconductor element has a thickness different from a thickness of the first semiconductor element.

[0101] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the support layer has a second convex portion at least a portion of which is embedded in the insulator below the second semiconductor element.

[0102] (Appendix 4) 3. The semiconductor device according to claim 1, wherein a portion of the second semiconductor element is located below a lower surface of the insulator.

[0103] (Appendix 5) 3. The semiconductor device according to claim 1, wherein a lower surface of the second semiconductor element and a lower surface of the insulator are disposed at the same position in the vertical direction.

[0104] (Appendix 6) The semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor element has a semiconductor layer and an electrode arranged on a lower surface of the semiconductor layer, the support layer has a wiring layer and a connection portion that connects the wiring layer and the electrode, and the first convex portion is the connection portion.

[0105] (Appendix 7) 7. The semiconductor device according to claim 6, wherein the wiring layer and the connection portion are integrally formed.

[0106] (Appendix 8) A power conversion device using the semiconductor device according to any one of claims 1 to 7.

[0107] (Appendix 9) A control system using the semiconductor device according to any one of claims 1 to 7. [Explanation of symbols]

[0108] 1 First wiring layer 2 Support layer 21 Second wiring layer 3. First Semiconductor Element 3a Semiconductor layer 3b First electrode (source electrode) 3c Second electrode (gate electrode) 3d Third electrode (drain electrode) 3e Insulating film 5. Insulation 7a First connection part 7b Second connection 7c Third connection part (first convex part) 9a First insulating protection layer 9b Second insulating protection layer 10 Metal Block 13 First Protection Section 14 Release layer 15 Temporary adhesive layer 16 Release film 17 Resist 18 Temporary adhesive layer 19 Peeling layer 20 Second Protection Section 100 Semiconductor device 200 Semiconductor device 300 Semiconductor device 500 Control System 501 Battery (power source) 502 Boost Converter 503 Buck Converter 504 Inverter 505 Motor (Driven object) 506 Drive control unit 507 Arithmetic section 508 Storage section 600 Control System 601 Three-phase AC power supply (power supply) 602 AC / DC Converter 604 Inverter 605 Motor (Driven object) 606 Drive control unit 607 Arithmetic unit 608 Storage section

Claims

1. The support base and a first semiconductor element provided above the support layer; a second semiconductor element provided above the support layer; an insulator provided above the support layer and having at least a portion of the first semiconductor element and at least a portion of the second semiconductor element embedded therein; The support layer has a first protrusion, at least a portion of which is embedded in the insulator below the first semiconductor element.

2. The semiconductor device according to claim 1 , wherein the second semiconductor element has a thickness different from a thickness of the first semiconductor element.

3. The semiconductor device according to claim 1 , wherein said support layer has a second protrusion, at least a portion of which is embedded in said insulator below said second semiconductor element.

4. The semiconductor device according to claim 1 , wherein a portion of said second semiconductor element is located below a lower surface of said insulator.

5. 2. The semiconductor device according to claim 1, wherein a bottom surface of said second semiconductor element and a bottom surface of said insulator are disposed at the same position in the vertical direction.

6. the first semiconductor element has a semiconductor layer and an electrode disposed on a lower surface of the semiconductor layer; the support layer has a wiring layer and a connection portion that connects the wiring layer and the electrode, The semiconductor device according to claim 1 , wherein the first protrusion is the connection portion.

7. 7. The semiconductor device according to claim 6, wherein said wiring layer and said connection portion are integrally formed.

8. A power conversion device using the semiconductor device according to any one of claims 1 to 7.

9. A control system using the semiconductor device according to any one of claims 1 to 7.

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