LED array

Abstract

To provide a different approach to the growth and then fabrication of μLED arrays.SOLUTION: A method for manufacturing a light emitting diode (LED) array includes a step for forming a semiconductor layer (100) of group III nitride material, a step for forming a dielectric mask layer (104) covering the semiconductor layer, the dielectric mask layer having an array of holes through the dielectric mask layer, each exposing an area of the semiconductor layer, and a step for growing LED structures (108) in each of the holes.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to light emitting diodes (LEDs) and methods for manufacturing LED arrays. The present invention has particular application to arrays of LEDs on the micrometer scale. [Background technology]

[0002] There is a significantly growing demand for the development of III-nitride light-emitting diodes (LEDs) on the micrometer scale, also referred to as micro-sized LEDs or even micro-LEDs (μLEDs). Micro-LEDs are the main building blocks for new generation displays and visible light communication (VLC) applications. III-nitride μLEDs offer several unique features for display applications compared to organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs). Unlike LCDs, III-nitride microdisplays, in which μLEDs are the main building blocks, are self-emissive. Monochrome displays using μLEDs offer high resolution, high efficiency, and high contrast ratios. OLEDs are typically operated at current densities several orders of magnitude lower than semiconductor LEDs in order to maintain a reasonable lifetime. As a result, the luminance of OLEDs is relatively low, typically 3000 cd / m for full-color displays. 2 while III-nitride μLEDs are 10 5 cd / m 2 III-nitride μLEDs exhibit high luminance above 100 nm. Of course, III-nitride μLEDs inherently exhibit long operating lifetimes and chemical robustness in comparison to OLEDs. It is therefore expected that III-nitride μLEDs can potentially replace LCDs and OLEDs for high-resolution and high-brightness displays in a wide range of near-future applications, such as smartphones. In addition to display applications, μLEDs exhibit significantly reduced junction capacitance as a result of their reduced dimensions compared to broad-area LEDs, thus potentially leading to high-speed transmission with GHz modulation bandwidth in VLC applications.

[0003] Currently, III-nitride μLEDs are fabricated exclusively by means of a combination of standard photolithography methods and subsequent dry etching processes on standard III-nitride LED wafers, which is similar to the fabrication of conventional broad-area LEDs with typical device areas of 300 μm×300 μm or even larger dimensions (ZY Fan, JY Lin, and HX Jiang, J. Phys. D: Appl. Phys. 41, 094001 (2008); HX Jiang and JY Lin, Optical Express 21, A476 (2013)). The only major difference in device fabrication between broad-area LEDs and μLEDs is the device dimensions. Typically, μLEDs range in diameter from 50 μm to several micrometers.

[0004] There are several fundamental problems with current approaches to the fabrication of III-nitride μLEDs. First, dry etching processes, such as inductively coupled plasma (ICP) dry etching, have been widely used in the semiconductor industry to define both large area LED mesas and μLED mesas. Therefore, the surface and sidewall damage introduced by the dry etching process significantly enhances the nonradiative recombination rate (F. Olivier, A. Daami, C. Licitra, and F. Templier, Appl. Phys. Lett. 111, 022104 (2017); S.S. Konoplev, K.A. Bulashevich, and S.Y. Karpov, Phys. Status Solidi A 215, 1700508 (2017); W. Chen, G. Hu, J. Lin, J. Jiang, M. Liu, Y. Yang, G. Hu, Y. Lin, Z. Wu, Y. Liu, and B. Zhang, Appl. Phys. Express 8, 032102 (2015); C.-M. Yang, D.-S. Kim, Y.S. Park, J.-H. Lee, YS Lee, and J.-H. Lee, Opt. Photonics J. 2, 185 (2012); Y. Zhang, E. Guo, Z. Li, T Wei, J. Li, X. Ye, and G. Wang, IEEE Photonics Technol. Lett. 24, 243 (2012); P. Zuo, B. Zhao, S. Yan, G. Yue, H. Yang, Y. Li, H. Wu, Y. Jiang, H. Jia, J. Zhou, and H. Chen, Opt. Quantum Electron. 48, 1 (2016). This problem becomes more severe in LEDs with reduced dimensions, especially for μLEDs with large surface-to-bulk-volume ratios. So far, all reports indicate that the peak external quantum efficiency (EQE) decreases with decreasing μLED dimensions (D. Hwang, A. Mughal, C. D. Pynn, S. Nakamura, and S. P. DenBaars, Appl. Phys. Express 10, 032101 (2017); P. Zuo, B. Zhao, S. Yan, G. Yue, H. Yang, Y. Li, H. Wu, Y. Jiang, H. Jia, J. Zhou, and H. Chen, Opt. Quantum Electron.48, 1(2016);F.Olivier, S.Tirano, L.Dupre', B.Aventurier, C.Largeron, and F.Templier, J.Lumin.191, 112(2017);P.Tia n, JJDMcKendry, J.Herrnsdorf, S.Watson, R.Ferreira, IMWatson, E.Gu, AEKelly, and MDDawson, Appl.Phys.Lett.105, 171107 (2014)).

[0005] This reduction is due to surface recombination and sidewall damage of the mesa from dry etching that creates sidewall defects for non-radiative recombination. Sidewall passivation using dielectric materials can reduce the effects of plasma-induced damage in LEDs to some extent, but the improvement is minimal even when advanced atomic layer deposition (ALD) methods are used for surface passivation instead of the standard plasma-enhanced chemical vapor deposition (PECVD) methods.

[0006] Second, current approaches, which entail the use of a combination of standard photolithography and subsequent dry etching processes, usually lead to the waste of huge areas of the epiwafer. For example, to fabricate a μLED array with a diameter of 12 μm and a pitch distance of 15 μm (it is very challenging to further reduce the pitch distance by current photolithography methods), 50% material of the epiwafer needs to be etched away, which means that 50% of the epiwafer is wasted.

[0007] Third, future smart displays, including microdisplays and VLCs, need to be operated with ultra-high response speeds, and therefore ultra-fast electrical channels are needed for the interconnections between the LED driving transistors and the individual LED components.

[0008] Current μLED arrays are electrically connected by the n-GaN of a III-nitride LED wafer, where the typical fabrication procedure for a μLED array is to use a dry etching process to etch the LED wafer down to the n-GaN, which is the only electrical channel to connect all the μLEDs. Summary of the Invention [Problem to be solved by the invention]

[0009] It is therefore desirable to develop different approaches to the growth and then fabrication of μLED arrays to address these issues. Any new approach will have to be built on a scalable foundation to meet industrial demands. [Means for solving the problem]

[0010] The present invention provides a method of manufacturing a light emitting diode (LED) array, the method including the steps of forming a semiconductor layer of a III-nitride material, forming a dielectric mask layer overlying the semiconductor layer, the dielectric mask layer having an array of holes therethrough, each exposing an area of ​​the semiconductor layer, and growing an LED structure in each of the holes.

[0011] An LED structure can be grown on the exposed areas of the semiconductor layers. Growth is generally in an upward direction because no growth occurs from the dielectric sidewalls of the hole. The upward growth of the LED structure into the hole can therefore result in a layered LED structure, with each of the layers being generally flat or planar and of substantially constant thickness.

[0012] The semiconductor layer may be formed on a substrate of, for example, a III-nitride such as GaN, or of sapphire, silicon (Si), silicon carbide (SiC), or of glass.

[0013] Growing the LED structure in each of the holes may include growing an n-type layer, at least one active layer, and a p-type layer in each of the holes. The at least one active layer may be between the n-type layer and the p-type layer. The at least one active layer may include at least one quantum well layer, and may include multiple quantum well layers. These may be formed, for example, from InGaN or another suitable III-nitride material. The n-type layer and the p-type layer may further be composed of III-nitride materials such as GaN, InGaN, or AlGaN.

[0014] At least one active layer may have an upper surface that is below the upper surface of the dielectric layer. If only one quantum well layer is present, the upper surface is the upper surface of that quantum well layer. If multiple quantum well layers are present, the upper surface is the upper surface of the uppermost quantum well layer. The upward direction may be defined as the direction of growth of the semiconductor layers and / or of the LED structure.

[0015] Forming the dielectric mask layer may include growing a layer of dielectric material, forming a mask over the dielectric mask layer, e.g., using photolithography, and etching an array of holes into the layer of dielectric material using the mask. Alternatively, the dielectric layer may be grown around areas where holes will later be formed, e.g., using a mask formed during growth of the dielectric layer, e.g., by photolithography with subsequent growth and / or etching.

[0016] The method may further include the step of etching each of the exposed areas of the semiconductor layer prior to the step of growing an LED structure in each of the holes.

[0017] The semiconductor layer may provide a common contact for all of the LED structures.

[0018] The semiconductor layer may be doped. For example, the semiconductor layer may include a single layer of n-type or p-type III-nitride material. Alternatively, the semiconductor layer may include a first sub-layer and a second sub-layer, the heterointerface between which is arranged to form a two-dimensional charge carrier gas at the heterointerface. The sub-layers may form a buffer layer and a barrier layer. The two-dimensional charge carrier gas may be, for example, a two-dimensional electron gas (2DEG). Two-dimensional hole gases (2DHG) may also be used, but typically these have a lower charge carrier density and / or mobility. For example, a heterostructure including a layer of GaN and a layer of AlGaN or InGaN, or more generally two layers of AlGaN with different Al content or two layers of InGaN with different In content, may be formed by doping the two layers. It is well known that a 2DEG can form at the interface between the AlGaN layer and the InGaN layer, and the electron density in the 2DEG varies with several factors, including the Al content in the AlGaN layer or the In content in the InGaN layer. Other III-nitride heterointerfaces can be used with the same effect.

[0019] The method may further include forming one or more contact layer areas covering the LED structures. The, or each, contact layer area may extend beyond at least one of the LED structures so as to be in electrical contact with at least one of the LED structures. The contact layer areas may be electrically insulated from one another.

[0020] The holes, and therefore the LED structures, may be arranged in a regular array. The array may be a square array, or it may be a rectangular array or a hexagonal array. The array may have a pitch, i.e. the distance between the centers of the nearest pairs of holes or LEDs, of 4 μm to 500 μm. The holes, and therefore also the LED structures, may have a maximum diameter of 1 to 500 μm, or 5 to 500 μm.

[0021] The present invention further provides for manufacturing an LED display comprising an LED array according to the present invention.

[0022] The present invention further provides an LED array including a semiconductor layer, a dielectric layer extending beyond the semiconductor layer and having an array of holes therethrough, and an LED device formed in each of the holes.

[0023] The invention further provides an LED display comprising and an LED array according to the invention. [Brief description of the drawings]

[0024] [Figure 1] Figure 1a shows an as-grown template formed in a process according to a first embodiment of the invention, Figure 1b shows the template of Figure 1a with a masking pattern formed in a mask layer of the template, Figure 1c shows the template of Figure 1a with micro LEDs grown in holes in the mask layer, and Figure 1d shows the template of Figure 1c with electrical contacts formed on the template. [Diagram 2] Figure 2a shows an as-grown template formed in a process according to a second embodiment of the invention, Figure 2b shows the template of Figure 2a with a masking pattern formed in a mask layer of the template, Figure 2c shows the template of Figure 2a with micro LEDs grown in holes in the mask layer, and Figure 2d shows the template of Figure 2c with electrical contacts formed on the template. [Diagram 3] FIG. 2c is a cross-sectional view through the LED structure of the template of FIG. 2d. [Figure 4] FIG. 2 is a scanning electron microscope image of an LED array according to an embodiment of the present invention. [Diagram 5]FIG. 2 shows the electroluminescence spectrum of an LED array according to an embodiment of the present invention. [Figure 6] FIG. 13 illustrates the variation of internal quantum efficiency of an embodiment of the present invention as a function of LED diameter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Referring to FIG. 1a, in a first embodiment of the present invention, a semiconductor layer, e.g., a standard An n-type GaN (n-GaN) layer 100 is initially grown on a substrate 102. The substrate 102 can be a GaN substrate or any foreign substrate such as sapphire, silicon (Si), silicon carbide (SiC), or even glass. The GaN layer 100 can be grown by means of any standard GaN growth method using either metalorganic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), or any other suitable growth method. The resulting "as-grown n-GaN template" can have a thickness above 10 μm, but typically the thickness is in the range of 500 nm to 10 μm. Subsequently, a dielectric layer 104, such as silicon dioxide (SiO2) or silicon nitride (SiN), or any other suitable dielectric material, is deposited on the n-GaN layer 100 by using PECVD or any other suitable deposition method. The thickness of the dielectric layer may be in the range of 20 nm to 500 μm.

[0026] Referring to FIG. 1b, an array of holes 106 is then formed in the dielectric layer 104. The holes 106 are typically on the micrometer scale, hence they are referred to as microholes. This can be done by means of photolithography and then an etching process, which can be dry or wet etching. The use of photolithography is advantageous because it allows the holes, and hence the LEDs formed in those holes, to be formed precisely with the desired location, shape and size. In forming the microholes 106, the dielectric layer 104 is etched through the entire thickness of the dielectric layer 104, down to the upper surface of the n-GaN layer 100. The microhole diameter can be 1 μm to 500 μm, or 3 μm to 500 μm, and the pitch distance, i.e. the distance between the centers of the nearest neighboring microholes, can be, for example, 4 μm to 500 μm. Further etching of the n-GaN layer 100 only in the micro-hole area can be performed using the remaining dielectric layer 104 as a mask. The n-GaN etch depth can be from zero (meaning no GaN etching) to 10 μm depending on the n-GaN layer thickness. Typically, the optimal etching method or conditions will be different for the n-GaN layer than for the dielectric layer. For example, SF6 etching can be used to etch the dielectric layer 104 but will not etch the n-GaN layer 100. Therefore, etching all the way through the dielectric layer 104 and stopping at the top surface of the semiconductor layer 100 is easy to achieve. This further has advantages for the quality of the LED structure grown in the hole 106.

[0027] The holes 106 are, in the embodiment shown, rounded, specifically circular, in cross-section, although other cross-sections, for example oval or square, may be used.

[0028] Next, referring to FIG. 1c, a standard III-nitride LED structure is grown on the exposed areas of the GaN layer 100. However, because only discrete areas of the GaN layer 100 are exposed by the micro-holes 106 in the dielectric layer or mask, the LED structure is formed as an array of discrete LEDs 108 separated by remaining portions of the dielectric layer 104 between the micro-holes 106. The LED structures 108 are grown by either MOVPE or MBE methods, or any other suitable growth method. Growth occurs from the exposed areas of the GaN (or other semiconductor) layer upwards, and not from the sidewalls of the holes 106. Thus, a layered LED structure can be built up inside each of the holes 106, with each of the layers being substantially flat or planar. The LED structure can include an n-GaN layer 110, an active region 112, and then a final p-doped GaN layer 114. The active region 112 may include an InGaN prelayer, an InGaN-based multiple quantum well (MQW), and a thin p-type AlGaN layer (not shown) as a blocking layer. An example of an LED structure is described in more detail below with reference to FIG. 3. As mentioned above, due to the dielectric mask 104, the LED structure is shown in FIG. 1c, forming a μLED array. As shown in FIG. 1, the nanoparticles can be grown only within the micropores 106.

[0029] It is important that the topmost layer of InGaN MQWs 112 should not extend above the upper surface of the dielectric layer 104, which may result in shorting effects after the template is fabricated into the final μLED array. It is also important that the overgrown n-GaN 110 in each of the micro-hole areas directly contacts the n-GaN layer 100 in the unetched portion of the template below the dielectric mask 104, such that all the individual μLEDs are electrically connected to each other by the n-GaN layer 100 in the unetched portion below the dielectric mask 104.

[0030] 1d, once the LED array structure is completed, further device fabrication is performed, including forming electrical contacts to the array. For example, a top contact layer 116 may be formed over the dielectric mask layer 104 and over the top p-GaN layer of the individual micro LED devices 108. The top contact layer 116 thus forms a common p-contact for all of the LED devices 108. The top contact layer 116 may be formed from ITO or a Ni / Au alloy. An anode 118 may then be formed on the p-contact layer 116. For example, a portion of the dielectric layer 104 may be etched away, and then a portion of the LED structure on the etched dielectric layer section may be etched further down to the n-GaN, which exposes an area 120 of the n-GaN 100, and a cathode 122 may be formed on the exposed area 120 of the n-GaN.

[0031] If an LED array is used in a display, the continuous contact layer 116 can be replaced by several separate contact layer areas, each covering a respective group of LED structures 108. Each group can include only one LED structure 108 or the group can include multiple LED structures, for example 2 or 3 or 4. The contact layer areas are electrically isolated from each other, for example by being spaced apart from each other. This allows each group of LED structures to be addressable, i.e. switched on and off independently of the others. In particular, each of the contact layer areas can be connected to a respective switching device to form a display in which each LED or group of LEDs forms a pixel. The precise control of the location and size and shape of the LED structures provided by photolithography is important in ensuring that the contact layer areas can be correctly aligned with the LED structures to allow them to be individually addressed.

[0032] Because overgrowth of the LED structure occurs only in the micro-hole areas 106, it has been found that the growth rate during formation of the LED device is significantly increased, in some cases about four times faster, compared to that grown under identical conditions on a planar template without any patterning features.

[0033] It will be appreciated that various modifications to the above described embodiments are possible. For example, in one variation, the structure is reversed, a p-GaN layer is grown on a substrate and covered with a dielectric layer, and then the p-GaN layer of the LED device 108 is formed first, followed by the multiple quantum well layer, and then the n-GaN layer. An n-contact layer is then formed above the top surface of the dielectric layer in place of the p-contact layer, and the positions of the anode and cathode are reversed.

[0034] In the configurations of FIGS. 1a to 1d, the overgrown n-GaN 110 in the micro-holes 106 ensures that all the individual μLEDs 108 are interconnected by the n-GaN layer 100. To be electrically connected, the n-GaN of the unetched portion of the n-GaN layer 100 under the dielectric mask 104 must match. Instead of using the n-GaN 100 of the unetched portion of the n-GaN layer 100 under the dielectric mask 104 as the electrically connected channel, in a further embodiment, a III-nitride heterostructure with a two-dimensional electron gas (2DEG) at the heterojunction is used as the semiconductor layer instead of the n-GaN layer. In this embodiment, a standard AlGaN / GaN HEMT structure is used. The electron gas with high sheet carried density and high electron mobility (2DEG) formed at the interface between the AlGaN barrier and the GaN buffer of the HEMT structure is used as the electrically connected channel.

[0035] 2a to 2d, to manufacture such a device, a standard AlGaN / GaN HEMT structure is first grown on a GaN substrate or any foreign substrate such as sapphire, Si, SiC, or even glass by means of any standard GaN growth technique using either MOVPE or MBE methods or any other epitaxial method. Specifically, in this embodiment, a GaN layer 200 forming a buffer layer is grown on a substrate 202, and then an AlGaN layer 201 forming a barrier layer is grown on the GaN layer 200. This structure is referred to herein as the "as-grown HEMT template". Subsequently, a dielectric layer 204, such as SiO2 or SiN or any other dielectric material, for example with a thickness in the range of 2 nm to 500 μm, is deposited on the as-grown HEMT template by using PECVD or any other suitable deposition method. After that, by means of photolithography and then etching processes (which may be dry or wet etching), the dielectric layer 204 is etched down to the surface of the HEMT structure to form a micro-hole array 206 in the dielectric layer 204, where the micro-hole diameter may be from a few μm to 500 μm and the pitch distance between adjacent hole centers may be in the range of 10 μm to 500 μm. Further etching of the as-grown HEMT in the micro-hole area may be performed using the remaining area of ​​the dielectric layer 204 as a mask. The as-grown HEMT etch depth may be from zero (meaning no etching at all) to 10 μm depending on the AlGaN barrier position of the as-grown HEMT template. However, in general, the etching will extend downwards at least as far as the heterointerface between the two layers 200, 201 of the as-grown HEMT structure to provide good electrical contact between each of the LED structures and the 2DEG.

[0036] Next, a standard III-nitride LED structure is grown on the dielectric mask patterned HEMT template characterized by micro-holes by either MOVPE or MBE methods, or any other epitaxial method. This may include, for example, growing an n-GaN layer, an InGaN pre-layer, an InGaN-based MQW as the active region, and then a thin p-type AlGaN as a blocking layer, and then a final p-doped GaN. Due to the dielectric mask, the LED structure grows only in the micro-holes 206, forming discrete micro-LED devices 208 in the micro-holes, as shown in FIG. 2c.

[0037] Similar to the embodiment of FIGS. 1a to 1d, the important point is that the upper surface of the InGaN MQWs 212 should be below the upper surface of the dielectric layer 204 to avoid shorting effects after fabrication into the final μLED array.

[0038] Referring to FIG. 3, the LED structures in the LED arrays of FIGS. 1a-1d and 2a-2d may have any suitable structure, but in one example, the LED structures may include an n-GaN layer 310, an InGaN preliminary layer 316 formed above the n-GaN layer 310, several InGaN quantum well layers 312 formed above the preliminary layer 316, a p-doped blocking layer 318, for example of p-AlGaN, and then a p-GaN layer 314. It will be appreciated that this structure may be varied in several ways. As pointed out above, it is preferred that the top surface of the uppermost one of the quantum well layers 312 is below the top surface of the dielectric layer. It is even more preferred that the top surface of the blocking layer 318 is also below the top surface of the dielectric layer.

[0039] Another important point is that the overgrown n-GaN in the micro-hole area directly contacts the interface between the AlGaN barrier and the GaN buffer of the as-grown HEMT structure in the unetched portion below the dielectric mask 204, such that all individual μLEDs are electrically connected by the 2DEG formed at the interface between the AlGaN barrier and the GaN buffer of the HEMT structure (i.e., the unetched portion) below the dielectric mask. Once the LED structure is completed, any suitable standard device fabrication can be performed similar to the embodiment of Figures 1a to 1d, where each device will include several individual μLED components as shown in Figure 2d, where all individual μLEDs 208 share a common p-contact 216, separated by the remaining dielectric mask 204 to eliminate shorts in each device.

[0040] It should be noted that in the embodiment of Figures 2a-2d, prior to any standard LED fabrication steps, selective etching of the dielectric mask 204 may be required to expose a portion of the surface of the HEMT structure, where the cathode contact 222 is fabricated on the exposed HEMT surface, as shown in Figure 2d. The selective etch may be a dry etch or a wet etch.

[0041] As an example, FIG. 4 shows a typical scanning microscope image of a μLED array epiwafer, fabricated as described above, where each μLED has a diameter of 40 μm.

[0042] As an example, FIG. 5 shows the electroluminescence spectrum of a μLED with a diameter of 40 μm as a function of the injection current.

[0043] FIG. 6 shows the internal quantum efficiency (IQE) of μLEDs formed as described above, measured as a function of μLED diameter. The figure shows that the IQE of the LED increases by decreasing the μLED diameter. The results are different from those of all previous μLEDs fabricated using conventional techniques. This suggests that the method described above avoided the dry-etching induced sidewall damage typically produced during conventional fabrication processes.

Claims

1. 1. A method of manufacturing a light emitting diode (LED) array, the method comprising: forming a semiconductor layer of a Group III-nitride material; forming a dielectric mask layer overlying the semiconductor layer, the dielectric mask layer having an array of holes therethrough, each exposing an area of ​​the semiconductor layer; and growing an LED structure in each of the holes.

2. 2. The method of claim 1, wherein growing an LED structure in each of the holes comprises growing an n-type layer, at least one active layer, and a p-type layer in each of the holes.

3. The method of claim 1 or 2, wherein the at least one active layer has an upper surface that is below a top surface of the dielectric layer.

4. 4. The method of claim 1, wherein the step of forming the dielectric mask layer comprises growing a layer of dielectric material and etching the array of holes into the layer of dielectric material.

5. 5. The method of claim 1, further comprising the step of etching each of the exposed areas of the semiconductor layer prior to the step of growing the LED structure in each of the holes.

6. 6. The method of claim 1, wherein the semiconductor layer provides a common contact for all of the LED structures.

7. The method of claim 1 , wherein the semiconductor layer is doped.

8. 7. The method of claim 1, wherein the semiconductor layer comprises a first sublayer and a second sublayer, the heterointerface between the first sublayer and the second sublayer being arranged to form a two-dimensional charge carrier gas.

9. 9. The method of claim 1, wherein the LED structures are micro LED structures and the array is a regular array with a pitch of 4 μm to 500 μm.

10. 10. The method of claim 1, further comprising forming a plurality of contact layer areas overlying the LED structures, each of the contact layer areas making electrical contact with a respective group of the LED structures.

11. 11. A method of manufacturing an LED display, comprising: manufacturing an LED array including the mask layer and the LED structure by the method of any one of claims 1 to 10; and manufacturing an LED display including the LED array.

12. 1. An LED array comprising: a semiconductor layer; a dielectric layer extending above said semiconductor layer and having an array of holes extending therethrough; and an LED device formed in each of said holes.

13. 13. The LED array of claim 12, wherein each of the LED devices includes an n-type layer, at least one active layer, and a p-type layer.

14. 14. The LED array of claim 12 or 13, wherein the at least one active layer has an upper surface that is below a top surface of the dielectric layer.

15. 15. An LED array according to any one of claims 12 to 14, wherein the semiconductor layer provides a common contact for all of the LED structures.

16. 16. The LED array of claim 12, wherein the semiconductor layer is doped.

17. 16. The LED array of claim 12, wherein the semiconductor layer comprises a first sublayer and a second sublayer, a heterointerface between the first sublayer and the second sublayer arranged to form a two-dimensional charge carrier gas.

18. 18. The LED array of claim 12, wherein the LED structures are micro LED structures and the array is a regular array with a pitch of 4 μm to 500 μm.

19. 19. The LED array of claim 12, further comprising a plurality of contact layer sections extending over the LED structures, each of the contact layer sections being in electrical contact with a respective group of the LED structures.

20. 20. An LED display comprising an LED array according to any one of claims 12 to 19.

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