Semiconductor device

Abstract

To provide a transistor with stable electric characteristics, a transistor with small current at non-conduction, a transistor with large current at conduction, a semiconductor device including the transistor, or a strong semiconductor device.SOLUTION: A semiconductor device includes a first insulator with excess oxygen, a semiconductor on the first insulator, a second insulator on the semiconductor, and a conductor including a region overlapping with the semiconductor through the second insulator. Between the first insulator and the semiconductor, a region containing boron or phosphorus is provided.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. In particular, The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a storage Alternatively, the present invention relates to a semiconductor device, a semiconductor device, a display device, a light-emitting device, The present invention relates to a method for manufacturing a lighting device, a power storage device, a memory device, or a processor. A method for driving a display device, a light-emitting device, a lighting device, a power storage device, a storage device, or a processor Regarding.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include a semiconductor device. [Background technology]

[0003] Technology that uses semiconductors on substrates with insulating surfaces to construct transistors has been attracting attention. Such transistors are widely used in semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor that can be used for transistors.

[0004] Silicon used as a semiconductor in transistors is either amorphous silicon or polycrystalline silicon depending on the application. For example, silicon nitride, single crystal silicon, etc. are used to make large display devices. When applied to transistors, amorphous silicon has established film formation technology for large-area substrates. On the other hand, it is preferable to use a transistor that constitutes a high-performance display device with an integrated driving circuit. When applied to transistors, it is possible to fabricate polycrystalline transistors with high field effect mobility. Silicon is preferably used. It is also suitable for use in transistors that make up integrated circuits. In this case, it is preferable to use single crystal silicon, which has a higher field effect mobility. Silicon is shaped by subjecting amorphous silicon to high-temperature heat treatment or laser light treatment. It is known how to achieve this.

[0005] In recent years, oxide semiconductors have been attracting attention. Since the film can be formed using the above method, it can be used as a semiconductor for transistors that constitute large display devices. In addition, a transistor including an oxide semiconductor has high field-effect mobility. This makes it possible to realize a highly functional display device with an integrated driving circuit. It is possible to improve and reuse some of the transistor production equipment currently in use, so capital investment is There is also the advantage of being able to reduce

[0006] As a method for imparting stable electrical characteristics to a transistor using an oxide semiconductor, A technology for doping oxygen into an insulator that comes into contact with a body has been disclosed (see Patent Document 1). By using the technique disclosed in Reference 1, oxygen vacancies in an oxide semiconductor can be reduced. As a result, the variation in electrical characteristics of transistors using oxide semiconductors can be reduced, and reliability can be improved. The reliability can be improved.

[0007] Meanwhile, a transistor including an oxide semiconductor has a large leakage current in a non-conducting state. For example, the leakage current characteristics of a transistor using an oxide semiconductor are known to be small. A low power consumption CPU that utilizes this technology has been disclosed (see Patent Document 2).

[0008] In addition, by forming a well-type potential in the active layer made of semiconductor, a high electric field effect It has been disclosed that a transistor having high mobility can be obtained (see Patent Document 3). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2011-243974 A [Patent Document 2] JP 2012-257187 A [Patent Document 3] JP 2012-59860 A Summary of the Invention [Problem to be solved by the invention]

[0010] It is an object of the present invention to provide a transistor having stable electrical characteristics. It is an object of the present invention to provide a transistor that has a small current when it is turned on. It is an object of the present invention to provide a transistor having a large current. Another object of the present invention is to provide a semiconductor device having a high resistance. Another object of the present invention is to provide a novel semiconductor device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] (1) One aspect of the present invention is a semiconductor device comprising a first insulator having excess oxygen and a semiconductor on the first insulator. a second insulator on the semiconductor, and a conductor having a region overlapping the semiconductor via the second insulator. and a semiconductor having a region containing boron or phosphorus between the first insulator and the semiconductor. It is a body device.

[0013] (2) Alternatively, in one embodiment of the present invention, the region containing boron or phosphorus does not overlap with the conductor. The semiconductor device according to (1) has a region.

[0014] (3) Alternatively, one embodiment of the present invention is a first insulator having excess oxygen and a A semiconductor, a first conductor and a second conductor on the semiconductor, and a semiconductor, a first conductor and a second conductor on the semiconductor and a second insulator on the second conductor, and a region overlapping the semiconductor through the second insulator. and a third conductor having no area overlapping with the first conductor, The semiconductor device has a region containing boron or phosphorus between a conductor.

[0015] (4) Alternatively, in one embodiment of the present invention, the region containing boron or phosphorus overlaps with the third conductor. The semiconductor device according to claim 3, further comprising a region where the insulating film is not formed.

[0016] (5) Alternatively, in one aspect of the present invention, the first insulator is silicon oxide or silicon oxynitride. The semiconductor device according to any one of (1) to (4) is a semiconductor device.

[0017] (6) Alternatively, in one embodiment of the present invention, the semiconductor includes any one of (1) to ( 5) is a semiconductor device according to the present invention.

[0018] Note that in the semiconductor device of one embodiment of the present invention, the oxide semiconductor may be replaced with another semiconductor. It's okay. Effect of the Invention

[0019] It is possible to provide a transistor having stable electrical characteristics. Alternatively, it is possible to provide a transistor that has a large current when conducting. Alternatively, a semiconductor device having the transistor can be provided. Alternatively, a robust semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. Locations can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 7]1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] FIG. 2 is a diagram for explaining ion incidence. [Figure 15] 4A and 4B are schematic cross-sectional views illustrating the diffusion of excess oxygen inside a semiconductor device. [Figure 16] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a circuit diagram of a memory device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a block diagram of an RF tag according to an embodiment of the present invention. [Figure 20] 1A to 1C are diagrams illustrating examples of use of an RF tag according to one embodiment of the present invention. [Figure 21] FIG. 2 is a block diagram showing a CPU according to an embodiment of the present invention. [Figure 22] FIG. 1 is a circuit diagram of a memory element according to one embodiment of the present invention. [Figure 23] 1A and 1B are a top view and a circuit diagram of a display device according to one embodiment of the present invention. [Figure 24] 1A and 1B are diagrams illustrating a display module according to one embodiment of the present invention. [Diagram 25] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 26] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 27]Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 28] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 29] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 30] Electron diffraction pattern of CAAC-OS. [Diagram 31] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 32] 1A and 1B are cross-sectional views showing stacked layers of semiconductors and diagrams showing band structures. [Diagram 33] FIG. 1 shows the relationship between substrate temperature and ion intensity using TDS. [Diagram 34] FIG. 13 is a graph showing the relationship between the phosphorus ion implantation concentration and the amount of released oxygen. [Diagram 35] FIG. 13 is a graph showing the relationship between etching depth and the amount of released oxygen. [Diagram 36] FIG. 1 shows the relationship between substrate temperature and ion intensity using TDS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0023] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0024] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". .

[0025] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. However, the ordinal numbers used to identify an aspect of the present invention may not be consistent.

[0026] Even if a material is described as a "semiconductor," if its electrical conductivity is sufficiently low, it may be considered an "insulator." In addition, the boundary between "semiconductor" and "insulator" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguishable from "insulator." Similarly, the term "insulator" used in this specification may be interpreted as "semiconductor." " This can sometimes be rephrased as ".

[0027] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it should be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguished from "conductor." Similarly, the term "conductor" used in this specification may be used interchangeably with "semiconductor." " This can sometimes be rephrased as ".

[0028] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. Also, if the semiconductor is silicon, impurities that change the properties of the semiconductor may occur. Examples of the elements include oxygen, elements of Group 1 except hydrogen, elements of Group 2, elements of Group 13, elements of Group 15, Group elements, etc.

[0029] In the following embodiments, the semiconductor is an oxide semiconductor. However, the present invention is not limited to this. For example, the semiconductor may have a polycrystalline structure, a single crystalline structure, etc. Alternatively, a material having a strain, such as strained silicon, germanium, etc., may be used. Alternatively, a semiconductor that can be used as the semiconductor may be gallium arsenide, which is applicable to HEMT. Aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide Silicon germanium, etc. may be used. By using these semiconductors, high speed operation The transistor can be suitable for performing the above-mentioned operations.

[0030] In this specification, when it is stated that A has a region of concentration B, for example, If the entire depth direction of a region has a concentration of B, the average If the value is concentration B, then if the median value in the depth direction in a region of A is concentration B, then A If the maximum value in the depth direction in a region of A is concentration B, then If the minimum value in the direction is concentration B, then the convergence value in the depth direction in a region of A is concentration B. This includes cases where the area in which a reliable value of A can be obtained through measurement is concentration B.

[0031] In this specification, A has an area of ​​size B, length B, thickness B, width B or distance B. For example, when describing an area of ​​A, the whole area has size B, length B, and thickness B. , width B or distance B, the average value of A in a certain area has size B, length B, thickness If A has size B, width B or distance B, then the median value of an area of ​​A has size B, length B, thickness B If A has a length B, width B, or distance B, then the maximum value in a certain area of ​​A has a size B, length B, If thickness B, width B, or distance B, the minimum value of an area of ​​A is size B, length B , thickness B, width B or distance B, the convergence value in a region of A is the size B, length When B, thickness B, width B or distance B is used, a certain value of A itself can be obtained by measurement. This includes cases where the area has size B, length B, thickness B, width B or distance B, etc.

[0032] <Transistor structure 1> FIG. 1A is an example of a top view of a transistor according to one embodiment of the present invention. An example of a cross-sectional view corresponding to the dashed dotted line A1-A2 and the dashed dotted line A3-A4 is shown in FIG. In FIG. 1(A), some parts such as insulators are omitted for ease of understanding.

[0033] The transistor shown in FIG. 1A and FIG. 1B includes a conductor 413 on a substrate 400 and a An insulator 402 having a protrusion on the plate 400 and on the conductor 413, and a The semiconductor 406a, the semiconductor 406b on the semiconductor 406a, and the semiconductor 406b on the semiconductor 406b. 406c, an insulator 412 on the semiconductor 406c, a conductor 404 on the insulator 412, and an insulator and an insulator 408 on the insulator 402, the semiconductor 406b, and the conductor 404. Although the conductor 413 is a part of a transistor here, the present invention is not limited to this. For example, the conductor 413 may be a component separate from a transistor.

[0034] Note that the semiconductor 406b functions as a channel formation region of a transistor. The conductor 404 is a first gate electrode (also referred to as a front gate electrode) of a transistor. The conductor 413 functions as a second gate electrode (backgate) of the transistor. The insulator 408 also functions as a barrier layer. The insulator 408 has a function of blocking oxygen and / or hydrogen, for example. Alternatively, the insulator 408 may be, for example, a semiconductor 406a or / and a semiconductor 406b. It has a higher ability to block oxygen and / or hydrogen than 06c.

[0035] The transistor receives the conductors 424a and 424b through the conductors 426a and 426b, etc. and the conductor 424b may be electrically connected to the conductor 426a. The conductor 426b is connected to the insulator 408, the insulator 418 on the insulator 408, and the insulator 418 on the insulator 408. 18 and the source of the transistor through the openings provided in the insulator 428. The conductor 426a and the drain region are electrically connected to each other. In the example shown, the conductor 426b and the region 423 are in contact with each other, but the present invention is not limited to this. For example, the conductor 426a and the conductor 426b do not need to be in contact with the region 423. In addition, the conductor 424a and the conductor 424b function as, for example, wiring of a semiconductor device. Yes.

[0036] In addition, in the A3-A4 cross section, the semiconductor 406c is at least the upper surface and In addition, the conductor 404 is in contact with the semiconductor 406c and the side surface in the A3-A4 cross section. The conductor 41 faces the upper surface and the side surface of the semiconductor 406b through the insulator 412. The lower surface of the semiconductor 406b is exposed through the insulator 402. The semiconductor 406c may not be included. It is not necessary to have 408.

[0037] In FIG. 1B, the transistor is formed of an insulator 402 and a semiconductor 40 The region 423 of the semiconductor 406a is larger than the other regions. In addition, the region 423 of the insulator 402 has a lower resistance than the other regions. The region 423 is an area that has a high ability to block oxygen. Elements with high bond energy with oxygen, elements with high reactivity with oxygen, or elements with high reactivity with oxygen Region 423 is a region that contains elements that react to form stable oxides. , boron, carbon, nitrogen, neon, magnesium, aluminum, silicon, phosphorus, Cr, Calcium, Titanium, Vanadium, Chromium, Manganese, Iron, Cobalt, Germanium , krypton, strontium, yttrium, zirconium, niobium, molybdenum, Xenon, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten The region 423 contains one or more selected from the group consisting of boron and phosphorus. The region 423 is, for example, 5×10 19 atoms / cm 3 End , preferably 1 x 10 20 atoms / cm 3 More preferably, 2×10 20 at oms / cm 3 More preferably, 5×10 20 atoms / cm 3 The area includes more than In this specification, the above elements are sometimes referred to as impurities.

[0038] In the following description, the semiconductors 406a, 406b, and 406c are oxide semiconductors. A case where the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c are may be a semiconductor other than an oxide semiconductor.

[0039] Note that the insulator 402 is an insulator containing excess oxygen.

[0040] For example, an insulator containing excess oxygen is an insulator that has the function of releasing oxygen by heat treatment. For example, silicon oxide containing excess oxygen releases oxygen when subjected to heat treatment. Therefore, the insulator 402 is a silicon oxide that can move oxygen through the film. That is, the insulator 402 may be an insulator having oxygen permeability. For example, The insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a.

[0041] The insulator containing excess oxygen may have a function of reducing oxygen vacancies in the semiconductor 406b. In the semiconductor 406b, oxygen vacancies form DOS, which become hole traps, etc. When hydrogen enters the oxygen vacancy site, it can generate electrons as carriers. Therefore, by reducing oxygen vacancies in the semiconductor 406b, the transistor becomes stable. It is possible to impart excellent electrical properties.

[0042] Here, the insulators that release oxygen when heated are those that, as determined by TDS analysis, are those that are heated to 100°C or higher and 70°C or lower. 1×10 in the range of surface temperatures below 0℃ or between 100℃ and 500℃ 18 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 It may even release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0043] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0044] The total amount of gas released when the measurement sample was subjected to TDS analysis was calculated based on the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can then be calculated.

[0045] For example, the results of a TDS analysis of a silicon substrate containing a given density of hydrogen as a standard sample, From the TDS analysis results of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is expressed as follows: Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the CH3OH is derived from oxygen molecules. The possibility of this is low, so it is not considered here. The abundance of oxygen atoms and oxygen molecules containing the oxygen atom with mass number 18 in nature is also The rate is so small that it is not taken into consideration.

[0046] N O2 =N H2 / S H2 ×S O2 ×α

[0047] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Epson Corporation was used. ×10 16 atoms / cm 2 The measurements were performed using a silicon substrate containing hydrogen atoms.

[0048] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It is possible to estimate even if

[0049] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released in terms of oxygen atoms is This is twice the amount released.

[0050] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators that contain peroxide radicals have an ESR g value of 2. It may also have an asymmetric signal near 01.

[0051] Alternatively, an insulator containing excess oxygen can be called silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon atoms per unit volume. The number of electrons and oxygen atoms was measured by Rutherford backscattering (RBS). The values ​​were measured using ion scattering spectrometry (ICS).

[0052] As shown in FIG. 1B, the semiconductor 406b is electrically connected by the electric field of the conductor 404. (The electric field generated by the conductor can electrically surround the semiconductor.) The structure of the star is called the surrounded channel (s-channel) structure. As a result, a channel may be formed in the bulk of the semiconductor 406b. The s-channel structure allows a large current to flow between the source and drain of the transistor. This makes it possible to increase the current (on-state current) when the semiconductor is conductive.

[0053] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, a semiconductor having the transistor can be The device can be a highly integrated, high-density semiconductor device. The transistor has a channel length of preferably 40 nm or less, more preferably 30 nm or less. More preferably, the region is 20 nm or less, and the transistor preferably has a channel width of Preferably, the thickness is 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. has.

[0054] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on-state). or a source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is a value, a maximum value, or a minimum value in the region where the channel is formed. Or the average value.

[0055] The channel width is, for example, the width of the semiconductor (or transistor) when it is in the on-state in a top view. The region where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows) forms a channel. The length of the region where the source and drain face each other is called the length of the region where the source and drain face each other. In one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. In this specification, the channel width is any one of the values ​​in the region where the channel is formed, This can be the maximum, minimum or average value.

[0056] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0057] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0058] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0059] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0060] In addition, a voltage lower or higher than that of the source electrode is applied to the conductor 413, The threshold voltage of the transistor may be shifted in a positive or negative direction. By shifting the threshold voltage of the transistor in the positive direction, the transistor In some cases, a normally-off state in which the transistor is non-conductive (off state) can be realized. The voltage applied to the conductor 413 may be variable or fixed. When the voltage applied to the conductor 413 is made variable, a circuit for controlling the voltage is connected to the conductor 413 and The terminating resistor may be connected to the

[0061] Next, regarding semiconductors applicable to the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, etc. He explains.

[0062] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, the inclusion of indium increases carrier mobility (electron mobility). 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. , yttrium, or tin. Other elements that can be used for M include ho, Uranium, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, Molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. However, as the element M, a combination of two or more of the above elements may be used in some cases. The element M is, for example, an element having a high bond energy with oxygen. The element M is an element having a higher energy than indium. Alternatively, the element M is, for example, an oxide semiconductor. The semiconductor 406b is an element that has the function of increasing the energy gap of the It is preferable that the oxide semiconductor contains zinc. When the oxide semiconductor contains zinc, it may be easily crystallized.

[0063] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 6b is a zinc-free oxide such as zinc tin oxide or gallium tin oxide. Oxide semiconductors containing lead, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. That's okay.

[0064] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The excitation voltage is preferably from 3 eV to 3.5 eV, and more preferably from 3 eV to 3.8 eV.

[0065] For example, the semiconductor 406a and the semiconductor 406c contain oxygen other than that constituting the semiconductor 406b. It is an oxide semiconductor composed of one or more elements. Semiconductor 406 The semiconductor 406a and b are made of one or more elements other than oxygen. Since the semiconductor 406c is formed, the interface between the semiconductor 406a and the semiconductor 406b and the semiconductor An interface state is unlikely to be formed at the interface between the conductor 406b and the semiconductor 406c.

[0066] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c each contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, the sum of In and M is preferably When 100 atomic %, In is preferably less than 50 atomic % and M is preferably less than 50 atomic %. atomic % or more, more preferably In is less than 25 atomic %, and M is 75 atomic % or more. When the semiconductor 406b is an In-M-Zn oxide, In and When the sum of M is 100 atomic %, In is preferably 25 atomic % or more, M is less than 75 atomic %, more preferably In is 34 atomic % or more, and M is 6 When the semiconductor 406c is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 50 atomic %. %, M is 50 atomic % or more, and more preferably In is less than 25 atomic %. The semiconductor 406c is of the same type as the semiconductor 406a. The oxide of the above may also be used.

[0067] The semiconductor 406b is an oxide having a higher electron affinity than the semiconductors 406a and 406c. For example, the semiconductor 406b is made of a material selected from the semiconductors 406a and 406c. The electron affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. It is more preferable to use an oxide having a larger molecular weight by 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0068] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor 406c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and Preferably, the ratio is 90% or more.

[0069] At this time, when a gate voltage is applied, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c Of these, a channel is formed in the semiconductor 406b having the larger electron affinity.

[0070] Here, between the semiconductor 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the semiconductor 406c, The semiconductor 406b may have a mixed region of the semiconductor 406c. Therefore, the level density of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c is low. In the laminate, the energy changes continuously near each interface (also called continuous junction). 32A shows a band structure of the semiconductor 406a, the semiconductor 406b, and FIG. 32(B) is a cross-sectional view of a semiconductor 406c laminated in this order. ) is the energy (Ec) of the conduction band minimum corresponding to the dashed line P1-P2 of the semiconductor 40 FIG. 32(C) shows a case where the electron affinity of the semiconductor 406c is larger than that of the semiconductor 6a. 4 shows a case where the electron affinity of the semiconductor 406c is smaller than that of the body 406a.

[0071] At this time, the electrons flow into the semiconductor 406b, not into the semiconductor 406a and the semiconductor 406c. As described above, the semiconductor 406a and the semiconductor 406b move mainly through the interface. and the interface state density at the interface between the semiconductor 406b and the semiconductor 406c. By lowering the temperature, the movement of electrons in the semiconductor 406b is less hindered, and the The on-state current of the transistor can be increased.

[0072] The on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. For example, if there are no factors that impede the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel formation region is large. will be done.

[0073] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 406b (The surface to be formed, the semiconductor 406a in this case) is the root mean square of the area of ​​1 μm × 1 μm Root (RMS: Root Mean Square) roughness is less than 1 nm, preferably 0.6 nm or less, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm x 1 μm is less than 1 nm. Preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm m. Also, the maximum height difference (PV) in the range of 1 μm x 1 μm ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably The RMS roughness, Ra and PV are measured by SII Nanotech. The measurement was performed using a scanning probe microscope system SPA-500 manufactured by Knology Co., Ltd. It is possible.

[0074] In oxide semiconductors, oxygen vacancies can cause degradation of the electrical characteristics of transistors. Therefore, reducing oxygen vacancies in the channel formation region can improve the stability of the transistor. On the other hand, the source region and When an oxide semiconductor is used for the drain region, the resistance of the oxide semiconductor is reduced due to oxygen vacancies. Therefore, in order to increase the on-current of the transistor, it is possible to create oxygen vacancies. Sometimes it's better to do so.

[0075] For example, when an oxide semiconductor has oxygen vacancies (Vo), Hydrogen can enter the donor level. In the following, water can enter the oxygen vacancy site. The state where an oxygen vacancy occurs is sometimes expressed as VoH. Therefore, supplying oxygen to the oxide semiconductor , VoH can be reduced.

[0076] In the transistor shown in FIG. 1, when excess oxygen is released from insulator 402, insulator 40 The second region 423 prevents oxygen from being supplied to the source and drain regions. On the other hand, oxygen can be supplied to the channel forming region while avoiding the region 423. Therefore, the oxygen in the channel formation region is reduced while suppressing the increase in resistance of the source region and the drain region. Only the defects can be effectively reduced. That is, the region 423 provides stable electrical characteristics. In this way, a transistor having a large on-state current can be obtained.

[0077] In addition, when the transistor has an s-channel structure, the entire semiconductor 406b is Therefore, the thicker the semiconductor 406b, the larger the channel area. That is, the thicker the semiconductor 406b, the higher the on-state current of the transistor. For example, 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, Preferably, the semiconductor 406b has a region with a thickness of 100 nm or more. For example, the thickness is set to 300 nm or less, preferably 2 a semiconductor 406b having a region with a thickness of 00 nm or less, more preferably 150 nm or less; Just do that.

[0078] In addition, in order to increase the on-state current of the transistor, the thickness of the semiconductor 406c is preferably as small as possible. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the semiconductor 406c may be a semiconductor having a channel region. The semiconductor 406b is then subjected to a thermal treatment using an element other than oxygen (such as hydrogen or silicon) that constitutes the adjacent insulator. The semiconductor 406c has a function of blocking the intrusion of certain substances. For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the semiconductor 406c has a region having a thickness of 2 nm or more. The semiconductor 406c is formed by: It is preferable that the material has oxygen blocking properties.

[0079] In order to increase reliability, the semiconductor 406a is thick and the semiconductor 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor 406a may have a region with a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 406a, the semiconductor 406a can be prevented from being heated at the interface between the adjacent insulator and the semiconductor 406a. The distance from the semiconductor 406b where the channel is formed can be increased. Since the productivity of the device may decrease, for example, the thickness is set to 200 nm or less, preferably 120 nm or less. The semiconductor 406a may have a thickness of 80 nm or less, and more preferably a thickness of 80 nm or less. stomach.

[0080] For example, a secondary ion mass spectrometry (S In IMS (Secondary Ion Mass Spectrometry) , 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Not yet More preferably, 2×10 18 atoms / cm 3 The region where the silicon concentration is less than In addition, between the semiconductor 406b and the semiconductor 406c, a 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0081] In order to reduce the hydrogen concentration in the semiconductor 406b, the semiconductor 406a and the semiconductor 406 It is preferable to reduce the hydrogen concentration in the semiconductor 406a and the semiconductor 406c. In, 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5, more preferably ×10 18 atoms / cm 3 The semiconductor 406 has a region with a hydrogen concentration of 1000 to 15000 . In order to reduce the nitrogen concentration of b, the nitrogen concentration of the semiconductor 406a and the semiconductor 406c is reduced. It is preferable that the semiconductor 406a and the semiconductor 406c have a SIMS resolution of 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is better Preferably 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atom s / cm 3 The nitrogen concentration ranges as follows:

[0082] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. The flip-flop may shift the threshold voltage of the transistor in the positive direction. The copper concentration on or inside the semiconductor 406b is preferably as low as possible. 06b has a copper concentration of 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / c m 3 or less, or 1×10 18 atoms / cm 3 It is preferred to have a region where: In addition, it is preferable that the copper concentration on the surface or inside of the semiconductor 406a is low. Conductor 406a has a copper concentration of 1×10 19 atoms / cm 3 Below, 5 x 10 18 atom s / cm 3 or less, or 1×10 18 atoms / cm 3 It is preferred that the region In addition, it is preferable that the copper concentration on the surface or inside of the semiconductor 406c is low. For example, semiconductor 406c has a copper concentration of 1×10 19 atoms / cm 3 Below, 5 x 10 18 a toms / cm 3 or less, or 1×10 18 atoms / cm 3 Have a region where This is preferable.

[0083] The three-layer structure described above is an example. For example, a two-layer structure without semiconductor 406a or semiconductor 406c Alternatively, the semiconductor 406a may be disposed above or below the semiconductor 406c. The semiconductors 406a, 406b, and 406c are illustrated above and below. Alternatively, a four-layer structure having any one of the semiconductors 406a and 406b may be used. At least two of the following locations are located below the semiconductor 406a, above the semiconductor 406c, and below the semiconductor 406c. Any of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c. Alternatively, it may have an n-layer structure (n is an integer of 5 or more) having one or more layers.

[0084] <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0085] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0086] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0087] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include a conductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0088] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0089] <caac-os> First, let me explain about CAAC-OS. xis aligned nanocrystals) It is also possible.

[0090] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0091] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0092] The following describes the CAAC-OS observed by TEM. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0093] FIG. 27(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 27(A). From FIG. 27(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0094] As shown in Figure 27(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 27(B) and Figure 27(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination of the The zeolites can also be referred to as nanocrystals (nc).

[0095] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 27(D)). The inclination between the pellets observed in FIG. 27(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0096] FIG. 28(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 28(A). The enlarged Cs-corrected high-resolution TEM images are shown in Figs. 28(B), 28(C) and 28(D), respectively. 28(D). From Fig. 28(B), Fig. 28(C) and Fig. 28(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0097] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 29(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0098] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0099] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 29(B). In the case of a single crystal oxide semiconductor such as InGaZnO4, the 2θ is fixed at around 56° and the φ shift is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0100] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 30(A) is obtained. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 30(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 30(B) This is thought to be due to the (110) plane.

[0101] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can also be considered an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0102] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or may cause hydrogen By capturing atoms, they can become a carrier generation source.

[0103] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0104] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) can reduce the carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. A transistor using C-OS has electrical characteristics in which the threshold voltage is negative (normal In addition, the acid is highly pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be discharged and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0105] In addition, because the density of defect states in CAAC-OS is low, the capacitive coupling generated by light irradiation can be suppressed. Therefore, the transistor using CAAC-OS is less likely to be captured by the defect level. The electrical characteristics of a transistor vary little when exposed to visible or ultraviolet light.

[0106] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0107] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- The nc-OS is called the "High Resolution Oxide Semiconductor." In some cases, the grain boundaries cannot be clearly seen in the TEM images. Therefore, in the following, we will refer to the pellets in nc-OS as the pellets of the same origin. The crystalline part of S is sometimes called a pellet.

[0108] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy region.

[0109] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0110] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0111] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0112] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystal parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0113] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0114] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is observed. It is measured.

[0115] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the A structure that has order but no long-range order is sometimes called an amorphous structure. According to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. In addition, oxides with at least long-range order cannot be called solid oxide semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, the CAAC-OS and nc-OS are It cannot be called a compound semiconductor.

[0116] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0117] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0118] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0119] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0120] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0121] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0122] Figure 31 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 31, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 31, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0123] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0124] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0125] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0126] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0127] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a semiconductor and a CAAC-OS.

[0128] In FIG. 1, the substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, and a sapphire substrate. , stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. The semiconductor substrate may be, for example, a single semiconductor substrate such as silicon or germanium; Or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, nitrogen oxide Compound semiconductor substrates such as lead and gallium oxide. A semiconductor substrate having an insulating region thereon, such as SOI (Silicon On Insulator) The conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive Resin substrates, etc., or substrates with metal nitrides, substrates with metal oxides, etc. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, A substrate provided with a conductor or insulator, a substrate provided with a semiconductor or insulator on a conductor substrate Alternatively, a substrate having an element mounted thereon may be used. The elements that can be used include capacitance elements, resistance elements, switch elements, light-emitting elements, and memory elements. be.

[0129] A flexible substrate may be used as the substrate 400. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil having woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. The substrate 4 may have a property of returning to its original shape. Alternatively, the substrate 4 may have a property of not returning to its original shape. The thickness of 00 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the thickness is set to 15 μm or more and 300 μm or less. The weight of the semiconductor device can be reduced. In addition, by making the substrate 400 thin, the weight of the semiconductor device can be reduced. When using a material with a stretchy surface, it may be possible for the material to return to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 400 may be damaged if it is dropped or the like. In other words, a robust semiconductor device can be provided. do.

[0130] The substrate 400, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or a glass. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.0. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester or polystyrene. Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, so it is suitable for flexible substrates. 400 is preferable.

[0131] The conductor 413 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. nium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Lithium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Tin, Tantalum and A conductor containing one or more of tungsten and silicon may be used in a single layer or a multilayer structure. For example, Conductors that may be alloys or compounds include aluminum-containing conductors, copper- and titanium-containing conductors, etc. , conductors containing copper and manganese, conductors containing indium, tin and oxygen, conductors containing titanium and Conductors containing nitrogen may also be used.

[0132] The insulator 402 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, The insulator 402 may be silicon oxynitride, silicon nitride, or the like. The insulating material may contain nitrogen-containing insulators such as nitrogen oxide.

[0133] The insulator 402 may serve to prevent diffusion of impurities from the substrate 400. When the semiconductor 406b is an oxide semiconductor, the insulator 402 provides oxygen to the semiconductor 406b. It can play a role in providing

[0134] The insulator 412 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, Alternatively, the electrodes may be used in layers.

[0135] The conductor 404 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. nium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Lithium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Tin, Tantalum and A conductor containing one or more of tungsten and silicon may be used in a single layer or a multilayer structure. For example, Conductors that may be alloys or compounds include aluminum-containing conductors, copper- and titanium-containing conductors, etc. , conductors containing copper and manganese, conductors containing indium, tin and oxygen, conductors containing titanium and Conductors containing nitrogen may also be used.

[0136] The insulator 408 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, The insulator 408 is preferably made of aluminum oxide, oxide nitride, or the like. Silicon oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, A single layer of insulator containing lanthanum, neodymium oxide, hafnium oxide or tantalum oxide. Alternatively, they may be used in a laminated form.

[0137] The insulator 418 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, The insulator 418 is preferably silicon oxide or oxynitride. An insulator containing silicon carbide may be used in a single layer or a multilayer structure.

[0138] The insulator 428 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, The insulator 428 is preferably silicon oxide or oxynitride. An insulator containing silicon carbide may be used in a single layer or a multilayer structure.

[0139] The conductor 426a and the conductor 426b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, an alloy or a compound may be used, and a conductor containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0140] The conductor 424a and the conductor 424b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, an alloy or a compound may be used, and a conductor containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0141] In FIG. 1, the conductor 404 which is the first gate electrode of the transistor and the second gate electrode In the example shown in FIG. 1, the conductor 413 serving as the electrode is not electrically connected to the The structure of the transistor is not limited to this. For example, as shown in FIG. 4 and the conductor 413 may be electrically connected via the conductor 405 or the like. With this structure, the same potential is supplied to the conductor 404 and the conductor 413. Therefore, the switching characteristics of the transistor can be improved. ) a structure not including the conductor 413 may also be used.

[0142] Alternatively, in FIG. 1, a conductor electrically connecting the source and drain regions of the transistor may be used. Although the example in which the conductor 426a and the conductor 426b are in contact with the semiconductor 406b is shown, The structure of the transistor according to one embodiment is not limited to this. For example, as shown in FIG. The conductor 426a and the conductor 426b penetrate the semiconductor 406b and the semiconductor 406a. 3B, the semiconductor 402 may be in contact with the insulator 402. It is also possible for the semiconductor 406b to penetrate and come into contact with the semiconductor 406a.

[0143] Alternatively, in FIG. 1, the region 423 may extend over the entire depth direction of the semiconductor 406a and the semiconductor 406b. 6b in the depth direction, an example is shown. For example, as shown in FIG. 4(A), the region 423 may be a semiconductor Alternatively, the insulating layer 406 may be provided over the entire depth of the body 406a and the semiconductor 406b.

[0144] Alternatively, for example, as shown in FIG. 4B, the conductor 404 may have a tapered angle. In that case, for example, the region 423 may have a gradient in the depth direction. The shape may be different.

[0145] Alternatively, in FIG. 1, the semiconductor 406c and the insulator 412 are disposed in the area where the conductor 404 overlaps. However, the structure of a transistor according to one embodiment of the present invention is not limited to this example. For example, as shown in FIG. 5A, the semiconductor 406c and the insulator 412 are Alternatively, the semiconductor 406a may be disposed so as to cover the body 406b and the semiconductor 406a. As shown in FIG. 1, the semiconductor 406c is disposed so as to overlap the semiconductor 406b, and the insulator 412 is disposed The semiconductor 406c may be disposed so as to cover the semiconductor 406b and the semiconductor 406a. .

[0146] <Transistor structure 2> FIG. 6A is an example of a top view of a transistor according to one embodiment of the present invention. An example of a cross-sectional view corresponding to the dashed dotted line B1-B2 and the dashed dotted line B3-B4 is shown in FIG. In FIG. 6(A), some parts such as insulators are omitted for ease of understanding.

[0147] The transistor shown in FIG. 6A and FIG. 6B includes a conductor 413 on a substrate 400 and a An insulator 402 having a protrusion on the plate 400 and on the conductor 413, and a The semiconductor 406a, the semiconductor 406b on the semiconductor 406a, and the upper surface of the semiconductor 406b are in contact with each other. The conductors 416a and 416b that are not in contact with the side surfaces of the semiconductor 406b and the semiconductor 406c are 06b in a region that does not overlap with the conductor 416a and the conductor 416b. 406c, an insulator 412 on the semiconductor 406c, a conductor 404 on the insulator 412, and an insulator and an insulator 408 on the insulator 402, the semiconductor 406b, and the conductor 404. Although the conductor 413 is a part of a transistor here, the present invention is not limited to this. For example, the conductor 413 may be a component separate from a transistor.

[0148] The conductor 416a and the conductor 416b may be, for example, boron, nitrogen, oxygen, or fluorine. Fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel , copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, Conductors containing one or more of indium, tin, tantalum and tungsten, in a single layer or For example, a conductor containing aluminum may be used as an alloy or a compound. , conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin and Conductors containing titanium and oxygen, conductors containing titanium and nitrogen, etc. may also be used.

[0149] The transistor illustrated in FIG. 6 has a conductor 416a and a The difference is that it has a conductor 416b, but the rest of the configuration is similar. Therefore, the details of the transistor shown in FIG. 6 are the same as those of the transistor shown in FIG. The description can be taken into consideration.

[0150] The transistor illustrated in FIG. 6 has a conductor 416a and a and the conductor 416b, a transistor with a large on-state current can be realized. There may be cases where this is possible.

[0151] <Transistor structure 3> FIG. 7A is an example of a top view of a transistor according to one embodiment of the present invention. An example of a cross-sectional view corresponding to the dashed dotted line C1-C2 and the dashed dotted line C3-C4 is shown in FIG. In FIG. 7(A), some parts such as insulators are omitted for ease of understanding.

[0152] The transistor shown in FIG. 7A and FIG. 7B includes a conductor 413 on a substrate 400 and a An insulator 402 having a protrusion on the plate 400 and on the conductor 413, and a The semiconductor 406a, the semiconductor 406b on the semiconductor 406a, and the upper surface and Conductor 416a and conductor 416b in contact with the side surfaces of semiconductor 406b and conductor 416b on semiconductor 406b. 16a and the semiconductor 406c arranged in a region not overlapping with the conductor 416b, and the semiconductor 4 06c, an insulator 412, a conductor 404 on the insulator 412, and a semiconductor on the insulator 402. 406b and an insulator 408 on the conductor 404. The conductor 413 is a part of a transistor, but is not limited to this. may be a component independent of the transistor.

[0153] The transistor illustrated in FIG. 7 has a conductor 416a and a The difference is that the conductor 416b contacts the side surface of the semiconductor 406b. Therefore, the details of the transistor shown in FIG. 7 are similar to those of the transistor shown in FIG. The description of the transistor can be taken into consideration.

[0154] The transistor illustrated in FIG. 7 has a conductor 416a and a The transistor has a larger on-state current in proportion to the contact between the conductor 416b and the side surface of the semiconductor 406b. It may be possible to achieve this.

[0155] In FIG. 7, the conductor 404 which is the first gate electrode of the transistor and the second gate electrode In the example shown in FIG. 1, the conductor 413 serving as the electrode is not electrically connected to the The structure of the transistor is not limited to this. For example, as shown in FIG. 4 and the conductor 413 may be electrically connected via the conductor 405. With this configuration, the same potential is supplied to the conductor 404 and the conductor 413. Therefore, the switching characteristics of the transistor can be improved. As shown in FIG. 4, a structure without the conductor 413 may be used.

[0156] Alternatively, in FIG. 7, the region 423 is provided only in a portion of the semiconductor 406b in the depth direction. However, the structure of a transistor according to one embodiment of the present invention is not limited to this. For example, As shown in FIG. 9A, the region 423 is a region of the semiconductor 406a and the semiconductor 406b in the depth direction. It may be provided throughout the entire area.

[0157] Alternatively, for example, as shown in FIG. 9B, the conductor 404 may have a tapered angle. In that case, for example, the region 423 may have a gradient in the depth direction. The shape may be different.

[0158] Alternatively, in FIG. 7, the semiconductor 406c and the insulator 412 are disposed in the region overlapping with the conductor 404. However, the structure of a transistor according to one embodiment of the present invention is not limited to this example. For example, as shown in FIG. 10A, the semiconductor 406c is It may be arranged so as to cover the semiconductor 406a. Alternatively, as shown in FIG. 10(B), The semiconductor 406c is disposed so as to cover the semiconductor 406b and the semiconductor 406a. 12 is a conductor 416a, a conductor 416b, a semiconductor 406c, a semiconductor 406b, and a semiconductor It may be arranged so as to cover 406a.

[0159] <Transistor structure 4> FIG. 11A is an example of a top view of a transistor according to one embodiment of the present invention. FIG. 11(B) is a cross-sectional view of the example of FIG. 11 corresponding to the dashed line D1-D2 and the dashed line D3-D4. In FIG. 11(A), some parts such as insulators are omitted for ease of understanding. Shown below.

[0160] The transistors shown in FIGS. 11A and 11B include a conductor 413 on a substrate 400 and a 4, an insulator 402 having a convex portion on the substrate 400 and on the conductor 413, and a convex portion of the insulator 402 A semiconductor 406a on the portion, a semiconductor 406b on the semiconductor 406a, and an upper surface of the semiconductor 406b The conductor 416a and the conductor 416b contacting the side surface and the conductor 416b on the semiconductor 406b a semiconductor 406c disposed in a region that does not overlap with the conductor 416a but overlaps with the conductor 416b; An insulator 412 on the conductor 406c, a conductor 404 on the insulator 412, and an insulator 402 on the conductor 406c. and an insulator 408 on the semiconductor 406b and the conductor 404. In this transistor, the conductor 404 overlaps with the conductor 416b. In the present embodiment, the conductor 413 is a part of a transistor, but is not limited to this. The current collector 413 may be a separate component from the transistor.

[0161] 11 is different from the transistor shown in FIG. 7 in that the conductor 404 is conductive. The difference is that it has an area that overlaps with the body 416b, but the other configurations are similar. Therefore, the details of the transistor shown in FIG. 11 are the same as those of the transistor shown in FIG. The descriptions in the above may be taken into consideration.

[0162] As shown in FIG. 11B, a gate electrode The region where the conductor 404 and the conductor 416b overlap is called the Lov region.

[0163] If the Lov region is too large, the parasitic capacitance increases, which can affect the switching characteristics of the transistor. Therefore, the size of the Lov region shown in FIG. Less than 100% of the size of the channel-forming region, preferably less than 80%, more preferably less than 50% For example, the size of the Lov region is less than 50 nm, preferably less than 20 nm. More preferably, it is less than 10 nm.

[0164] The transistor illustrated in FIG. 11 has a conductor 404, which is different from the transistor illustrated in FIG. A transistor with a large on-state current is realized by the area overlapping with the conductor 416b. It may be possible.

[0165] The transistor structures shown above are only examples, and combinations of these structures are also within the scope of the present invention. This falls within the scope of the embodiment.

[0166] <How to fabricate a transistor> As an example, a method for manufacturing the transistor shown in FIG. 1 will be described below with reference to FIGS. I will explain this in more detail.

[0167] First, a substrate 400 is prepared.

[0168] Next, a conductor that will become the conductor 413 is formed. The conductor that will become the conductor 413 is formed by sputtering. Chemical Vapor Deposition (CVD) ) method, molecular beam epitaxy (MBE) or Pulsed Laser Deposition (PLD) ) method, Atomic Layer Deposition (ALD) method, etc. The film may be formed using, for example,

[0169] The CVD method is a method that uses plasma CVD (PECVD: Plasma ECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method Furthermore, depending on the source gas used, it can be classified into metal CVD (MCVD:Met D) method, etc. al CVD) method, Metal Organic CVD (MOCVD) method ) methods.

[0170] The plasma CVD method can produce high-quality films at relatively low temperatures. The thermal CVD method uses plasma. Since no plasma damage occurs, a film with few defects can be obtained.

[0171] In the CVD method, the composition of the resulting film can be controlled by adjusting the flow rate ratio of the source gases. For example, in the MCVD and MOCVD methods, a film of any composition can be produced by adjusting the flow rate ratio of the source gases. In addition, for example, in the MCVD method and the MOCVD method, By changing the flow rate ratio of the source gases, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the transistors can be improved.

[0172] Next, a part of the conductor that is to become the conductor 413 is etched to form the conductor 413.

[0173] Next, an insulator 402 is formed (see FIG. 12A). The insulator 402 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the insulator 402 is flattened from the top surface by a CMP method or the like. By flattening the top surface of the insulator 402, the subsequent process becomes easier and the transistor can be formed more easily. For example, the CMP method can improve the yield of the RM of the insulator 402. S roughness is 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Alternatively, Ra in an area of ​​1 μm×1 μm is set to less than 1 nm, preferably less than 0.6 nm. less than 0.5 nm, more preferably less than 0.4 nm; or The PV in an area of ​​1 μm×1 μm is less than 10 nm, preferably less than 9 nm, more preferably Preferably, the thickness is less than 8 nm, more preferably less than 7 nm. However, according to one embodiment of the present invention, The transistor is not limited to the case where the top surface of the insulator 402 is planarized.

[0174] The insulator 402 may be formed to contain excess oxygen. Oxygen may be added after the film is formed. The addition of oxygen is carried out, for example, by ion implantation using an accelerated The voltage is set to 2 kV or more and 100 kV or less, and the dose is set to 5 × 10 14 ions / cm 2 More than 5× 10 16 ions / cm 2 This can be done as follows.

[0175] When the insulator 402 is made of a laminated film, each film is formed by the above-mentioned film forming method. For example, the first layer may be formed by a CVD method, and the second layer may be formed by a CVD method. The first layer may be deposited by the ALD method. Alternatively, the first layer may be deposited by the sputtering method, and the second layer may be deposited by the ALD method. The film may be formed by the ALD method. By stacking these films, it is possible to give each layer a different function or property. By doing so, a more suitable film can be formed as the entire laminated film.

[0176] In other words, the nth layer (n is a natural number) is formed by sputtering, CVD, MBE or P The n+1th layer is formed by at least one of the LD method, ALD method, etc. At least one of the following methods is used: CVD, MBE, PLD, ALD, etc. The film is formed by one of two methods. Note that the film formation methods for the nth layer and the n+1th layer are different even if they are the same. The n-th film and the (n+2)-th film may be formed by the same film formation method. Alternatively, the deposition method may be the same for all the films.

[0177] Next, a semiconductor to be the semiconductor 406a and a semiconductor to be the semiconductor 406b are formed in this order. The semiconductor that becomes the semiconductor 406a and the semiconductor that becomes the semiconductor 406b are formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0178] The semiconductor 406a and the semiconductor 406b are In- When forming a Ga-Zn oxide layer by MOCVD, trimethylisocyanate is used as the source gas. Indium, trimethylgallium, dimethylzinc, etc. may be used. The gas combination is not limited, and triethylindium may be used instead of trimethylindium. Alternatively, triethylgallium may be used instead of trimethylgallium. Dimethyl zinc may be replaced by diethyl zinc.

[0179] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 300° C. or higher and 500° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. In order to improve the crystallinity of the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b, It is also possible to remove impurities such as hydrogen and water.

[0180] Next, a part of the semiconductor that will become the semiconductor 406a and a part of the semiconductor that will become the semiconductor 406b are etched. The semiconductor 406a and the semiconductor 406b are formed by etching (see FIG. 12B).

[0181] Next, a semiconductor film that will become the semiconductor 406c is formed. The film may be formed by deposition, CVD, MBE, PLD, ALD, or the like. .

[0182] In addition, the semiconductor 406c is a semiconductor that is made by growing an In-Ga-Zn oxide layer by MOCVD. Therefore, when forming the film, the source gas is trimethylindium, trimethylgallium, and The combination of raw material gases is not limited to the above, and may be any combination of raw material gases. Instead of methylindium, triethylindium or the like may be used. Instead of gallium, triethylgallium or the like may be used. Also, instead of dimethylzinc, Diethyl zinc and the like may also be used.

[0183] Next, a second heat treatment may be performed. A semiconductor having higher oxygen permeability than the semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than the semiconductor 406a is selected as the semiconductor to be used. For the semiconductor 406a, a semiconductor that is permeable to oxygen is selected. A semiconductor having an oxygen blocking function is selected as the semiconductor 406c. When the second heat treatment is performed, the semiconductor 406a is transferred to the insulator 402 through the semiconductor 406a. The excess oxygen migrates to the semiconductor 406b, which becomes the semiconductor 406c. Therefore, the outward diffusion of excess oxygen is difficult. By performing the second heat treatment, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the second heat treatment is performed so that excess oxygen (oxygen) in the insulator 402 is oxidized to the semiconductor 40 For example, the first heat treatment may be performed at a temperature at which the diffusion of the first and second ions occurs. Alternatively, the second heat treatment may be performed at a temperature 20° C. or higher and 150° C. or lower than that of the first heat treatment. If the temperature is lower than 40° C. or less by 100° C., the excess acid is removed from the insulator 402. This is preferable because it does not release oxygen.

[0184] Next, an insulator that will become the insulator 412 is formed. The insulator that will become the insulator 412 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0185] In addition, when the insulator 412 is made of a laminated film, each film is formed by CVD. method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE method, PL The film may be formed by a different film formation method such as a deposition method, an ALD method, etc. For example, the first layer may be formed by MOCVD and the second layer may be formed by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the MOCVD method. The first layer may be deposited by ALD and the second layer by sputtering. Even if a film is formed by the ALD method, a second layer is formed by the sputtering method, and a third layer is formed by the ALD method, In this way, by using different film forming methods, different properties can be obtained for each layer. By stacking these films, the laminated film can be made to have different functions and properties. As a whole, a more suitable membrane can be formed.

[0186] In other words, when the insulator 412 is made of a laminated film, for example, the n-th film is , CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE The n+1th layer is formed by at least one of the following methods: , CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE The n-th layer is formed by at least one of the methods of the PLD method, the ALD method, and the like, and the n-th layer is formed by the n-th method. The deposition method may be different between the nth layer and the +1st layer (n is a natural number). The film formation method may be the same for the n+2th layer film. Alternatively, the film formation method may be the same for all the films. may be the same.

[0187] Next, a third heat treatment may be performed. A semiconductor having higher oxygen permeability than the semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than the semiconductor 406a is selected as the semiconductor to be used. A semiconductor having an oxygen blocking function is selected as the semiconductor for the body 406c. Alternatively, for example, the semiconductor 406a may be an insulator having a higher oxygen permeability than the insulator that becomes the insulator 412. That is, a semiconductor having a higher oxide content than the semiconductor 406a is selected as the insulator to be the insulator 412. In other words, a semiconductor 406a that is permeable to oxygen is selected. In addition, a semiconductor having the function of blocking oxygen is selected as the insulator 412. In this case, a third heat treatment is performed to turn the semiconductor into an insulator. Excess oxygen contained in the insulator 402 moves to the semiconductor 406b via 406a. The conductor 406b is covered with a semiconductor that becomes the semiconductor 406c and an insulator that becomes the insulator 412. Therefore, the outward diffusion of excess oxygen is unlikely to occur. By carrying out the treatment, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the third heat treatment is performed so that excess oxygen (oxygen) in the insulator 402 diffuses into the semiconductor 406b. For example, the description of the first heat treatment may be referred to. Alternatively, the third heat treatment is performed at a temperature 20° C. or higher and 150° C. or lower than that of the first heat treatment, preferably If the temperature is 40° C. or more (100° C.) lower, excess oxygen (oxygen) is released from the insulator 402. It is preferable that the insulator 412 has a function of blocking oxygen. In this case, the semiconductor 406c does not need to have a function of blocking oxygen. do not have.

[0188] Next, a conductor that will become the conductor 404 is formed. The conductor that will become the conductor 404 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0189] The insulator 412 functions as a gate insulator of the transistor. When the conductor that becomes the conductor 404 is formed, the insulator that becomes the insulator 412 is not damaged. It is preferable to use a film forming method. That is, it is preferable to use the MCVD method or the like for forming the conductive film. I wish.

[0190] In addition, when the conductor 404 is made of a laminated film, each film is formed by CVD. method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE method, PL The film may be formed by a different film formation method such as a deposition method, an ALD method, etc. For example, the first layer may be formed by MOCVD and the second layer may be formed by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the MOCVD method. The first layer may be deposited by ALD and the second layer by sputtering. Even if a film is formed by the ALD method, a second layer is formed by the sputtering method, and a third layer is formed by the ALD method, In this way, by using different film forming methods, different properties can be obtained for each layer. By stacking these films, the laminated film can be made to have different functions and properties. As a whole, a more suitable membrane can be formed.

[0191] That is, when the conductor 404 is made of a laminated film, for example, the n-th film is , CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE The n+1th layer is formed by at least one of the following methods: , CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE The n-th layer is formed by at least one of the methods of the PLD method, the ALD method, and the like, and the n-th layer is formed by the n-th method. The deposition method may be different between the nth layer and the +1st layer (n is a natural number). The film formation method may be the same for the n+2th layer film. Alternatively, the film formation method may be the same for all the films. may be the same.

[0192] In addition, the conductor that becomes the conductor 404 or at least one of the laminated films of the conductor that becomes the conductor 404 At least one film and an insulator that will become the insulator 412, or a stack of insulators that will become the insulator 412 At least one of the films may be formed by the same film formation method. The LD method may also be used. This allows the film to be formed without being exposed to the air. As a result, it is possible to prevent the inclusion of impurities. The conductor 404 is connected to the insulator 412, which is in contact with the conductor 404. The same film formation method may be used for the insulating material to be formed. This allows the films to be formed in the same chamber. As a result, the inclusion of impurities can be prevented.

[0193] In addition, the conductor that becomes the conductor 404 or at least one of the laminated films of the conductor that becomes the conductor 404 At least one film and an insulator that will become the insulator 412, or a stack of insulators that will become the insulator 412 At least one of the films may be formed by the same deposition method. A deposition method may be used. This allows the film to be formed without being exposed to the air. As a result, the inclusion of impurities can be prevented.

[0194] Next, a part of the conductor that will become the conductor 404 is etched to form the conductor 404. The conductor 404 is formed to overlap at least a portion of the semiconductor 406b.

[0195] Next, a portion of the insulator that will become the insulator 412 is etched, similar to the conductor that will become the conductor 404. However, in the transistors shown in FIG. 5(A) and FIG. 5(B), When making a stator, the insulator that becomes insulator 412 does not need to be etched.

[0196] Next, the semiconductor 40 is etched, as are the conductors that become the conductors 404 and the insulators that become the insulators 412. A part of the semiconductor 406c is etched to form the semiconductor 406c. ) When manufacturing a transistor shown in FIG. 4, a semiconductor to be the semiconductor 406c is etched. You don't have to.

[0197] The conductor that becomes the conductor 404, the insulator that becomes the insulator 412, and the semiconductor 406c When etching a portion of the semiconductor, the same photolithography process may be used. Alternatively, the conductor 404 may be used as a mask to form the insulator 412. The semiconductor that will become 406c may be etched. The conductor 404 and the semiconductor 406c have the same shape in the top view. The insulator 412 and / or the semiconductor 406c may have a protruding (protruding) shape. The conductor 404 protrudes from the insulator 412 and / or the semiconductor 406c. By forming the shape in this way, the occurrence of defective shapes is reduced, Gate leakage current may be reduced.

[0198] Next, impurities are added (see FIG. 13A). The impurities are added to the conductor 404, etc. The mask is used as the impurity. For example, helium, boron, carbon, nitrogen, neon, Magnesium, aluminum, silicon, phosphorus, argon, calcium, titanium, vanadium Cr, Chromium, Manganese, Iron, Cobalt, Germanium, Krypton, Strontium, Yttrium, zirconium, niobium, molybdenum, xenon, lanthanum, cerium, Addition of one or more selected from ozimium, hafnium, tantalum and tungsten As impurities, in particular, boron or phosphorus may be added.

[0199] The impurity may be added by, for example, a plasma treatment, an ion doping treatment, or the like. The method of doping impurities is not limited to the above-mentioned method. For example, Impurities can also be added during the formation of the insulator 408 or the like.

[0200] Here, impurities are doped throughout the insulator 402, the semiconductor 406a, and the semiconductor 406b. In order to achieve this, it is preferable to use an ion doping process. A method of doping by mass separation of ionized raw material gas, or a method of doping by mass separation of ionized raw material gas There are also methods for doping without mass separation. When performing mass separation, the ion species to be added On the other hand, if mass separation is not performed, It is possible to add high concentrations of ions at 1000 nm. It is also possible to generate atomic or molecular clusters. Alternatively, an ion doping method may be used in which the atoms are ionized by doping.

[0201] The method of doping impurities will be described in detail below with reference to FIG.

[0202] For example, the acceleration voltage in the ion doping process is preferably 0.5 kV or more and 100 kV or less. Preferably, the voltage is 1 kV or more and 50 kV or less, more preferably, 1 kV or more and 30 kV or less, and even more preferably The voltage is set to 1 kV or more and 10 kV or less. The ion implantation concentration is 1×10 15 ato ms / cm 2 More than 2×10 15 atoms / cm 2 More preferably, 5×10 15 atoms / cm 2 More preferably, 1×10 16 atoms / cm 2 More preferably, 2×10 16 atoms / cm 2 That is all.

[0203] The addition of ions by the ion doping process is performed at a specific angle (e.g., perpendicular) to the sample surface. It is preferable to carry out the method shown in FIG. 14. FIG. 14 shows one A simplified diagram showing how the on is incident on the sample surface at angles (θ) and (φ). It is.

[0204] The x-axis, y-axis, and z-axis in the figure are straight lines that intersect at the point of incidence of an ion. The y-axis is a straight line that is arbitrarily determined on the surface of the sample. The y-axis is a straight line that is on the surface of the sample and perpendicular to the x-axis. The z-axis is the normal to the sample surface at the point of incidence. The angle (θ) is the angle The angle (φ) is the angle between the direction of incidence of the ions and the z-axis in the top view. This is the angle between the incident direction and the x-axis.

[0205] When ions are incident on the sample surface only at specific angles (θ, φ), the amount of added ions is For example, if an object is placed on the sample surface, some areas may not be visible. Therefore, it is necessary to introduce ions from multiple angles. It is preferable to reduce the effect of shadows on the sample surface by irradiating the sample with light.

[0206] As shown in FIG. 14(A1) and FIG. 14(A2), the ions are irradiated at a first angle with respect to the sample surface. After the first incident angle (θ,φ), the second incident angle (θ,φ) is used. The angle (θ, φ) and the second angle (θ, φ) are different in at least one of θ and φ. do.

[0207] In the first angle (θ, φ), the angle (θ) is, for example, equal to or greater than 0° and less than 90°, preferably The second angle ( In the case of (θ, φ), the angle (θ) is, for example, 0° or more and less than 90°, preferably 30° or more. The second angle (θ, φ) is preferably 88° or less, and more preferably 60° or more and 85° or less. The angle (φ) at the first angle (θ, φ) is, for example, 90° or more larger than the angle (φ) at the second angle (θ, φ). The angle is 270° or less, and preferably 135° to 225°. The first angle (θ, φ) and the second angle (θ, φ) shown are merely examples and are not intended to be limiting. It is not something that can be achieved.

[0208] The ion incidence angle is classified into two types: a first angle (θ, φ) and a second angle (θ, φ). For example, the angle (θ, φ) of the first to nth angles (n is a natural number of 2 or more) may be set. The first to n-th angles (θ, φ) may be at least one of θ and φ. Includes different angles.

[0209] Alternatively, as shown in FIG. 14(B), ions are incident on the sample surface at a first angle (θ, φ). After the beam is projected, the angle (θ) passes through 90° and is scanned in the θ direction to a second angle (θ, φ). (This is also called θ scanning.) However, the angle (φ) at which the ions are incident is 1 The type is not limited, and the light may be incident at angles (φ) of 1 to n (n is a natural number of 2 or more). By scanning the ion incidence angle by θ, it is possible to obtain a high aspect ratio (e.g., 1 or more). , 2 or more, 5 or more, or 10 or more) even in openings, etc., Therefore, an oxygen blocking region can be formed without any gaps.

[0210] In the first angle (θ, φ), the angle (θ) is, for example, equal to or greater than 0° and less than 90°, preferably The second angle ( In the case of (θ, φ), the angle (θ) is, for example, 0° or more and less than 90°, preferably 30° or more. The first angle (θ, φ) and the second angle (θ, φ) are preferably 88° or less, and more preferably 60° or more and 85° or less. The two angles (θ, φ) may be the same angle (θ).

[0211] The θ scan may be performed continuously, for example, at 0.5°, 1°, 2°, 3°, 4°, 5°, 6°, 10°, 12°, 18°, 20°, 24° or 30° steps It is also possible to scan in stages.

[0212] Alternatively, the ions may be incident on the sample surface at a first angle (θ, φ) as shown in FIG. After the incident light is incident, it is scanned in the φ direction (also called φ scan) to a second angle (θ, φ). However, the angle (θ) at which the ions are incident is not limited to one type, and may be any of the first to fourth types. The light may be incident at an nth angle (θ) (n is a natural number of 2 or more).

[0213] In the first angle (θ, φ) and the second angle (θ, φ), the angle (θ) is, for example, 0 30° or more and less than 88°, preferably 60° or more and less than 85°. The first angle (θ, φ) and the second angle (θ, φ) are the same angle (φ). This is also fine.

[0214] The φ scan may be performed continuously, for example, at 0.5°, 1°, 2°, 3°, 4°, 5°, 6°, 10°, 12°, 18°, 20°, 24° or 30° steps It is also possible to scan in stages.

[0215] Although not shown, the θ scan and the φ scan may be performed in combination.

[0216] In this manner, the impurity-added region 423 may be formed (see FIG. 13B). .).

[0217] By using the method shown in FIG. 14, the region 423 is applied to the region that does not overlap with the conductor 404. In addition, the conductive material 404 can be formed uniformly in the region where the conductive material 404 overlaps. The variation in the electrical characteristics of the transistors can be reduced.

[0218] Next, the insulator 408 is formed. The insulator 408 is formed by a method such as a sputtering method, a CVD method, or an MBE method. The film may be formed by a method such as a PLD method or an ALD method.

[0219] Next, a fourth heat treatment may be performed. A semiconductor having higher oxygen permeability than semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than that of semiconductor 406a is selected. Select a semiconductor having a blocking function. A semiconductor having a higher oxygen permeability than the insulator 412 is selected. Select a semiconductor that is less oxygen permeable than the conductor 406a. As a, a semiconductor having higher oxygen permeability than the insulator 408 is selected. As the oxygen permeability, a semiconductor having a lower oxygen permeability than the semiconductor 406a is selected. A semiconductor having an oxygen permeability is selected as 406a. In this case, a fourth heat treatment is performed to select an insulator having an oxygen blocking function. By this, excess oxygen contained in the insulator 402 is transferred to the semiconductor 406 through the semiconductor 406a. The semiconductor 406b moves to the semiconductor 406c, the insulator 412, or the insulator 408. Because the oxygen is covered with a thin layer of chlorine, the outward diffusion of excess oxygen is difficult. By performing the fourth heat treatment in the same manner, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the fourth heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into a semiconductor. The temperature may be set to a temperature at which the diffusion of the metal to the metal layer 406b occurs. For example, see the description of the first heat treatment. Alternatively, the fourth heat treatment may be performed at a temperature 20° C. to 150° C. higher than that of the first heat treatment. If the temperature is set to be lower than the above, preferably by 40° C. or more and 100° C., excess oxygen will be removed from the insulator 402. This is preferable because the insulator 408 has a function of blocking oxygen. In this case, the third semiconductor 406c and / or the insulator 412 block oxygen. It is not essential that the function is not provided.

[0220] All of the first heat treatment, the second heat treatment, the third heat treatment and the fourth heat treatment are It is acceptable not to carry out any or all of the above.

[0221] Next, the insulator 418 is formed. The insulator 418 is formed by a sputtering method, a CVD method, or an MBE method. The film may be formed by a method such as a PLD method or an ALD method.

[0222] In the above manner, the transistor shown in FIG. 1 can be manufactured.

[0223] Note that although the method for manufacturing the transistor shown in FIG. 1 is described as an example here, the present invention is not limited to this. For example, the part of the method for manufacturing a transistor shown here and its assembly are not limited to the above. This combination may be used as a method for manufacturing transistors other than those shown in FIG.

[0224] <Behavior of excess oxygen> The behavior of excess oxygen inside a semiconductor device will be described below with reference to FIG.

[0225] FIG. 15A shows a substrate 50, an insulator 52 on the substrate 50, and an island-shaped semiconductor on the insulator 52. 5 is a schematic cross-sectional view of a sample having a semiconductor 56 and an insulator 68 on the semiconductor 56. In the sample shown in FIG. 15(A), the insulator 52 is made of excess oxygen (denoted as ex-O in the figure). The insulator contains

[0226] The insulator 52 may be an oxide, an oxynitride, or the like. Silicon oxide or silicon oxynitride may be used as the material 2. In this document, oxynitride means a material containing nitrogen at 0.1 atomic % or more but less than 25 atomic %. The term "nitride oxide" refers to an oxide containing oxygen at 0.1 atomic % or more and 25 atomic % or less. This refers to nitrides that contain less than mic %.

[0227] For the semiconductor 56 and the insulator 68, the semiconductor 406 and the insulator 68 are described above for redundancy. Please refer to the description of b and the insulator 402, and the description here will be omitted.

[0228] When heat is applied, excess oxygen diffuses through the insulator 52. For example, When the excess oxygen reaches the interface between the insulator 52 and the semiconductor 56, it fills the oxygen vacancies in the semiconductor 56. By reducing the oxygen vacancies in the semiconductor 56, the oxygen vacancies in the semiconductor 56 can be reduced. The defect level density caused by the above can be reduced.

[0229] However, all of the excess oxygen that diffuses through the insulator 52 reaches the interface between the insulator 52 and the semiconductor 56. For example, excess oxygen that diffuses through the insulator 52 does not reach the insulator 68. Alternatively, for example, the excess oxygen that diffuses through the insulator 52 may In some cases, the metal may react with wiring that constitutes the semiconductor device, increasing the wiring resistance.

[0230] Therefore, the sample structure shown in Figure 15(A) may not be efficient in utilizing excess oxygen. be.

[0231] Figures 15(B) and 15(C) show sample structures that can efficiently utilize excess oxygen. An example is shown below.

[0232] FIG. 15(B) shows a sample having a structure similar to that of the sample shown in FIG. 15(A). However, The sample shown in FIG. 15(B) is different in that the insulator 52 has a region 53 in the vicinity of the insulator 68. The region 53 corresponds to the region 423 described above. In the present embodiment, the insulator 52 is an insulator containing excess oxygen. The region 53 is The depth is 1 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, and more preferably The region 53 is a region having a depth of 10 nm or more and 100 nm or less. In this case, the insulating layer 54 may be provided over the entire insulator 52.

[0233] Region 53 is an oxygen blocking region. For example, the insulator 52 may be doped with helium, boron, or carbon. , nitrogen, neon, magnesium, aluminum, silicon, phosphorus, argon, calcium , titanium, vanadium, chromium, manganese, iron, cobalt, germanium, krypton, Strontium, yttrium, zirconium, niobium, molybdenum, xenon, lanthanum One selected from the group consisting of cerium, neodymium, hafnium, tantalum and tungsten. By adding the above, it may be possible to form an oxygen blocking region 53. The above-mentioned impurities are unlikely to cause the metal to have high resistance. Adding silicon or phosphorus to the alloy gives it high oxygen blocking properties (small oxygen diffusion coefficient), which is particularly good. The region 53 can be formed, for example, in the insulator 52 by forming the above-mentioned impurity. Pure 5×10 19 atoms / cm 3 More than 1×10 20 atoms / cm 3 More preferably, 2×10 20 atoms / cm 3 More than or equal to 5×1 0 20 atoms / cm 3 This is an area that includes the above.

[0234] The behavior of excess oxygen in the sample shown in FIG. 15(B) is as follows.

[0235] When heat is applied, excess oxygen diffuses through the insulator 52. The excess oxygen that diffuses through the insulator 52 is When the oxygen reaches the interface between the insulator 52 and the semiconductor 56, it can fill the oxygen vacancies in the semiconductor 56. can.

[0236] Excess oxygen diffusing through the insulator 52 is unlikely to penetrate the region 53, so the insulator 52 and the semiconductor A higher proportion of excess oxygen reaches the interface with semiconductor 56. In addition, for example, the excess oxygen diffused in the insulator 52 can be filled in the insulating layer 53. It is possible to suppress outward diffusion through the insulator 68. Alternatively, for example, the insulator 5 Excess oxygen diffuses through the semiconductor device and reacts with the conductors and low resistance regions that make up the semiconductor device, causing resistance It is possible to suppress the increase in resistance.

[0237] Therefore, the sample shown in FIG. 15(B) has a structure that allows efficient utilization of excess oxygen. It can be seen that.

[0238] Similarly, FIG. 15(C) is a sample having a similar structure to the sample shown in FIG. 15(A). However, the sample shown in FIG. 15(C) is different in that the insulator 68 has a region 69. In the sample shown in (C), the insulator 68 is an insulator containing excess oxygen. The depth from the top surface of the edge 68 is 1 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less. The thickness of the region is preferably 10 nm or more and 100 nm or less.

[0239] Region 69 is an oxygen blocking region. For example, the insulator 68 may be doped with helium, boron, or carbon. , nitrogen, neon, magnesium, aluminum, silicon, phosphorus, argon, calcium , titanium, vanadium, chromium, manganese, iron, cobalt, germanium, krypton, Strontium, yttrium, zirconium, niobium, molybdenum, xenon, lanthanum One selected from the group consisting of cerium, neodymium, hafnium, tantalum and tungsten. Adding the above may result in the formation of an oxygen blocking region 69. In addition, when boron or phosphorus is added to the insulator 68, it becomes a particularly good material with high oxygen blocking properties. The region 69 can be formed, for example, in the insulator 68 by forming the above-mentioned impurity Pure 5×10 19 atoms / cm 3 More than 1×10 20 atoms / cm 3 More preferably, 2×10 20 atoms / cm 3 More than or equal to 5×1 0 20 atoms / cm 3 This is an area that includes the above.

[0240] The behavior of excess oxygen in the sample shown in FIG. 15(C) is as follows.

[0241] When heat is applied, excess oxygen diffuses through the insulator 68. The excess oxygen that diffuses through the insulator 68 is When the interface between the insulator 68 and the semiconductor 56 is reached, oxygen vacancies in the semiconductor 56 can be filled. can.

[0242] Excess oxygen diffusing through the insulator 68 is unlikely to penetrate the region 69, so the insulator 68 and the semiconductor A higher proportion of excess oxygen reaches the interface with semiconductor 56. In addition, for example, the excess oxygen diffused in the insulator 68 can be filled in the outer Alternatively, for example, the excess diffusion in the insulator 68 can be suppressed. To suppress an increase in wiring resistance due to a reaction of oxygen with wiring constituting a semiconductor device can be done.

[0243] Therefore, the sample shown in FIG. 15(C) has a structure that allows efficient utilization of excess oxygen. It can be seen that.

[0244] Although not shown, the sample structure shown in FIG. 15(B) and the sample structure shown in FIG. 15(C) are combined. For example, both the insulator 52 and the insulator 68 may be insulators containing excess oxygen. Alternatively, for example, the insulator 52 may have a region 53 adjacent to the insulator 68, In addition, the insulator 68 may have a structure having a region 69 .

[0245] <Semiconductor device> An example of a semiconductor device according to one embodiment of the present invention will be described below.

[0246] An example of a semiconductor device including a transistor according to one embodiment of the present invention will be described below. do.

[0247] FIG 16A shows a cross-sectional view of a semiconductor device of one embodiment of the present invention. The device has a transistor 2200 using a first semiconductor on the bottom and a transistor 2200 using a second semiconductor on the top. In FIG. 16A, a transistor 2100 using a second semiconductor is shown. As the transistor 2100, the transistor illustrated in FIG. 6 is used.

[0248] The first semiconductor may be a semiconductor having a different energy gap from the second semiconductor. For example, the first semiconductor is a semiconductor other than an oxide semiconductor, and the second semiconductor is an oxide semiconductor. The first semiconductor is silicon, germanium, etc., with a polycrystalline structure or single crystal structure. Alternatively, a semiconductor having strain, such as strained silicon, may be used. As the first semiconductor, a high electron mobility transistor (HEMT) Gallium arsenide and arsenide applicable to the Ron Mobility Transistor Aluminum gallium, indium gallium arsenide, gallium nitride, indium phosphide, silicon Cone germanium or the like may be used. By using these semiconductors for the first semiconductor, The transistor 2200 can be suitable for high-speed operation. By using a conductor as the second semiconductor, the transistor 2100 has a small off-state current. can be done.

[0249] The transistor 2200 may be either an n-channel type or a p-channel type. In addition, the transistor 2100 or / and the transistor The transistor 2200 may be any of the transistors described above or the transistor shown in FIG. There are cases where it is okay not to use it.

[0250] The semiconductor device shown in FIG. 16A is a transistor having an insulator 2201 and an insulator 2207 interposed therebetween. The transistor 2100 is disposed on the upper side of the transistor 2200. Between the transistor 2100 and the transistor 2100, a plurality of conductors 2202 functioning as wiring are arranged. In addition, multiple conductors 2203 embedded in various insulators are used to separate the upper and lower layers. The wiring and electrodes are electrically connected to each other. 2204 on the transistor 2100, a conductor 2205 on the insulator 2204, and a transistor A conductor formed in the same layer (through the same process) as the source and drain electrodes of the capacitor 2100. and a conductive material 2206.

[0251] The insulator 2204 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Nitrium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, di A single layer of insulator containing zinc, lanthanum, neodymium, hafnium or tantalum. Alternatively, a laminated structure may be used. Note that the insulator 2204 may be made of silicon nitride oxide or silicon nitride. The insulating material may contain nitrogen.

[0252] Alternatively, the insulator 2204 may be made of a resin. For example, polyimide, polyamide, or arsenic may be used. Resin containing acrylic, silicone, etc. may be used. By using resin, the insulator 220 In some cases, it may not be necessary to flatten the top surface of 4. Also, the resin forms a thick film in a short time. Therefore, productivity can be increased.

[0253] By stacking multiple transistors, multiple circuits can be arranged at high density. This can be done.

[0254] Here, the first semiconductor used in the transistor 2200 is a single semiconductor included in a semiconductor substrate 2211. When crystalline silicon is used, hydrogen in the insulator near the first semiconductor of the transistor 2200 The concentration is preferably high. The hydrogen terminates the dangling bonds of silicon. This can improve the reliability of the transistor 2200. When an oxide semiconductor is used as the second semiconductor of the transistor 2100, It is preferable that the hydrogen concentration in the insulator near the semiconductor of 2 is low. This is one of the factors that generate carriers in the transistor 2100, and therefore reduces the reliability of the transistor 2100. Therefore, the transistor 2200 using single crystal silicon, In the case where the transistor 2100 including an oxide semiconductor is stacked, hydrogen is introduced between the transistors. The placement of the insulator 2207 having a blocking function increases the reliability of both transistors. It is useful for

[0255] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Insulators including hafnium nitride and yttria-stabilized zirconia (YSZ) are used in a single layer. Alternatively, they may be used in a laminated form.

[0256] In addition, a thin film was formed on the transistor 2100 using an oxide semiconductor so as to cover the transistor 2100. It is preferable to form an insulator having a function of blocking hydrogen on the substrate. Insulators similar to the insulator 2207 can be used, and in particular aluminum oxide can be used. The aluminum oxide film is resistant to both impurities such as hydrogen and moisture, and oxygen. Therefore, the insulating film covering the transistor 2100 has a high blocking effect of preventing the penetration of the film. By using an aluminum oxide film as the transistor 2208, the oxide film included in the transistor 2100 Prevents oxygen from being released from the oxide semiconductor and prevents water and hydrogen from being mixed into the oxide semiconductor. can be prevented.

[0257] It should be noted that the transistor 2200 is not limited to a planar type transistor, but may be of various types. For example, a FIN type transistor can be used. An example of a cross-sectional view in this case is shown in FIG. An insulator 2212 is disposed on the semiconductor substrate 2211. The protrusion does not have to have a thin tip. For example, the protrusion may have a shape of a substantially rectangular parallelepiped. The semiconductor substrate 2211 may have a convex portion or a convex portion with a thick tip. A gate insulator 2214 is disposed thereon, and a gate electrode 2213 is disposed thereon. A source region and a drain region 2215 are formed in the semiconductor substrate 2211. In this embodiment, the semiconductor substrate 2211 has a protrusion. The semiconductor device according to the present invention is not limited to the above. For example, a SOI substrate is processed to form a protruding semiconductor device. A conductive region may be formed.

[0258] In the above circuit, if the electrodes of the transistors 2100 and 2200 are connected differently, By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0259] The circuit diagram shown in FIG. 17A includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected. 4 shows the configuration of an S inverter.

[0260] The circuit diagram shown in FIG. 17B is that of a transistor 2100 and a transistor 2200. The source and drain of each transistor are connected. It can function as a so-called CMOS analog switch.

[0261] A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied FIG. 18 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0262] The semiconductor device shown in FIG. 18A includes a transistor 3200 using a first semiconductor and a The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0263] The transistor 3300 is a transistor including an oxide semiconductor. The low off-state current of 00 allows the memory contents to be stored in a specific node of the semiconductor device for a long period of time. That is, it is possible to hold the data without requiring a refresh operation or Since the frequency of flash operations can be reduced significantly, the semiconductor device has low power consumption. It becomes.

[0264] In FIG. 18A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0265] The semiconductor device illustrated in FIG. 18A can hold a gate potential of the transistor 3200. This property makes it possible to write, hold, and read information, as shown below. do.

[0266] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the The signal is applied to a node FG that is electrically connected to one of the electrodes of the capacitance element 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two different potential levels (hereafter referred to as low-level charge and high-level charge) ) is applied. After that, the potential of the fourth wiring 3004 is applied to the transistor. The transistor 3300 is set to a potential at which it is non-conductive, thereby making the transistor 3300 non-conductive. As a result, charge is held (retained) at node FG.

[0267] Since the off-state current of the transistor 3300 is extremely small, the charge of the node FG is maintained for a long period of time. This is retained.

[0268] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, 3002 takes a potential according to the amount of charge held in the node FG. This is the transistor If 3200 is an n-channel type, a high-level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it in a "conductive state." Then, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential between For example, in a write, the charge applied to node FG can be determined. When a high-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." On the other hand, the node FG When a low-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. It can be put out.

[0269] When memory cells are arranged in an array, the information of a desired memory cell is read. In order not to read information from other memory cells, A potential at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to FG. , that is, V th_H A lower potential may be applied to the fifth wiring 3005. A potential at which transistor 3200 is "on" regardless of the charge applied to the FG. , that is, V th_L A higher potential may be applied to the fifth wiring 3005 .

[0270] The semiconductor device shown in FIG. 18B differs from the semiconductor device shown in FIG. 18A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information more easily.

[0271] The reading of data in the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and electric charges are redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is expressed by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0272] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), , the potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V 1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (= It can be seen that it is higher than (CB×VB0+C×V0) / (CB+C)).

[0273] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0274] In this case, the transistor in which the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the driving circuit.

[0275] The above-described semiconductor device includes a transistor including an oxide semiconductor and having an extremely low off-state current. By applying this, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary or can be performed very infrequently. Therefore, a semiconductor device with low power consumption can be realized. Even if there is no potential (but the potential is preferably fixed), It is possible to retain the stored contents.

[0276] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is an issue with semiconductors, and reliability has been dramatically improved. Furthermore, information can be written depending on whether the transistor is conductive or non-conductive. This allows high speed operation.

[0277] <RFタグ> In the following, the above-mentioned transistor or RF tag including a memory device will be described with reference to FIG. I will explain this in more detail.

[0278] The RF tag according to one embodiment of the present invention has a memory circuit therein, stores information in the memory circuit, and It is a device that transmits and receives information to and from the outside world using contact means, such as wireless communication. RF tags are used for individual authentication to identify items by reading their individual information. It is possible to use it in systems such as these. Sex is required.

[0279] The structure of an RF tag will be described with reference to FIG. 19. FIG. 19 is a block diagram showing an example of the structure of an RF tag. FIG.

[0280] As shown in FIG. 19, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 804. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, a reverse current flows in the semiconductor of the transistor having a rectifying effect included in the demodulation circuit 807. For example, an oxide semiconductor capable of sufficiently suppressing the inverse This suppresses the deterioration of the rectification effect caused by the directional current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. The data transmission format is electromagnetic, with a pair of coils facing each other and communicating through mutual induction. Coupling method, electromagnetic induction method that communicates by induced electromagnetic fields, radio wave method that communicates using radio waves The RF tag 800 can be used for any of these methods.

[0281] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential. The limiter circuit may include a limiter circuit. When the internally generated voltage is large, the power above a certain level is controlled so as not to be input to the downstream circuit. This is a circuit for

[0282] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0283] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit that performs modulation based on the

[0284] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. It has. Also, the ROM 811 stores unique numbers (IDs) and outputs in accordance with processing. It is a circuit for performing such operations.

[0285] Note that each of the above circuits can be appropriately selected or omitted.

[0286] Here, the storage device described above can be used as the storage circuit 810. In one aspect of the present invention, since the storage device can retain information even when the power supply is cut off, it is suitable for an RF tag. Furthermore, in one aspect of the present invention, since the power (voltage) required for writing data is lower than that of a conventional non-volatile memory, it is also possible not to cause a difference in the maximum communication distance between the time of reading data and the time of writing data. Furthermore, it is possible to suppress the occurrence of malfunction or miswriting due to insufficient power during data writing.

[0287] Also, since the storage device according to one aspect of the present invention can be used as a non-volatile memory, it can also be applied to the ROM 811. In that case, it is preferable that the producer separately prepares a command for writing data to the ROM 811 and makes it impossible for the user to rewrite it freely. After the producer writes the unique number before shipment and then ships the product, it is possible to assign unique numbers only to the non-defective products to be shipped, rather than to all the manufactured RF tags, so that the unique numbers of the products after shipment do not become discontinuous, and customer management corresponding to the products after shipment becomes easy.

[0288] <Usage Example of RF Tag> Hereinafter, a usage example of an RF tag according to one aspect of the present invention will be described with reference to FIG. 20. Although the applications of RF tags are wide-ranging, for example, banknotes, coins, securities, bearer bonds, certificates ​ (See Figure 20(A)) and packaging containers (Wrapping paper, bottles, etc.) See Figure 20(C).), recording media (DVDs, video tapes, etc., see Figure 20(B).), Vehicles (bicycles, etc., see Figure 20 (D)), personal belongings (bags, glasses, etc.), food, plants , animals, the human body, clothing, daily necessities, medicines and medical products including drugs, or electronic devices (liquid crystal displays display devices, EL display devices, television devices, or mobile phones) or each item It can be used by attaching it to a tag (see Figure 20 (E) and Figure 20 (F)). can.

[0289] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. The RF tag 4000 according to one embodiment of the present invention can provide an authentication function to items, By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention relates to an embodiment of the present invention, which is applied to the body, personal belongings, food, clothing, daily necessities, electronic devices, etc. By attaching RF tags 4000, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag 4000 according to one embodiment of the present invention can be attached. By attaching the tag, security against theft and the like can be improved.

[0290] As described above, the RF tag according to one embodiment of the present invention can be used for the above-mentioned applications. can.

[0291] <cpu> The following describes a CPU including the above-mentioned transistor and the above-mentioned semiconductor device such as the memory device. I will explain it below.

[0292] FIG. 21 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0293] The CPU shown in FIG. 21 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. 21 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 21 is regarded as one core, and a multi-core processor including multiple cores is used. Alternatively, the CPU may be configured to operate each core in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It may be a bit, etc.

[0294] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0295] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0296] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0297] In the CPU shown in FIG. 21, a register 1196 is provided with a memory cell. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0298] In the CPU shown in FIG. 21, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0299] FIG. 22 is a circuit diagram of an example of a storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a A circuit 1202 that prevents stored data from volatilizing when the circuit is turned off, a switch 1203, and a switch 1204. 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0300] Here, the above-mentioned memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential at which the transistor 1209 is turned off is continuously input. For example, the gate of the transistor 1209 is grounded via a load such as a resistor. .

[0301] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conductive or non-conductive state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The conductive or non-conductive state of transistor 1214 is selected.

[0302] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0303] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0304] A control signal WE is input to the gate of the transistor 1209. and the switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first and second terminals of one switch is selected. When the terminals of the switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. It becomes.

[0305] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 22, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. The signal is then input to the circuit 1201.

[0306] In FIG. 22, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0307] In addition, in FIG. 22, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a silicon or silicon-based transistor may be used. The memory element 1 can be a transistor in which a channel is formed in a silicon substrate. All the transistors used in 200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements besides the transistor 1209. The remaining transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0308] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0309] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0310] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor The off-current is significantly smaller than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 12 Even when power supply voltage is not supplied to 00, the signal held in the capacitance element 1208 is retained for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0311] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0312] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to a conductive state or a non-conductive state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0313] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0314] Although the memory element 1200 has been described as being used as a CPU, the memory element 1200 can also be used as a DSP ( Digital Signal Processor), Custom LSI, PLD (Pr LSIs such as grammable logic devices, RF-ID (Radi o Frequency Identification).

[0315] <Display device> A configuration example of a display device according to one embodiment of the present invention will be described below.

[0316] [Configuration example] FIG. 23A shows a top view of a display device according to one embodiment of the present invention. In the display device according to one embodiment of the present invention, a pixel circuit is provided using a liquid crystal element. FIG. 23C shows a display device according to one embodiment of the present invention in which an organic EL element is provided in a pixel. 4 shows a pixel circuit in the case where the pixel circuit is used.

[0317] The transistor used in the pixel can be any of the above-described transistors. An example using an n-channel transistor is shown. A transistor manufactured through one process may be used as a driver circuit. By using the above-mentioned transistors in the element and driving circuit, the display quality is high and / or This results in a highly reliable display device.

[0318] An example of a top view of an active matrix display device is shown in FIG. On the upper surface of the display device 5000, a pixel portion 5001, a first scanning line driving circuit 5002, a second scanning line driving circuit 5003, and a A signal line driver circuit 5003 and a signal line driver circuit 5004 are arranged in the pixel portion 5001. Therefore, the first scanning line is electrically connected to the signal line driver circuit 5004 and is connected to a plurality of scanning lines. The driver circuit 5002 and the second scanning line driver circuit 5003 are electrically connected. In the regions partitioned by the scanning lines and the signal lines, pixels each having a display element are arranged. The display device substrate 5000 is made of a flexible printed circuit board (FPC). A timing control circuit (controller, control I d Circuit) is connected to the C).

[0319] A first scanning line driver circuit 5002, a second scanning line driver circuit 5003 and a signal line driver circuit 5 004 is formed on the same substrate 5000 as the pixel portion 5001. In comparison with the case where the display device is manufactured by using a drive circuit, the manufacturing cost of the display device can be reduced. If a separate operating circuit is created, the number of connections between the wiring will increase. By providing a driver circuit, the number of connections between wiring can be reduced, improving reliability, or and / or yield can be improved.

[0320] [Liquid crystal display device] An example of the circuit configuration of a pixel is shown in FIG. 1 shows a pixel circuit that can be applied to a liquid crystal display device, etc.

[0321] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. The electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel electrodes of the multi-domain designed pixels to The signals applied to the electrodes can be controlled independently.

[0322] A gate wiring 5012 of a transistor 5016 and a gate wiring 5017 of a transistor 5017 13 are separated so that different gate signals can be applied to them. A source electrode or drain electrode 5014 functioning as a line is connected to a transistor 5016. The transistor 5016 and the transistor 5017 are commonly used. The transistors described above can be used as appropriate for 17. This allows for high display quality. And / or, a highly reliable liquid crystal display device can be provided.

[0323] A first pixel electrode electrically connected to the transistor 5016 and a second pixel electrode electrically connected to the transistor 5017 The shape of the second pixel electrode that is electrically connected to the first pixel electrode will be described. The first pixel electrode has a V-shaped shape separated by a slit. The second pixel electrode is formed so as to surround the outside of the first pixel electrode.

[0324] The gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012. The gate electrode of the gate electrode 5017 is electrically connected to the gate wiring 5013. Different gate signals are applied to the gate wiring 5012 and the transistor 5013. By varying the operation timing of the transistor 5017, the alignment of the liquid crystal can be controlled.

[0325] Also, a capacitance line 5010, a gate insulator functioning as a dielectric, and a first pixel electrode or A capacitance element may be formed by a capacitance electrode electrically connected to the second pixel electrode.

[0326] The multi-domain structure has a first liquid crystal element 5018 and a second liquid crystal element 5019 in one pixel. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween. do.

[0327] Note that a display device according to one embodiment of the present invention is not limited to the pixel circuit shown in FIG. For example, if a switch, a resistor, a capacitor, a transistor, etc. are newly added to the pixel circuit shown in FIG. Additional components such as sensors, logic circuits, etc. may also be added.

[0328] [Organic EL display device] Another example of the circuit configuration of a pixel is shown in FIG. 23(C). 3 shows the pixel structure of the device.

[0329] In the organic EL element, a pair of electrodes that the organic EL element has is turned on by applying a voltage to the light emitting element. Electrons are injected from one electrode and holes are injected from the other electrode into a layer containing a light-emitting organic compound, An electric current flows, and the electrons and holes recombine to form light-emitting organic compounds. An excited state is formed, and light is emitted when the excited state returns to the ground state. Therefore, such a light-emitting element is called a current-excitation type light-emitting element.

[0330] FIG. 23C is a diagram showing an example of a pixel circuit. Here, one pixel has an n-channel type An example using two transistors will be described. Note that the above-mentioned n-channel transistors are used. In addition, the pixel circuit is suitable for digital time gray scale driving. It can be used.

[0331] Regarding the configuration of an applicable pixel circuit and the operation of pixels when digital time gray scale driving is applied, I will explain it below.

[0332] The pixel 5020 includes a switching transistor 5021, a driving transistor 5022, The switching transistor 502 includes a light emitting element 5024 and a capacitor element 5023. 1, the gate electrode is connected to the scanning line 5026, and the first electrode (the source electrode, the drain electrode) The first electrode (the other of the source electrode and drain electrode) is connected to a signal line 5025, and the second electrode (the other of the source electrode and drain electrode) is connected to a drive The gate electrode of the driving transistor 5022 is connected to the gate electrode of the driving transistor 5022. The gate electrode is connected to a power supply line 5027 via a capacitor element 5023, and the first electrode is connected to a power supply line 5024. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 5024. The second electrode of the light-emitting element 5024 corresponds to a common electrode 5028. is electrically connected to a common potential line formed on the same substrate.

[0333] The switching transistor 5021 and the driving transistor 5022 are the transistors described above. This allows for high quality and / or reliable display. This will result in a high-performance organic EL display device.

[0334] The potential of the second electrode (common electrode 5028) of the light emitting element 5024 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027. For example, GND, 0V, etc. can be set as the low power supply potential. The high and low power supply potentials are set so that the potential difference is equal to or greater than the threshold voltage of the light-emitting element. By applying a voltage to the transistor 5024, a current flows through the light emitting element 5024, causing it to emit light. The forward voltage of the light emitting element 5024 refers to a voltage required for achieving a desired luminance, and is at least Both include forward threshold voltage.

[0335] The capacitor 5023 is substituted for the gate capacitance of the driving transistor 5022. The gate capacitance of the driving transistor 5022 can be omitted. A capacitance may be formed between the hole formation region and the gate electrode.

[0336] Next, a signal to be input to the driving transistor 5022 will be described. In the case of the above method, the driving transistor 5022 is in two states, on or off. The video signal is input to the driving transistor 5022. In order to operate the inverter 2 in the linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the driving transformer. A signal line 5025 is connected to the gate electrode of a transistor 5022. A voltage equal to or greater than the threshold voltage Vth of the transistor 5022 is applied.

[0337] When analog gradation driving is performed, the gate electrode of the driving transistor 5022 is connected to the light emitting element 50 24 plus the threshold voltage Vth of the driving transistor 5022. A voltage is applied to the driving transistor 5022 so that the driving transistor 5022 operates in the saturation region. A signal is input to cause a current to flow through the light emitting element 5024. Also, the driving transistor 5022 is saturated. In order to operate the transistor 5022 in the low-side region, the potential of the power supply line 5027 is By making the video signal analog, the light emitting element 5024 receives the video signal. A current corresponding to the signal flows, enabling analog gray scale driving.

[0338] Note that the pixel configuration of a display device according to one embodiment of the present invention is not limited to that shown in FIG. For example, a pixel circuit shown in FIG. 23C may include a switch, a resistor, a capacitor, a sensor, a transistor, and a A register or logic circuit may be added.

[0339] When the above-mentioned transistor is applied to the circuit illustrated in FIG. 23, the source electrode ( The drain electrode (first electrode) is electrically connected to the high potential side, and the drain electrode (second electrode) is electrically connected to the low potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential of the second gate electrode is controlled by a control circuit or the like. The potentials given above, such as a potential lower than the potential given to the source electrode, can be input to the electrode. It is sufficient to complete it.

[0340] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various A display element, a display device, a light-emitting element, or a light-emitting device can have various elements. , EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, graphene Rating light valve (GLV), plasma display panel (PDP), MEM S (Microelectromechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), IMOD (Interference Modulation) (energy modulation) element, electrowetting element, piezoelectric ceramic disk The display device has at least one of a display element using a carbon nanotube, etc. In addition to these, contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects. An example of a display device using an EL element is an EL display. An example of a display device using electron emission elements is the field emitter. Surrounding Display (FED) or Surrounding Display (SED) face-conduction electron-emitter display An example of a display device using liquid crystal elements is a liquid crystal display (transmission type liquid crystal display). LCD, semi-transmissive LCD, reflective LCD, direct-view LCD These include display devices that use electronic ink or electrophoretic elements. An example of such a display device is electronic paper.

[0341] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light (W In order to display full color on a display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) , yellow (Y), etc. can be used in appropriate combination. The color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the amount of light emitted by organic EL elements and inorganic EL elements by about 30%. When using elements to display full color, R, G, B, Y, and W are each represented by a light emitting element. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be further reduced.

[0342] <module> A display module including a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG. The explanation will be given using:

[0343] The display module 8000 shown in FIG. 24 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 is connected to FPC8003, and touch panel 8005 is connected to FPC8005. Cell 8006, backlight unit 8007, frame 8009, printed circuit board 801 0 and a battery 8011. 011, the touch panel 8004 may not be provided.

[0344] The semiconductor device according to one embodiment of the present invention can be used for the cell 8006, for example.

[0345] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the cell 8005. The shape and dimensions can be changed as appropriate to fit the size of 06.

[0346] The touch panel 8004 is a resistive or capacitive touch panel. The cell 8006 can be used by overlapping it with the opposite substrate (sealing substrate). It is also possible to provide a panel function. It is also possible to provide an optical sensor to make it an optical touch panel. It is also possible to provide a touch sensor electrode in each pixel to create a capacitive touch panel. It is.

[0347] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the unit 8007 and may be configured to use a light diffusion plate.

[0348] The frame 8009 protects the cell 8006 and also operates the printed circuit board 8010. It may also have a function as an electromagnetic shield to block the electromagnetic waves generated. The plate 8009 may function as a heat sink.

[0349] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. In some cases, the battery 8011 may not be required.

[0350] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0351] <Electronic equipment> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0352] FIG. 25A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. 25A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0353] FIG. 25B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit 9 13, a second display unit 914, a connection unit 915, an operation key 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 may be configured to switch according to the angle between the first display unit 913 and the second display unit 913. and a display having a function as a position input device added to at least one of the first and second display units 914. The function of the position input device may be achieved by touching the display device. The function as a position input device can be added by providing a touch panel. It can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It is possible.

[0354] FIG. 25C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0355] FIG. 25(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, and a freezer door 93. Holds 3rd place.

[0356] FIG. 25E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0357] FIG. 25(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear window. It has 954 etc.

[0358] <Electronic device having a curved display or light-emitting area> Hereinafter, an electronic device having a curved surface in a display area or a light-emitting area, which is an example of an electronic device according to one aspect of the present invention, will be described. The electronic device having the above-mentioned configuration will be described with reference to FIG. As an example, an information device, particularly an information device having portability (portable device) will be described. Examples of information devices with mobile capabilities include mobile phones (phablets, smartphones ( This also includes smartphones, tablet devices (slate PCs), etc.

[0359] FIG. 26(A-1) is a perspective view illustrating the external shape of the mobile device 1300A. FIG. 26(A-3) is a top view of the portable device 1300A. FIG.

[0360] FIG. 26(B-1) and FIG. 26(B-2) are perspective views illustrating the external shape of the portable device 1300B. FIG.

[0361] FIG. 26(C-1) and FIG. 26(C-2) are perspective views illustrating the external shape of the portable device 1300C. FIG.

[0362] <Mobile devices> The portable device 1300A has functions such as telephone, email creation and viewing, notebook or information viewing, etc. It has one or more functions selected from the above.

[0363] The mobile device 1300A has display units provided along multiple surfaces of the housing. The display unit can be provided by arranging a display device having a transparent property along the inside of the housing. This allows text information, image information, etc. to be stored in the first area 1311 and / or the second area 1312. It can be displayed at 1312.

[0364] For example, images for three operations can be displayed in the first area 1311 (see FIG. 26(A-1). In addition, as shown in the dashed rectangle in the figure, text information, etc., is stored in the second area. It can be displayed in area 1312 (see FIG. 26(A-2)).

[0365] When the second region 1312 is placed on the top of the mobile device 1300A, the mobile device 1300A In the state where the portable device 1300A is stored in the breast pocket of the clothes, The user can easily check the displayed text and image information (Figure 26 (A-3) For example, the telephone number or name of the caller of an incoming call may be recorded on the mobile device 130. It can be observed from above 0A.

[0366] The portable device 1300A may have an input device between the display device and the housing, in the display device, or on the housing. The input device may include, for example, a touch sensor, a light sensor, an ultrasonic sensor, etc. When the input device is disposed between the display device and the housing or on the housing, a matrix is ​​used. Resistive switch type, resistive film type, ultrasonic surface acoustic wave type, infrared type, electromagnetic induction type, A capacitive touch panel may be used. Alternatively, the input device may be placed inside the display device. In this case, an in-cell type sensor or an on-cell type sensor may be used.

[0367] The mobile device 1300A includes a vibration sensor and a vibration sensor that detects the vibration. The device is provided with a storage device storing a program for switching to a mode for rejecting incoming calls based on the above. This allows the user to lightly tap the portable device 1300A on the clothes to vibrate it. By providing this, the device can be switched to a mode in which incoming calls are rejected.

[0368] The mobile device 1300B has a display unit having a first area 1311 and a second area 1312. The display device 1300 has a housing 1310 for supporting a display unit.

[0369] The housing 1310 has a plurality of bends, and the longest bend of the housing 1310 is the first region. It is sandwiched between a first region 1311 and a second region 1312.

[0370] The portable device 1300B has a second region 1312 on the side, which is provided along the longest bend. It can be used towards.

[0371] The mobile device 1300C has a display unit having a first area 1311 and a second area 1312. The display device 1300 has a housing 1310 for supporting a display unit.

[0372] The housing 1310 has a plurality of bends, and the second longest bend of the housing 1310 is The first region 1311 and the second region 1312 .

[0373] The portable device 1300C can be used with the second area 1312 facing up. EXAMPLES

[0374] In this embodiment, the insulator containing excess oxygen is silicon oxide or silicon oxynitride. Pure phosphorus was added and oxygen release by TDS was evaluated.

[0375] The method for preparing the sample is as follows.

[0376] First, a silicon substrate was prepared as a substrate. Next, the silicon substrate was oxidized by a thermal oxidation method. A first silicon oxide film having a thickness of 100 nm was then formed on the surface by sputtering. Thus, a second silicon oxide film having a thickness of 300 nm was formed.

[0377] The second silicon oxide was formed using a synthetic quartz target and 50 sccm of oxygen as the deposition gas. The pressure was set to 0.4 Pa, the deposition power was set to 1.5 kW (13.56 MHz), and the target The substrate distance was set to 60 mm, and the substrate temperature was set to 100° C. during film formation.

[0378] Next, phosphorus ions (P + ) was injected to obtain Example Sample 1 and Example Sample Sample 2 and Example Sample 3 were prepared.

[0379] The phosphorus ions were added by ion implantation at an acceleration voltage of 30 kV. Sample 1 has a phosphorus ion implantation concentration of 1×10 15 ions / cm 2 Example sample 2 was , phosphorus ion implantation concentration is 2×10 15 ions / cm 2 The example sample 3 is phosphorus The ion implantation concentration is 1×10 16 ions / cm 2 As a comparative example, A sample was prepared that was not implanted with ions.

[0380] FIG. 33 shows the TDS results for Example Sample 1, Example Sample 2, Example Sample 3, and Comparative Example Sample. The relationship between the substrate temperature and the ion intensity of the mass-to-charge ratio (M / z) of 32 is shown in Fig. 1. The samples were cut into 10 mm × 10 mm pieces and the measurement was performed. The gas emitted includes oxygen gas (O2). In this example, the gas detected at M / z 32 All gas is considered to be oxygen gas.

[0381] As shown in FIG. 33, the comparative sample, which is not implanted with phosphorus ions, is On the other hand, the example sample 1, which was implanted with phosphorus ions, released oxygen gas at a temperature of about 1000°C or less. Example Sample 2 and Example Sample 3 released less oxygen gas than the Comparative Example Sample. I found out.

[0382] From FIG. 33, the amount of oxygen released from Example Sample 1 is 8.1×10 15 atoms / cm 2 (2. 7×10 20 atoms / cm 3 ) The amount of oxygen released from Example Sample 2 was 5. 5×10 15 atoms / cm 2 (1.8×10 20 atoms / cm 3 ) was. The amount of oxygen released from Example Sample 3 was 1.1×10 14 atoms / cm 2 (3.7×10 18 atoms / cm 3 The amount of oxygen released from the comparative sample was 1.1×10 1 6 atoms / cm 2 (3.7×10 20 atoms / cm 3 ) Note that the unit The amount of oxygen released per unit area was calculated based on the thickness of the second silicon oxide of 300 nm.

[0383] FIG. 34 shows the amount of released oxygen calculated from FIG. 33. The amount of released oxygen is calculated in terms of oxygen atoms. FIG. 34 shows the relationship between the phosphorus ion implantation concentration and the amount of oxygen released. The amount of oxygen released from a comparative sample into which ions were not implanted is shown by a dashed line.

[0384] Therefore, in order to reduce the amount of oxygen released by heating, an acceleration voltage of 30 kV is required. So, let's say we put 1×10 phosphorus ions into silicon oxide. 15 ions / cm 2 More than 2, preferably ×10 15 ions / cm 2 More preferably, 1×10 16 ions / cm 2 End It was found that a concentration of

[0385] As shown in Figure 33, by implanting phosphorus ions into an insulator that can release oxygen by heating, It can be seen that the amount of oxygen released by heating can be reduced.

[0386] Next, a method for producing Example Sample 4 will be described.

[0387] First, a silicon substrate was prepared as a substrate. Next, the silicon substrate was oxidized by a thermal oxidation method. Then, silicon oxide with a thickness of 3 nm was formed on the surface by CVD. A 00 nm thick silicon oxynitride film was formed.

[0388] Silicon oxynitride was formed with deposition gas of silane 2sccm and nitrous oxide 4000sccm. The pressure was set to 700 Pa, the deposition power was set to 250 W (60 MHz), and the electrode distance was set to 9 m. The film was formed at a substrate temperature of 400°C.

[0389] Next, phosphorus ions (P + ) was injected to prepare Example Sample 4. The phosphorus ions were added by ion implantation at an acceleration voltage of 30 kV. Sample 4 has a phosphorus ion implantation concentration of 1×10 16 ions / cm 2 It was decided.

[0390] Therefore, the difference between Example Sample 3 and Example Sample 4 is that the second silicon oxide is used. The only option is to use silicon oxynitride.

[0391] Next, Example Sample 3 and Example Sample 4 were etched, and the etching depth and the amount of oxygen released were measured. The relationship between the above was evaluated. Example sample 3 and example sample 4 were cut into 10 mm x 10 mm pieces. For TDS measurements, one cut piece of sample was used for each measurement.

[0392] FIG. 35 shows the thickness of the second silicon oxide or silicon oxynitride without etching as a reference ( The amount of oxygen released at each etching depth was plotted. The etchant contains 6.7% ammonium hydrogen fluoride and 12. The experiment was carried out at 20°C using a mixed solution containing 7% (Stella Chemifa LAL500). 5(A) shows the amount of oxygen released from Example Sample 3, and FIG. 35(B) shows the amount of oxygen released from Example Sample 4. Each is shown.

[0393] FIG. 35 shows the calculated second silicon oxide or silicon oxynitride. The calculation is based on the TRIM (Transport of Ion in M atter) and the density is 2.2g / cm 3 The calculations were carried out as follows: It was found that the maximum phosphorus concentration was found at a thickness of about 50 to 60 nm.

[0394] As shown in FIG. 35(A), in the example sample 3, the second silicon oxide is etched to a depth of 50 nm. It was found that the amount of oxygen released increased by oxidizing the second silicon oxide at 90°C. It was found that the amount of oxygen released was maximized by etching to a depth of 100 nm. As shown in FIG. 35B, in the example sample 4, the silicon oxynitride is etched to a depth of 78 nm. It was found that the amount of oxygen released increased when silicon oxynitride was 83 nm. It was found that the amount of oxygen released was maximized by etching to a depth of 100 nm.

[0395] As shown in Figure 35, when the area where the phosphorus concentration in the insulator is at its maximum is etched, the amount of oxygen released is It was found that the phosphorus concentration changed significantly. 20 atoms / c m 3 It was found that by doing so, a region exhibiting high oxygen blocking properties could be formed. It was also found that oxygen released by heating was retained in the low phosphorus concentration region. It was.

[0396] From this example, insulators containing excess oxygen, such as silicon oxide and silicon oxynitride, It can be seen that by adding phosphorus as an impurity, an oxygen blocking region can be formed. EXAMPLES

[0397] In this embodiment, boron is added as an impurity to silicon oxide, which is an insulator containing excess oxygen. The oxygen release due to TDS was evaluated.

[0398] The method for preparing the sample is as follows.

[0399] First, a silicon substrate was prepared as a substrate. Next, the silicon substrate was oxidized by a thermal oxidation method. A first silicon oxide film having a thickness of 100 nm was then formed on the surface by sputtering. Thus, a second silicon oxide film having a thickness of 300 nm was formed.

[0400] The second silicon oxide was formed using a synthetic quartz target and 50 sccm of oxygen as the deposition gas. The pressure was set to 0.4 Pa, the deposition power was set to 1.5 kW (13.56 MHz), and the target The substrate distance was set to 60 mm, and the substrate temperature was set to 100° C. during film formation.

[0401] Next, boron ions (B + ) to prepare Example Sample 5. did.

[0402] The boron ions were added by ion implantation at an acceleration voltage of 10 kV. Sample 5 has a boron ion implantation concentration of 1×10 16 ions / cm 2 In addition, the comparison As an example sample, a sample without ion implantation was prepared. It is the same as the sample shown in the previous example.

[0403] FIG. 36 shows the relationship between the substrate temperature and the M / z of 32 in Example Sample 5 and Comparative Example Sample by TDS. The relationship between the on-state intensity and the TDS measurement was performed on each sample cut into 10 mm x 10 mm pieces. This was carried out against.

[0404] As shown in FIG. 36, the comparative sample, which is not implanted with boron ions, shows a Oxygen gas was released at temperatures below 0°C. On the other hand, Example Sample 5, which was implanted with boron ions, It was found that the amount of oxygen gas released was smaller than that of the comparative sample.

[0405] From FIG. 36, the amount of oxygen released from Example Sample 5 is 3.1×10 15 atoms / cm 2 (1. 0×10 20 atoms / cm 3 The amount of oxygen released by the comparative sample was 1.1 ×10 16 atoms / cm 2 (3.7×10 20 atoms / cm 3 ) It was The amount of oxygen released per unit volume was calculated based on the thickness of the second silicon oxide, 300 nm.

[0406] Therefore, in order to reduce the amount of oxygen released by heating, an acceleration voltage of 10 kV is required. So, let’s say we add 1×10 boron ions to silicon oxide. 16 ions / cm 2 Injected at a concentration of I found out what I should do.

[0407] As shown in Figure 36, boron ions are implanted into an insulator that can release oxygen when heated. This also shows that the amount of oxygen released by heating can be reduced.

[0408] In this example, boron was added as an impurity to silicon oxide, which is an insulator containing excess oxygen. It can be seen that the oxygen blocking region can also be formed by adding [Explanation of symbols]

[0409] 50 Substrates 52 Insulators 53 areas 56 Semiconductors 68 Insulators 69 areas 400 Substrates 402 Insulator 404 Conductors 405 Conductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 408 Insulator 412 Insulators 413 Conductors 416a Conductor 416b Electric conductor 418 Insulator 423 areas 424a Conductor 424b Conductor 426a Conductors 426b Conductors 428 Insulator 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 1300A Portable Devices 1300B Portable Devices 1300C Portable Devices 1310 Case 1311 area 1312 area 2100 Transistor 2200 Transistor 2201 Insulators 2202 Conductors 2203 Conductors 2204 Insulators 2205 Conductors 2206 Conductors 2207 Insulators 2208 Insulator 2211 Semiconductor substrate 2212 Insulators 2213 Gate electrode 2214 Gate insulator 2215 Source and drain regions 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF tags 5000 boards 5001 Pixel unit 5002 Scanning line driver circuit 5003 Scanning line driver circuit 5004 Signal line driver circuit 5010 Capacitor wiring 5012 Gate wiring 5013 Gate wiring 5014 Drain electrode 5016 Transistor 5017 Transistor 5018 Liquid crystal element 5019 Liquid crystal element 5020 pixels 5021 Switching transistor 5022 Driving transistor 5023 Capacitive element 5024 Light emitting element 5025 Signal Line 5026 Scan Lines 5027 Power line 5028 Common electrode 5100 pellets 5120 PCB 5161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Cell 8007 Backlight unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery< / cpu>

Claims

1. a first transistor having a first channel formation region including silicon; a second transistor having a second channel formation region including an oxide semiconductor, a first conductive layer having a region located over the first channel formation region and functioning as a gate electrode of the first transistor; a first insulating layer having a region overlying the first conductive layer; a second conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a first gate electrode of the second transistor; an oxide semiconductor layer having a region located above the second conductive layer and having the second channel formation region; a second insulating layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the second insulating layer and functioning as a second gate electrode of the second transistor; a third insulating layer having a region located above the third conductive layer; a fourth conductive layer having a region located above the third insulating layer and electrically connected to one of the source and the drain of the second transistor through an opening provided in the third insulating layer; a fifth conductive layer having a region in contact with an upper surface of the first insulating layer and electrically connected to one of the source and drain of the first transistor; the fourth conductive layer and the fifth conductive layer have an overlapping region; a shortest distance between a lower surface of the third conductive layer and an upper surface of the first insulating layer is shorter than a shortest distance between a lower surface of the oxide semiconductor layer and an upper surface of the first insulating layer in a cross-sectional view in a channel width direction of the second transistor.

2. In claim 1, the oxide semiconductor layer has a first region in contact with the fourth conductive layer and a second region not overlapping with the opening, a thickness of the oxide semiconductor layer in the first region is smaller than a thickness of the oxide semiconductor layer in the second region.

3. In claim 1 or 2, the fourth conductive layer is not electrically connected to the fifth conductive layer in a cross-sectional view in a channel length direction of the second transistor.

Images