Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics and high reliability.SOLUTION: A semiconductor device includes: a first insulator; a first conductor and a second conductor on the first insulator; an oxide disposed between the first conductor and the second conductor; a second insulator on the first conductor, the second conductor, and the oxide; and a third conductor on the second insulator. A side surface of the first conductor includes a region in contact with one side surface of the oxide. A side surface of the second conductor includes a region in contact with the other side surface of the oxide. The height of an upper surface of the first conductor, the height of an upper surface of the second conductor, and the height of an upper surface of the oxide are substantially equal. The conductivity of the first conductor is higher than that of the oxide, and the conductivity of the second conductor is higher than that of the oxide.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect of the invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and electronic There are cases where the equipment and the like can be said to include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. An aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the issue of the [Background technology]

[0004] Development of integrated circuits (ICs) using semiconductor elements The development and manufacturing of CPUs and memory requires ICs with higher integration density. Such ICs are mounted on circuit boards, e.g. These are mounted on printed wiring boards to form computers, information terminals, display devices, automobiles, etc. They are used as components in various electronic devices. They are also used in artificial intelligence (AI) systems. Research is also underway to use it in medicine.

[0005] As computers and information terminals, desktop computers, laptop computers, etc. Known examples of such devices include mobile phones, tablet computers, smartphones, and mobile phones.

[0006] Silicon-based semiconductor materials are widely known as semiconductor materials used in semiconductor elements. As another material, oxide semiconductors have been attracting attention.

[0007] In addition, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). . [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0009] One embodiment of the present invention provides a semiconductor device having good electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and Another object of the present invention is to provide a manufacturing method thereof. It is an object of the present invention to provide a semiconductor device that can be integrated and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity and a manufacturing method thereof. It shall be one of the following.

[0010] In addition, in a semiconductor device including a transistor having an oxide semiconductor, One of the objectives is to suppress the on-state current and improve the reliability. Another object of the present invention is to provide a transistor including a high-frequency oxide semiconductor. An object of the present invention is to provide a transistor including an oxide semiconductor and having a low current. Another object of the present invention is to provide a semiconductor device with reduced power consumption. It is an object of the present invention to provide a semiconductor device with an improved wave number.

[0011] Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a module for implementing the semiconductor device or the module. One of the objectives of the present invention is to provide an electronic device having a module.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a semiconductor device comprising a first insulator, a first conductor on the first insulator, and a second conductor. an oxide disposed between the first conductor and the second conductor; and a second insulator on the second conductor and on the oxide, and a third conductor on the second insulator; The side surface of the first conductor has a region in contact with one side surface of the oxide, and the second conductor The side of the oxide has a region in contact with the other side of the oxide, and the height of the upper surface of the first conductor and the height of the second conductor are The height of the top surface of the conductor and the height of the top surface of the oxide are approximately equal, and the first conductor a first conductor having a higher electrical conductivity than the oxide, and a second conductor having a higher electrical conductivity than the oxide, It is.

[0014] The first conductor and the second conductor are each selected from the group consisting of In, Sn, W, Ti, and It is preferable that the Si content is at least one of Si.

[0015] The first conductor and the second conductor are each selected from the group consisting of Zn, Ti, Ga, and Nb. It may include any one or more of the following.

[0016] The oxide is made of In, an element M (wherein M is Al, Ga, Y, or Sn), and Zn. It is preferred that it includes

[0017] In addition, the carrier density of the first conductor and the second conductor is higher than the carrier density of the oxide. It is preferable that the difference is higher than the above.

[0018] In one embodiment of the present invention, a first insulator is formed over a substrate, and an oxide film is formed over the first insulator. A mask is formed on the oxide film by lithography, and the oxide film is removed from the area that does not overlap with the mask. The oxide is formed by removing the conductive film, and a conductive film is formed by covering the oxide with a mask. Part of the conductive film is isotropically etched to expose the side of the mask, and the mask is then removed. In this manner, the conductive film on the mask is lifted off.

[0019] In addition, the conductive film is preferably formed by a sputtering method.

[0020] In addition, a film forming method in which the film forming speed of the conductive film is slower in the horizontal direction than in the vertical direction is used. is preferred. Effect of the Invention

[0021] According to one embodiment of the present invention, a semiconductor device having good electrical characteristics and a manufacturing method thereof are provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, miniaturization or high integration can be achieved. In addition, according to one embodiment of the present invention, a semiconductor device and a manufacturing method thereof can be provided. A semiconductor device with higher productivity and a manufacturing method thereof can be provided.

[0022] In addition, in a semiconductor device including a transistor having an oxide semiconductor, In addition, the oxide semiconductor, which has a large on-current, can be used. In addition, a transistor having an oxide semiconductor with a low off-state current can be provided. It is possible to provide a transistor having a conductor. It is also possible to provide a semiconductor device having an improved operating frequency. can.

[0023] Alternatively, a novel semiconductor device can be provided. Alternatively, a semiconductor device or a module having the semiconductor device or the module can be provided. An electronic device can be provided.

[0024] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0025] [Figure 1] Fig. 1A is a top view showing the semiconductor device, and Fig. 1B and Fig. 1C are cross-sectional views showing the semiconductor device. [Diagram 2] Fig. 2A is a top view showing the semiconductor device, and Fig. 2B and Fig. 2C are cross-sectional views showing the semiconductor device. [Diagram 3] Fig. 3A is a top view showing the semiconductor device, and Fig. 3B and Fig. 3C are cross-sectional views showing the semiconductor device. [Figure 4] Fig. 4A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 4B and Fig. 4C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Diagram 5] Fig. 5A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 5B and Fig. 5C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 6] Fig. 6A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 6B and Fig. 6C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 7] Fig. 7A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 7B and Fig. 7C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 8] Fig. 8A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 8B and Fig. 8C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 9] Fig. 9A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 9B and Fig. 9C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 10] Fig. 10A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 10B and Fig. 10C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 11] Fig. 11A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 11B and Fig. 11C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 12] Fig. 12A is a top view illustrating a method for manufacturing a semiconductor device, and Fig. 12B and Fig. 12C are cross-sectional views illustrating the method for manufacturing a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating the energy band structure of an oxide semiconductor. [Figure 14] FIG. 14 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 15] Fig. 15A is a block diagram showing a configuration example of a storage device, and Fig. 15B is a schematic diagram showing a configuration example of a storage device. [Figure 16] 16A to 16H are circuit diagrams showing configuration examples of a memory device. [Figure 17] Fig. 17A is a block diagram of the semiconductor device, and Fig. 17B is a schematic diagram of the semiconductor device. [Figure 18] 18A to 18E are schematic diagrams of a storage device. [Figure 19] 19A to 19F are diagrams showing electronic devices. [Figure 20] FIG. 20 is a graph showing the dependency of the sheet resistance of indium tin oxide on the heat treatment time. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiment.

[0027] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The figures are merely schematic illustrations, and are not limited to the shapes or values ​​shown in the drawings. During the manufacturing process, layers and resist masks may become unintentionally damaged due to processes such as etching. However, in order to make it easier to understand, this may not be reflected in the drawings. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, when referring to the same function, The hatch patterns are the same and may not be numbered.

[0028] In addition, in particular in top views (also called "plan views") and perspective views, etc., the invention is easily understood. In order to simplify the illustration, some of the components may be omitted. may be omitted.

[0029] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second In addition, the terms "the" or "the third" may be used interchangeably in the description of the present specification. The ordinal numbers listed in the specification do not match the ordinal numbers used to identify an aspect of the present invention. There are cases.

[0030] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0031] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are both considered to be disclosed in this specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. The connections other than those shown in the drawings or text are also included in the drawings or text. Let us assume that.

[0032] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0033] An example of a direct connection between X and Y is The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, An element (e.g., a switch, transistor, or capacitor) that allows electrical connection between X and Y. (capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) In this case, X and Y are connected.

[0034] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be on and off. A switch can be in a conductive state (on) or a non-conductive state (off) to allow current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This also includes the case where and Y are directly connected.

[0035] An example of a case where X and Y are functionally connected is the case where the functional connection between X and Y is possible. Circuits that perform the functions of the following: logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) (e.g., circuits that generate One or more devices (such as a synthesis circuit, memory circuit, or control circuit) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X is If the signal is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. This also includes the case where Y is electrically connected.

[0036] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A channel forming region is formed between the source and drain through the channel forming region. In this specification and the like, the term "channel formation region" refers to a refers to the region through which current mainly flows.

[0037] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0038] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate (the part of the semiconductor through which current flows) overlaps with the This refers to the distance between the source and drain in the region where the channel is formed. In addition, the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one of the lengths in the region where the channel is formed. The value, maximum, minimum or average value.

[0039] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate and the junction (where the current flows) overlap, or the region where the channel is formed The length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of the transistor may not be determined to a single value. In the above, the channel width is any one value, maximum value, or maximum in the region where the channel is formed. The minimum or average value.

[0040] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter also referred to as the "effective channel width") shown in the top view of the transistor The channel width that is actually used (hereinafter also referred to as the "apparent channel width") may differ from the For example, if the gate covers the side of the semiconductor, the effective channel width is For example, when the gate width is too small, the effect of the gate width cannot be ignored. In a transistor in which the side of the semiconductor is covered by a metal, the channel formation region is formed on the side of the semiconductor. In this case, the effective channel width is larger than the apparent channel width. The channel width is larger.

[0041] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0042] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW: S In addition, in this specification, In this document, when simply referring to channel width, it means enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used, It may refer to the effective channel width. Note that channel length, channel width, and effective channel The channel width, apparent channel width, and enclosed channel width are determined by analyzing cross-sectional TEM images. The value can be determined, for example, by

[0043] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor characteristics may be deteriorated. The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, for example: Hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Oxides In the case of a semiconductor, water may also function as an impurity. In some cases, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of a semiconductor include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0044] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. For example, the oxygen content is preferably 55 atomic % or more and 65 atomic % or less. , nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The concentration range of 0.1 atomic % to 10 atomic % is also called oxynitride. A silicon film is a film whose composition contains more nitrogen than oxygen. Preferably, nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, Silicon concentration is 25 atomic % to 35 atomic % and hydrogen concentration is 0.1 atomic % to 10 atomic % It refers to what is included in the range.

[0045] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0046] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0047] In addition, the transistors shown in this specification and the like are not field-effect transistors unless otherwise specified. In addition, unless otherwise specified, the transistors shown in this specification and the like are n Therefore, its threshold voltage (also called "Vth") is , unless expressly stated, shall be greater than 0V.

[0048] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that the two straight lines are arranged at an angle of -30° to 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0049] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is considered to be included in the hexagonal crystal system. It is assumed that

[0050] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from passing through. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I call.

[0051] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal An oxide may be called an oxide semiconductor. In other words, the transistor can be a transistor including an oxide or an oxide semiconductor.

[0052] (Embodiment 1) <Configuration Example 1 of Semiconductor Device> 1A, 1B, and 1C show a transistor 200 according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a transistor 200 and its surroundings.

[0053] FIG. 1A is a top view of a semiconductor device having a transistor 200. 1B is a cross-sectional view of the semiconductor device shown in FIG. 1A along line A1-A2. 1 is a cross-sectional view of a portion indicated by a dashed line in FIG. 1, and is a cross-sectional view of a transistor 200 in a channel length direction. FIG. 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in FIG. 1A. It is also a cross-sectional view of the transistor 200 in the channel width direction. Some elements have been omitted for clarity.

[0054] The semiconductor device according to one embodiment of the present invention includes an insulator 214 on a substrate (not shown), A transistor 200 on the top, an insulator 280 on the transistor 200, and a The insulator 214, the insulator 280, and the insulator 281 are interlayer films. Also, a conductive layer that is electrically connected to the transistor 200 and functions as a plug. The plug includes a conductor 240 (conductor 240a and conductor 240b). An insulator 241 (insulator 241a and insulator 241b) is provided on the side of the functional conductor 240. 1b) is provided on the insulator 281 and the conductor 240. The conductor 246 (conductor 246a and conductor 246b) is electrically connected to the 46b) is provided.

[0055] In addition, the insulators 272, 280, and 281 are in contact with the inner walls of the openings. 241a is provided, and a first conductor of the conductor 240a is provided in contact with the side surface of the first conductor 241a. A second conductor of the conductor 240a is provided inside the insulator 272. 280, and an insulator 241b is provided in contact with the inner wall of the opening of the insulator 281. A first conductor of the conductor 240b is provided in contact with the first conductor of the conductor 240b, and a second conductor of the conductor 240b is provided further inward. Here, the height of the upper surface of the conductor 240 and the upper surface of the insulator 281 are In the transistor 200, the height of the first conductor of the conductor 240 can be made to be approximately the same. The present invention is not limited to the above-mentioned configuration, but may be modified in various ways. For example, the conductor 240 may be a single layer or a laminated structure of three or more layers. In the case where the structure has a laminated structure, ordinal numbers are given in the order of formation, and the layers are divided into groups. There may be cases where it is different.

[0056] [Transistor 200] As shown in FIG. 1, the transistor 200 includes an insulator 216 on an insulator 214 and an insulator A conductor 205 disposed so as to be embedded in the insulator 216, and a conductor Insulator 222 on 205, insulator 224 on insulator 222, and conductor on insulator 224 242a and conductor 242b, and a conductive material disposed between the conductive material 242a and the conductive material 242b The oxide 230, the conductor 242a, the conductor 242b, and the insulator 25 on the oxide 230. 0 and the conductor 260 (conductor 260a and conductor 260b) on the insulator 250. In addition, the side surface of the conductor 242a has an area in contact with one side surface of the oxide 230. The side of the conductor 242b has a region in contact with the other side of the oxide 230. The height of the upper surface of the conductor 242a, the height of the upper surface of the conductor 242b, and the height of the upper surface of the oxide 230 The heights are roughly the same.

[0057] In addition, the insulators 222, 272, and 281 are each formed of hydrogen (e.g., hydrogen atoms). It is preferable that the material has a function of suppressing the diffusion of at least one of hydrogen molecules and the like. The insulators 222, 272, and 281 are made of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable that the insulating material has a function of suppressing the diffusion of at least one of the molecules. 222, insulator 272, and insulator 281 have higher oxygen and It is preferable that one or both of the insulators have low hydrogen permeability. and the insulator 281 have higher permeability to one or both of oxygen and hydrogen than the insulator 250. The insulators 222, 272, and 281 preferably have low transmissivity. Each of these preferably has a lower permeability to oxygen and / or hydrogen than the insulator 280. .

[0058] As shown in FIG. 1B and FIG. 1C, the insulator 272 is disposed on the top and side surfaces of the conductor 260 and the insulator The side of 250, the top and side of conductor 242a, the top and side of conductor 242b, and the insulating It is preferable that the insulator 280 contacts the upper surface of the insulator 272. The insulating layer 272 separates the insulating layer 224 from the oxide 230. The permeation of oxygen and / or hydrogen from the insulator 280 to the conductor 260 is suppressed. In this way, oxidation of the conductor 260 can be suppressed.

[0059] In the transistor 200, the oxide 23 is formed in the channel formation region and in the vicinity thereof. Although a single layer structure of 0 is shown, the present invention is not limited to this. For example, A multi-layer structure or a stacked structure of three or more layers may be provided. Although the conductor 260 is shown in FIG. 1 as having a two-layer structure, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers. This is also fine.

[0060] Here, conductor 260 serves as the gate of transistor 200, and conductor 242a and conductor 242b function as a source and a drain, respectively. The transistor 200 has an oxide 230 including a channel formation region, which functions as an oxide semiconductor. It is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor).

[0061] The transistor 200 having an oxide semiconductor in a channel formation region is in a non-conducting state. Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be formed into films by sputtering or the like, and therefore are suitable for use as highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0062] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum or gallium). Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, yttrium, or the like. The oxide 230 may be In-Ga oxide, In- Zn oxide may also be used.

[0063] In addition, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate, resulting in poor reliability. In addition, oxygen vacancies may exist in a region in an oxide semiconductor where a channel is formed. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in the region to be covered are reduced as much as possible. This transistor has stable electrical characteristics and improved reliability. The data can be provided.

[0064] In addition, the oxide 230 is provided so as to contact both sides thereof and functions as a source or drain. The conductive material 242 (the conductive material 242a and the conductive material 242b) that can be used is a conductive oxide. In particular, it is preferable to use a substitutional type impurity in which the generation of carriers does not depend only on oxygen vacancies. It is preferable that the oxide is a conductive oxide that generates carriers by pure donors. Even if the oxygen vacancies in the conductor 242 are repaired by excess oxygen, the carrier density in the conductor 242 Therefore, the conductive oxide can suppress the decrease in the conductivity even in a state where there are few oxygen vacancies. It is believed that carriers are generated, which makes it possible to create a transistor with high on-state characteristics. The conductor 242 may be any one of tin, tungsten, titanium, and silicon. It is preferable that the oxide contains indium or indium tin oxide. Tungsten-containing indium oxide, tungsten oxide-containing indium zinc oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Zinc oxide and indium tin oxide doped with silicon may also be used.

[0065] Alternatively, zinc oxide doped with gallium or titanium oxide doped with niobium may be used.

[0066] In addition, the electrical conductivity of the conductor 242 is preferably higher than the electrical conductivity of the oxide 230. In addition, the carrier density of the conductor 242 is preferably higher than the carrier density of the oxide 230. With this structure, the oxide 230 functions as a channel formation region, and the conductive The current collector 242 can function as a source or a drain.

[0067] As shown in FIG. 1B, a transistor 200 according to one embodiment of the present invention has a channel formation region The oxide 230, which functions as a source or drain, is connected to the conductor 24, which functions as a source or drain, on both sides of the oxide 230. 2. The height of the upper surface of the conductor 242 and the thickness of the oxide 230 are The heights of the upper surfaces are approximately equal. With this configuration, the channel formation of the oxide 230 The shortest distance between the top surface of the region and the conductor 260 functioning as a gate is Since the distance between the first and second electrodes is approximately equal to the shortest distance between the first and second electrodes 260, a transistor with a small parasitic capacitance is provided. In addition, a step is formed between the channel formation region of the oxide 230 and the conductor 260. is not formed or is only slightly formed on the channel forming region of the oxide 230, The insulator 250 on the conductor 242 can be provided without overcoming any steps, so that the insulation This is preferable because it improves the covering property of the insulator 250 and improves the dielectric strength voltage of the insulator 250.

[0068] As shown in FIG. 1C, a conductor 260 functioning as a gate is disposed in the channel forming region. The side and top surfaces of the oxide 230 are covered with an insulator 250. The electric field of the oxide 260 in the channel formation region can be easily applied to the entire oxide 230 in the channel formation region. The on-current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0069] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, it is possible to provide a semiconductor device having a transistor with high frequency characteristics. Alternatively, the fluctuation of the electrical characteristics can be suppressed, and the electrical characteristics can be stabilized while improving reliability. It is possible to provide a semiconductor device having an improved off-state current. It is possible to provide a semiconductor device having the above structure.

[0070] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0071] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Preferably, the conductor 205 is embedded in the insulator 216 .

[0072] Here, the conductor 260 functions as a first gate (also called a top gate). The conductor 205 also functions as a second gate (also called a bottom gate). In this case, the potential applied to the conductor 205 may be different from the potential applied to the conductor 260. By changing the voltages independently, the Vth of the transistor 200 can be controlled. In particular, applying a negative potential to the conductor 205 can It is possible to increase Vth above 0V and reduce the off-current. Applying a negative potential to 205 reduces the potential applied to the conductor 260 compared to not applying a negative potential. The drain current when the potential is 0V can be reduced.

[0073] As shown in FIG. 1A, the conductor 205 is set to be larger than the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 is disposed in the oxide 230 along the channel width direction. It is preferable that the film is stretched even in the region outside the end intersecting with the acid direction. The conductor 205 and the conductor 26 are disposed on the outer side of the side surface of the oxide 230 in the channel width direction. It is preferable that the conductor 205 overlaps the conductor 202 via an insulator. By doing so, in the processing using plasma in the manufacturing process after the formation of the conductor 205, It may be possible to alleviate localized charging (called charge-up). One aspect of the invention is not limited to this. The conductor 205 includes at least the conductor 242a and the conductor It is sufficient to overlap with the oxide 230 located between the conductive material 242b.

[0074] With the above configuration, the electric field of the conductor 260 having the function of the first gate and The electric field of the conductor 205, which functions as a second gate, energizes the channel forming region. In the present specification, the first gate and the second gate The structure of a transistor in which the channel formation region is electrically surrounded by an electric field is called surro This is called the unded channel (S-channel) structure.

[0075] The conductor 205 is in contact with the inner wall of the opening of the insulator 216, and a lower layer of the conductor 205 is formed. The upper layer of the conductor 205 is formed inside the lower layer of the conductor 205. The height of the upper surface of the body 205 and the height of the upper surface of the insulator 216 can be approximately the same.

[0076] Here, the lower layer of the conductor 205 is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, and nitrogen molecules. It has a function to suppress the diffusion of impurities such as nitrogen oxide molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use a conductive material that has a high conductivity (i.e., the impurities are unlikely to penetrate the conductive material). Has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material (which is difficult for oxygen to permeate). The function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of either the above impurities or the above oxygen. In this specification, the term "a material having such a function" refers to a material having a function of suppressing one or all of the diffusions. Such a conductor may be called a conductive barrier film.

[0077] The lower layer of the conductor 205 has a function of suppressing the diffusion of oxygen, It is possible to prevent the upper layer from oxidizing and decreasing the conductivity. Function of suppressing oxygen diffusion Examples of conductive materials having the formula include titanium, titanium nitride, tantalum, tantalum nitride, It is preferable to use ruthenium or ruthenium oxide. The underlayer film may be a single layer or a multilayer of the above-mentioned conductive material. The impurities such as the above are prevented from diffusing into the transistor 200 through the conductor 205. In this embodiment, the conductor 205a is made of tantalum nitride and titanium nitride. Use .

[0078] The upper layer of the conductor 205 is made of a material mainly composed of tungsten, copper, or aluminum. In this embodiment, a conductive material having a high conductivity is used as the upper layer of the conductor 205. , tungsten is used.

[0079] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and the oxide The insulating or conductive material on the upper layer of the oxide semiconductor is separated into different layers without being exposed to the atmosphere. By continuously depositing the seeds, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity This is preferable because a highly intrinsic oxide semiconductor film can be formed.

[0080] For example, a deposition apparatus having multiple process chambers may be used to deposit the insulator 216 and the conductive layer 217. Disposed on body 205 are insulator 222, insulator 224, and oxide 230. The films may be formed successively in sequence.

[0081] The insulators 214, 272, and 281 are configured to prevent impurities such as water or hydrogen from A barrier insulating film that prevents foreign matter from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 214, the insulator 272, and the insulator The body 281 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (NO , NO, NO2, etc.), and has the function of suppressing the diffusion of impurities such as copper atoms (the above impurities It is preferable to use an insulating material through which oxygen (e.g., oxygen atoms) does not easily penetrate. The material has a function of suppressing the diffusion of at least one of oxygen molecules (the material is difficult for the oxygen to permeate). a) It is preferable to use an insulating material.

[0082] For example, it is preferable to use silicon nitride as the insulator 214 and the insulator 281. This is preferable. As a result, impurities such as water or hydrogen are absorbed from the substrate side to the transistor side rather than the insulator 214. It is possible to suppress the diffusion of the oxide to the transistor 200 side. This can suppress the oxygen from diffusing toward the substrate side relative to the insulator 214.

[0083] For example, aluminum oxide or the like can be used as the insulator 272. As a result, impurities such as water or hydrogen are absorbed into the insulator 272 located above the insulator 272. 80, or / and conductor 246, etc., to the transistor 200 side. It is possible.

[0084] The insulator 214 and the insulator 281 may have a laminated structure. The laminated structure of the aluminum film and the silicon nitride film is formed on the insulator 214 and the insulator 281. It is preferable to use the aluminum oxide film to supply oxygen to the lower part of the insulator 214. In addition, the silicon nitride film can expand from the substrate side to the transistor 200 side. The diffusion of impurities such as hydrogen and water can be suppressed. In addition, the silicon nitride film can supply oxygen to the transistor 2 from the outside. It is possible to suppress the diffusion of impurities such as hydrogen and water that diffuse to the 00 side.

[0085] In addition, the insulators 216 and 280 have a lower dielectric constant than the insulator 214. It is preferable to use a material with a low dielectric constant as the interlayer film to reduce the parasitic capacitance between wirings. For example, the insulator 216 and the insulator 280 may be made of silicon oxide, silicon oxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon doped silicon oxide, carbon and nitrogen doped silicon oxide, or vacancy-containing silicon oxide. Silicon oxide or the like may be used appropriately.

[0086] The insulator 222 and the insulator 224 function as gate insulators.

[0087] Here, it is preferable that the insulator 224 in contact with the oxide 230 is heated to release oxygen. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. Therefore, the reliability of the transistor 200 can be improved.

[0088] Specifically, the insulator 224 is made of an oxide material from which some oxygen is released when heated. The oxide that releases oxygen by heating is called TDS (Thermal Dynamics) oxide. The amount of oxygen molecules released was 1.0 ×10 18 molecules / cm 3 More than 1.0×10 19 molecu les / cm 3 More preferably, 2.0×10 19 molecules / cm 3 Below Above, or 3.0×10 20 molecules / cm 3 The oxide film is as above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower, or The range of 100°C or higher and 400°C or lower is preferred.

[0089] The insulator 222 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 is preferably a barrier insulating film that suppresses the It is preferable that the insulator 222 and the insulator 27 have a lower hydrogen permeability than the insulator 224. 2, the insulator 224 and the oxide 230 are surrounded, and water or Impurities such as hydrogen can be prevented from entering the transistor 200 .

[0090] Further, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, Preferably, the body 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 2. This is preferable because it can reduce diffusion below 22. This can suppress reaction with the body 224 and the oxygen contained in the oxide 230.

[0091] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Insulators containing oxides include aluminum oxide, hafnium oxide, aluminum and hafnium oxide, and It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The emission of hydrogen and the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0092] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0093] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 (BST) or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progresses, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as the insulator, the physical thickness can be maintained while This makes it possible to reduce the gate potential during transistor operation.

[0094] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. good.

[0095] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the energy gap should be 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large energy gap, The off-state current of the transistor can be reduced. A semiconductor device with low power consumption can be provided.

[0096] The electron affinity or the energy level Ec of the conduction band minimum is the vacuum level as shown in Figure 13. The ionization potential Ip, which is the difference between Evac and the energy Ev at the top of the valence band, and the The ionization potential Ip can be calculated, for example, from the energy gap Eg. Ultraviolet Photoelectron Spectroscopy (UPS) The energy gap can be measured using a spectroscopy (Energy Gap) device. Eg can be measured, for example, using a spectroscopic ellipsometer.

[0097] The insulator 250 functions as a gate insulator. The insulator 250 is formed on the oxide 230c. The insulator 250 is preferably disposed in contact with the surface. , silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and oxide doped with carbon. Silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies were used. In particular, silicon oxide and silicon oxynitride are stable against heat. This is preferable.

[0098] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing it in contact with the upper surface of the oxide 230c, the channel forming region of the oxide 230b In addition, the insulator 250 can effectively supply oxygen to the insulator 224. It is preferable that the concentration of impurities such as water or hydrogen is reduced. , preferably 1 nm or more and 20 nm or less.

[0099] A metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0100] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the oxide. By making the base insulator have a laminated structure of the insulator 250 and the metal oxide, the base insulator is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. .

[0101] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tin, titanium, tantalum, nickel, germanium, magnesium, etc. The metal oxide may contain one or more metals selected from the following: Aluminum oxide, an insulator containing oxides of either or both of aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a material such as a laminate.

[0102] Alternatively, the metal oxide may function as a part of the gate. In the above, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the conductive material on the channel formation region side, oxygen released from the conductive material forms a channel. This makes it easier for the area to be supplied.

[0103] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing silicon and nitrogen may also be used. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide doped with silicon may also be used. The use of such a material allows the channel to be formed. In some cases, hydrogen can be captured from the metal oxide that is formed. It may be possible to capture hydrogen that is mixed in through insulators, etc.

[0104] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of at least one of the above-mentioned elements.

[0105] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can suppress the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, nitride, and the like. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0106] The conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated material. For example, a laminated structure of titanium, titanium nitride and the conductive material may be used. .

[0107] The insulator 280 may be, for example, silicon oxide, silicon oxynitride, or nitride. Silicon oxide doped with fluorine, silicon oxide doped with carbon, carbon and and silicon oxide doped with nitrogen, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with voids, This is preferable because it makes it possible to easily form a region containing oxygen that is desorbed by heating.

[0108] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. In addition, the top surface of the insulator 280 may be planarized.

[0109] The insulator 281 prevents impurities such as water or hydrogen from entering the insulator 280 from above. It is preferable that the insulator 281 functions as a barrier insulating film that suppresses the insulator 281. An insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. .

[0110] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material having the following components: 0b may have a laminated structure.

[0111] In addition, when the conductor 240 has a laminated structure, the insulator 281, the insulator 280, and the insulator The conductor in contact with the body 272 has a function of suppressing the permeation of impurities such as water or hydrogen. It is preferable to use a conductive material, such as tantalum, tantalum nitride, titanium, or titanium nitride. It is preferable to use titanium, ruthenium, or ruthenium oxide. Conductive materials that have the function of suppressing the permeation of impurities such as hydrogen are used in single layers or multilayers. By using the conductive material, the oxygen added to the insulator 280 can be converted into the conductor 240. a and the conductor 240b. Impurities such as water or hydrogen are oxidized from the layer through the conductors 240a and 240b. It is possible to prevent the foreign matter from being mixed into the object 230.

[0112] The insulators 241a and 241b may be, for example, aluminum oxide or silicon nitride. The insulator 241a and the insulator 241b may be an insulator such as silicon nitride oxide. The body 241b is provided in contact with the insulator 272, and therefore is protected from water or Impurities such as hydrogen are mixed into the oxide 230 through the conductor 240a and the conductor 240b. In addition, oxygen contained in the insulator 280 can be prevented from and can be prevented from being absorbed by the conductor 240b.

[0113] In addition, the conductive material 240a and the conductive material 240b are in contact with each other on the upper surface thereof and function as wiring. Conductor 246 (conductor 246a and conductor 246b) may be arranged. 46 shall be made of conductive materials mainly composed of tungsten, copper, or aluminum. The conductor may have a laminated structure, for example, titanium, titanium nitride, etc. The conductive material may be laminated to the insulating material. The insulating film 11 may be formed so as to be embedded in the insulating film 11 .

[0114] <Configuration Example 2 of Semiconductor Device> Here, a semiconductor device having a transistor 201 having a different configuration from the transistor 200 is used. 2A, 2B, and 2C are diagrams illustrating a transistor according to an embodiment of the present invention. 2A and 2B are a top view and a cross-sectional view of a transistor 201 and the periphery of the transistor 201.

[0115] FIG. 2A is a top view of a semiconductor device including a transistor 201. 2B is a cross-sectional view of the semiconductor device shown in FIG. 2A. 2 is a cross-sectional view of a portion indicated by a dashed line in FIG. 1, and is a cross-sectional view of a transistor 201 in a channel length direction. FIG. 2C is a cross-sectional view of the area indicated by the dashed line A3-A4 in FIG. 2A. 2A is a cross-sectional view of the transistor 201 in the channel width direction. Some elements have been omitted for clarity.

[0116] [Transistor 201] As shown in FIG. 2, the transistor 201 includes an insulator 216 on an insulator 214 and an insulator A conductor 205 disposed so as to be embedded in the insulator 216, on the insulator 216, and on the conductor 2 2. The insulator 222 on the conductor 205, the insulator 224 on the insulator 222, and the conductor 205 on the insulator 224. 42a and conductor 242b, and an acid disposed between conductor 242a and conductor 242b. The oxide 230a and the conductor 242a and the conductor 242b are disposed on the oxide 230a. The oxide 230b is placed on the conductor 242a, the conductor 242b, and the oxide 230b. The oxide 230c, the insulator 250 on the oxide 230c, and the conductor 26 on the insulator 250. 0 (conductor 260a and conductor 260b). The surface has an area in contact with one side surface of the oxide 230a and the oxide 230b, and the conductor 2 The side of 42b has an area in contact with the other side of oxide 230a and oxide 230b. In addition, the height of the upper surface of the conductor 242a, the height of the upper surface of the conductor 242b, and the height of the oxide 242 The heights of the upper surfaces of 30b are approximately equal.

[0117] For example, oxide 230a, oxide 230b, and oxide 230c may be In-M- Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, Beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the group consisting of tungsten, tungsten, and tungsten. The element M may be aluminum, gallium, yttrium, or tin. The material 230 may be In-Ga oxide or In-Zn oxide.

[0118] In addition, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate, resulting in poor reliability. In addition, oxygen vacancies may exist in a region in an oxide semiconductor where a channel is formed. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in the region to be covered are reduced as much as possible. This transistor has stable electrical characteristics and improved reliability. The data can be provided.

[0119] In addition, a saw is provided in contact with both sides of the oxide 230a and the oxide 230b. Conductors 242 (conductors 242a and 242b) functioning as a source and a drain; It is preferable to use a conductive oxide as the material. In particular, when the generation of carriers is caused only by oxygen vacancies, It is a conductive oxide that generates carriers by substitutional impurity donors, regardless of the In other words, even if the oxygen vacancies in the conductor 242 are repaired by excess oxygen, the conductor Therefore, the conductive oxide can suppress the decrease in the carrier density in the oxygen It is believed that carriers are generated even when there are few defects, so transistors with high on-state characteristics can be produced. The conductor 242 may be tin, tungsten, titanium, or silicon. It is preferable that the material contains one or more of silicon and indium. Indium tin oxide, indium oxide with tungsten oxide, indium oxide with tungsten oxide Indium zinc oxide, Indium oxide with titanium oxide, Indium with titanium oxide Tin oxide, indium zinc oxide, and silicon doped indium tin oxide may be used. stomach.

[0120] Alternatively, zinc oxide doped with gallium or titanium oxide doped with niobium may be used.

[0121] The conductivity of the conductor 242 is greater than that of the oxide 230a and the oxide 230b. In addition, the carrier density of the conductor 242 is preferably high. It is preferable that the carrier density of the oxide 230b is higher than that of the oxide 230c. The oxide 230a and the oxide 230b function as a channel forming region, and the conductor 242 can function as a source or a drain.

[0122] As shown in FIG. 2B, the transistor 201 according to one embodiment of the present invention has a channel formation region The oxide 230b, which functions as a source or drain, is attached to both sides of the conductor 2 The height of the upper surface of the conductor 242 and the oxide 230 are sandwiched between the conductor 242 and the oxide 230. The heights of the upper surfaces of the oxides 230b are approximately equal. The shortest distance between the top surface of the hole formation region and the conductor 260 functioning as a gate is Since the distance between the conductor 260 and the transistor 260 is approximately equal to the shortest distance between the conductor 260 and the transistor 260, a transistor with a small parasitic capacitance can be provided. In addition, between the channel formation region of the oxide 230b and the conductor 260, Since no or only a small step is formed in the channel forming region of the oxide 230b, The insulator 250 on the conductor 242 can be provided without overcoming any steps. Therefore, the covering property of the insulator 250 is improved, and the withstand voltage of the insulator 250 is improved, which is preferable. I wish.

[0123] 2C, the oxide 230a and The height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap is The depth is preferably located at a position lower than the height of the bottom surface of the oxide 230b. , the oxide 230b and the conductor 260 are not overlapped in the area of ​​the bottom surface of the conductor 260. The difference between the height and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably is 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0124] As shown in FIG. 2C, a conductor 260 functioning as a gate is formed in the channel forming region The side surfaces of the oxide 230a and the oxide 230b and the top surface of the oxide 230b are covered with an insulator 25. 0, and the electric field of the conductor 260 is spread over the oxide 23 in the channel formation region. Therefore, the on-state of the transistor 201 is easily affected by the oxide 230a and the oxide 230b. This increases the on-state current and improves the frequency characteristics.

[0125] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, it is possible to provide a semiconductor device having a transistor with high frequency characteristics. Alternatively, the fluctuation of the electrical characteristics can be suppressed, and the electrical characteristics can be stabilized while improving reliability. It is possible to provide a semiconductor device having an improved off-state current. It is possible to provide a semiconductor device having the above structure.

[0126] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b on the oxide 230a. The oxide 230c is located on the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0127] The oxide 230 has a layered structure made of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the constituent elements The atomic ratio of element M in the oxide 230b is the atomic ratio of element M in the metal oxide in the constituent elements. It is preferable that the atomic ratio of the metal oxide 230a is larger than that of the element M. In the metal oxide used for the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In is larger than that of the element M in the metal oxide. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. The object can be used.

[0128] In addition, the oxide 230b preferably has crystallinity. -OS(c-axis aligned crystalline oxide sem It is preferable to use a crystalline material such as CAAC-OS. Oxides have few impurities and defects (such as oxygen vacancies), high crystallinity, and a dense structure. This suppresses the extraction of oxygen from the oxide 230b by the source or drain. This can suppress the extraction of oxygen from the oxide 230b even when a heat treatment is performed. Since the transistor 201 can be prevented from being damaged by high temperatures during the manufacturing process (so-called Thermal budget.

[0129] In addition, the energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the oxide is higher than the minimum energy of the conduction band of 0b. The electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. It is preferable that

[0130] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, The energy level of the conduction band minimum changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is In order to achieve this, the oxide At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c In this case, the defect level density of the mixed layer formed in the step (b) is preferably reduced.

[0131] Specifically, the oxide 230a is In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of 1:1:0.5 may be used. In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] gold The oxide 230c may be a metal oxide having a composition of In:Ga:Zn=1:3:4. [Atomic ratio], In:Ga:Zn=4:2:3 [Atomic ratio], Ga:Zn=2:1 [Atomic ratio] In addition, a metal oxide having an atomic ratio of Ga:Zn=2:5 may be used. A specific example of the compound 230c having a layered structure is In:Ga:Zn=4:2:3[ A stacked structure with In:Ga:Zn=4:1 atomic ratio and Ga:Zn=2:1 atomic ratio. 2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio] stacked structure, In:Ga:Z Examples include a layered structure with n=4:2:3 [atomic ratio] and gallium oxide.

[0132] At this time, the main path of the carriers is the oxide 230b. By configuring the oxide 30c as described above, the interface between the oxide 230a and the oxide 230b and the oxide This can reduce the defect state density at the interface between the nitride 230b and the oxide 230c. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 201 has high In addition, the oxide 230c is formed in a laminated structure. In this structure, the defect state density at the interface between the oxide 230b and the oxide 230c is In addition to the effect of lowering the temperature, the constituent elements of the oxide 230c diffuse to the insulator 250 side. More specifically, the oxide 230c has a laminated structure, and the laminated In order to position an oxide that does not contain In at the top of the structure, the In that can diffuse to the insulator 250 side is The insulator 250 functions as a gate insulator, so that the diffusion of In can be suppressed. If the oxide 230c is dispersed, the transistor characteristics will be deteriorated. By doing so, it is possible to provide a highly reliable semiconductor device. The configuration and effects of the transistor 201 can be understood with reference to the transistor 200. This can be done.

[0133] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0134] <Substrate> The substrate on which the transistor 200 and the transistor 201 are formed may be, for example, an insulating substrate. The substrate may be a solid substrate, a semiconductor substrate, or a conductive substrate. Glass substrate, quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia Examples of semiconductor substrates include silicon substrates, resin substrates, etc. , germanium-based semiconductor substrates, or silicon carbide, silicon germanium, Compound semiconductor substrates made of gallium arsenide, indium phosphide, zinc oxide, and gallium oxide Furthermore, the semiconductor substrate having an insulating region therein, for example, SOI (Silicon On Insulator) substrates. Examples of substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. There are also substrates with conductive materials on insulating substrates, and substrates with metal oxides. or a substrate on which a semiconductor is provided, a substrate on which a conductor or an insulator is provided on a semiconductor substrate, There are also substrates in which semiconductors or insulators are provided on a conductive substrate. The elements provided on the substrate may include a capacitance element, a resistance element, and the like. These include transistors, switching elements, light-emitting elements, and memory elements.

[0135] <Insulator> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0136] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. The material should be selected accordingly.

[0137] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum and hafnium, and oxides containing aluminum and hafnium oxide-nitride having silicon and hafnium; oxide-nitride having silicon and hafnium; Examples of suitable materials include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0138] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen, silicon oxide with voids, or resin, etc. be.

[0139] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, , for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon , phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulators containing tungsten, neodymium, hafnium, or tantalum are used in single or multilayer configurations. Specifically, the insulating material has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or metal oxides such as tantalum oxide, aluminum nitride, titanium aluminum nitride, Metal nitrides such as titanium oxide, silicon oxynitride, or silicon nitride can be used. .

[0140] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0141] <Conductor> Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from aluminum, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten nitride, nitrides containing titanium and aluminum, tantalum and aluminum Aluminum nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, etc. Tantalum nitride, titanium nitride, nitrides containing titanium nitride and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or oxides that are difficult to oxidize. It is a material that maintains its conductivity even if it absorbs impurity elements such as phosphorus. Highly conductive semiconductors, such as nickel-containing polycrystalline silicon, Silicide such as silicide may also be used.

[0142] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0143] In the case where an oxide is used for the channel formation region of a transistor, The functional conductor combines the above-mentioned material containing the metal element with a conductive material containing oxygen. In this case, it is preferable to use a laminate structure in which an oxygen-containing conductive material is used as a channel. It is preferable to provide the conductive material containing oxygen on the channel formation region side. Thus, oxygen released from the conductive material is easily supplied to the channel formation region.

[0144] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing silicon and nitrogen may also be used, such as titanium nitride and tantalum nitride. In addition, a conductive material containing nitrogen such as indium tin oxide or tungsten oxide may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide, titanium oxide, indium tin oxide, indium zinc oxide, Silicon-doped indium tin oxide may also be used. The use of such a material may be used to form a channel. In some cases, the metal oxides surrounding the outer insulator can trap hydrogen. In some cases, it may be possible to capture hydrogen that is mixed in from sources such as

[0145] <Metal oxide> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0146] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or Or multiple types may be included.

[0147] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. The element M can be aluminum, gallium, yttrium, or The element M can be tin, etc. Other elements that can be used for M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, combinations of the aforementioned elements may be used.

[0148] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0149] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, CAAC-OS, polycrystalline amorphous oxide semiconductor, nc-OS, pseudo-amorphous oxide semiconductor (a-like OS) phos-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0150] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0151] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. It is difficult to confirm the presence of the crystal structure due to the distortion of the lattice arrangement. This is because the CAAC-OS is aligned in the ab-plane direction. In the case of the ferroelectric material, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0152] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M tend to have a layered structure. When the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn ) layer. Also, when the indium in the In layer is replaced with the element M, (In, M) layer.

[0153] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is designed to prevent impurities and defects (oxygen vacancies (VO)). CAAC- is a metal oxide with low acancy. Metal oxides with OS have stable physical properties. Therefore, Metal oxides are heat resistant and highly reliable.

[0154] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0155] In addition, indium oxide, which is a type of metal oxide containing indium, gallium, and zinc, In the case of IGZO, the nanocrystals mentioned above make it stable. In particular, IGZO tends to have difficulty growing crystals in air. , small crystals (e.g., For example, the nanocrystals mentioned above may be structurally more stable.

[0156] The a-like OS is a metal oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has voids or low density regions. The ke-OS has a lower crystallinity than the nc-OS and CAAC-OS.

[0157] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention can be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more kinds.

[0158] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0159] In addition, when an alkali metal or alkaline earth metal is contained in a metal oxide, a defect level is formed. Therefore, alkali metals or alkaline earth metals may form a carrier. A transistor that uses a metal oxide containing metals in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide Specifically, it is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. Potassium metal or alkaline earth metal concentration (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by 1 ×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Below do.

[0160] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is recommended to use metal oxides that contain hydrogen. Such a transistor is likely to have normally-on characteristics.

[0161] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5×1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, it is possible to impart stable electrical characteristics.

[0162] It is preferable to use a thin film with high crystallinity as the metal oxide used as the semiconductor of a transistor. By using the thin film, the stability or reliability of the transistor can be improved. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, thin films of single crystal metal oxides or thin films of polycrystalline metal oxides are Formation on a substrate requires high temperature or laser heating steps. This increases the cost of the process and also reduces the throughput.

[0163] <Method for manufacturing semiconductor device> Next, a semiconductor device having a transistor 201 according to the present invention shown in FIG. The manufacturing method will be described with reference to Figs. 4 to 12. In Figs. 4 to 12, (B) of each figure shows the part indicated by the dashed line A1-A2 in (A). 2 is a cross-sectional view taken along the channel length direction of the transistor 201. In addition, (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). 1 and 2 are cross-sectional views of the transistor 201 in the channel width direction. In the figure, some elements have been omitted for clarity.

[0164] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The deposition of 14 was performed by sputtering, chemical vapor deposition (CVD), Deposition method, Molecular Beam Epitaxy (MBE) eam Epitaxy method, Pulsed Laser Deposition (PLD) Deposition) method or ALD (Atomic Layer Deposit) This can be done using the (ion) method or the like.

[0165] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are further classified into the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method.

[0166] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc., contained in a semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage occurs. Since the thermal CVD method does not require any heat treatment, the yield of the semiconductor device can be increased. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0167] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time. This allows for extremely thin film deposition, film deposition on structures with high aspect ratios, and pinhole It is possible to form films with few defects such as holes, excellent coating properties, and low temperature film formation. In addition, the ALD method uses plasma to form films, called PEA. This includes the LD (Plasma Enhanced ALD) method. This may be preferable because it allows film formation at a lower temperature. Some casters contain impurities such as carbon. For this reason, the film formed by the ALD method may contain more impurities such as carbon than films formed by other deposition methods. The quantity of impurities was determined by X-ray photoelectron spectroscopy (XPS). This can be done using NMR spectroscopy.

[0168] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0169] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0170] In this embodiment, the insulator 214 is formed of silicon nitride by CVD. In this way, an insulator that is difficult for copper to penetrate, such as silicon nitride, is used as the insulator 214. Therefore, a metal that easily diffuses, such as copper, is used for the conductor layer (not shown) below the insulator 214. Even if the metal is present, it is possible to suppress the metal from diffusing into the upper layer through the insulator 214. In addition, by using an insulator such as silicon nitride that is difficult for impurities such as water or hydrogen to penetrate, As a result, the diffusion of impurities such as water or hydrogen from the layer below the insulator 214 can be suppressed. can.

[0171] Alternatively, the insulator 214 may have a two-layer structure. For example, aluminum oxide on silicon nitride. A film of aluminum may be formed.

[0172] Next, the insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is carried out by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0173] Next, an opening is formed in the insulator 216 so as to reach the insulator 214. The opening may be, for example, a groove or This also includes slits. The area where an opening is formed may also be referred to as an opening. The openings may be formed by wet etching, but it is more preferable to use dry etching. Insulator 214 is preferably formed by etching insulator 216. It is preferable to select an insulator that functions as an etching stopper film when etching. For example, When a silicon oxide film is used for the insulator 216 forming the groove, the insulator 214 is made of silicon nitride. A film of aluminum oxide, a film of hafnium oxide, or the like may be used.

[0174] After the opening is formed, a conductive film that will become the conductor 205 is formed. The conductive film has properties that suppress the permeation of oxygen. For example, tantalum nitride, tungsten nitride, etc. Stainless steel, titanium nitride, etc. can be used. Alternatively, tantalum, tungsten, titanium It can be a laminated film of molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film that becomes the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out using a PLD method, an ALD method, or the like.

[0175] In this embodiment, the conductive film that becomes the conductor 205 has a multi-layer structure. A tantalum nitride film is formed by a deposition method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductive film that becomes the conductor 205, Even if a metal that easily diffuses, such as copper, is used as the conductive film on the conductive film that becomes the conductor 205, The metal can be prevented from diffusing out of the conductor 205 .

[0176] Next, a conductive film is formed on the conductive film that will become the conductor 205. The conductive film is formed by plating. The method is performed using the deposition method, sputtering method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, the conductive film on the conductive film that becomes the conductor 205 is A film of a low resistance conductive material such as copper is deposited.

[0177] Next, CMP (Chemical Mechanical Polishing) By carrying out the above, the upper layer of the conductive film which becomes the conductor 205 and the A portion of the lower layer is removed to expose the insulator 216. As a result, the conductor 205 is only present in the opening. As a result, a conductive film that becomes a flat conductive body 205 is formed. (See FIG. 4.) In addition, in some cases, the insulator 216 may be removed by the CMP process. There is.

[0178] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0179] A conductive film that will become the conductor 205 is formed on the insulator 214. The deposition of the film is performed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The conductive film that becomes the conductor 205 can be a multi-layer film. In this embodiment mode, a tungsten film is formed as the conductive film to be the conductor 205.

[0180] Next, the conductive film that becomes the conductor 205 is processed by lithography. Form.

[0181] In the lithography method, first, the resist is exposed through a mask. The resist mask is formed by removing or leaving the resist-removed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. are used to A resist mask can be formed by exposing the photoresist to light. A liquid immersion technique may be used in which the substrate is filled with liquid (e.g., water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not necessary. The resist mask can be removed by ashing or the like. Which dry etching process is performed, which wet etching process is performed, and which dry etching process is performed After the treatment, wet etching is performed, or after the treatment, dry etching is performed. It is possible to carry out the filtering process.

[0182] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating layer that is a hard mask material is formed on the conductive film that is to be the conductor 205. An insulating film and a conductive film are formed, a resist mask is formed on the insulating film and a hard mask material is etched. By this etching, a hard mask of a desired shape can be formed. The etching of the conductive film may be performed after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be lost during etching. After etching the conductive film that becomes the conductor 205, the hard mask is removed by etching. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, If it is possible to do so, it is not necessary to remove the hard mask.

[0183] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. : Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power source may be applied to one of the parallel plate type electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching apparatus or the like can be used.

[0184] Next, an insulating film that becomes the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film that becomes the body 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. In this embodiment, the insulating layer 216 is formed by depositing an insulating film on the insulating layer 216. The film is made of silicon oxide by the CVD method.

[0185] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is In this embodiment, the thickness of the conductor 205 is set to 150 nm, and the insulating The thickness of the insulating film that becomes the body 216 is set to 350 nm.

[0186] Next, the insulating film that will become the insulator 216 is subjected to CMP processing. A part of the film is removed to expose the surface of the conductor 205. This results in a conductive The above is a description of the different formations of the conductor 205 and the insulator 216. This is the method.

[0187] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulating layer, an insulator containing oxide of one or both of aluminum and hafnium is formed. In addition, the insulator containing oxide of either or both of aluminum and hafnium is As examples, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium It is preferable to use aluminum and hafnium aluminate. Insulators containing oxides of one or both of these metals provide excellent barrier properties against oxygen, hydrogen, and water. The insulator 222 has a barrier property against hydrogen and water, so that the transistor Hydrogen and water contained in the structure provided around the rotor 201 are absorbed through the insulator 222. The oxide 230a, the oxide 230b, and the like are prevented from diffusing into the inside of the transistor 201. In addition, the generation of oxygen vacancies in the oxide 230c can be suppressed.

[0188] The insulator 222 is formed by sputtering, CVD, MBE, PLD, or A. This can be done using the LD method or the like.

[0189] Next, the insulator 224 is deposited on the insulator 222. The deposition of the insulator 224 is carried out by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. .

[0190] Subsequently, a heat treatment is preferably performed. The reaction temperature is preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower. The heat treatment may be performed in a nitrogen or inert gas atmosphere, or in an atmosphere of oxidizing gas at a concentration of 10ppm. m or more, 1% or more, or 10% or more. Heat treatment is also performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by To compensate for the lost oxygen, the gas contains 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed in an atmosphere containing the above-mentioned.

[0191] In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour, and then the The heat treatment is then performed in an oxygen atmosphere at a temperature of 400°C for one hour. Impurities such as water and hydrogen contained in the body 224 can be removed.

[0192] The heat treatment may be performed after the formation of the insulator 222. Heat treatment conditions can be used.

[0193] Here, in order to form an excess oxygen region in the insulator 224, a plasma containing oxygen is used under reduced pressure. The oxygen-containing plasma treatment may be, for example, a high-density plasma treatment using microwaves. It is preferable to use a device having a power source that generates plasma. Alternatively, RF ( The plasma may have a power source that applies a high-density plasma. By applying RF to the substrate, high density oxygen radicals can be generated. In this way, oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, In order to compensate for the desorbed oxygen, a plasma treatment including oxygen may be performed. By appropriately selecting the processing conditions, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, the heat treatment is not necessary.

[0194] Here, aluminum oxide is formed on the insulator 224 by, for example, a sputtering method. A film may be formed and CMP may be performed until the aluminum oxide reaches the insulator 224. By performing CMP, the surface of the insulator 224 is planarized and smoothed. By placing the aluminum oxide on the insulator 224 and performing CMP, This makes it easier to detect the end point of the MP. Also, a part of the insulator 224 is polished by CMP. However, the thickness of the insulator 224 may become thin. By planarizing and smoothing the surface of the insulator 224, the oxide film to be formed later can be easily formed. In some cases, it may be possible to prevent deterioration of the coverage and to prevent a decrease in the yield of the semiconductor device. On the insulator 224, an aluminum oxide film is formed by sputtering. In this case, oxygen can be added to the insulator 224, which is preferable.

[0195] Next, an oxide film 230A1 and an oxide film 230B1 are formed in this order on the insulator 224 (FIG. 4). It is preferable that the oxide film is formed continuously without exposing it to the air environment. By forming the oxide film 230A1 and the oxide film 230B1 without exposing them to the atmosphere, the oxide film 230A1 and the oxide film 230B1 are exposed to the atmosphere. The oxide film 230A1 and the oxide film 230A2 can be prevented from being impurities or moisture from adhering to each other. The vicinity of the interface with 230B1 can be kept clean.

[0196] The oxide film 230A1 and the oxide film 230B1 are formed by a sputtering method, a CVD method, or a M method. This can be performed using a BE method, a PLD method, an ALD method, or the like.

[0197] For example, the oxide film 230A1 and the oxide film 230B1 are formed by a sputtering method. In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen in the sputtering gas, the excess oxygen in the oxide film is reduced. In addition, when the oxide film is formed by sputtering, In this case, the above-mentioned In-M-Zn oxide target can be used.

[0198] In particular, when the oxide film 230A1 is formed, a part of the oxygen contained in the sputtering gas becomes insulating. Therefore, the sputtering gas of the oxide film 230A1 may be supplied to the body 224. The percentage of oxygen contained in the Just do that.

[0199] In addition, when the oxide film 230B1 is formed by a sputtering method, the sputtering gas may contain The ratio of oxygen contained in the film is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. When the oxygen-deficient oxide semiconductor is used as a channel forming The transistors used in the region have relatively high field effect mobility. The oxygen content of the ring gas is 70% or more, preferably 80% or more, and more preferably In this case, part of the oxygen contained in the sputtering gas may be This may be preferable because it may be supplied to the oxide film 230A1.

[0200] In the present embodiment, the oxide film 230A1 is formed by sputtering In:Ga Zn=1:1:0.5 (2:2:1), or 1:3:4 [Atomic ratio] target is used for film formation. By the ring method, the atomic ratio of In:Ga:Zn=4:2:4.1 or 1:1: The oxide film 230A1 and the oxide film By appropriately selecting the film formation conditions and atomic ratio, the oxide 230a and It is advisable to form the oxide 230b in accordance with the desired characteristics.

[0201] Next, a heat treatment may be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. By the heat treatment, water, hydrogen, etc. in the oxide film 230A1 and the oxide film 230B1 are removed. In this embodiment, the impurities are removed at a temperature of 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. cormorant.

[0202] Next, a film that will become the hard mask 244 is formed. The film that will become the hard mask 244 is formed as follows. , sputtering, CVD, MBE, PLD, ALD, etc. The film that will become the hard mask 244 is the oxide film 23 in the subsequent process. When processing the 0A1 and the oxide film 230B1, the hard mask 244 is etched. For example, silicon oxide, silicon oxynitride, silicon nitride, and silicon nitride oxide are preferable. Silicon, aluminum oxide, hafnium oxide, tungsten, molybdenum, aluminum Examples of the material that can be used include titanium, titanium nitride, tantalum, and tantalum nitride.

[0203] Next, the film that will become the hard mask 244 is processed by lithography. Next, the oxide film 23 is etched using the hard mask 244 as an etching mask. The oxide film 230A1 and the oxide film 230B1 are processed to form the oxide 230A2 and the oxide 230B2. In this process, the region of the insulator 224 that does not overlap with the oxide film 230A2 is formed. The thickness of the film may become thinner (see FIG. 5).

[0204] Next, a conductive film 242A is formed so as to cover the insulator 224 and the hard mask 244. The conductive film 242A is formed by sputtering, CVD, MBE, or PL. The conductive film 242A can be formed by a vertical deposition method, an ALD method, or the like. It is preferable that the deposition rate in the horizontal direction is smaller than the deposition rate in the vertical direction. When the horizontal speed is 1, the film formation speed in the horizontal direction is preferably 0.5 or less. For example, bias sputtering is a method in which a film is formed while applying a potential to a substrate. A shield plate (collimator) with holes is inserted between the holes to control the deposition direction. Sputtering method, or long-throw sputtering, where the distance between the substrate and the target is long A method such as the sizing method can be used.

[0205] The conductive film 242A may be made of any of tin, tungsten, titanium, and silicon. Preferably, the material contains one or more of indium and indium tin oxide. , indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide with titanium oxide, indium tin oxide with titanium oxide, indium Indium zinc oxide, indium tin oxide doped with silicon may also be used. Alternatively, zinc oxide doped with lithium or titanium oxide doped with niobium may be used. Indium tin oxide is used.

[0206] Next, a portion of the conductive film 242A is isotropically etched (isotropic etching). In this case, the upper surface of the conductor 242B and the upper surface of the oxide 232B2 are at approximately the same height. The conductive film 242A on the side of the hard mask 244 is removed. A conductor 242B is formed on the edge 224, and a conductor 242C is formed on the hard mask 244. This etching is performed by dry etching or wet etching. The Ching method can be used.

[0207] Next, the hard mask 244 is etched from the side. Compared to the etching rate of the mask 244, the conductor 242B is hardly etched. It is preferable that the etching rate of the conductor 242B is low. This shows the mask 244 being etched. Next, the hard mask 244 is completely etched. This causes the conductor 242C on the hard mask to be lifted off. The height of the upper surface of the conductor 242B is approximately equal to the height of the upper surface of the conductor 242B (see FIG. 9).

[0208] Next, the oxide 230A2, the oxide 230B2, and the conductive The conductive body 242B is processed to form the oxide 230a, the oxide 230c, the conductive body 242a, and the conductive body 242B. Here, the oxide 230a, the oxide 230b, the conductor 242a, and The conductor 242b is formed so that at least a portion of the conductor 205 overlaps with the conductor 205. In this process, the thickness of the insulator 224 in the region not overlapping the oxide 230a becomes thin. In addition, the oxide 230a of the insulator 224, the conductor 242a, and the conductor 242 The thickness of the film in the area not overlapping with b may be thin (see FIG. 10).

[0209] Next, a first heat treatment may be performed. The first heat treatment is performed in an atmosphere containing oxygen. Alternatively, the first heat treatment is preferably performed under reduced pressure and without exposure to the atmosphere. Subsequently, an oxide film that becomes the oxide 230c may be formed. The moisture and hydrogen adsorbed on the surface of the oxide 230b are removed, and the oxide 230b is then The moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment in step 1 is preferably 100° C. or higher and 400° C. or lower, more preferably 150° C. or lower. In this embodiment, the temperature of the first heat treatment is 200° C. Work under reduced pressure.

[0210] Next, an oxide film that becomes the oxide 230c is formed (see FIG. 11). Oxide film is formed by sputtering, CVD, MBE, PLD, or ALD. The oxide film that becomes the oxide 230c can be formed by using a Ga atom with respect to In. It is preferable that the atomic ratio of Ga to In in the oxide 230b is larger than that of Ga to In in the oxide 230b. In the embodiment, the oxide film that becomes the oxide 230c is formed by sputtering In. The film is formed using a target with an atomic ratio of Ga:Zn=1:3:4.

[0211] The oxide film that becomes the oxide 230c may be a laminated film. For example, a sputtering method may be used. The film was formed using a target with an atomic ratio of In:Ga:Zn=4:2:4.1. Then, a film was formed using a target of In:Ga:Zn=1:3:4 [atomic ratio]. Good too.

[0212] In particular, when the oxide film that becomes the oxide 230c is formed, the amount of oxygen contained in the sputtering gas is Some of the oxide may be supplied to the oxide 230a and the oxide 230b. The ratio of oxygen contained in the sputtering gas for the oxide film to be the product 230c is preferably 70% or more. It is preferable that the ratio is 80% or more, and more preferably 100%.

[0213] Next, a second heat treatment may be performed. The second heat treatment is performed under reduced pressure and without exposure to the atmosphere. Alternatively, the insulating film that will become the insulator 250 may be formed continuously without performing such a process. By carrying out this process, the moisture and water adsorbed on the surface of the oxide film that becomes the oxide 230c are removed. The oxide film 230a, the oxide film 230b, and the oxide film 230c are formed by removing the oxide. The second heat treatment temperature is 10 The temperature of the second heat treatment is preferably 0° C. or more and 400° C. or less. In this embodiment, the temperature of the second heat treatment is set to 200° C. Let us assume that.

[0214] Next, an insulating film that will become the insulator 250 is formed (see FIG. 11). The film is formed by sputtering, CVD, MBE, PLD, or ALD. The insulating film that becomes the insulator 250 can be formed by a CVD method. It is preferable to form a silicon film. The temperature is preferably 250° C. or higher and lower than 450° C., and particularly preferably around 350° C. By depositing the insulating film at 350℃, an insulating film with few impurities can be formed. can be done.

[0215] Next, a conductive film that will become the conductor 260a and the conductor 260b is formed. The conductive film that becomes the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method or an ALD method. For example, a CVD method can be used. In this embodiment, the conductive film that becomes the conductor 260a is formed by the ALD method. Then, a conductive film that becomes the conductor 260b is formed by the CVD method (see FIG. 11).

[0216] Next, an oxide film that will become oxide 230c and an insulating film that will become insulator 250 are formed by a lithography method. The insulating film, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are processed and oxidized. The object 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) are formed. Here, the conductor 260 is formed so as to overlap at least a portion of the conductor 205. (See Figure 11.)

[0217] Next, a third heat treatment may be performed. The third heat treatment is performed in a nitrogen atmosphere or an oxygen atmosphere. The third heat treatment can be carried out in an atmosphere containing nitrogen and oxygen. When the reaction is carried out in an atmosphere containing nitrogen and oxygen, The ratio of oxygen is preferably 5% or more and 20% or less of the total of nitrogen and oxygen. The temperature of the heat treatment in step 3 is preferably 300° C. or higher and 450° C. or lower, more preferably 30 The temperature is 0° C. or higher and 400° C. or lower. Typically, a temperature of 350° C. or thereabouts is suitable. The heat treatment time is 100 hours or less, preferably 1 hour or more and 48 hours or less. Typically, a treatment time of 24 hours or thereabouts is suitable. By this, the moisture concentration and the hydrogen concentration in the oxide 230, the insulator 250 and the insulator 280 are This can reduce the carrier density in the channel formation region of the oxide 230. In the embodiment, the heat treatment is performed in a nitrogen atmosphere at a temperature of 350° C. for 24 hours. Preferably, the third heat treatment is performed under conditions that do not oxidize the conductor 260 .

[0218] Next, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242 An insulator 272 is deposited covering the layer 272a and the conductor 260 (see FIG. 11).

[0219] The insulator 272 is formed by sputtering, CVD, MBE, PLD or AL. The insulator 272 has a function of suppressing the permeation of oxygen. For example, it is preferable to use an insulating film formed by sputtering or ALD. Aluminum oxide, silicon nitride, silicon oxide, or gallium oxide may be deposited. The insulator 272 may have a two-layer structure. For example, an oxide film is formed by sputtering. Alternatively, a layer of aluminum may be deposited, and then a layer of aluminum oxide may be deposited by the ALD method. By using such a structure, pinholes can be formed on the aluminum oxide film formed by sputtering. Even if defects such as holes or voids occur, the film is formed by the ALD method, which has excellent coverage. The aluminum oxide is preferable because it can fill the defects.

[0220] Next, an insulating film that will become the insulator 280 is formed on the insulator 272. The insulating film is formed by sputtering, CVD, MBE, PLD, or ALD. Next, the insulating film that will become the insulator 280 is subjected to CMP processing, and the upper surface forms a flat insulator 280 (see FIG. 12).

[0221] Next, a fourth heat treatment may be performed. The fourth heat treatment is performed under reduced pressure without exposure to the atmosphere. It is preferable to form an insulating film that will become the insulator 281 on the insulator 280 without forming a layer on the insulator 280. By carrying out such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 are removed. The insulating film that becomes the insulator 281 is preferably formed by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film that becomes the insulator 281 is, for example, aluminum oxide by sputtering. It is preferable to form a film of aluminum. The insulator 281 may have a two-layer structure. For example, Then, an aluminum oxide film is formed by sputtering, and then a In this way, a silicon nitride film may be formed. Impurities such as water or hydrogen diffuse from the outside into the transistor 201 through the insulator 281. This can prevent the occurrence of such a problem (see Figure 12).

[0222] Next, a fifth heat treatment may be performed. In this embodiment, the fifth heat treatment is performed in a nitrogen atmosphere at 400° C. The heat treatment is performed at a temperature of 1 hour. The oxygen can be implanted into the insulator 280. The oxygen can also be implanted through the oxide 230c. 230a and 230b.

[0223] Next, the conductor 242a and the conductor 242b are connected to the insulator 272, the insulator 280, and the insulator 281. An opening is formed so as to reach the conductive body 242b (see FIG. 2). The opening is formed by lithography. This can be done using the method.

[0224] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator The conductive film is formed by sputtering, CVD, M This can be done by using a BE method, a PLD method, an ALD method, or the like. As the insulating film, it is preferable to use an insulating film having a function of suppressing oxygen permeation. For example, it is preferable to form a film of aluminum oxide or silicon nitride by the ALD method. The anisotropic etching may be performed by, for example, a dry etching method. By configuring the wall portion in this way, the permeation of oxygen from the outside is suppressed, and the conductive layer to be formed next is The conductor 240a and the conductor 240b can be prevented from being oxidized. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240b. Cut.

[0225] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water and hydrogen. It is preferable to use a laminated structure containing a conductor such as tantalum nitride or titanium nitride. The conductor 24 may be a laminate of tungsten, molybdenum, copper, etc. The conductive film that becomes 0 is formed by sputtering, CVD, MBE, PLD or AL. This can be done using Method D or the like.

[0226] Next, a CMP process is performed to remove the conductive film that will become the conductor 240a and the conductor 240b. A portion of the conductive film is removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By this, it is possible to form the conductors 240a and 240b having flat upper surfaces ( (See FIG. 2.) Note that the CMP process may remove a part of the insulator 281. .

[0227] Next, a conductive film that will become the conductor 246 is formed. This can be done using the sputtering method, CVD method, MBE method, PLD method, or ALD method. can.

[0228] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 240a. The conductor 246a contacts the upper surface of the conductor 240b, and the conductor 246b contacts the upper surface of the conductor 240b. (See Figure 2.)

[0229] Through the above steps, a semiconductor device including the transistor 201 shown in FIG. 2 can be manufactured. do.

[0230] <Modifications of the semiconductor device> In the following, referring to FIG. 3, the present invention will be described, which is different from the above-mentioned <Configuration Example 1 of the Semiconductor Device>. An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described.

[0231] FIG. 3A is a top view of a semiconductor device having a transistor 200. 3B is a cross-sectional view of the semiconductor device shown in FIG. 3A along the line A1-A2. 1 is a cross-sectional view of a portion indicated by a dashed line in FIG. 1, and is a cross-sectional view of a transistor 200 in a channel length direction. FIG. 3C is a cross-sectional view of the area indicated by the dashed line A3-A4 in FIG. 3A. 3A is a cross-sectional view of the transistor 200 in the channel width direction. Some elements have been omitted for clarity.

[0232] In the semiconductor device shown in FIG. 3, the semiconductor device shown in <Configuration Example 1 of the semiconductor device> The structures having the same functions as the structures constituting the structure shown in FIG. 1 are denoted by the same reference numerals.

[0233] The configuration of the transistor 200 will be described below with reference to FIG. In the item, the constituent material of the transistor 200 is described in <Configuration Example 1 of the Semiconductor Device>. The materials detailed above can be used.

[0234] [Transistor 200] As shown in FIG. 3, the transistor 200 includes an insulator 216 on an insulator 214 and an insulator A conductor 205 disposed so as to be embedded in the insulator 216, on the insulator 216, and on the conductor 2 05, an insulator 222 on the insulator 222, and an oxide layer 224 on the insulator 224. 30, conductor 242a and conductor 242b on oxide 230, conductor 242a, conductor Conductor 242b, insulator 250 on oxide 230, and conductor 260 on insulator 250. (conductor 260a and conductor 260b). The bottom surface of the conductor 242a has an area in contact with the oxide 230, and the bottom surface of the conductor 242b has an area in contact with the oxide 230. The side surface and the bottom surface of the conductor 242b have an area in contact with the oxide 230. The height of the top surface of the body 242a, the height of the top surface of the conductor 242b, and the height of the top surface of the oxide 230 The sizes are roughly equal.

[0235] The semiconductor device shown in FIG. 3 is the semiconductor device shown in <Configuration Example 1 of the Semiconductor Device> (see FIG. 1). The shape of the oxide 230 is different from that of the oxide 230. In the process of forming the oxide 230, the oxide film is not completely removed and is half-etched. By using this method, it is possible to form the oxide 230 having such a shape. The bottom surface of the conductor 242 functioning as a drain or a gate is in contact with the oxide 230. This is preferable because it may be possible to suppress the short channel effect of the transistor 200. For other configurations and effects, the semiconductor device shown in FIG. 1 can be referred to.

[0236] The configuration, structure, method, etc. shown in the present embodiment may be used in other embodiments and examples. The configurations, structures, methods, etc. shown in the above may be used in appropriate combination.

[0237] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0238] [Storage device] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG. The semiconductor device includes a transistor 200, a transistor 300, and a capacitance element 100. The transistor 200 is provided above the transistor 300, and the capacitance element 100 is provided above the transistor 300. The transistor 300 and the transistor 200 are provided above each other. The transistor 200 may be the transistor 200 described in the previous embodiment, or the transistor 2 01 can be used.

[0239] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0240] In the semiconductor device shown in FIG. 14, a wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0241] In addition, the memory device shown in FIG. 14 has a memory cell array arranged in a matrix. It can be configured.

[0242] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 that functions as a gate. 315, which acts as a gate insulator, and a semiconductor region consisting of a portion of the substrate 311. 313, and low resistance region 314a and low resistance region 314b functioning as a source or drain. The transistor 300 may be a p-channel or n-channel type. Any deviation is acceptable.

[0243] Here, the transistor 300 shown in FIG. 14 has a semiconductor region 313 ( A part of the substrate 311 has a convex shape. The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may be used. Since it uses a protruding part, it is also called a FIN type transistor. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. Here, a case where a protrusion is formed by processing a part of a semiconductor substrate is shown, but a SOI substrate is also processed. A semiconductor film having a convex shape may be formed by the above-mentioned method.

[0244] Note that the transistor 300 shown in FIG. 14 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0245] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. a conductor 110 serving as the first electrode, a conductor 120 serving as the second electrode, and and an insulator 130 that functions as a dielectric.

[0246] Also, for example, the conductor 112 provided on the conductor 246 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used for the capacitor 100, the transistor 200, and has a function as a plug or wiring that is electrically connected to the transistor 300 .

[0247] In FIG. 14, the conductor 112 and the conductor 110 are shown to have a single-layer structure. However, the present invention is not limited to this, and may be a laminated structure of two or more layers. For example, Conductors that have barrier properties between weak conductors and those with high electrical conductivity have good adhesion to conductors with high electrical conductivity. may form a highly conductive material.

[0248] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrogen Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium The conductive layer may be formed as a laminate or a single layer.

[0249] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, or a material with high dielectric strength. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, so that it can ensure sufficient capacitance. By using an insulator having a large dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0250] In addition, oxide is an insulator for high dielectric constant (high-k) materials (materials with a high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium an oxide having silicon and hafnium, an oxide nitride having silicon and hafnium, or an oxide nitride having silicon and hafnium Nitrides containing fluorine.

[0251] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon oxide, silicon nitride, silicon nitride, silicon oxide doped with fluorine, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, vacancy-containing silicon oxide Examples include concrete or resin.

[0252] <Wiring layer> Between each structure, a wiring layer is provided in which an interlayer film, wiring, plugs, etc. are provided. Also, a plurality of wiring layers may be provided according to the design. Conductors that function as wiring or wiring may be grouped together and given the same symbol. In addition, in the present specification and the like, the wiring and the plug that are electrically connected to the wiring may be integrated. That is, when a part of the conductor functions as a wiring, or when the conductor In some cases, some parts also function as plugs.

[0253] For example, an insulator 320, an insulator 322, and an insulator 323 are provided on the transistor 300 as an interlayer film. The edge member 324 and the insulator 326 are laminated in this order. The insulators 322, 324, and 326 are connected to the capacitive element 100 or the transistor. A conductor 328 and a conductor 330 are embedded in the conductive layer 200. The conductor 328 and the conductor 330 function as plugs or wiring.

[0254] In addition, the insulator that functions as an interlayer film acts as a flattening film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be chemically mechanically polished ( The surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0255] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In the insulating layer 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0256] Similarly, the insulators 210, 212, 214, and 216 are each provided with a conductive The conductive body 218 and the conductive body (conductive body 205) constituting the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 120 and the insulator 130 function as a plug or wiring for connecting the conductor 120 and the insulator 130. On top of 130 is an insulator 150 .

[0257] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0258] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0259] For example, the insulators 150, 212, 352, and 354 have relatively low resistance. It is preferable to have an insulator with a low dielectric constant. For example, the insulator may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon Silicon oxide doped with oxygen, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies The insulator preferably comprises silicon or resin, or silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. It is preferable that the insulating layer has a laminated structure of silicon oxide and a resin. Silicon oxynitride is thermally stable, so by combining it with resin, The laminated structure can have a low dielectric constant. Examples of the resin include polyester and Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Examples include plastic or acrylic.

[0260] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulator 210, the insulator 350, etc., do not contain impurities such as hydrogen and Insulators having a function of suppressing the permeation of oxygen may be used.

[0261] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon oxide nitride, silicon nitride, etc. can be used. .

[0262] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as arsenic, A silicide such as nickel silicide may also be used.

[0263] For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1 12, etc., may be a metal material, an alloy material, a metal nitride material, or the like formed from the above-mentioned materials. Conductive materials such as metal oxide materials can be used in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that is also electrically conductive. It is preferable to use tungsten. Alternatively, low resistance conductive materials such as aluminum and copper can be used. It is preferable to form the wiring from a low-resistance conductive material. can be done.

[0264] <Wiring or plug of layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In that case, the insulator having the excess oxygen region and an insulator having a barrier property is provided between the conductor and the insulator having the excess oxygen region. It is preferable to provide such a function.

[0265] For example, in FIG. 14, an insulating layer is formed between the insulator 224 having excess oxygen and the conductor 245. The insulator 276 is preferably provided in contact with the insulator 222 and the insulator 272. By providing the insulator 224 and the transistor 200, the insulator 224 and the transistor 200 have a barrier property. Further, the insulator 276 may be formed into a sealing structure by the insulator 280. It is preferable that the insulator 276 also contacts a part of the insulator 280. This makes it possible to suppress the diffusion of oxygen and impurities.

[0266] In other words, by providing the insulator 276, the excess oxygen contained in the insulator 224 is absorbed by the conductor 24 In addition, the insulator 276 can prevent impurities from being absorbed by the insulator 276. The hydrogen, which is a substance, is prevented from diffusing into the transistor 200 via the conductor 245. It is possible.

[0267] The insulator 276 is made of a material that suppresses the diffusion of impurities such as water or hydrogen, and oxygen. It is advisable to use an insulating material that has the function of providing insulation. For example, aluminum oxide or hafnium oxide is In addition, for example, magnesium oxide, gallium oxide, etc. , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Metal oxides such as tantalum oxide or tantalum oxide, silicon oxide nitride or silicon nitride, etc. can be used.

[0268] The above is a description of the configuration example. By using this configuration, In a semiconductor device using a transistor, the fluctuation of electrical characteristics is suppressed and the reliability is improved. Alternatively, a transistor including an oxide semiconductor having a large on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. do.

[0269] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0270] (Embodiment 3) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 15 and 16. Transistors used as conductors (hereinafter sometimes referred to as OS transistors) and capacitive elements This section describes a storage device to which the OS is applied (hereinafter, sometimes referred to as an OS memory device). The OS memory device includes at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. The off-state current of the OS transistor is extremely small, so The memory device has excellent retention characteristics and can function as a non-volatile memory.

[0271] <Storage device configuration example> FIG. 15A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 141. 1, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, It includes a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0272] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, and write The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal. RDATA is output to the outside of the memory device 1400. For example, the memory device may have a row decoder, a word line driver circuit, etc., and may select a row to be accessed. do.

[0273] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 11, and the high power supply voltage (VIL) for the memory cell array 1470. The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The decoder and column decoder are input to the data decoder, and WDATA is input to the write circuit.

[0274] The control logic circuit 1460 processes external input signals (CE, WE, RE). It processes the row decoder and column decoder control signals and generates the row decoder and column decoder control signals. CE is the chip enable signal. where WE is a write enable signal and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these. Instead, other control signals may be input as necessary.

[0275] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the recell MC, the number of memory cells MC in one row, etc.

[0276] In FIG. 15A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. However, the present embodiment is not limited to this. For example, As shown in FIG. 15B, a memory cell array 1470 is overlapped on a part of the peripheral circuit 1411. For example, the memory cell array 1470 may be provided so as to overlap the memory cell array 1470. A sense amplifier may be provided.

[0277] FIG. 16 illustrates an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0278] [DOSRAM] 16A to 16C show examples of circuit configurations of memory cells in a DRAM. A DRAM using a one-transistor, one-capacitor type memory cell is called a DOSRAM. (Dynamic Oxide Semiconductor Random Acce. The memory cell 1471 shown in FIG. The transistor M1 has a gate (front end) and a capacitance element CA. The gate is a gate electrode (sometimes called a front gate) and a back gate.

[0279] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0280] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0281] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. The back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 1473 shown in FIG. As described above, a transistor with a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with M1.

[0282] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This means that the leakage current of the transistor M1 can be made very low. The frequency of memory cell refresh can be reduced by using resistor M1 for long-term retention. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very low, the memory cells 1471, 1472, The memory cell 1473 can hold multi-level data or analog data.

[0283] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0284] [NOSRAM] 16D to 16H show a circuit diagram of a gain cell type memory cell having two transistors and one capacitor. FIG. 16D shows an example of a circuit configuration. The memory cell 1474 shown in FIG. 16D includes a transistor M2 and a transistor The transistor M2 has a front gate. In this specification, the term "gate" refers to a gate that is a semiconductor device that has a gate electrode and a back gate. A memory device having a gain cell type memory cell using an OS transistor as the transistor M2 , NOSRAM(Nonvolatile Oxide Semiconductor It is sometimes called RAM.

[0285] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0286] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0287] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be a memory cell 1475 shown in FIG. In addition, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 1476 shown in FIG. As shown in the figure, a transistor with a single gate structure, i.e., a transistor without a back gate, For example, the memory cell MC may be configured as shown in FIG. As shown in FIG. 6G, the wiring WBL and the wiring RBL are connected to one wiring BIL. The configuration may be such that the above-mentioned components are combined together.

[0288] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as M2, and the transistor 300 is used as M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very low. This allows the written data to be held for a long time by the transistor M2. This reduces the frequency of refreshing the memory cells. In addition, the memory cell refresh operation can be eliminated. Since the resistance is extremely low, multi-value data or analog data can be stored in the memory cell 1474. The same is true for memory cells 1475 to 1477.

[0289] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. In some cases, the field effect mobility is higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as the transistor By using a Si transistor for transistor M3, a transistor Since the memory cell can be provided with a transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0290] The transistor M3 may be an OS transistor. When OS transistors are used, the memory cell array 1470 is configured with only n-type transistors. A circuit can be constructed using the same.

[0291] FIG. 16H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 16H includes transistors M4 through M6 and a capacitance element C The memory cell 1478 has wirings BIL, RW L, WWL, BGL, and GNDL. The GNDL line is a low-level The memory cell 1478 is connected to a wiring R instead of the wiring BIL. It may be electrically connected to BL and WBL.

[0292] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0293] The transistors M5 and M6 are n-channel Si transistors or p-channel Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 is circuited using only n-type transistors. A path can be constructed.

[0294] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor 200 is used as the transistor M4, and the transistors M5 and M6 are the transistors 300. The capacitance element CC can be a capacitance element 100. By using an OS transistor as the gate driver, the leakage current of transistor M4 is made very low. It can be made easier.

[0295] Note that the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are The configuration is not limited to the above. The arrangement or functions of lines, circuit elements, etc. may be changed, deleted, or added as necessary. stomach.

[0296] The configuration shown in this embodiment mode may be appropriately combined with configurations shown in other embodiment modes and examples. It can be used in combination.

[0297] (Embodiment 4) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. An example of the chip 1200 is shown. A plurality of circuits (systems) are implemented on the chip 1200. The technology of integrating multiple circuits (systems) onto a single chip is called system-on-chip (SCC). This is sometimes called System on Chip (SoC).

[0298] As shown in FIG. 17A, the chip 1200 includes a CPU (Central Processor). ing Unit) 1211, GPU (Graphics Processing Un) it) 1212, one or more analog calculation units 1213, one or more memory controllers controller 1214, one or more interfaces 1215, one or more network The circuit 1216 is a clock circuit.

[0299] The chip 1200 is provided with bumps (not shown), and as shown in FIG. A first surface of a printed circuit board (PCB) 1201 In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201. 1203.

[0300] The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0301] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This will be possible.

[0302] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0303] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit and a digital / analog conversion circuit. The multiply-and-accumulate circuit may be provided in the

[0304] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0305] The interface 1215 includes a display device, a speaker, a microphone, a camera, a The controller has an interface circuit for connecting to external devices such as a Such interfaces include computers, mobile phones, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) There can be.

[0306] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0307] The above circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering process, and the chip 1200 can be produced at low cost.

[0308] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a DRAM 122 1, and the motherboard 1203 on which the flash memory 1222 is provided is a GPU module. It can be called module 1204.

[0309] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, its excellent image processing capabilities make it a smart device. Phones, tablet devices, laptop PCs, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep Neural Networks (DNNs), Convolutional Neural Networks (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can perform operations such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0310] The configuration shown in this embodiment mode may be appropriately combined with configurations shown in other embodiment modes and examples. It can be used in combination.

[0311] (Embodiment 5) In this embodiment mode, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is used in, for example, various electronic devices (e.g., Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (e.g., D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 18 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a format and used in various storage devices and removable memory.

[0312] FIG. 18A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, The device includes a cap 1102, a USB connector 1103, and a board 1104. The board 1104 includes , are housed in a housing 1101. For example, the substrate 1104 includes a memory chip 1105, The controller chip 1106 is attached to the memory chip 110 on the board 1104. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 5 or the like.

[0313] FIG. 18B is a schematic diagram of the external appearance of an SD card, and FIG. 18C is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a board 111. The substrate 1113 is housed in a housing 1111. For example, the substrate 1113 has , memory chip 1114, and controller chip 1115 are attached to the board 11. By providing a memory chip 1114 on the back side of the SD card 1110, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This allows the memory chip to communicate with the host device and the SD card 1110 wirelessly. The data in the memory chip 1114 on the substrate 1113 can be read and written. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 114 or the like.

[0314] FIG. 18D is a schematic diagram of the external appearance of an SSD, and FIG. 18E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 includes a memory chip. A chip 1154, a memory chip 1155, and a controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156, for example, An OSRAM chip can be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By doing so, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 1154 or the like.

[0315] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0316] (Embodiment 6) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 19 shows a processor such as a CPU or a GPU according to an embodiment of the present invention. Specific examples of electronic devices equipped with the chip are given below.

[0317] <Electronic equipment and systems> A GPU or chip according to an embodiment of the present invention can be installed in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Personal computers, computer monitors, digital signage tal Signage, large game machines such as pachinko machines, etc. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos, Examples of the optical fiber include frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, It is possible to equip child devices with artificial intelligence.

[0318] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. And if a secondary battery is included, the antenna may be used for contactless power transmission.

[0319] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Numbers, distance, light, liquids, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) It may have.

[0320] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar Functions such as displaying date or time, running various software (programs) a function to read out a program or data recorded on a recording medium; The electronic device may have the following functions: FIG. 19 shows an example of the electronic device.

[0321] [mobile phone] FIG. 19A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As a user interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510. It is prepared.

[0322] The information terminal 5500 uses artificial intelligence by applying the chip according to one embodiment of the present invention. It can run applications that use artificial intelligence. For example, an application that recognizes a conversation and displays the conversation content on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. The application to be displayed on the display unit 5511 and the application to perform biometric authentication such as fingerprint or voiceprint are displayed. Applications, etc.

[0323] [Information terminal 1] FIG. 19B shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303. 303.

[0324] The desktop information terminal 5300 is similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop 5300, it is possible to develop new artificial intelligence.

[0325] In the above description, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Figs. 19A and 19B, the smartphone and desktop It can be applied to information terminals other than information terminals. Smartphones and desktop Examples of information terminals other than information terminals include PDAs (Personal Digital Assistants). Assistant, notebook type information terminal, workstation, etc.

[0326] [electric appliances] FIG. 19C shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The refrigerator 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, and the like.

[0327] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, The Electric Freezer Refrigerator 5800 is a refrigerator that can store food and drink. It also has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients, and the ... It can also have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0328] In this example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water servers, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0329] [Game consoles] FIG. 19D shows a portable game machine 5200, which is an example of a game machine. The mobile phone 5200 includes a housing 5201, a display portion 5202, a button 5203, and the like.

[0330] By applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, It is possible to realize a portable game machine 5200 with low power consumption. In addition, the low power consumption allows: Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and The impact on the module can be reduced.

[0331] Furthermore, by applying a GPU or chip according to one embodiment of the present invention to the portable game machine 5200, This makes it possible to realize a portable game machine 5200 having artificial intelligence.

[0332] Originally, the game progress, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 520 By applying artificial intelligence to 0, it is possible to express things in ways that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, the characters that appear in the game, This makes it possible to express things such as a person's behavior changing as they change.

[0333] In addition, when playing a game that requires multiple players on the portable game machine 5200, the artificial intelligence This allows you to create anthropomorphic game players, so you can make your opponents artificially intelligent. By making the game a game player, you can play the game by yourself.

[0334] In FIG. 19D, a portable game machine is illustrated as an example of a game machine. The game machine to which the GPU or chip of the present invention is applied is not limited to this. Examples of game machines to which the chips can be applied include home game machines, entertainment facilities, etc. Arcade game machines installed in facilities (game centers, amusement parks, etc.), and sports facilities Examples of equipment include a pitching machine for batting practice.

[0335] [Mobile object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the vicinity of the driver's seat of the automobile. can be applied to.

[0336] FIG. 19E1 shows an automobile 5700 as an example of a moving object, and FIG. 19E2 shows the interior of the automobile. FIG. 19E2 shows the area around the windshield in the vehicle. In addition to the display panels 5701, 5702, and 5703, An attached display panel 5704 is shown.

[0337] The display panels 5701 to 5703 display a speedometer, a tachometer, It can provide various information by displaying the distance traveled, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be adjusted to suit the user's preferences. The display panel can be changed as needed to suit the needs of the user, making it possible to enhance the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0338] The display panel 5704 displays images from an imaging device (not shown) installed in the automobile 5700. By projecting images, it is possible to compensate for blind spots that are blocked by pillars. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, This can compensate for blind spots and increase safety. By doing so, the driver can check for safety more naturally and without feeling uneasy. 4 can also be used as a lighting device.

[0339] The GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the 5700 automobile. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0340] In the above description, an automobile is used as an example of a moving object. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, etc.) These include drones, unmanned aerial vehicles (drones), airplanes, and rockets. Applying the chip of one embodiment of the present invention to a moving object and providing a system using artificial intelligence can be done.

[0341] [Broadcasting System] The GPU or chip according to one embodiment of the present invention can be applied to a broadcasting system.

[0342] FIG. 19F shows a schematic diagram of data transmission in a broadcasting system. 19F is a signal transmitted from broadcasting station 5680 to the television receivers in each home. The diagram shows the path of the signal until it reaches the TV 5600, which is equipped with a receiving device. A broadcast signal received by an antenna 5650 is transmitted via the receiving device (not shown). Transmitted to TV5600.

[0343] In FIG. 19F, antenna 5650 is a UHF (Ultra High Frequency cy) antenna is shown, but as antenna 5650, it is a BS·110°CS antenna. It can also be used for antennas and CS antennas.

[0344] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with the Na5650, you can watch terrestrial TV broadcasts with the TV5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 19F, but may be an artificial satellite broadcasting system. It may also be satellite broadcasting using stars, or data broadcasting via optical fiber lines.

[0345] The above-mentioned broadcasting system applies the chip according to one embodiment of the present invention to broadcast programs using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is turned on, the broadcast data is compressed, and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be improved. Recognizing display patterns contained in displayed images using motion compensation prediction, which is one of the methods It is also possible to perform intraframe prediction using artificial intelligence. For example, low-resolution broadcast data is received and the high-resolution TV5600 displays that broadcast data. When displaying the image, the decoder restores the broadcast data by performing up-conversion, etc. Image interpolation can be performed.

[0346] The AI-based broadcasting system described above is expected to be useful in the future, as the amount of broadcast data increases. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0347] In addition, as an application of artificial intelligence on the TV5600 side, for example, A recording device having the above-mentioned function may be provided. By having the AI ​​of the company learn the user's preferences, it can automatically present programs that match the user's preferences. It can be recorded automatically.

[0348] Electronic device described in the present embodiment, functions of the electronic device, application examples of artificial intelligence, and effects thereof etc. can be appropriately combined with the descriptions of other electronic devices.

[0349] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement. EXAMPLES

[0350] In this embodiment, samples A to C each having a conductor 242 are manufactured, and the conductor is formed by heat treatment. The variation in sheet resistance of the body 242 was evaluated.

[0351] The method for preparing the sample is described below. First, a silicon wafer is used. Silicon oxide was formed on the substrate by thermal oxidation to a thickness of 100 nm.

[0352] Next, silicon oxynitride is deposited on the silicon oxide to a thickness of 300 nm by using a CVD method. Next, oxygen was implanted into the silicon oxynitride using an ion implantation apparatus. The oxygen ion implantation conditions were acceleration energy of 60 keV and ion implantation dose of 2.0×10 16 / cm 2 It was decided.

[0353] Next, a film of indium tin oxide is formed as the conductor 242 by sputtering. The indium tin oxide was prepared using a target with a weight ratio of In2O3:SnO2 = 9:1. The deposition gas used was 40 sccm of Ar gas and 5 sccm of oxygen gas at a pressure of 0.4 P. The film was formed at a DC power of 0.2 kW and a substrate temperature of 200°C. The film thickness of sample B was 10 nm, and the film thickness of sample C was 20 nm.

[0354] Next, a heat treatment was performed on Sample A, Sample B, and Sample C. The heat treatment was performed in a nitrogen atmosphere. The heating temperature was 400°C in an atmosphere, and the heating treatment time was none (0 hours), 1 hour, and 4 hours. The time was.

[0355] Next, for samples A, B, and C, the heat treatment time (0 hours, 1 hour, and The sheet resistance of the indium tin oxide was measured after 4 hours of exposure to heat. 10 shows a graph of the heat treatment time dependence of the sheet resistance of indium tin oxide of sample C. .

[0356] The sheet resistance of the sample that was not subjected to heat treatment (heat treatment time 0 hours) was indium tin. The results varied depending on the oxide thickness (5 nm, 10 nm, and 20 nm). When the heat treatment time was 1 hour, the thickness of the sample (5 nm, 10 nm, and 20 nm) In both cases, the sheet resistance is 1.0×10 3 (Ω / sq.) to 2.0×10 3 (Ω / sq. In addition, when the heat treatment time was 4 hours, the thickness of the sample (5 nm, 10 nm) m and 20 nm), the sheet resistance was 2.0×10 3 (Ω / sq.) to 4.0 ×10 3 (Ω / sq.)

[0357] Many conductors are oxidized by the effect of oxygen, resulting in an increase in the sheet resistance of the conductor. The indium tin oxide used in this example was heated to form a The effect of oxygen diffused from silicon oxynitride containing excess oxygen placed adjacent to the surface is suppressed. It was found that the low sheet resistance was maintained.

[0358] As described above, the indium tin oxide used in this example can be used as a transistor according to one embodiment of the present invention. It was confirmed that the MOSFETs could function as the source and drain of the MOSFETs.

[0359] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. It is Noh. [Explanation of symbols]

[0360] 100: Capacitive element, 110: Conductor, 112: Conductor, 120: Conductor, 130: Insulator , 150: insulator, 200: transistor, 201: transistor, 205: conductor, 2 05a: conductor, 205b: conductor, 210: insulator, 212: insulator, 214: insulator , 216: insulator, 218: conductor, 222: insulator, 224: insulator, 230: oxide , 230a: oxide, 230A1: oxide film, 230A2: oxide, 230b: oxide, 2 30B1: oxide film, 230B2: oxide, 230c: oxide, 232B2: oxide, 24 0: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator , 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b : conductor, 242B: conductor, 242C: conductor, 244: hard mask, 245: conductor body, 246: conductor, 246a: conductor, 246b: conductor, 250: insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 272: Insulator, 276: Insulator, 28 0: insulator, 281: insulator, 300: transistor, 311: substrate, 313: semiconductor region region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: Wiring

Claims

[Claim 1] A first insulator; a first conductor on the first insulator, and a second conductor; an oxide disposed between the first conductor and the second conductor; a second insulator on the first conductor, on the second conductor, and on the oxide; a third conductor on the second insulator; a side surface of the first conductor has a region in contact with one side surface of the oxide; a side surface of the second conductor has a region in contact with the other side surface of the oxide; a height of an upper surface of the first conductor, a height of an upper surface of the second conductor, and a height of an upper surface of the oxide are each approximately equal; the first conductor has a higher electrical conductivity than the oxide; the second conductor has a higher electrical conductivity than the oxide; the first conductor and the second conductor each contain In and one or more of Sn, W, Ti, or Si; The first conductor and the second conductor each contain one or more of Zn, Ti, Ga, or Nb; The oxide contains In, an element M (wherein M is Al, Ga, Y, or Sn), and Zn; A semiconductor device, wherein the carrier density of the first conductor and the second conductor is higher than the carrier density of the oxide.

Images