Semiconductor device

Abstract

To provide a semiconductor device having a novel structure that can hold storage contents even when no power is supplied and that has no restriction in the number of writing times.SOLUTION: A semiconductor device comprises: a first memory cell that has a first transistor and a second transistor, the first and second transistors being superposed at least partially; a second memory cell that has a third transistor and a fourth transistor, the third and fourth transistors being superposed at least partially; and a drive circuit. The second memory cell is provided on the first memory cell. The first transistor is configured to include a first semiconductor material. The second transistor, the third transistor, and the fourth transistor are configured to include a second semiconductor material.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using a semiconductor element and a method for manufacturing the same. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into volatile and non-volatile types, which retain their memory contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, when information is read from a DRAM, the charge on the capacitor is lost. Every time information is read, a write operation is required again. In a transistor, a transistor is generated by a leakage current (off-state current) between the source and drain in the off state. Even when the transistor is not selected, charge flows in and out, so data is retained. This period is short. Therefore, a write operation (refresh operation) is required at regular intervals. It is difficult to reduce power consumption sufficiently. Since the contents are lost, other methods using magnetic or optical materials are required to retain the memory contents for a long period of time. A storage device is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem that the memory element may become non-functional after a certain number of writes. In order to alleviate the effect of this problem, for example, the number of write operations to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, flash memory uses floating gates to hold charges or To remove the charge, a high voltage is required, and a circuit for this purpose is also required. In addition, it takes a relatively long time to retain or remove the charge, making it difficult to write or erase. There is also the problem that it is not easy to increase the speed. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, one aspect of the present invention provides a method for storing data in a memory device that can retain stored data even when power is not supplied. The present invention aims to provide a semiconductor device having a new structure that is capable of performing write operations without limiting the number of times the device can be written. Another object of the present invention is to increase the degree of integration of a semiconductor device having a new structure. It shall be one. [Means for solving the problem]

[0011] In one embodiment of the present invention, a semiconductor device is formed using an oxide semiconductor. A transistor using an oxide semiconductor has a low leakage current. Because they are so small, they can retain information for a long period of time. When a thermally-induced oxide semiconductor is used, the degree of thermal decomposition is more remarkable, and the thermal decomposition can be continued for an extremely long period of time. This makes it possible to retain information.

[0012] More specifically, for example, the following configuration can be adopted.

[0013] In one aspect of the present invention, one of the source and the drain is connected to a first bit line. a first transistor having a source or a drain connected to the first transistor line; a first memory cell having a second transistor connected to a gate of the second bit; Either the source or the drain is connected to a first source line, and either the source or the drain is connected to a second source line. a third transistor connected to the other terminal of the first transistor; and a second transistor connected to the gate of the third transistor. a second memory cell having a first transistor and a second transistor; a driver circuit for driving the memory cell, and forming a channel formation region of the first transistor. a semiconductor material for forming channel formation regions of the second to fourth transistors; The materials are different, and the second memory cell overlaps at least a portion of the first memory cell. The semiconductor device has memory cell arrays stacked in such a way that the memory cells are aligned in a direction perpendicular to the semiconductor substrate.

[0014] In the above structure, the semiconductor material for forming the channel formation region of the first transistor is an oxide. It is preferable that the semiconductor material is a semiconductor material other than a nitride semiconductor. The semiconductor material for forming the channel formation regions of the second to fourth transistors is an oxide semiconductor. It is preferable that the insulating layer 10 includes a conductive material.

[0015] In the above structure, a part of the driver circuit includes a channel formation region of the first transistor. It is preferable that the semiconductor material is included in the driving circuit. A part of the circuit is a semiconductor material forming channel formation regions of the second to fourth transistors. It is preferable that the material is composed of a material having a thickness of 100 nm or less.

[0016] In the above structure, a part of the driver circuit includes a channel formation region of the first transistor. Another part of the driving circuit is composed of second to fourth transistors. It is preferable that the semiconductor material used for forming the channel forming region of the MOSFET is included.

[0017] In the above configuration, the first source line is electrically connected to the second source line. In the above configuration, the driver circuit is preferably It is preferable that the memory cell array has a selector circuit for selecting one of the memory cells. the first bit line and the second bit line are electrically connected to a selector circuit It is preferable that the above-mentioned

[0018] In the above, the transistor is formed using an oxide semiconductor material. One embodiment of the present invention is not limited to this. Materials, such as wide-gap materials including silicon carbide (more specifically, e.g. For example, a semiconductor material having an energy gap Eg of more than 3 eV may be used.

[0019] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating layer" is not limited to "directly under". ", it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation.

[0020] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0021] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It is possible.

[0022] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects.

[0023] For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as Effect of the Invention

[0024] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain memory contents for a longer period of time. In other words, the refresh operation is unnecessary. This makes it possible to reduce the frequency of refresh operations, or to make the frequency of refresh operations extremely low. It is possible to sufficiently reduce power consumption. In addition, even if there is no power supply, it can be used for a long period of time. It is possible to retain memory contents for a long period of time.

[0025] Furthermore, in the semiconductor device according to one embodiment of the present invention, a high voltage is not required for writing data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating layer does not occur at all. Semiconductor devices do not have the limitations on the number of times they can be rewritten, which is an issue with conventional non-volatile memory. This dramatically improves reliability. Furthermore, the on and off states of the transistors determine the Since the information is written in the memory, high-speed operation can be easily realized. Another advantage is that no additional action is required.

[0026] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. Therefore, by combining this with a transistor using an oxide semiconductor, This makes it possible to sufficiently ensure high speed operation of the device (for example, information reading operation). In addition, transistors using materials other than oxide semiconductors can be used in various applications requiring high-speed operation. Circuits (logic circuits, driver circuits, etc.) can be realized suitably.

[0027] In this way, transistors using materials other than oxide semiconductors (more broadly speaking, transistors that can operate satisfactorily) and transistors that use oxide semiconductors (or, more broadly, transistors that can operate satisfactorily) By integrating a transistor with a particularly low off-state current, It is possible to realize a semiconductor device that achieves this.

[0028] Furthermore, in one embodiment of the present invention, by stacking a part of the memory cells and the driver circuits, It is therefore possible to provide a semiconductor device with improved reliability. [Brief description of the drawings]

[0029] [Figure 1]FIG. [Diagram 2] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 3] FIG. 1 is a block diagram of a semiconductor device. [Figure 4] FIG. 1 is a block diagram of a semiconductor device. [Diagram 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 8] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 10] FIG. 1 is a block diagram of a semiconductor device. [Figure 11] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 13] FIG. 1 is a block diagram of a semiconductor device. [Figure 14] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 15] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 20] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0031] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. The actual position, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0033] (Embodiment 1) In this embodiment, a structure of a semiconductor device and a manufacturing method thereof according to one embodiment of the present invention will be described. This will be described with reference to FIGS.

[0034] <Cross-sectional structure of semiconductor device> FIG. 1 shows a cross section of a semiconductor device. In FIG. 1, A1-A2 represents a channel of a transistor. The cross-sectional view is perpendicular to the channel length direction of the transistor, and B1-B2 is parallel to the channel length direction of the transistor. The semiconductor device shown in FIG. The first stacked body 210a has a transistor 1 using a first semiconductor material in the lower part. 60 and a transistor 162 using a second semiconductor material on the upper portion. The stack 210b has a transistor 170 using a second semiconductor material in the lower part and The first stack 210 also includes a transistor 172 using the second semiconductor material. In FIG. 2A, a layer including a transistor 160 using a first semiconductor material is a stack 213a. The layer including the transistor 162 using the second semiconductor material is referred to as a stack 213b. In addition, the second stack 210b includes a transistor 170 using a second semiconductor material. A layer including the transistor 172 using the second semiconductor material is stacked on the stack 213c. This is referred to as layer 213d.

[0035] In addition, in FIG. 1, the first stack 210a includes a transistor 160 and a transistor 16 2 and the capacitance element 164 are shown, but a configuration having a plurality of each is also possible. Similarly, the second stack 210b includes a transistor 170, a transistor 172, and a capacitor. Although a configuration having one each of the child 174 is shown, a configuration having a plurality of each is also included.

[0036] Here, it is preferable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor, and the second semiconductor material may be an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon. The material used is silicon germanium, silicon carbide, or gallium arsenide. It is preferable to use a single crystal semiconductor. A transistor can easily operate at high speed. Alternatively, an organic semiconductor material may be used. A transistor using an oxide semiconductor can retain charge for a long time due to its characteristics. do.

[0037] Transistor 160, transistor 162, transistor 170 and transistor 17 Either n-channel or p-channel transistors can be used for 2. Here, transistor 160, transistor 162, transistor 170 and The transistor 172 will be described as an n-channel transistor. The technical essence of one embodiment of the present invention is to provide a semiconductor device that can suppress off-state current, such as an oxide semiconductor, in order to retain data. The semiconductor material that can be sufficiently reduced is used for the transistors 162 and 172. Since the semiconductor device is used for a wide range of applications, the semiconductor device is required to be manufactured in a wide range of materials and structures. The specific configuration of the device is not necessarily limited to that shown here.

[0038] The transistor 160 is disposed on a substrate 100 that includes a semiconductor material (such as silicon). A channel forming region 116 is formed by arranging impurity layers 116 so as to sandwich the channel forming region 116. A region 120, a metal compound region 124 in contact with the impurity region 120, and a channel forming region 1 A gate insulating layer 108 is provided on the gate insulating layer 108. In the figure, the source electrode and the drain electrode are not explicitly shown. However, for convenience, such a state may be included in the term "transistor." In this case, the source and drain regions are shown in order to explain the connection relationship of the transistor. In other words, in this specification, The reference to a source electrode may include a source region.

[0039] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 160 . Here, the electrode 126 functions as a source electrode or a drain electrode of the transistor 160. In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. An insulating layer 128 is provided in contact with the transistor 160. In order to achieve this, the transistor 160 must have a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, In the case of the gate electrode 110, a sidewall insulating layer is provided on the side of the gate electrode 110. The impurity region 120 is provided including a region with a different impurity concentration formed in a region overlapping the layer. That's fine.

[0040] The transistor 162 includes an oxide semiconductor layer 144 provided over the insulating layer 128 and the like, and an oxide semiconductor layer 144 formed over the insulating layer 128 and the like. a source or drain electrode 142a electrically connected to the nitride semiconductor layer 144; The source or drain electrode 142b, the oxide semiconductor layer 144, the source or drain electrode A gate electrode covering the source or drain electrode 142a and the source or drain electrode 142b. a gate insulating layer 146 provided over the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 144; The transistor in the second stacked body 210b has a gate electrode 148a. The configuration of the transistor 170 and the transistor 172 can be similar to that of the transistor 162. can.

[0041] Here, the oxide semiconductor layer used in the transistor, such as the oxide semiconductor layer 144, is formed by hydrogen or the like. By thoroughly removing impurities and providing sufficient oxygen, It is preferable that the oxide semiconductor layer is highly purified. The concentration is 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The above-mentioned oxidation The hydrogen concentration in the semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This is measured by mass spectroscopy. The oxygen concentration is sufficiently reduced and sufficient oxygen is supplied to fill the energy gap caused by oxygen deficiency. In the oxide semiconductor layer with reduced defect levels in the gate, the carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Less than 1.45×10 10 / c m 3 For example, the off-state current at room temperature (25° C.) (here, unit channel width (1 μm) is 100zA (1zA (zeptoampere) is 1×10 -21 A) Below , preferably 10zA or less. In this way, i-type (intrinsic) or substantially i-type By using a modified oxide semiconductor, a transistor with excellent off-state current characteristics can be obtained. The transistors 162, 170, 172, etc. can be obtained.

[0042] In addition, the transistors 162, 170, and 172 are miniaturized. In order to suppress leakage current between elements due to the above, an oxide semiconductor layer processed into an island shape is However, a structure in which the oxide semiconductor layer is not processed into an island shape may be adopted. In the case where no processing is performed, contamination of the oxide semiconductor layer due to etching during processing can be prevented.

[0043] The capacitor 164 includes a source electrode or drain electrode 142a, a gate insulating layer 146, and a and the conductive layer 148b. That is, the source electrode or drain electrode 142a The conductive layer 148b functions as one electrode of the capacitor 164, and the conductive layer 148c functions as the other electrode of the capacitor 164. This structure ensures sufficient capacity. In addition, when the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked, The insulation between the source or drain electrode 142a and the conductive layer 148b is sufficiently ensured. Furthermore, if capacitance is not required, the capacitor element 164 may be omitted. The configuration of the capacitance element 174 is similar to that of the capacitance element 164.

[0044] In the transistor 162 and the capacitor 164, the source electrode or the drain electrode The ends of the electrode 142a and the source or drain electrode 142b are tapered. It is preferable that the source electrode or drain electrode 142a is a source electrode or drain electrode. The end of the electrode 142b is tapered to improve the coverage of the gate insulating layer 146. In this case, the taper angle is, for example, 30° or more and 60° or less. The taper angle is set to 0° or less. Or the drain electrode 142a) is rotated from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side and bottom of the layer when observed from the side. The same applies to the resistor 172 and the capacitance element 174.

[0045] An insulating layer 150 and an insulating layer 152 are provided on the transistor 162 and the capacitor element 164. Then, the gate insulating layer 146, the insulating layer 150, the insulating layer 152, etc. are formed. An electrode 154 is provided in the opening, and wiring that connects to the electrode 154 is provided on the insulating layer 152. In FIG. 1, the electrode 126 and the electrode 154 are used to form a metal compound A wiring 156 is connected to the region 124, the source electrode or drain electrode 142b, and the wiring 156. However, one embodiment of the present invention is not limited to this. For example, the source electrode or drain electrode 14 2b may be directly connected to the metal compound region 124. Alternatively, the wiring 156 may be directly connected to the It may be connected to the source electrode or the drain electrode 142b.

[0046] In FIG. 1, the metal compound region 124 and the source or drain electrode 142b and a source electrode or drain electrode 142b and a wiring 156. That is, the source electrode of the transistor 160 is arranged to overlap with the electrode 154. 1, an electrode 126 serving as a source or drain electrode of a transistor 162; The area where the drain electrode 142b contacts the source electrode or drain electrode of the transistor 162. The area where the electrode 142b and the electrode 154 are in contact with each other overlaps with the area where the electrode 142b and the electrode 154 are in contact with each other. By adopting the out, it is possible to suppress the increase in element area caused by the contact region. In other words, the degree of integration of the semiconductor device can be increased.

[0047] In this embodiment, the transistor 160 in the first stack 210a is a transistor 162 and the capacitor 164. The conductive layer 148b of the capacitor 164 is a source electrode or a drain electrode of the transistor 162. The electrode 142a and the gate electrode 110 of the transistor 160 are at least partially overlapped. By adopting such a planar layout, a high density of memory cells can be achieved. For example, if the minimum processing dimension is F, the area occupied by the memory cell is 15F 2 ~25F 2 It is possible to make the following:

[0048] In the second stack 210b, the transistor 170 is also and the capacitance element 174 are provided so as to overlap at least partially. The electrode of the transistor 174 (corresponding to the conductive layer 148b of the capacitor 164) is A source electrode or drain electrode (a source electrode or drain electrode 14 of the transistor 162) 2a) and the gate electrode of the transistor 170 (corresponding to the gate electrode 1 of the transistor 160 10) and is provided at least partially overlapping each other. The first laminate 210a and the second laminate 210b are laminated with an insulating layer 158 interposed therebetween. This allows for further integration of the semiconductor device.

[0049] In FIG. 1, two layers, a first laminate 210a and a second laminate 210b, are laminated. However, one embodiment of the present invention is not limited to this example, and may have a laminated structure of three or more layers. In that case, the third laminate may have the same structure as the second laminate 210b. By applying such a stacked structure, the integration of semiconductor devices can be improved. This can further improve the efficiency.

[0050] <Circuit configuration of semiconductor device> Next, the circuit configuration and operation of the semiconductor device shown in FIG. 1 will be described with reference to FIG. Note that in the circuit diagram, The OS code may also be added.

[0051] <Basic configuration> In the semiconductor device shown in FIG. 2(A-1), a first wiring (1st Line) and a transistor The source electrode (or drain electrode) of the transistor 160 is electrically connected to the second wiring ( 2nd Line) and the drain electrode (or source electrode) of the transistor 160. Also, the third wiring (3rd Line) and the transistor 162 The source electrode (or drain electrode) is electrically connected to the fourth wiring (4th Li ne) is electrically connected to the gate electrode of the transistor 162. The gate electrode of the transistor 160 and the drain electrode (or source electrode) of the transistor 162 are The fifth wiring (5th Lin) is electrically connected to one of the electrodes of the capacitance element 164. e) is electrically connected to the other electrode of the capacitor 164. The circuit configuration shown in FIG. 1 corresponds to the circuit configuration included in the first laminate 210a shown in FIG. It functions as a reseller.

[0052] Here, the transistor 162 is, for example, a transistor including an oxide semiconductor. A transistor using an oxide semiconductor has the characteristic of having an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 1 It is possible to hold the potential of the gate electrode of 60 for an extremely long period of time. By including the capacitance element 164, the charge applied to the gate electrode of the transistor 160 This makes it easier to store information and to read out the stored information.

[0053] Note that the transistor 160 is not particularly limited, and may be, for example, a semiconductor other than an oxide semiconductor. Transistors using semiconductor materials are applied. The aim is to improve the speed at which information is read. From the viewpoint of high switching speed, for example, transistors using single crystal silicon, It is preferable to use a transistor having a low resistance.

[0054] In the semiconductor device shown in FIG. 2B, a first wiring (1st Line) and a transistor The source electrode (or drain electrode) of 170 is electrically connected to the second wiring (2n d Line) and the drain electrode (or source electrode) of the transistor 170 are electrically Also, the third wiring (3rd Line) and the source of the transistor 172 are connected to The source electrode (or drain electrode) is electrically connected to the fourth wiring (4th Line ) is electrically connected to the gate electrode of the transistor 172. The gate electrode of transistor 170 and the drain electrode (or source electrode) of transistor 172 is electrically connected to one of the electrodes of the capacitance element 174, and is a fifth wiring (5th Line) The other electrode of the capacitor 174 is electrically connected to the The circuit configuration corresponds to the circuit configuration included in the second stack 210b shown in FIG.

[0055] Here, the transistor 170 and the transistor 172 are formed using the above-described oxide semiconductor. The above-described transistor using an oxide semiconductor has a low off-state current. Therefore, the transistor 172 is turned off. This allows the potential of the gate electrode of the transistor 170 to be held for an extremely long period of time. By providing the capacitance element 174, the gate of the transistor 170 This makes it easier to hold the charge given to the electrode, and easier to read out the stored information. Note that the transistor 170 and the transistor 172 each using an oxide semiconductor are The channel length (L) is set to 10 nm or more and 1000 nm or less, so power consumption is small and It also has the advantage of being able to operate at a sufficiently high speed.

[0056] As shown in FIG. 2C, the capacitor 164 is not provided in the configuration shown in FIG. This is also the case in FIG. 2B, and the capacitance element 174 is provided. It is possible to configure it so that

[0057] In the semiconductor device shown in FIG. 2A-1, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: In the semiconductor device shown in FIG. 2B, data can be written in the same manner as in FIG. Since the signal can be written, held, and read, a detailed description will be omitted.

[0058] First, writing and holding information will be described with reference to FIG. The potential of the fourth wiring is set to a potential at which the transistor 162 is turned on. 162 is turned on. As a result, the potential of the third wiring is The gate electrode of the transistor 160 and the capacitance element 164 are applied to the A certain charge is applied to the electrode (writing). Charge (hereinafter, the charge that gives the low potential is called charge Q L , the charge that gives the high potential is charge Q H The word " In addition, charges that give three or more different potentials are Then, the potential of the fourth wiring is applied to the transistor 1. By setting the potential at which the transistor 162 is turned off, the transistor The charge applied to the gate electrode of the transistor 160 is retained (retained).

[0059] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0060] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the transistor electrode, the second wiring has a different potential. If the transistor 160 is an n-channel type, then the gate electrode of the transistor 160 is connected to Q H is given The apparent threshold V th_H is connected to the gate electrode of transistor 160. L but Given the apparent threshold V th_L This is because the temperature is lower than that of the The threshold voltage of the transistor 160 is the fifth threshold voltage required to turn the transistor 160 "on". Therefore, the potential of the fifth wire is V th_H and V th_L By setting the potential V0 at the midpoint between For example, in writing, Q H If given, the fifth wire The potential of V0 (>V th_H ), transistor 160 is in the "on state." Q L is given, the potential of the fifth wire is V0( <Vth_L ) even if The transistor 160 remains in the "off state." Therefore, the potential of the second wiring is not observed. The stored information can be read out.

[0061] When memory cells are arranged in an array, only the information of a desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and When the information of the other memory cells is not read, the first memory cell of the memory cell that is not the object of reading is For the wiring of 5, the transistor 160 is in the "off state" regardless of the state of the gate electrode. That is, V th_H Alternatively, a smaller potential can be applied to the gate. The potential at which transistor 160 is "on" regardless of its polarity, i.e., V th_L A larger potential may be applied to the fifth wiring.

[0062] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are now given a charge related to the new information.

[0063] In this manner, the semiconductor device according to one embodiment of the present invention can directly store data by rewriting the data. This makes it possible to quickly rewrite information. No need to extract charge from the floating gate using high voltages, and the erase operation is In other words, the semiconductor device can operate at high speed. It will be realized.

[0064] The drain electrode (or source electrode) of the transistor 162 is connected to the transistor 160. The gate electrode of the semiconductor device is electrically connected to the non-volatile memory element. This has the same effect as the floating gate of a floating gate type transistor. Therefore, in the figure, the drain electrode (or source electrode) of transistor 162 and the transistor The portion to which the gate electrode of 60 is electrically connected is sometimes called the floating gate portion FG. When the transistor 162 is off, the floating gate portion FG is in the insulator. It can be seen as buried, and the charge is held in the floating gate portion FG. The off-state current of the transistor 162 using a compound semiconductor is Since the transistor 162 is 1 / 100,000th of the transistor, the leakage current of the transistor 162 is It is possible to ignore the loss of charge stored in the gate FG. The transistor 162, which uses a quartz semiconductor, can retain information even without power supply. It is possible to realize a nonvolatile memory device.

[0065] For example, the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA Ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 164 is about 10 fF. In some cases, at least 10 4It is possible to hold data for more than 100 seconds. However, it goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0066] In this case, the gate problem pointed out in the conventional floating gate type transistor is There is no problem of deterioration of the gate insulating layer (tunnel insulating layer). This solves the problem of degradation of the gate insulating layer when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times it can be written. In addition, in the conventional floating gate type transistor, writing and erasing The high voltage required for this is also unnecessary.

[0067] The semiconductor device shown in FIG. 2(A-1) includes elements such as transistors that constitute the semiconductor device. It is possible to think of it as including resistance and capacitance, as shown in Figure 2(A-2). That is, in FIG. 2(A-2), the transistor 160 and the capacitor 164 are It is considered to be composed of resistance and capacitance. R1 and C1 are The resistance value R1 is the resistance value and the capacitance value of the capacitance element 164. R2 and C2 correspond to the resistance of the insulating layer that connects the transistor 1 and the 60, and the resistance R2 is the gate capacitance when the transistor 160 is in the on state. The capacitance C2 corresponds to the resistance of the gate insulating layer. The capacitance formed between the source electrode or drain electrode, and the gate electrode and the channel This corresponds to the capacitance value of the capacitance formed between the

[0068] The resistance between the source and drain electrodes of the transistor 162 when it is in the off state (actual If the gate leakage of transistor 162 is sufficiently small, then In the condition, if R1 and R2 satisfy R1 ≧ ROS and R2 ≧ ROS, the charge The retention period (or information retention period) of the current is mainly due to the on-state of the transistor 162. The input current is determined by the input current.

[0069] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. In addition, it becomes difficult to secure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment has the above-mentioned characteristics. It is desirable that the above conditions be satisfied.

[0070] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≧ C2. When the potential of the floating gate portion FG is controlled by the fifth wiring, This allows the potential of the line to be efficiently applied to the floating gate portion FG, The potential difference between the potentials applied to the wiring (for example, the read potential and the non-read potential) is reduced. This is because it can be suppressed.

[0071] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are formed by the gate insulating layer of the transistor 160 and the insulating layer of the capacitance element 164. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer are It is desirable to appropriately set the length and other factors so as to satisfy the above-mentioned relationship.

[0072] In the semiconductor device shown in this embodiment, the floating gate portion FG is a flash It has the same effect as the floating gate of a floating gate type transistor such as a memory. However, the floating gate portion FG of this embodiment is a floating gate of a flash memory or the like. In flash memory, the control gate has fundamentally different characteristics. The voltage applied to the floating gate of the adjacent cell is high, so the effect of the potential on the floating gate of the adjacent cell is In order to prevent this from happening, it is necessary to maintain a certain amount of space between the cells. This is one of the factors that hinder the high integration of semiconductor devices. This is due to the fundamental principle of flash memory, which is to generate a tunnel current by applying a voltage That is why.

[0073] On the other hand, the semiconductor device according to the present embodiment has a transistor switch using an oxide semiconductor. It operates by switching and does not use the principle of charge injection by tunnel current as described above. In other words, unlike flash memory, a high electric field for injecting charges is not required. Therefore, there is no need to consider the effect of high electric fields due to the control gate on adjacent cells. This makes it easier to achieve high integration.

[0074] In addition, flash memory does not require a high electric field or large peripheral circuits (such as a boost circuit). For example, when the memory cell according to the present embodiment is printed The maximum and minimum voltages applied simultaneously to each terminal of the memory cell The maximum value of the difference between the two levels of information (1 bit) is , 5V or less, preferably 3V or less.

[0075] The relative dielectric constant εr1 of the insulating layer constituting the capacitance element 164 and the relative dielectric constant εr2 of the insulating layer constituting the transistor 160 are When the relative dielectric constant εr2 of the insulating layer is made different from that of the insulating layer constituting the capacitance element 164, S1 and the area S2 of the insulating layer that constitutes the gate capacitance of the transistor 160 are 2· It is easy to realize C1 ≧ C2 while satisfying S2 ≧ S1 (preferably S2 ≧ S1). Specifically, for example, the insulating layer constituting the capacitance element 164 is made of hafnium oxide. A film made of a high-k material such as tungsten, or a film made of a non-high-k material such as hafnium oxide. A laminated structure of a film made of a metal oxide semiconductor and a film made of an oxide semiconductor is adopted to make εr1 10 or more, preferably 15 As described above, silicon oxide is used for the insulating layer that constitutes the gate capacitance, and εr2 = It can be 3 to 4.

[0076] By using such a structure in combination, the semiconductor device according to one embodiment of the present invention can be further improved. High integration is possible.

[0077] In order to increase the memory capacity of a semiconductor device, in addition to increasing the integration density, a method of multi-level data storage is also being adopted. For example, it is possible to configure the memory cell to write three or more levels of information. This allows for a larger memory capacity than when writing information in two stages. For example, , as mentioned above, the charge Q L , charge Q giving high potential H In addition to the above, other potentials By providing the charge Q to the gate electrode of the first transistor, multi-values ​​can be realized. In this case, F 2 Even if a circuit configuration is adopted in which can be secured.

[0078] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of positive hole-causing transistors instead of n-type transistors. It goes without saying that a p-type transistor can be used as the carrier.

[0079] As described above, the semiconductor device according to the present embodiment is suitable for high integration. Semiconductors with higher integration density due to the sharing of wiring for various devices and the reduction of contact areas. It is possible to provide an apparatus.

[0080] <Application Examples> Next, application examples of the above-mentioned semiconductor device will be described with reference to FIGS.

[0081] FIG. 3 is an example of a block diagram of a semiconductor device. The semiconductor device shown in FIG. The image display device includes an array 201, a first driving circuit 202, and a second driving circuit 203.

[0082] First, the memory cell array 201 will be described. The memory cell array 201 is a stacked The memory cell arrays 211a to 211c are also provided.

[0083] The memory cell array 211a includes n (n is an integer of 2 or more) bit lines BL and m (m is an integer of 2 or more) A signal line S of m (an integer of 2 or more), a word line WL of m, and a line k (k is n or less or m or less). The source lines SL (a natural number) and the memory cells 212a are arranged in a matrix of m (rows) by n (columns). Here, the memory cell 212a has a region arranged in a shape of a triangle. It is preferable to use the configuration shown in A-1). The signal lines S are represented as signal lines S(1,1) to S(m,1), and the word lines WL are represented as word lines W L(1,1) to WL(m,1). The bit lines BL are represented as bit lines BL(1,1) to BL(n,1).

[0084] The memory cell 212a includes a first transistor, a second transistor, and a first capacitance element. Here, the memory cell 212a has the first stacked body 210a shown in FIG. In the memory cell 212a, the first transistor corresponds to the The second transistor is a transistor 160 in the configuration shown in FIG. The first capacitance element corresponds to the capacitance element 162, and the second capacitance element corresponds to the capacitance element 164. In 212a, a gate electrode of a first transistor and a drain of a second transistor The electrode (or source electrode) and one of the electrodes of the first capacitance element are electrically connected to each other. The source line SL and the source electrode of the first transistor are electrically connected to each other. A bit line BL, a source electrode (or a drain electrode) of the second transistor, and a The drain electrode of the transistor is electrically connected to the word line WL. The other electrode is electrically connected to the signal line S, and the gate electrode of the second transistor is electrically connected to the signal line S. That is, the source line SL is electrically connected to the first The bit line BL is connected to the first line (1st Line), the second line (2nd Line) and The signal line S is connected to the third line (3rd Line), and the signal line S is connected to the fourth line (4th Line). The code line WL corresponds to the fifth line (5th Line).

[0085] The memory cell array 211a includes a memory cell including a first semiconductor material and a second semiconductor material. By applying rule 212a, the read operation can be accelerated while ensuring a sufficient retention period. It is possible.

[0086] The memory cell array 211b includes n (n is an integer of 2 or more) bit lines BL and m (m is an integer of 2 or more) A signal line S of m (an integer of 2 or more), a word line WL of m, and a line k (k is n or less or m or less). The source lines SL (a natural number) and the memory cells 212b are arranged in a matrix of m (rows) by n (columns). Here, the memory cell 212b has a region arranged in a shape of a triangle. It is preferable to use the configuration shown in B). The signal lines S are represented as signal lines S(1,2) to S(m,2), and the word lines WL are represented as word lines WL( WL(m,2) to WL(m,2). BL is represented as bit lines BL(1,2) to BL(n,2).

[0087] The memory cell 212b includes a third transistor, a fourth transistor, and a second capacitance element. Here, the memory cell 212b has the second stacked body 210b shown in FIG. In the memory cell 212b, the third transistor corresponds to the 2(B), the fourth transistor is a transistor The first capacitance element corresponds to capacitance element 172, and the second capacitance element corresponds to capacitance element 174. In 2b, a gate electrode of a third transistor and a drain electrode of a fourth transistor (or a source electrode) and one of the electrodes of the second capacitance element are electrically connected to each other, The line SL and the source electrode of the third transistor are electrically connected. The third transistor is connected to the source line BL. The drain electrode of the second capacitor is electrically connected to the word line WL. The other is electrically connected, and the signal line S and the gate electrode of the fourth transistor are electrically connected. That is, the source line SL is connected to the first wiring (1st Line), the bit line BL is connected to the second wiring (2nd Line) and the third wiring (3rd Line). The third line, the signal line S, the fourth line, and the word line W. L corresponds to the 5th Line.

[0088] The memory cell array 211c has the same configuration as the memory cell array 211b. In other words, the memory cell array 211c is , a plurality of memory cells 212c. Also, a signal The lines S are represented as signal lines S(1,3) to S(m,3), and the word lines WL are represented as word lines WL(1 WL(m,3) to WL(m,3). L is represented as bit lines BL(1,3) to BL(n,3).

[0089] The memory cell array 211b and the memory cell array 211c include a second semiconductor material. By applying the memory cell 212b and the memory cell 212c, the manufacturing process is repeated. This allows for a sufficient retention period for information without being careless.

[0090] Furthermore, by forming the memory cell arrays 211a to 211c into a stacked structure, This allows for greater integration.

[0091] In FIG. 3, the memory cell arrays 211a to 211c are not connected to each other. However, one embodiment of the present invention is not limited to this. The source line SL of the array 211a and the source line S of the memory cell array 211b L is electrically connected to the memory cell 212a and the memory cell 212b. This can reduce the number of source lines SL. A source line SL connected to the memory cell 212a and a source line SL connected to the memory cell 212b are connected to the The memory cell 212a and the memory cell 212b are electrically connected to the line SL. can also be electrically connected.

[0092] In the semiconductor device shown in FIG. 3, the memory cell arrays 211a to 211c include The recells are arranged in a matrix of m rows x n columns. The embodiment is not limited to this. The memory cell configurations do not need to be the same, and may be different. .

[0093] The first drive circuit 202 and the second drive circuit 203 each include a plurality of circuits. The driving circuit 202 includes a selector 221, a circuit 222 including a buffer, and a row decoder. The second driving circuit 203 includes a selector 231, a circuit group 232, and , and a column decoder 233. The circuit group 232 includes a write circuit group 234 and a read It includes a circuit group 235 and a register group 236 .

[0094] FIG. 4 is a simplified block diagram showing an example of a stacked state of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 4, the memory cell array 201 has a three-layer structure. The first driving circuit 202 and the second driving circuit 203 have a structure in which the laminate is one layer. The array 211a is provided in the first stack 210a, and the memory cell array 211b is provided in the second stack 210b. The memory cell array 211c is provided on the second stack 210b. The first driving circuit 202 and the second driving circuit 203 are provided in the laminate. The first laminate 210a is provided with the second laminate 210b.

[0095] 5 shows an example of a circuit diagram of the selector 231 of the semiconductor device shown in FIGS. In this embodiment, the selector 231 is provided in the first stack 210a. The selector 231 has a plurality of transistors. 11a through BL(1,1) to BL(n,1). The memory cell array 211b is connected to the memory cell array 211c via BL(1,2) to BL(n,2). The selector 211c is connected to the channel array 211c via BL(1,3) to BL(n,3). 231 is connected to the bit line BL and the circuit group 2 in accordance with the layer selection signals LAY1, LAY2, and LAY3. When the signal LAY1 is active, BL(1,1) to BL (n,1) and the terminal of the circuit group 232 are electrically connected. If the signal LAY2 is active, L(1,2) to BL(n,2) are electrically connected to the terminals of the circuit group 232. If it is active, BL(1,3) to BL(n,3) and the terminals of the circuit group 232 are electrically connected.

[0096] FIG. 6 shows an example of a block diagram of the circuit group 232 of the semiconductor device shown in FIGS. Here, the circuit group 232 will be described as being provided in the first stack 210a. 232 includes a write circuit group 234, a read circuit group 235, and a register group 236. The write circuit group 234 includes a plurality of write circuits 237, and receives a write enable signal WE, a write potential Vwrite, and a signal output from the register group 236 are input. The output signals output from the plurality of write circuits 237 are input to the selector 231. The read circuit group 235 includes a read circuit 238 and receives a read enable signal R E and a read potential Vread are input, and the output signal is input to the register group 236. In addition, a terminal for reading out the read circuit 238 is connected to the selector 231. The group 236 receives input data DIN and outputs output data DOUT. The signal from the read circuit group 235 is input to the star group 236, which is connected to the write circuit group 234. The signals input to the write circuit group 234 are inverted versions of each other. The write circuit 237, the read circuit 238, and the register 23 9, each of which has the same number as the number of columns of the memory cell array.

[0097] The operation of the circuit group 232 shown in Fig. 6 will be described. The operation of writing data to the register group 236 and the operation of reading data from the register group 236 to the outside. 6 to the memory cell, and the operation of writing data from the memory cell to the register group 236 The operation of reading out the data will now be described.

[0098] The operation of writing data to the register group 236 from the outside is performed when the signal DIN is input to the register group 236. The operation of reading data from the register group 236 to the outside is carried out by storing the data in the register. This is done by outputting the data stored in the star group 236 as a signal DOUT. The operation of writing data from the register group 236 to a memory cell is performed by a write enable signal WE is active, the write circuit group 234 receives the signal output from the register group 236. As a result, the write voltage is selected and output on the bit line BL. A voltage is applied and data is written to the memory cell. The operation of reading data to 236 is performed while the read enable signal RE is active. The read circuit group 235 determines the bit line potential to read data from the memory cells. This is done by outputting the data and storing the outputted data in the register group 236.

[0099] The read circuit 238 may be, for example, the read circuit shown in FIG. The read circuit shown in FIG. 1 includes a sense amplifier SA, a load transistor, and a switch. The sense amplifier SA compares the bit line potential with the read potential Vread and outputs the result. The read enable signal RE determines whether or not the read circuit and the bit line are electrically connected to each other.

[0100] The write circuit 237 may be, for example, the write circuit shown in FIG. The write circuit shown in Figure 1 is composed of three switches, and is driven by a pair of mutually inverting signals. The potential of either Vwrite or GND is selected by the write enable signal WE. This determines whether or not the selected potential is supplied.

[0101] 9 shows an example of a circuit diagram of the selector 221 of the semiconductor device shown in FIGS. The selector 221 will be described as being provided in the first stack 210a.

[0102] The selector 221 has a plurality of transistors. Ray 211a and WL(1,1) to WL(m,1) and S(1,1) to S(m,1) Similarly, the memory cell array 211b and the memory cells WL(1,2) to WL(m , 2) and S(1, 2) to S(m, 2), and the memory cell array 21 Connected to 1c via WL(1,3)~WL(m,3) and S(1,3)~S(m,3) The selector 221 selects a layer according to the layer selection signals LAY1, LAY2, and LAY3. The signal line WL and the signal line S are electrically connected to the terminal of the circuit 222. The signal LAY1 is active. Then, WL(1,1) to WL(m,1) and S(1,1) to S(m,1) and circuit 22 When the signal LAY2 is active, WL(1,2) to WL(m , 2) and S(1, 2) to S(m, 2) are electrically connected to the terminals of the circuit 222. If is active, WL(1,3) to WL(m,3) and S(1,3) to S(m,3 ) and the terminal of the circuit 222 are electrically connected.

[0103] The circuits provided in the first driving circuit 202 and the second driving circuit 203 are made of a first semiconductor material. By forming the first driving circuit 202 and the second driving circuit 203 using a material, It can be operated quickly.

[0104] FIG. 10 is a simplified block diagram showing another example of a stacked state of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 10, the memory cell array 201 has a three-layer structure. The selectors 221a, 221b, and 221c of the driving circuit 202 and the second driving circuit The selectors 231a, 231b, and 231c of the path 203 have a three-layer structure. The other circuits included in the first driving circuit 202 and the second driving circuit 203 are formed of a single laminate. The memory cell array 211a, the selector 221a, and the selector 231a are A memory cell array 211b, a selector 221b and a selector 221c are provided in one stack 210a. The selector 231b is provided in the second stack 210b, and includes a memory cell array 211c and a selector 231b. The connector 221c and the selector 231c are provided in the third stack 210c.

[0105] FIG. 11 shows a selector 231a in the second driving circuit 203 of the semiconductor device shown in FIG. 11 shows an example of a circuit diagram of the selector 231b and 231c. The difference between Figure 11 and Figure 5 is the layered structure of the selector. In FIG. 5, the transistors of the selector are provided in the first stack 210a. In the first embodiment, the transistors of the selector are arranged across three layers. The selector 231a in the operation circuit 203 is formed in the same layer as the memory cell array 211a. The selector 231b is formed in the same layer as the memory cell array 211b. The selector 231c is formed in the same layer as the memory cell array 211c. The selector 231a in the second driving circuit 203 is configured to include a first semiconductor material, The selector 231b and the selector 231c are configured to include a second semiconductor material.

[0106] The circuit group 232 of the semiconductor device shown in FIG. 10 is the same as the circuit group 232 of the semiconductor device shown in FIG. The circuit configuration and the laminated structure are sufficient. For details, refer to the example block diagram shown in Figure 6. It is possible.

[0107] FIG. 12 shows a selector 221a in the first driving circuit 202 of the semiconductor device shown in FIG. 12 shows an example of a circuit diagram of the selector 221b and 221c. The difference between Figure 12 and Figure 9 is the layered structure of the selector. In FIG. 9, the transistors of the selector are provided in the first stack 210a. In the second embodiment, the transistors of the selector are arranged across three layers. The selector 221a in the operation circuit 202 is formed in the same layer as the memory cell array 211a. The selector 221b is formed in the same layer as the memory cell array 211b. The selector 221c is formed in the same layer as the memory cell array 211c. The selector 221a in one of the driving circuits 202 is configured to include a first semiconductor material, The selector 221b and the selector 221c are configured to include a second semiconductor material.

[0108] By adopting such a configuration, the area occupied by the driving circuit can be reduced and the memory density can be increased. In addition, by increasing the area of ​​the memory cell array, the memory capacity can be increased. It is possible.

[0109] FIG. 13 is a simplified block diagram showing another example of a stacked state of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 13, the memory cell array 201 has a three-layer structure. The first driving circuit 202 and the second driving circuit 203 are partially formed into a laminated structure consisting of multiple layers. The memory cell array 211a, the selector 221a, the selector 231a, the circuit group 2 32a is provided in the first stack 210a, and includes a memory cell array 211b, a selector 22 1b, a selector 231b and a circuit group 232b are provided in a second stack 210b, The memory cell array 211c, the selector 221c, and the selector 231c are connected to the third stack 2. It is provided in 10c.

[0110] The difference between FIG. 13 and FIG. 10 is the structure of the second driving circuit 203. For example, in FIG. 13, the circuit group 232 in the second driving circuit 203 has a single-layer structure. The circuit groups 232a and 232b in the driver circuit 203 have a two-layer laminated structure.

[0111] The selectors 231a to 231c and the selectors 221a and 221b of the semiconductor device shown in FIG. b, 221c are the selectors 231a, 231b, 231c and The selectors 221a to 221c may have the same circuit configuration and laminated structure. Reference can be made to the example block diagrams shown in FIG. 11 and FIG. 12, respectively.

[0112] FIG. 14 shows a circuit group 232a, 232b in the second driver circuit 203 of the semiconductor device shown in FIG. 14 shows an example of a circuit diagram of the selectors 231a, 231b, and 231c. The circuit groups 232a and 232b have the same circuit configuration as the circuit group 232 shown in FIG. The difference between the circuit groups 232a and 232b shown in FIG. 14 and the circuit group 232 shown in FIG. 6 is the laminated structure. In FIG. 6, the transistors included in the circuit group 232 are provided in the first stack 210a. However, in FIG. 14, the transistors in the circuit groups 232a and 232b are arranged across two layers. For example, the circuit group 232a in the second driver circuit 203 is a memory cell array The circuit group 232b is formed in the same layer as the memory cell array 211b. That is, the circuit group 232a in the second driving circuit 203 is formed in the same layer. The circuit group 232b is configured to include a first semiconductor material, and the circuit group 232c is configured to include a second semiconductor material. can be.

[0113] The circuit group 232a shown in FIG. 14 includes a register group 236 and a read circuit group 235. The circuit group 232b shown in FIG. 14 includes a write circuit group 234. A read circuit group 235 is The read circuit may be, for example, the read circuit shown in FIG. The write circuit in the write circuit group 234 is, for example, the write circuit shown in FIG. The write circuit shown in FIG. 15 includes three transistors including a second semiconductor material. The inverted signal pair is configured with a resistor to select either Vwrite or GND. A potential is selected, and the supply of the selected potential is determined by the write enable signal WE. It is decided.

[0114] By adopting such a configuration, the area occupied by the driving circuit can be reduced and the memory density can be increased. In addition, by increasing the area of ​​the memory cell array, the memory capacity can be increased. It is possible.

[0115] In this embodiment, the memory cell array 201, the first driver circuit 202, or the second driver circuit Although an example in which the driver circuit 203 is stacked in three layers has been described, one embodiment of the present invention is not limited to this. Alternatively, it may have a laminated structure of two layers or four or more layers.

[0116] <Method for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the lower transistor 160 in the layer 210a is shown in FIG. 16 and FIG. 17. Then, a method for manufacturing the upper transistor 162 and the capacitor element 164 will be described with reference to This will be described with reference to Figs. 18 and 19. The transistor 170, the transistor 172, and the capacitor 174 are fabricated as follows: The method for manufacturing the capacitor 162 and the capacitor element 164 is similar to that for manufacturing the capacitor 162 and the capacitor element 164, so the details will be omitted. .

[0117] <Method of manufacturing the lower transistor> A method for manufacturing the lower transistor 160 will be described with reference to FIGS. .

[0118] First, a substrate 100 containing a semiconductor material is prepared. Single crystal semiconductor substrates such as silicon carbide and silicon germanium, polycrystalline semiconductor substrates, silicon germanium, etc. Any compound semiconductor substrate, SOI substrate, etc. can be applied. As the substrate 100, a single crystal silicon substrate is used as an example. Generally, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. In this specification, a semiconductor layer made of a material other than silicon on an insulating surface is referred to as a substrate. In other words, the semiconductor layer of an "SOI substrate" is also included in the term "substrate". The semiconductor layer is not limited to silicon. In addition, the SOI substrate may be made of an insulating material such as a glass substrate. The present invention also includes a structure in which a semiconductor layer is provided on a peripheral substrate via an insulating layer.

[0119] When a single crystal semiconductor substrate such as a silicon wafer is used as the substrate 100 containing a semiconductor material, In this case, it is preferable because the read operation of the semiconductor device can be performed at a high speed.

[0120] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 16(A)). The protective layer 102 is made of, for example, silicon oxide or silicon nitride. For example, an insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurity elements that give n-type conductivity include, for example, phosphorus and arsenic. In addition, the impurity element that imparts p-type conductivity can be, for example, boron. , aluminum, gallium, etc. can be used.

[0121] Next, etching is performed using the protective layer 102 as a mask, and the This removes a portion of the substrate 100 from the exposed area. A semiconductor region 104 separated from the region is formed (see FIG. 16(B)). For this purpose, it is preferable to use dry etching, but wet etching may also be used. The etching gas and etching solution should be selected appropriately depending on the material to be etched. can be done.

[0122] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 16(C)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer can be removed by polishing processes such as CMP (chemical mechanical polishing) or etching. After the semiconductor region 104 is formed, Alternatively, after the element isolation insulating layer 106 is formed, the protective layer 102 is removed.

[0123] Here, CMP processing is a process in which the surface of the workpiece is treated chemically and mechanically based on the surface. This is a method of flattening the surface by a combination of mechanical actions. A cloth is attached, and slurry (abrasive) is supplied between the workpiece and the polishing cloth while the polishing stage is The surface of the workpiece is rotated or swung to mix the slurry with the surface of the workpiece. This is a method of polishing that uses a chemical reaction between the surface and the mechanical polishing action of the abrasive cloth and the workpiece. be.

[0124] As a method for forming the element isolation insulating layer 106, in addition to a method for selectively removing the insulating layer, a method for forming the element isolation insulating layer 106 using an acid Alternatively, a method of forming an insulating region by implanting an element may be used.

[0125] Next, an insulating layer is formed on the surface of the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. Complete.

[0126] The insulating layer is to be a gate insulating layer later. For example, the insulating layer is formed by heat treatment ( Instead of heat treatment, high density Plasma treatment may be applied. High density plasma treatment may be performed using, for example, He, Ar, Kr, X A mixture of rare gases such as e, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Of course, it is possible to form an insulating layer by using a CVD method, a sputtering method, etc. The insulating layer may be formed of silicon oxide, silicon oxynitride, silicon nitride, or oxide. Hafnium, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (H fSi x O y (x>0, y>0)), nitrogen-doped hafnium aluminate (HfA l x O y It is preferable that the layer structure be a single layer structure or a multilayer structure including (x>0, y>0) etc. The thickness of the insulating layer is, for example, 1 nm to 100 nm, preferably 10 nm to 50 nm. It can be made 0 nm or less.

[0127] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a semiconductor material such as polycrystalline silicon can be used to form the conductive layer. A layer containing the material may be formed. The method of forming the layer is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, or the like. Various film formation methods such as a deposition method, a deposition method, a spin coating method, etc. can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let us assume that.

[0128] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 16(C)).

[0129] Next, phosphorus (P) or arsenic (As) is added to the semiconductor region 104 to form a channel forming region. 16(D) and the impurity region 120 are formed (see FIG. 16(D)). Phosphorus or arsenic is added to form a p-type transistor. In this case, impurity elements such as boron (B) and aluminum (Al) may be added. The concentration of the added impurities can be set appropriately, but as semiconductor elements become highly miniaturized, If so, it is desirable to increase the concentration.

[0130] In addition, a sidewall insulating layer is formed around the gate electrode 110 to form a gate insulating film having a different impurity element. It is also possible to form an impurity region doped with a certain concentration.

[0131] Next, a metal layer 122 is formed so as to cover the gate electrode 110, the impurity region 120, etc. (FIG. The metal layer 122 is formed by vacuum deposition, sputtering, spin coating, etc. The metal layer 122 can be formed by using various film formation methods such as a deposition method. The semiconductor material that constitutes the semiconductor layer 4 is reacted with a metal material to form a low-resistance metal compound. Such a metal material is preferably titanium or tantalum. , tungsten, nickel, cobalt, platinum, etc.

[0132] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the pure region 120 (see FIG. 17(A)). When polycrystalline silicon or the like is used as the gate electrode 110, the gold of the gate electrode 110 is A metal compound region is also formed in the portion in contact with the metal layer 122.

[0133] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0134] Next, an electrode 126 is formed in a region that contacts a part of the metal compound region 124 (FIG. 17(B) ) The electrode 126 is formed, for example, by forming a layer containing a conductive material and then selectively removing the layer. The conductive material layer is made of aluminum, copper, titanium, tantalum, etc. The insulating layer 11 can be formed of a metal material such as tantalum or tungsten. Alternatively, a layer containing a conductive material may be formed using a semiconductor material such as silicon. Various deposition methods such as deposition, CVD, sputtering, and spin coating are used. There can be.

[0135] Next, an insulating layer 128 is formed so as to cover each of the components formed by the above-mentioned steps (FIG. 1). 7(C)). The insulating layer 128 is made of silicon oxide, silicon oxynitride, silicon nitride, or oxide. The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum. By using a low-k material for 128, the electrical resistance of the electrodes and wiring is reduced. This is preferable because it is possible to sufficiently reduce the capacitance caused by the insulating layer 128. A porous insulating layer using these materials may be used. The dielectric constant is lower than that of a non-insulating layer, which further reduces the capacitance caused by electrodes and wiring. The insulating layer 128 is made of an organic insulating material such as polyimide or acrylic. In this embodiment, the insulating layer 128 has a single-layer structure. However, one embodiment of the present invention is not limited thereto. A laminate structure of two or more layers may be used. In this case, for example, a silicon oxynitride layer, a silicon nitride oxide layer, and a silicon oxide layer The laminated structure may be:

[0136] After the insulating layer 128 is formed, the electrode 126 is formed by attaching the metal compound region 12 to the insulating layer 128. It is also possible to form an opening reaching up to the substrate 4 and fill the opening.

[0137] In this case, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is After forming a thinner titanium nitride film, a tungsten film is formed to fill the opening. The titanium film formed by the PVD method is The oxide film (such as a natural oxide film) of the lower electrode (here, the metal compound region 124) is reduced. The titanium nitride film formed after that has the function of reducing the contact resistance with the conductive material. It also has a barrier function that suppresses the diffusion of conductive materials. After forming the rear film, a copper film may be formed by plating.

[0138] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material (see FIG. 17(C)). In this way, a laminate 213a can be formed. The transistor 160 has a feature that it can operate at high speed. By using the transistor as a read transistor, information can be read at high speed. can be done.

[0139] Then, as a process before forming the transistor 162 and the capacitor element 164, the insulating layer 128 Then, a CMP process is performed to expose the upper surfaces of the gate electrode 110 and the electrode 126 (FIG. 17). (D)). The process for exposing the upper surfaces of the gate electrode 110 and the electrode 126 is In addition to the MP process, etching or other processes can be applied. In order to improve the characteristics of the insulating layer 128, it is desirable to make the surface of the insulating layer 128 as flat as possible. It is.

[0140] Before and after each of the above steps, further processes for forming electrodes, wiring, semiconductor layers, insulating layers, etc. may be performed. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. It is also possible to realize a highly integrated semiconductor device by adopting a multi-layer wiring structure.

[0141] In the above steps, the transistor 160 is used as the lower transistor. In the manufacturing process of the lower transistor, the first driving A second driving circuit 202 and a second driving circuit 203 can be fabricated.

[0142] <How to make the upper transistor> Next, a method for manufacturing the upper transistor 162 and the capacitor 164 will be described with reference to FIGS. The following description will be given with reference to FIG.

[0143] First, an oxide semiconductor layer is formed on the gate electrode 110, the electrode 126, the insulating layer 128, etc. The oxide semiconductor layer is processed to form the oxide semiconductor layer 144 (see FIG. 18A). Before forming the oxide semiconductor layer, the gate electrode 110, the electrode 126, and the insulating layer 12 An insulating layer that functions as a base may be provided on the insulating layer 8. The insulating layer may be formed by a sputtering method. It can be formed using PVD methods such as the plasma CVD method, etc. can.

[0144] The material used for the oxide semiconductor layer is the quaternary metal oxide In-Sn-Ga-Zn -O-based materials, ternary metal oxide In-Ga-Zn-O-based materials, In-Sn- Zn-O based materials, In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials, A Materials such as I-Ga-Zn-O, Sn-Al-Zn-O, and binary metal oxides are also used. In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn- Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In-Ga-O Materials based on In-O, Sn-O, Zn-O, etc. can be used. In addition, the above materials may contain SiO2. -Zn-O-based materials are those containing indium (In), gallium (Ga), and zinc (Zn). The composition ratio is not particularly important. It may contain elements other than those.

[0145] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m Materials expressed as (m>0) Here, M is selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and and Mn, or Ga and Co, etc. can be used.

[0146] The thickness of the oxide semiconductor layer is preferably 3 nm or more and 30 nm or less. If the conductor layer is made too thick (for example, more than 50 nm), the transistor will become normally-on. This is because there is a risk that the

[0147] The oxide semiconductor layer is formed by a method that is unlikely to be contaminated with impurities such as hydrogen, water, a hydroxyl group, or a hydride. For example, it can be manufactured by using a sputtering method.

[0148] In this embodiment, the oxide semiconductor layer is formed using an In-Ga-Zn-O oxide target. The film is formed by a sputtering method.

[0149] When using an In-Ga-Zn-O-based material as the oxide semiconductor, the target is For example, the composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio]. An oxide target can be used. The material and composition of the target are not limited to those mentioned above. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] It is also possible to use an oxide target having a composition ratio of:

[0150] In addition, when using an In-Zn-O-based material as an oxide semiconductor, the composition of the target used The composition ratio is In:Zn=50:1-1:2 in atomic ratio (In2O3 In:ZnO=25:1 to 1:4, preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of In2O3:ZnO=10:1 to 1:2), more preferably In:Zn=1 5:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used for forming an In-Zn-O oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0151] The target filling rate is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target with a high filling rate, the oxide semiconductor layer formed is dense. This is because it can be made into a film.

[0152] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. In addition, hydrogen, water, or a hydroxyl group may be added to the oxide semiconductor layer. In order to prevent contamination by impurities such as hydrogen, water, hydroxyl groups, and hydrides, It is preferable to use an atmosphere using a high purity gas that has been removed.

[0153] For example, the oxide semiconductor layer can be formed as follows.

[0154] First, the substrate is held in a deposition chamber maintained under reduced pressure, and the substrate temperature is increased to 200° C. for 5 minutes. 00°C or less, preferably more than 300°C and less than 500°C, more preferably 350°C or more and 400°C or less. Heat to below 50°C.

[0155] Next, while removing the remaining moisture in the film formation chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. A high-purity gas having been removed from the target was introduced into the target chamber, and an oxide semiconductor layer was formed on the substrate using the target. In order to remove the residual moisture in the deposition chamber, a cryopump is used as an exhaust means. Adsorption type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. It is also preferable that the exhaust means is a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen, water, hydroxyl groups, or hydrogen. Impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed. Hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of impurities can be reduced.

[0156] When the substrate temperature during film formation is low (for example, 100°C or lower), the oxide semiconductor contains hydrogen atoms. It is preferable to heat the substrate to the above-mentioned temperatures, since there is a risk of contamination with substances that may be harmful to the substrate. By heating the substrate to the above-mentioned temperature to form the oxide semiconductor layer, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, the oxide semiconductor layer is formed in a state where the substrate is heated to the above-mentioned temperature. By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be eliminated. It is possible to sufficiently reduce the concentration of substances. It is also possible to reduce damage caused by sputtering. This can be done.

[0157] As an example of the deposition conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, The direct current (DC) power supply was 0.5 kW, the substrate temperature was 400°C, and the deposition atmosphere was oxygen (oxygen flow rate If a pulsed DC power source is used, the powdery material generated during film formation is This is preferable because it can reduce particles (also called dust) and make the film thickness distribution uniform.

[0158] Before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. The powder adhering to the surface on which the oxide semiconductor layer is to be formed is removed by performing reverse sputtering to generate plasma. It is preferable to remove the crystalline substances (also called particles or dust). This is a method in which a voltage is applied to the plate, plasma is generated near the substrate, and the surface on the substrate side is modified. Instead of argon, gas such as nitrogen, helium, or oxygen may be used.

[0159] The oxide semiconductor layer is processed by forming a mask of a desired shape on the oxide semiconductor layer and then The above mask can be used as a photoresist. It can be formed by using a method such as lithography. Alternatively, it can be formed by using an inkjet method. Note that the etching of the oxide semiconductor layer may be performed by a dry etching method. Etching or wet etching may be used. Of course, these may be used in combination. good.

[0160] After that, the oxide semiconductor layer 144 may be subjected to heat treatment (first heat treatment). By performing the treatment, the substance including hydrogen atoms contained in the oxide semiconductor layer 144 can be further The structure of the oxide semiconductor layer 144 is adjusted, and defect levels in the energy gap are reduced. The heat treatment temperature is preferably 250°C or higher and 700°C or lower in an inert gas atmosphere. Preferably, the temperature is 450°C or higher and 600°C or lower, or lower than the distortion point of the substrate. Inert gas atmosphere For example, an atmosphere mainly composed of nitrogen or rare gas (helium, neon, argon, etc.) It is preferable to use an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen and rare gases such as helium, neon, and argon introduced into the equipment is 6N (99.9 999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0161] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element, and heating the workpiece in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage or contamination with water or hydrogen.

[0162] The above-mentioned heat treatment has the effect of removing hydrogen, water, etc., so the heat treatment is This heat treatment can also be called hydration treatment or dehydrogenation treatment. It can also be performed before processing the semiconductor layer into islands or after forming the gate insulating layer. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but also multiple times. good.

[0163] Next, a source electrode and a drain electrode (the same layer as this) are formed on the oxide semiconductor layer 144 etc. A conductive layer for forming a semiconductor device (including wiring formed by a method using a semiconductor device) is formed, and the conductive layer is processed to form a semiconductor device. The source or drain electrode 142a and the source or drain electrode 142b are formed. (See FIG. 18(B)).

[0164] The conductive layer can be formed by using a PVD method or a CVD method. The materials used are aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The selected elements or alloys containing the above elements can be used. Magnesium, zirconium, beryllium, neodymium, or scandium, or A combination of these materials may also be used.

[0165] The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single layer structure of a titanium nitride film or titanium film, a single layer structure of an aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, the conductive layer has a tapered shape. A source electrode or drain electrode 142a and a source electrode or drain electrode 142 It has the advantage of being easy to process into b.

[0166] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium zinc oxide alloy (In2O3-ZnO), or a combination of these metal oxide materials It is possible to use one containing silicon or silicon oxide.

[0167] The etching of the conductive layer is performed so that the source or drain electrodes 142a and It is preferable to perform this step so that the end of the source or drain electrode 142b has a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source or drain electrodes 142a and 142b are The gate insulating layer 14 to be formed later is etched to have a tapered shape. This improves the covering property of 6 and prevents discontinuity.

[0168] The channel length (L) of the upper transistor is determined by the source or drain electrode 142a and and the distance between the bottom ends of the source electrode or drain electrode 142b. Exposure for forming a mask used to form a transistor with a channel length (L) of less than 25 nm When applying light, extreme ultraviolet rays with a short wavelength of several nm to several tens of nm are used. It is preferable to use ultraviolet light. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. Therefore, the channel length (L) of the transistor to be formed later is set to 10 nm or more. It is also possible to make it 000nm (1μm) or less, which makes it possible to increase the operating speed of circuits. Furthermore, miniaturization also makes it possible to reduce the power consumption of the semiconductor device.

[0169] Next, a semiconductor layer is formed on the source electrode or drain electrode 142a or 142b. A gate insulating layer 146 is formed so as to be in contact with a part of 144 (see FIG. 18(C)).

[0170] The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 is made of a material such as silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating layer 146 is formed using a material containing a Group 13 element and oxygen. Examples of materials containing a Group 13 element and oxygen include gas oxide. Aluminum oxide, aluminum gallium oxide, etc. can be used. Tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfS i x O y(x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), nitrogen doped hafnium aluminate (Hf Al x O y N z (x>0, y>0, z>0)) and other high-dielectric constant (high-k) materials. The gate insulating layer 146 may be formed to include a single layer structure or a multi-layer structure made of the above-mentioned materials. The thickness of the laminate may be limited, but the thickness of the laminate may be selected from the group consisting of semiconductors, When miniaturizing devices, it is desirable to make them thinner in order to ensure the operation of transistors. For example, when silicon oxide is used, the thickness is set to 1 nm or more and 100 nm or less, preferably 10 The thickness can be from 100 nm to 50 nm.

[0171] The gate insulating layer 146 is formed using a method that does not allow impurities such as hydrogen and water to be mixed in. When the gate insulating layer 146 contains impurities such as hydrogen or water, the oxide semiconductor layer Impurities such as hydrogen and water may enter the oxide semiconductor layer, and oxygen may be released from the oxide semiconductor layer due to impurities such as hydrogen and water. The back channel of the oxide semiconductor layer becomes low-resistance (n-type) due to the extraction of This is because a parasitic channel may be formed. It is preferable to form the film so that it contains as little impurities as possible, such as hydrogen and water. It is preferable to form the film by a sputtering method. It is preferable to use a high-purity gas from which impurities such as hydrogen and water have been removed.

[0172] Note that the oxide semiconductor material used for the oxide semiconductor layer 144 contains a Group 13 element. For this reason, the oxide semiconductor layer 144 is formed using a material containing a Group 13 element and oxygen. When forming the gate insulating layer 146 in contact with the oxide semiconductor layer 144, the state of the interface with the oxide semiconductor layer 144 is This is because the material containing group 13 elements and oxygen and the oxide semiconductor material For example, the oxide semiconductor layer 144 and a gallium oxide By providing the gate insulating layer 146 in contact with the oxide semiconductor layer 144, It is possible to reduce hydrogen pile-up at the interface with the gate insulating layer 16. When aluminum oxide is used as 46, it has the property of being difficult for water to pass through. Therefore, the use of this material is advantageous in terms of preventing water from entering the oxide semiconductor layer 144. It is also preferable to have one.

[0173] As mentioned above, making the gate insulating layer thinner reduces gate leakage caused by the tunnel effect, etc. To solve the gate leakage problem, the gate insulating layer 146 is provided with the above-mentioned high By using a high-k material for the gate insulating layer 146, It is possible to increase the film thickness to suppress gate leakage while maintaining the electrical characteristics. In addition, the films containing high-k materials and silicon oxide, silicon nitride, and silicon oxynitride As a laminated structure with a film containing silicon oxide, silicon nitride, aluminum oxide, etc. good.

[0174] The gate insulating layer 146 preferably contains more oxygen than the stoichiometric composition. For example, when gallium oxide is used as the gate insulating layer 146, the stoichiometric composition ratio is Ga 2O 3+α (0<α<1). In addition, when aluminum oxide is used, , Al2O 3+α can be expressed as (0 < α < 1). Furthermore, when using gallium aluminum oxide, Ga x Al 2-x O 3+α it can be expressed as (0 < x < 2, 0 < α < 1). It can be done.

[0175] Incidentally, after forming the oxide semiconductor layer, after forming the oxide semiconductor layer 144, or after forming the gate insulating layer 1 46, oxygen doping treatment may be performed. Oxygen doping means adding oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) to the bulk. Note that the term "bulk" is used to clarify that oxygen is added not only to the thin film surface but also inside the thin film. Also, "oxygen doping" includes "oxygen plasma doping" in which plasma-oxidized oxygen is added to the bulk. By performing the oxygen doping treatment, the oxygen contained in the oxide semiconductor layer and the gate insulating layer can be made more than the stoichiometric composition ratio. It means adding oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) to the bulk. Note that the term "bulk" is used to clarify that oxygen is added not only to the thin film surface but also inside the thin film. Also, "oxygen doping" includes "oxygen plasma doping" in which plasma-oxidized oxygen is added to the bulk. By performing the oxygen doping treatment, the oxygen contained in the oxide semiconductor layer and the gate insulating layer can be made more than the stoichiometric composition ratio. It means adding oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) to the bulk. Note that the term "bulk" is used to clarify that oxygen is added not only to the thin film surface but also inside the thin film. Also, "oxygen doping" includes "oxygen plasma doping" in which plasma-oxidized oxygen is added to the bulk. By performing the oxygen doping treatment, the oxygen contained in the oxide semiconductor layer and the gate insulating layer can be made more than the stoichiometric composition ratio. It means adding oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) to the bulk. Note that the term "bulk" is used to clarify that oxygen is added not only to the thin film surface but also inside the thin film. Also, "oxygen doping" includes "oxygen plasma doping" in which plasma-oxidized oxygen is added to the bulk. By performing the oxygen doping treatment, the oxygen contained in the oxide semiconductor layer and the gate insulating layer can be made more than the stoichiometric composition ratio. It means adding oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) to the bulk. Note that the term "bulk" is used to clarify that oxygen is added not only to the thin film surface but also inside the thin film. Also, "oxygen doping" includes "oxygen plasma doping" in which plasma-oxidized oxygen is added to the bulk. By performing the oxygen doping treatment, the oxygen contained in the oxide semiconductor layer and the gate insulating layer can be made more than the stoichiometric composition ratio. By performing the oxygen doping treatment, the oxygen contained in the oxide semiconductor layer and the gate insulating layer can be made more than the stoichiometric composition ratio. It can be made more than the stoichiometric composition ratio.

[0176] The oxygen doping treatment is preferably performed using oxygen plasma excited by microwaves (for example, frequency 2.45 GHz) by the ICP (Inductively Coupled Plasma) method. It is preferably performed using oxygen plasma excited by microwaves (for example, frequency 2.45 GHz) by the ICP (Inductively Coupled Plasma) method. It is preferably performed using oxygen plasma excited by microwaves (for example, frequency 2.45 GHz) by the ICP (Inductively Coupled Plasma) method.

[0177] After forming the gate insulating layer 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 0°C or higher and 350°C or lower. For example, heat treatment at 250°C for 1 hour in a nitrogen atmosphere may be performed. It may be performed. By performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced. In addition, when the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 By supplying oxygen to the oxide semiconductor layer 144, oxygen vacancies in the oxide semiconductor layer 144 can be compensated for.

[0178] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be performed. In addition, a second heat treatment may be performed after the first heat treatment, or the first heat treatment may be performed after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It is okay to do so.

[0179] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor layer 144 is highly purified so that it contains as little hydrogen-containing material as possible. can.

[0180] Next, a conductive layer is formed to form the gate electrode (including the wiring formed in the same layer). The conductive layer is then processed to form a gate electrode 148a and a conductive layer 148b (FIG. 18(D)).

[0181] The gate electrode 148a and the conductive layer 148b are made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as the main components The gate electrode 148a and the conductive layer 148b can be formed using an alloy material having the same properties as the gate electrode 148a and the conductive layer 148b. 48b may have a single layer structure or a laminated structure.

[0182] Next, an insulating layer 146 is formed on the gate insulating layer 146, the gate electrode 148a, and the conductive layer 148b. 19A, the insulating layer 150 and the insulating layer 152 are formed. The film 52 can be formed by using a PVD method, a CVD method, or the like. Silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide, oxide The insulating film can be formed using a material containing an inorganic insulating material such as aluminum gallium nitride. The insulating layer 150 and the insulating layer 152 are made of a material having a low dielectric constant or a structure having a low dielectric constant (multiple layers). It is preferable to use a dielectric constant of the insulating layer 150 and the insulating layer 152. By lowering the temperature, the capacitance between wiring and electrodes can be reduced, and the operation speed can be increased. In the present embodiment, the insulating layer 150 and the insulating layer 152 are formed separately. Although the structure is a layer structure, one embodiment of the present invention is not limited to this, and may also be a laminated structure of two or more layers. good.

[0183] Next, a source electrode or drain electrode is formed on the gate insulating layer 146, the insulating layer 150 and the insulating layer 152. An opening 153 is then formed in the opening 153, reaching the source electrode 142b. Alternatively, an electrode 154 is formed in contact with the drain electrode 142b, and the electrode 154 is formed on the insulating layer 152. Then, a wiring 156 is formed in contact with the layer 213b (see FIG. 19B). The opening can be formed by selective etching using a mask or the like. This will be carried out by:

[0184] The electrode 154 is formed by, for example, forming a conductive layer by using a PVD method, a CVD method, or the like in a region including the opening 153. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by removing

[0185] More specifically, for example, a thin titanium film is formed by a PVD method in the area including the opening 153. After forming a thin titanium nitride film by the CVD method, a tongue is inserted into the opening 153. A method for forming a stainless film by the PVD method can be applied. The tantalum film reduces the oxide film (such as the natural oxide film) on the surface on which it is formed, and the lower electrode (in this case, the so The contact resistance between the source electrode and the drain electrode 142b is reduced. The titanium nitride film formed after that has a barrier function to suppress the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, a copper film is formed by plating. You may do so.

[0186] When a part of the conductive layer is removed to form the electrode 154, the surface of the electrode 154 becomes flat. For example, a titanium film or titanium nitride film is formed in the region including the opening 153. In the case where a tungsten film is formed so as to fill the opening 153 after forming a thin film, The subsequent CMP process removes unnecessary tungsten, titanium, titanium nitride, etc. In addition, the flatness of the surface can be improved. By flattening the surface, it is possible to form good electrodes, wiring, insulating layers, and semiconductor layers in the subsequent processes. It is possible to form the following:

[0187] The wiring 156 is formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. After forming a conductive layer using the above, the conductive layer is patterned to form the conductive film. The conductive layer may be made of aluminum, chromium, copper, tantalum, titanium, or molybdenum. The element selected from the group consisting of tungsten, tungsten, and alloys containing the above elements can be used. Yes, manganese, magnesium, zirconium, beryllium, neodymium, and scandium. The source electrode may be made of any one of the following materials or a combination of these materials. Or similar to the drain electrodes 142a, 142b, etc.

[0188] As a result, a second transistor including the transistor 160, the transistor 162, and the capacitor 164 is formed. A single laminate 210a is completed (see FIG. 19(B)).

[0189] Next, an insulating layer 158 is formed on the first laminate 210a, and a second laminate is formed on the insulating layer 158. The second stacked body 210b is formed (see FIG. 1). The transistor 170 includes a transistor 172 and a capacitance element 174. The method for manufacturing the transistor 172 and the capacitor 174 is the same as that for manufacturing the transistor 162 and the capacitor The method for producing the second laminate 21 is the same as that for the laminate 164, so the details will be omitted. When a third or fourth laminate is formed on the first insulating layer, the third or fourth laminate is formed on the second insulating layer. transistor 170, transistor 172 and capacitive element 174. The element may be formed.

[0190] The manufacturing process of a transistor using an oxide semiconductor layer does not require high-temperature treatment. This can be done without affecting other devices or wiring. The manufacturing process of the transistors described above uses semiconductor materials other than oxide semiconductors (e.g., silicon). The number of manufacturing steps is smaller than that of a transistor using an oxide semiconductor layer. By using the transistor laminate as the second laminate or the third laminate, the manufacturing cost can be reduced. It can be reduced.

[0191] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0192] (Embodiment 2) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 20. In this embodiment, Telephones, mobile phone devices, portable information terminals (including portable game consoles, audio playback devices, etc.) (including), digital cameras, digital video cameras, electronic paper, television equipment (television The above-described semiconductor device is applied to electronic devices such as a television receiver. This section explains what happens when

[0193] FIG. 20A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703 and the keyboard 704 are included. A memory circuit is provided inside at least one of the above-mentioned memory circuits. Therefore, data can be written and read at high speed. A notebook-type personal computer that can store data for a long period of time and consumes a sufficiently low amount of power. The computer is realized.

[0194] FIG. 20B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external The terminal 715 and the operation button 714 are provided. The main body 711 is equipped with a stylus 712 for operating the terminal. The memory circuit is provided with the semiconductor device described in the above embodiment. Therefore, information can be written and read at high speed, memory can be retained for a long period of time, and consumption is low. A portable information terminal with sufficiently reduced power consumption is realized.

[0195] FIG. 20C shows an electronic book 720 that uses electronic paper. The display device 720 is configured with two housings, namely, housing 721 and housing 723. The housing 721 and housing 723 each include a display unit 7 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the housing 7 via the shaft portion 737, and can be opened and closed around the shaft portion 737. 21 includes a power switch 731, operation keys 733, a speaker 735, etc. A memory circuit is provided inside at least one of the body 721 and the housing 723. The semiconductor device described in the above embodiment is provided in the circuit. It is also possible to read out the data at high speed, store the data for a long period of time, and consume a sufficiently low amount of power. E-books become a reality.

[0196] FIG. 20D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. It can be folded up and folded up, making it possible to make it compact and suitable for carrying. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, and an operation Key 745, pointing device 746, camera lens 747, external connection terminal 74 The housing 740 also includes a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. Also, the antenna is built into the housing 741. A memory circuit is provided inside at least one of the housings 740 and 741. The memory circuit is provided with the semiconductor device described in the above embodiment. It has high speed writing and reading of information, long-term memory retention, and low power consumption. Thus, a mobile phone with reduced noise can be realized.

[0197] FIG. 20E shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. The device is made up of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device described in the above embodiment is provided in the inside of 761. High speed writing and reading, long term memory retention, and low power consumption Thus, a digital camera having such a configuration is realized.

[0198] FIG. 20F shows a television device 770 including a housing 771, a display unit 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. The housing 771 and the remote control 780 can be used. The machine 780 is provided with a memory circuit therein, and the memory circuit includes the memory circuit described in the previous embodiment. Therefore, writing and reading of information is performed at high speed, A television device capable of long-term memory retention and sufficiently reduced power consumption is realized. can be.

[0199] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This makes it possible to realize electronic devices with reduced power consumption. [Explanation of symbols]

[0200] 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Gate electrode 116 Channel formation region 120 Impurity region 122 Metal layer 124 Metal compound area 126 electrode 128 Insulating Layer 142a Source electrode or drain electrode 142b Source or drain electrode 144 Oxide semiconductor layer 146 Gate Insulation Layer 148a Gate electrode 148b Conductive layer 150 Insulating layer 152 Insulating layer 153 Aperture 154 Electrode 156 Wiring 158 Insulating Layer 160 Transistors 162 Transistor 164 Capacitive element 170 Transistors 172 Transistors 174 Capacitive element 201 Memory cell array 202 First driving circuit 203 Second driving circuit 210a First laminate 210b Second laminate 210c Third laminate 211a Memory cell array 211b Memory cell array 211c Memory Cell Array 212a Memory cell 212b Memory cell 212c Memory Cell 213a Laminate 213b Laminate 213c Laminated body 213d Laminate 221 Selector 221a Selector 221b Selector 221c Selector 222 Circuit 223 Low Decoder 231 Selector 231a Selector 231b Selector 231c Selector 232 circuit group 232a circuit group 232b Circuit group 233 Column Decoder 234 circuit group 235 circuit group 236 Registers 237 Circuit 238 Circuit 239 Register 701 Case 702 Case 703 Display section 704 Keyboard 711 Main unit 712 Stylus 713 Display section 714 Operation button 715 External Interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power Switch 733 Operation Key 735 Speaker 737 Shaft 740 Case 741 Case 742 Display Panel 743 Speakers 744 Microphone 745 Operation Key 746 Pointing Device 747 Camera Lenses 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Device

Claims

[Claim 1] A driving circuit and a circuit controlled by the driving circuit, a first transistor disposed in the driver circuit and including a first silicon in a channel formation region; and a second transistor including a first oxide semiconductor in a channel formation region; a third transistor which is disposed in the circuit and has a second silicon in a channel formation region, a fourth transistor which has a second oxide semiconductor in a channel formation region, a fifth transistor which has the third oxide semiconductor in a channel formation region, and a sixth transistor which has the fifth oxide semiconductor in a channel formation region; the second silicon is stacked on the second oxide semiconductor via an insulating layer; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the third transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the sixth transistor; the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fifth transistor.

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