Semiconductor storage device

Abstract

To further increase storage capacity of a DRAM.SOLUTION: A semiconductor storage device includes a driver circuit having a part of a substrate including single-crystal semiconductor material, a multilayer wire layer provided on the driver circuit, and a memory cell array layer provided on the multilayer wire layer. In other words, in the semiconductor storage device, the driver circuit and the memory cell array are provided overlapping with each other. This can increase degree of integration of the semiconductor storage device, as compared with the case in which the driver circuit and the memory cell array are provided on the same plane of the substrate including the single-crystal semiconductor material.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a channel region formed of an oxide semiconductor. The present invention relates to a semiconductor memory device having memory cells each provided with a transistor that is configured to perform a write operation. [Background technology]

[0002] In recent years, oxides that combine high mobility and uniform device characteristics have been developed as materials for transistors. Metal oxides that exhibit semiconductor properties, known as compound semiconductors, are attracting attention. Indium oxide is used in a variety of applications. For example, indium oxide is used to form the pixels in liquid crystal displays. Metal oxides that exhibit semiconducting properties are used as electrode materials. These include tungsten oxide, tin oxide, indium oxide, and zinc oxide, and have semiconductor properties like these. A transistor using the above-mentioned metal oxide in a channel region is already known (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0004] Semiconductor memory devices include DRAM, SRAM, which are classified as volatile memory, and non-volatile Mask ROM, EPROM, EEPROM, flash memory, which are classified as nonvolatile memory, There are many types of memory that are formed using single crystal semiconductor substrates. Among the above mentioned memory devices, DRAM is a type of memory that uses transistors and capacitors. It has a simple structure in which memory cells are composed of capacitors, and is superior to other memory devices such as SRAM. Therefore, compared to other memory devices, the number of semiconductor elements required to configure memory cells is small. This allows for an increased storage capacity per unit area, thereby achieving lower costs.

[0005] As mentioned above, DRAM is suitable for large memory capacity, but it is necessary to suppress the increase in chip size. However, to realize a more highly integrated circuit, the size of the memory per unit area must be increased, just like other memory devices. To achieve this, each memory cell must have a higher memory capacity to hold a charge. It is necessary to reduce the area of ​​the capacitor provided in the cell and to reduce the area of ​​each memory cell. do not have.

[0006] For example, in order to reduce the area of ​​each memory cell, a deep trench is formed in a semiconductor substrate. A technique for providing a capacitor in the trench (a so-called trench type capacitor) or a technique for directly connecting the semiconductor substrate A technology that provides a long capacitor in the upward or almost vertical direction (so-called stacked capacitor) Specifically, capacitors with an aspect ratio of 50 or more have been developed. In addition, by providing multiple hierarchical wiring layers on the semiconductor substrate, Therefore, the electrical connections of the enormous number of semiconductor elements provided on the highly integrated semiconductor substrate are Technologies that enable interconnection (so-called multi-layer wiring technology) are also being developed.

[0007] Therefore, one aspect of the present invention aims to further increase the storage capacity of DRAM. This is the target. [Means for solving the problem]

[0008] A semiconductor memory device according to one embodiment of the present invention includes a driving element having a substrate including a single crystal semiconductor material. The gist of the invention is that a memory cell array is provided on a circuit via a multi-layer wiring layer.

[0009] Specifically, one embodiment of the present invention is a driver circuit including a part of a single crystal semiconductor substrate. a multilayer wiring layer including a plurality of wirings made of copper or a copper alloy provided on the wiring line; A memory cell array including a plurality of memory cells arranged in a matrix on the and a layer, wherein each of the driving circuit and the plurality of memory cells is made of a plurality of copper or copper alloy. The memory cells are electrically connected to each other through at least one of the wirings. A transistor in which the channel region is formed by a semiconductor and one of the electrodes is a capacitor electrically connected to one of the source and the drain. It is. Effect of the Invention

[0010] A semiconductor memory device according to one embodiment of the present invention includes a substrate including a single crystal semiconductor material. It is possible to provide the driver circuit and the memory cell array in an overlapping manner. Compared to a case where a drive circuit and a memory cell array are provided on the same plane on a substrate containing a crystalline semiconductor material. As a result, it becomes possible to increase the degree of integration of the semiconductor memory device. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a semiconductor memory device. [Diagram 2] 1A and 1B are diagrams illustrating examples of the configuration of a transistor included in a driver circuit. [Diagram 3]1A to 1H illustrate an example of a method for manufacturing a transistor. [Figure 4] FIG. 2 is a diagram showing a configuration example of a wiring layer. [Diagram 5] 1A to 1H are diagrams showing an example of a method for producing a wiring layer. [Figure 6] FIG. 2 shows an example of the configuration of a memory cell. [Figure 7] 1A to 1H illustrate an example of a method for manufacturing a transistor included in a memory cell. [Figure 8] FIG. 1 is a block diagram showing an example of the configuration of a microprocessor. [Figure 9] 1A to 1C are diagrams illustrating specific examples of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0013] First, a configuration example of a semiconductor memory device according to one embodiment of the present invention will be described with reference to FIGS. .

[0014] <Configuration example of semiconductor memory device> FIG. 1 is a diagram showing a configuration example of a semiconductor memory device. A driving circuit 100 having a portion of a substrate 10 including a crystalline semiconductor material, and a A multi-layer wiring layer 20 is provided on the multi-layer wiring layer 20 and is arranged in a matrix. and a memory cell array layer 30 including a plurality of memory cells 300.

[0015] The driving circuit 100 is made up of a plurality of semiconductors formed using a substrate 10 including a single crystal semiconductor material. Then, data is stored in each of the plurality of memory cells 300. It has the function of writing and reading.

[0016] The multi-layer wiring layer 20 includes a plurality of wirings each having a plane on which a plurality of wirings 200 are provided. The semiconductor elements included in the driving circuit 100 are and a function for electrically connecting the driving circuit 100 and each of the plurality of memory cells 300. In the multi-layer wiring layer 20, the plane on which the multiple wirings 200 are provided is a tiered structure. Specifically, a plurality of insulating layers, each having a wiring 200 embedded therein, are laminated. However, the wirings 200 provided on different planes are provided penetrating an insulating layer. The contact plug 201 is electrically connected to the semiconductor substrate 200. Although a multi-layer wiring layer 20 constituted by two wiring layers 20a and 20b is illustrated, The multilayer wiring layer 20 according to the present embodiment is not limited to two layers, but may be composed of three or more layers. It is also possible to use one or more layers of the multi-layer wiring layer 20 to connect bit lines of memory cells. It may be formed.

[0017] Each of the memory cells 300 includes a transistor 301 and a transistor A capacitor 302 is electrically connected to one of the source and drain of the transistor 301. do.

[0018] <Configuration example of the driving circuit 100> In the following, the driving circuit 100 is formed using a substrate 10 including a single crystal semiconductor material. An example of the transistor will be described with reference to FIG.

[0019] The transistor 160 shown in FIG. 2 is a channel formed on a substrate 10 that includes a single crystal semiconductor material. A pair of impurity regions 114 are provided on either side of the channel region 116. a, 114b, and a pair of high concentration impurity regions 120a, 120b (collectively referred to as "non-inorganic"). A gate insulating film 108 is provided on the channel region 116. A gate electrode 110 provided on the gate insulating film 108 is electrically connected to the impurity region 114a. A source electrode 130a electrically connected to the impurity region 114b and a drain electrode 130 b.

[0020] Sidewall insulating layers 118 are provided on the sides of the gate electrode 110. In addition, in the region of the substrate 10 including the single crystal semiconductor material that does not overlap with the sidewall insulating layer 118, In the semiconductor device 1, a pair of high concentration impurity regions 120a and 120b are present. A pair of metal compound regions 124a and 124b are present on the substrate 120a and 120b. An element isolation insulating layer 106 is provided on the transistor 10 so as to surround the transistor 160. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided to cover the transistor 160. The source electrode 130a is formed in an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. The drain electrode 130b is electrically connected to the metal compound region 124a through a hole. Through the openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128, the metal compound region 12 4b. That is, the source electrode 130a is electrically connected to the metal compound region 124 a, and is electrically connected to the high concentration impurity region 120a and the impurity region 114a. The drain electrode 130b is connected to the high concentration impurity region 120b via the metal compound region 124b. and the impurity region 114b.

[0021] <Example of how to fabricate a transistor> Next, an example of a method for manufacturing the transistor 160 will be described with reference to FIGS. The method for fabricating the transistor 160 is not limited to the following method, and the transistor 160 can be fabricated by known techniques.

[0022] First, a substrate 10 containing a single crystal semiconductor material is prepared (see FIG. 3(A)). The substrate 10 may include silicon, silicon carbide, silicon germanium, or arsenic. A single crystal semiconductor substrate such as gallium nitride, and an SOI substrate in which the single crystal layer is provided on an insulating layer Generally, an "SOI substrate" is a substrate that has a silicon on an insulating surface. The term "substrate" refers to a substrate having a semiconductor layer formed thereon. In this specification, however, the term "substrate" refers to a substrate having a silicon layer formed on an insulating surface. The term also includes a substrate having a semiconductor layer made of a material other than silicon. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The semiconductor device also includes a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. In this embodiment, the substrate 10 including a single crystal semiconductor material is a single crystal silicon substrate. Here is an example of using

[0023] A protective layer 102 is formed on the substrate 10 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a semiconductor device, an impurity that imparts n-type conductivity is The substrate 10 may be doped with an element or an impurity element that imparts p-type conductivity. In the case of n-type semiconductors, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron, aluminum, and Examples of the usable materials include aluminum, gallium, etc.

[0024] Next, etching is performed using the protective layer 102 as a mask. The part of the substrate 10 in the uncovered area (exposed area) is removed. The conductor region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0025] Next, an insulating layer is formed so as to cover the semiconductor region 104, and an insulating layer is formed in a region overlapping the semiconductor region 104. The insulating layer in the region is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer is removed by chemical mechanical polishing (CMP). There are processes such as polishing (polishing) and etching, but which one is used? After the semiconductor region 104 is formed or after the element isolation insulating layer 106 is formed, In this case, the protective layer 102 is removed.

[0026] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0027] The insulating layer will later become the gate insulating film, and is formed using CVD, sputtering, etc. Obtained silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or a multilayer structure of a film containing tungsten oxide, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. This is done using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, etc. The dielectric constant and thickness of the insulating layer can be determined according to the channel length of the transistor to be fabricated. It is determined depending on the application, but it can be, for example, 1 nm or more and 100 nm or less.

[0028] The layer containing the conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The insulating layer can be formed using a semiconductor material such as polycrystalline silicon, which has high electrical conductivity. The method of formation is not particularly limited, and examples of the method include deposition, C Various film formation methods such as the VD method, the sputtering method, and the spin coating method can be used. Note that an example in which the layer containing a conductive material is formed using a metal material will be described here. This shall be done.

[0029] Thereafter, the insulating layer and the layer containing a conductive material are selectively etched to form a gate insulating film 10. 8. The gate electrode 110 is formed (see FIG. 3(C)).

[0030] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Boron (B), phosphorus (P), arsenic (As), etc. are added to the semiconductor region 104 to form a shallow junction depth. A pair of impurity regions 114a and 114b having the same length are formed (see FIG. 3C). By forming the impurity regions 114a and 114b, the semiconductor region 104 under the gate insulating film 108 A channel region 116 is formed in the portion (see FIG. 3(C)). The concentration of the fluorine atom can be appropriately set, but when the semiconductor element is highly miniaturized, In this embodiment, after the insulating layer 112 is formed, a pair of insulators is formed. The process of forming the pure regions 114a and 114b is adopted, but the pair of impurity regions 114 Alternatively, the step of forming the insulating layer 112 may be performed after forming the layers 114a and 114b.

[0031] Next, the sidewall insulating layer 118 is formed (see FIG. 3(D)). The edge layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying anisotropic By applying a high-speed etching process, it can be formed in a self-aligned manner. At that time, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and a pair of impurities. It is preferable that the upper surfaces of the object regions 114a and 114b are partially exposed.

[0032] Next, the gate electrode 110, the pair of impurity regions 114a and 114b, and the sidewall insulating An insulating layer is formed to cover the layer 118 and the like. Boron (B), phosphorus (P), arsenic (As), etc. were added to a part of 4b to form a pair of high-concentration In this way, a pair of impurity regions 120a and 120b are formed (see FIG. 3(E)). Impurities of the opposite conductivity type are implanted outside the high concentration impurity regions 120a and 120b to form a so-called After that, the insulating layer is removed, and the gate electrode 110 and the side A gold layer is formed to cover the wall insulating layer 118, the pair of high concentration impurity regions 120a, 120b, etc. The metal layer 122 is formed (see FIG. 3(E)). The metal layer 122 is formed by vacuum deposition or sputtering. The metal layer 122 can be formed by various film forming methods such as a coating method, a spin coating method, etc. is a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to form a low-resistance metal compound. It is preferable to use a metal material such as titanium or tantalum. Examples of metals include tantalum, tungsten, nickel, cobalt, and platinum.

[0033] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A pair of metal compound regions 124a, 124b are in contact with the high concentration impurity regions 120a, 120b. The gate electrode 110 is formed of polycrystalline silicon or the like. When using the metal compound layer 122, the portion of the gate electrode 110 in contact with the metal layer 122 also has a metal compound region. A region will be formed.

[0034] As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but chemical reactions involving the formation of metal compounds are preferred. In order to improve the controllability of the reaction, it is necessary to use a method that allows for very short heat treatment times. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region having a sufficiently high electrical conductivity. By doing so, the electrical resistance can be sufficiently reduced, and the element characteristics can be improved. After metal compound regions 124a, 124b are formed, metal layer 122 is removed.

[0035] Next, an interlayer insulating layer 126 and an interlayer insulating film 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, oxide The insulating layer can be formed using an inorganic insulating material such as tantalum. In addition, the insulating layer can be formed using a material such as polyimide or acrylic. It is also possible to form the interlayer insulating layer 12 using an organic insulating material such as SiO 2 . 6 and the interlayer insulating layer 128, the configuration of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, its surface is planarized by CMP, etching, or the like. It is desirable to make it flat.

[0036] Thereafter, openings are formed in the interlayer insulating layer, the openings reaching the pair of metal compound regions 124a and 124b. An opening is formed, and a source electrode 130a and a drain electrode 130b are formed in the opening (FIG. 3). The source electrode 130a and the drain electrode 130b are, for example, in a region including an opening. After forming a conductive layer in the area using PVD or CVD, etching and CMP are performed. The insulating layer 11 can be formed by removing a part of the conductive layer using the above-mentioned method.

[0037] When forming the source electrode 130a and the drain electrode 130b, the surfaces of the electrodes must be flat. For example, a titanium film or titanium nitride film is applied to the area including the opening. When a tungsten film is formed to fill the opening after a thin silicon film is formed, The CMP after the step removes unnecessary tungsten, titanium, titanium nitride, etc. In this way, the flatness of the surface of the source electrode 130a and the drain electrode 130b can be improved. By planarizing the surface including the rain electrode 130b, a good electrode can be obtained in a later process. It becomes possible to form wiring, insulating layers, semiconductor layers, and the like.

[0038] As a result of the above, a transistor 160 is formed using the substrate 10 containing a single crystal semiconductor material. do.

[0039] <Configuration example of wiring layers 20a, 20b> An example of the configuration of the wiring layers 20a and 20b will be described below with reference to FIG.

[0040] The wiring layer 20a shown in FIG. 4 is provided in an opening of the insulating layer 202. and an insulating layer 203 provided on the insulating layer 202. , and wirings 200a and 200b provided in the openings of the insulating layer 203. The wiring layer 20b has a similar configuration to the wiring layer 20a.

[0041] Note that the insulating layer 202 is provided over the transistor 160 shown in FIG. The contact plug 201a is connected to the source electrode 130a of the transistor 160 and the wiring 200a, and the contact plug 201b is connected to the drain of the transistor 160. The conductive layer 130 is connected to the first electrode 130b and the wiring 200b.

[0042] <Example of a method for producing the wiring layers 20a and 20b> Next, an example of a method for producing the wiring layers 20a and 20b will be described with reference to FIG.

[0043] First, an insulating layer 202 is formed over the transistor 160 (see FIG. 5A). The insulating layer 202 is made of silicon oxide, nitride oxide, or the like. A single-layer structure or a multi-layer structure of a film containing an inorganic insulating material such as silicon or silicon nitride is suitable. For example, a stack of a silicon nitride film and a silicon oxide film can be used as the insulating layer 202. In particular, when the wirings 200a and 200b to be formed subsequently contain copper, If present, the thickness should be between 5 nm and 50 nm to prevent copper from diffusing into the transistor 160. A layered structure in which a silicon nitride film is formed and a silicon oxide film or the like of a required thickness is deposited on top of the silicon nitride film. The insulating layer 202 is preferably formed by a CVD method or a sputtering method. The method of measuring the thickness of the sample can be applied.

[0044] Next, a resist mask is formed over the insulating layer 202 by photolithography or the like. The insulating layer 202 is etched using the resist mask to form openings 204a and 20 In addition, when a photolithography method is used, an insulating film is formed in advance. It is preferable to form an anti-reflection film on the edge layer 202. During the exposure process of the lithography method, the conductive layer of the transistor 160 (the source electrode 130a It is possible to suppress the reflection of light by the insulating layer 130b, the drain electrode 130b, etc. It is possible to suppress the decrease in resolution in the photolithography method. The antireflection film can be appropriately selected depending on the material of the resist. For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and etching solution may be appropriately selected depending on the material to be etched. You can choose.

[0045] Next, a layer 20 containing a conductive material is formed so as to fill at least the openings 204a and 204b. As the layer 205 containing a conductive material, aluminum, titanium, Metals such as tantalum, tungsten, or their nitrides, or A film containing an alloy of these materials can be used. It is also possible to apply a laminated structure of these films. For example, a titanium film, a titanium nitride film, A stack of a tungsten film and a conductive material may be applied as the layer 205 containing a conductive material. In addition, if the wirings 200a and 200b to be formed later contain copper, the copper may be used as a transistor. The layer 205 containing the conductive material is formed of a nitride layer having a thickness of 5 nm to 50 nm so as not to diffuse into the capacitor 160. It is preferable to have a layer of titanium. The method for producing the layer 205 containing a conductive material is CV. D method, sputtering method, or the like can be applied.

[0046] Next, a film formed on the insulating layer 202 was removed so that at least the upper surface of the insulating layer 202 was exposed. The layer 205 containing the conductive material is removed by CMP (see FIG. 5(D)). Contact plugs 201a and 201b are formed.

[0047] Next, an insulating layer 203 is formed on the insulating layer 202 and the contact plugs 201a and 201b. As the insulating layer 203, silicon oxide, silicon nitride oxide, or nitride Films containing inorganic insulating materials such as silicon hydride, or organic silanes such as alkylsilanes A single layer or multilayer structure of insulating materials such as silicon resin (so-called SiOC film) For example, a laminate of a SiOC film and a silicon oxide film may be used as the insulating layer 20. The insulating layer 203 can be formed by a CVD method, a sintering method, or the like. A sputtering method, a spin coating method, or the like can be used.

[0048] Next, a resist mask is formed over the insulating layer 203 by photolithography or the like. At least the insulating layer 203 is etched using the resist mask to form a groove 206a , 206b are formed (see FIG. 5(F)). The insulating layer 203 is penetrated so that the upper surfaces of the contact plugs 201a and 201b are exposed. For example, the grooves 206a and 206b can be formed in a desired shape by controlling the processing time. In addition, when the photolithography method is used, the insulating layer is formed in advance as described above. It is preferable to form an anti-reflection film on the substrate 203. Etching (especially reactive ion etching) It is preferable to use

[0049] Next, a layer 207 containing a conductive material is formed so as to fill at least the grooves 206a and 206b. As the layer 207 containing a conductive material, copper, aluminum, titanium, etc. Metals such as tantalum, tungsten, or their nitrides, or A film containing an alloy of these materials can be used. It is also possible to apply a laminated structure of these films. For example, a tantalum nitride film and a copper film A stack of films can be applied as the layer 207 containing a conductive material. The layer 207 can be formed by a CVD method, a sputtering method, or a combination of these methods. A method in which a seed layer is formed by a method using a plating method and then electrolytic plating is performed can be applied.

[0050] As the layer 207 containing a conductive material, a wiring containing a film made of copper or a copper alloy is used. It is preferable that the wiring resistance is reduced. A tantalum nitride layer having a thickness of 5 nm to 50 nm is formed by a CVD method, and then a tantalum nitride layer having a thickness of 5 nm to 5 A first copper layer of 0 nm is formed by sputtering or the like. Then, A second copper layer is deposited by a solution plating method to obtain a layer 207 containing a conductive material. The tantalum nitride layer prevents copper from diffusing downward and also provides a tight seal with the insulating layer 203. It is used to improve adhesion, and the first copper layer acts as a seed for the second copper layer.

[0051] Next, a film formed on the insulating layer 203 was formed so that at least the upper surface of the insulating layer 203 was exposed. The layer 207 containing the conductive material is removed by CMP (see FIG. 5(H)). Lines 200a, 200b are formed.

[0052] In this manner, the wiring layer 20a is formed. The wiring layer 20b is also formed by the same process. It can be achieved.

[0053] <Configuration example of memory cell 300> An example of the configuration of the memory cell 300 will be described below with reference to FIG.

[0054] The memory cell 300 shown in FIG. 6 includes a transistor 301 and a transistor 302 having one electrode connected to the transistor 303. A capacitor 302 is electrically connected to one of the source and drain of the transistor 301. Furthermore, the transistor 301 includes a pair of conductive materials that function as a source or a drain. The layers 3011 and 3013 are made of a conductive material, and the layer 3014 is made of a conductive material that functions as a gate. The capacitor 302 has an oxide semiconductor layer 3012 which forms a capacitor region. A layer 3013 including a conductive material serving as the first electrode and a layer 3014 including a conductive material serving as the other electrode. Note that the conductive material-containing layer 3014 and the oxide semiconductor layer 301 2, and between the layer 3013 containing a conductive material and the layer 3016 containing a conductive material. 015 is provided.

[0055] The layer 3011 containing a conductive material is provided in an opening in the insulating layer 303. The edge layer 303 is an insulating layer provided on the wiring layer 20b shown in FIG. 1 and contains a conductive material. The layer 3011 is connected to the wiring 200c included in the wiring layer 20b.

[0056] In addition, in FIG. 6, a memory cell 3000 adjacent to the memory cell 300 and a memory A memory cell adjacent to the cell 300 and the memory cell 3000 and located in the vertical direction of the paper. Also shown is a layer 3020 comprising a conductive material that functions as a gate of a transistor in In FIG. 6, the layers 3014 and 3020 containing a conductive material are used as word lines of the memory cells. and the wiring 200c functions as a bit line.

[0057] <Example of a method for manufacturing the memory cell 300> Next, an example of a method for manufacturing the memory cell 300 will be described with reference to FIG.

[0058] First, an insulating layer 303 is formed on the wiring layer 20b (see FIG. 7(A)). The insulating layer 303 may be made of silicon oxide, silicon nitride oxide, or nitride. Inorganic insulating materials such as silicon oxide, hafnium oxide, aluminum oxide, and tantalum oxide A single layer structure or a laminate structure of a film containing an organic insulating material such as polyimide or acrylic. For example, a silicon nitride film and a silicon oxide film may be laminated to form an insulating film. The insulating layer 303 can be formed by a method such as CV D method, sputtering method, spin coating method, or the like can be applied.

[0059] Next, a resist mask is formed over the insulating layer 303 by photolithography or the like. The insulating layer 303 is etched using the resist mask to form an opening. In the case of performing photolithography, an anti-reflection layer is formed on the insulating layer 303 in advance as described above. It is preferable to form a film on the insulating layer. The etching is preferably performed by dry etching. However, wet etching may also be used. The etching temperature can be appropriately selected depending on the material to be etched.

[0060] Next, a conductive material is applied to at least the openings in the insulating layer 303 so as to fill them. A layer 3001 containing a conductive material is formed (see FIG. 7B). metals such as nium, titanium, tantalum, or tungsten, or nitrides thereof; Alternatively, a film containing an alloy of these may be used. It is also possible to apply a laminated structure of these films as the first embodiment. The layer 3001 may be formed by a CVD method, a sputtering method, or the like. can.

[0061] Next, a film formed on the insulating layer 303 was formed so that at least the upper surface of the insulating layer 303 was exposed. The layer 3001 containing the conductive material is removed by CMP (see FIG. 7(C)). A layer 3011 or the like including a conductive material that functions as a source or drain of the memory cell 300 is formed.

[0062] Next, an oxide semiconductor layer is formed over the insulating layer 303 and the layer containing a conductive material 3011. The oxide semiconductor is an In-Sn-Ga-Zn-O oxide semiconductor, which is a quaternary metal oxide. In-Ga-Zn-O oxide semiconductors and In-Sn-Zn -O-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based oxide semiconductors oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors In-Zn-O oxide semiconductors and Sn-Zn-O oxide semiconductors are binary metal oxides. Conductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg-O In-Mg-O oxide semiconductors, In-Ga-O oxide semiconductors, single-component In-O oxide semiconductors, Sn-O oxide semiconductors, Zn-O oxide semiconductors, In this specification, for example, In-Sn- Ga-Zn-O oxide semiconductors are semiconductors that are made of indium (In), tin (Sn), and gallium (Ga ), zinc (Zn), and its stoichiometric composition ratio is In addition, the oxide semiconductor may contain silicon.

[0063] The oxide semiconductor layer is preferably one in which impurities such as hydrogen, water, a hydroxyl group, or a hydride are not easily mixed. The oxide semiconductor layer is preferably formed by a sputtering method, for example. The deposition atmosphere is a rare gas (typically argon) atmosphere, oxygen The heating may be performed in an atmosphere of oxygen or a mixture of oxygen and rare gas. In order to prevent the inclusion of hydrogen, water, hydroxyl groups, hydrides, etc. in the layer, It is preferable to use a high-purity gas atmosphere from which impurities such as ions have been sufficiently removed.

[0064] Note that the oxide semiconductor layer may be amorphous. It is preferable to use an oxide semiconductor layer having crystallinity as the insulating film. By using a dielectric layer, the reliability (gate bias stress resistance) of the transistor is improved. Because it is possible.

[0065] The oxide semiconductor layer having crystallinity is ideally single-crystal. C-axis aligned crystal (also called CAAC) It is preferable that the oxide semiconductor layer has a crystal having a c-axis orientation. It refers to a hexagonal crystal in which the c-axis is perpendicular or nearly perpendicular to the surface (here, the upper surface of the insulating layer 303). .

[0066] The oxide semiconductor layer containing CAAC can also be formed by a sputtering method. In order to obtain an oxide semiconductor layer containing CAAC by a sputtering method, In the initial stage of deposition, hexagonal crystals are formed, and the crystals are used as seeds to form the It is essential to ensure that the crystal grows. To achieve this, the distance between the target and the substrate must be The substrate heating temperature is set to 100°C to 500°C. °C, preferably 200°C to 400°C, and more preferably 250°C to 300°C. In addition, the deposited oxide semiconductor is heated at a temperature higher than the substrate heating temperature during film formation. By heat treating the layer, micro defects in the film and defects at the layer interface can be repaired. can be done.

[0067] The oxide semiconductor layer containing CAAC is highly purified and has fewer defects due to oxygen vacancies. By having crystals oriented along the c-axis, it becomes easier to control the valence electrons to a weak p-type.

[0068] Next, a resist is formed by photolithography or the like, and the resist is used as a mask. The oxide semiconductor layer is then etched to form an oxide semiconductor layer 3012 or the like. See FIG. 7(D). It is preferable to use dry etching for this etching. In addition, the etching gas and etching solution are appropriately selected according to the material to be etched. It is possible.

[0069] Next, the oxide semiconductor layer 3012 may be subjected to heat treatment. Therefore, the substance containing hydrogen atoms in the oxide semiconductor layer 3012 is further removed, and the oxide semiconductor layer 3012 is oxidized. The structure of the compound semiconductor layer 3012 can be adjusted to reduce the defect level in the energy gap. The heat treatment temperature is 250°C or higher and 700°C or lower, preferably 40°C or lower, in an inert gas atmosphere. The temperature is between 50℃ and 600℃, or below the distortion point of the substrate. The inert gas atmosphere is An atmosphere mainly composed of nitrogen or rare gas (helium, neon, argon, etc.), It is desirable to use an atmosphere that does not contain water, hydrogen, etc. For example, The purity of rare gases such as nitrogen, helium, neon, and argon is 6N (99.9999%). or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less) and preferably 0.1 ppm or less).

[0070] By carrying out this heat treatment, impurities are reduced and the semiconductor becomes i-type (intrinsic semiconductor) or i-type only. By forming an oxide semiconductor film with nearly no gate charge, a transistor with extremely excellent characteristics can be realized. It is possible.

[0071] Next, the insulating layer 3002 is formed over the insulating layer 303 and the oxide semiconductor layer 3012 (FIG. 7 Note that the insulating layer 3002 serves as the gate insulator for the transistor 301 to be formed later. The insulating layer 3002 functions as an insulating film. A single layer structure of a film containing inorganic insulating materials such as hafnium, aluminum oxide, and tantalum oxide, or A method for forming the insulating layer may be a sputtering method. A method such as a tarring method can be applied.

[0072] Next, a layer containing a conductive material is formed over the insulating layer 3002. is made of metals such as aluminum, titanium, tantalum, or tungsten, or It is possible to apply a film containing an indium oxide or an alloy thereof. oxides such as indium, tungsten oxide, molybdenum oxide, indium nitride, zinc nitride It is also possible to use nitrides such as those mentioned above as the layer containing the conductive material. A laminated structure of films can also be applied. For this purpose, a CVD method, a sputtering method, or the like can be applied.

[0073] Next, a resist mask is formed on the layer containing the conductive material by photolithography or the like. The resist mask is used to form a conductive layer, and the conductive layer is etched. Layers 3014, 3020, etc., including the material are formed (see FIG. 7(F)). For this purpose, dry etching is preferably used, but wet etching may also be used. In addition, the etching gas and etching solution are appropriately selected according to the material to be etched. It is possible.

[0074] Next, an insulating layer 3003 is formed on the insulating layer 3002 and the layers 3014 and 3020 containing a conductive material. The insulating layer 3003 is formed of silicon oxide, silicon nitride oxide, silicon nitride, etc. A single film containing an inorganic insulating material such as polyimide or acrylic, or a single film containing an organic insulating material such as polyimide or acrylic. A layer structure, a laminated structure, or the like can be applied. As the deposition method, a CVD method, a sputtering method, a spin coating method, or the like can be applied. do.

[0075] Next, a resist is formed on the insulating layer 3003 by using a photolithography method or the like. The insulating layer 3003 is etched using the resist as a mask to form an opening. For this etching, dry etching is preferably used, but wet etching is also possible. In addition, the etching gas and etching solution are determined according to the material to be etched. It can be selected appropriately depending on the situation.

[0076] Next, a conductive material is applied to fill at least the openings in the insulating layer 3003. As the layer 3004 containing a conductive material, aluminum is formed. Metals such as aluminum, titanium, tantalum, or tungsten, or their nitrides Alternatively, a film containing a conductive material or an alloy thereof may be used. It is also possible to apply a laminated structure of these films as the conductive material 3004. The layer 3004 containing the fluorine-containing compound is formed by a CVD method, a sputtering method, or the like. can be done.

[0077] Next, a conductive film is formed on the insulating layer 3003 so that at least the upper surface of the insulating layer 3003 is exposed. The layer 3004 containing the conductive material is removed by CMP (see FIG. 7(H)). and a layer 3005 including a conductive material that functions as a source or drain of the memory cell 300. etc. are formed.

[0078] In this manner, the transistor 301 included in the memory cell 300 is formed. The capacitor 302 (stacked capacitor) of the recell 300 is formed by a known method. It can be appropriately formed.

[0079] <Regarding the semiconductor memory device disclosed in this specification> The semiconductor memory device disclosed herein has a substrate that includes a single crystal semiconductor material. A driving circuit, a multilayer wiring layer provided on the driving circuit, and a A memory cell array layer is provided. In the above-mentioned embodiment, the driving circuit and the memory cell array are provided so as to overlap each other. Compared to a case where a drive circuit and a memory cell array are provided on the same plane on a substrate containing a dielectric material, It is possible to increase the degree of integration of the semiconductor memory device.

[0080] In addition, wiring made of copper or a copper alloy is applied as the wiring included in the multi-layer wiring layer. This makes it possible to reduce the wiring resistance of the wiring. In other words, it is possible to suppress the operational delay of the semiconductor memory device. The wiring (so-called bit line) that writes and reads data to the memory cell is The effect is large when wiring made of copper or a copper alloy is used.

[0081] In addition, a transistor provided in a memory cell has a channel region made of an oxide semiconductor. It is preferable to use a transistor having a barrier such as an oxide semiconductor. A transistor with a wide band gap semiconductor in the channel region is a semiconductor such as silicon. The off-state current value is significantly lower than that of a transistor using a semiconductor material. In the memory cell of the semiconductor memory device, the leakage of charge from the capacitor is prevented. Therefore, it is possible to reduce the frequency of refresh operations. As a result, in the semiconductor memory device disclosed in this specification, the refresh operation It is possible to reduce power consumption by reducing the frequency of operations.

[0082] In addition, a stack type capacitor is used as a capacitor provided in a memory cell. This makes it possible to achieve both a large capacity and high integration of the memory cell. Furthermore, the semiconductor memory device disclosed in this specification is a stacked capacitor or a transistor. In comparison with a conventional semiconductor memory device having memory cells with a wrench-type capacitor, In this regard, the conventional semiconductor memory device is a semiconductor memory device having a substrate including a single crystal semiconductor material. A transistor included in a memory cell is provided using a multi-layer wiring on the memory cell. The term "layer" refers to a semiconductor memory device in which the layer is provided.

[0083] In the semiconductor memory device disclosed in this specification, one of the components constituting the stacked capacitor This is preferable in that the bit line is not close to the paired electrode and the word line. In the memory cell array of the semiconductor memory device to be described, the word lines (layer 30 containing a conductive material) 14, 3020, etc.) and a pair of electrodes (layers including a conductive material 3013, 3016, etc.) are provided on the opposite side of the bit line (wiring 200c) with the transistor 301 in between. In contrast, the word lines and capacitors of the conventional semiconductor memory device are formed by using the At least one of the pair of electrodes and the bit line is connected to the same transistor of the memory cell. This is because the semiconductor memory device disclosed in this specification is provided on the same side as the In the device, power consumption is reduced by reducing the parasitic capacitance generated in various wiring (especially bit lines). It is possible to reduce force and suppress operational delays, etc.

[0084] In addition, the capacitor 302 and the wiring 200c are provided with the transistor 301 interposed therebetween. This reduces design constraints on the capacitor 302 and the wiring 200c, and requires less surface area. A capacitor having a capacitance required for the product can be formed.

[0085] <Examples of semiconductor memory device usage> An example of the use of the above-mentioned semiconductor memory device will be described below with reference to FIG.

[0086] FIG. 8 is a block diagram showing a configuration example of a microprocessor. The processor includes a CPU 401, a main memory 402, a clock controller 403, a cache controller 404, serial interface 405, I / O port 406, terminal 407, an interface 408, a cache memory 409, etc. are formed. The microprocessor shown in Figure 8 is merely a simplified example of its configuration. Microprocessors have a wide variety of configurations depending on their applications.

[0087] To make the CPU 401 operate faster, a memory that is commensurately faster is required. However, a high-speed, large-capacity memory with an access time that matches the operating speed of the CPU 401 is required. Generally, the cost of using memory is high. In addition to the main memory 402, a static random access memory (SRAM) that is smaller in capacity than the main memory 402 but faster is also used. A cache memory 409 such as the above is interposed between the CPU 401 and the main memory 402. When the CPU 401 accesses the cache memory 409, the main memory 40 This makes it possible to operate at high speeds regardless of the speed of the input / output 2.

[0088] In the microprocessor shown in FIG. 8, the above-mentioned semiconductor memory device is included in the main memory 402. The above configuration allows for a highly integrated microprocessor and a highly reliable A microprocessor can be implemented.

[0089] The main memory 402 stores the programs executed by the CPU 401. For example, at the beginning of execution, the program stored in the main memory 402 is The downloaded program is downloaded to the cache memory 409. The data is not limited to those stored in the in-memory 402, and may be downloaded from other external memories. The cache memory 409 stores the program executed by the CPU 401. It not only stores the results of calculations by the CPU 401, but also functions as a work area. Store in.

[0090] The number of CPUs is not limited to one, but multiple CPUs may be provided. By doing this, the operation speed can be improved. In this case, the processing speed between CPUs If they are different, problems may occur when looking at the entire process, so each slave C The processing speed of the PUs may be balanced by the master CPU.

[0091] Although a microprocessor is exemplified here, the above-mentioned semiconductor memory device may be a Its uses are not limited to main memory of a microprocessor. For example, it is used to drive a display device. Used as video RAM for circuits and large capacity memory required for image processing circuits In addition, in various system LSIs, large capacity or small memory It can be used as a EXAMPLES

[0092] In this embodiment, an example of a semiconductor device having the above-mentioned semiconductor memory device will be described. The semiconductor device can be miniaturized by using a semiconductor memory device according to one embodiment of the present invention. In particular, in the case of a portable semiconductor device, the semiconductor memory device according to one embodiment of the present invention can be used. The advantage of using a storage device to make the device smaller is that it improves user convenience. The result is

[0093] The semiconductor memory device according to one aspect of the present invention is used in a display device, a notebook personal computer, , an image reproducing device equipped with a recording medium (typically DVD: Digital Versatile) A device that plays recording media such as a DVD and has a display that can display the images. In addition, the semiconductor memory device according to one embodiment of the present invention can be used for Examples of semiconductor devices that can achieve this include mobile phones, portable game consoles, personal digital assistants, electronic books, video Digital still camera, goggle-type display (head-mounted display) (car audio, digital audio player), navigation systems, audio playback devices Layers, etc.), copiers, facsimiles, printers, multifunction printers, ATM machines Examples of these semiconductor devices include ATMs and vending machines. show.

[0094] FIG. 9A shows a portable game machine. The portable game machine includes a housing 7031, a housing 7032, a display portion 7033, A display unit 7034, a microphone 7035, a speaker 7036, an operation key 7037, a star The semiconductor memory device according to one embodiment of the present invention is a portable game device. It can be used in an integrated circuit for controlling the driving of a portable game machine. By using a semiconductor memory device according to one embodiment of the present invention in an integrated circuit for It is possible to provide a portable game machine. The display unit 7033 and the display unit 7034 are the same as those of the portable game machine. The number is not limited to this.

[0095] FIG. 9B shows a mobile phone. The mobile phone includes a housing 7041, a display unit 7042, an audio input unit 7043, The device has a voice output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. A semiconductor memory device according to one aspect of the present invention is used in an integrated circuit for controlling the operation of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using a body storage device, a compact mobile phone can be provided.

[0096] FIG. 9C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 9C has a modem built in a housing 7051. The semiconductor memory device according to one aspect of the present invention is a semiconductor memory device for controlling the operation of a portable information terminal. The present invention can be used in an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor memory device according to one aspect of the present invention, a compact portable information terminal can be provided. This can be done. [Explanation of symbols]

[0097] 10 Substrate 20 multi-layer wiring layer 20a Wiring layer 20b wiring layer 30 Memory Cell Array Layer 100 Drive circuit 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108 Gate insulating film 110 Gate electrode 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel Area 118 Sidewall insulating layer 120a High concentration impurity region 120b High concentration impurity region 122 Metal layer 124a Metal compound area 124b Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a Source electrode 130b Drain electrode 160 Transistors 200 Wiring 200a wiring 200b wiring 200c wiring 201 Contact plug 201a Contact plug 201b Contact plug 202 Insulating layer 203 Insulating layer 204a opening 204b opening 205 Layer containing conductive material 206a Groove 206b Groove 207 Layer containing conductive material 300 memory cells 301 Transistor 302 Capacitor 303 Insulating layer 401 CPU 402 Main Memory 403 Clock Controller 404 Cache Controller 405 Serial Interface 406 I / O ports 407 Terminal 408 Interface 409 Cache Memory 3000 memory cells 3001 Layer containing conductive material 3002 Insulation layer 3003 Insulation layer 3004 Layer containing conductive material 3005 Layer containing conductive material 3011 Layer containing conductive material 3012 Oxide semiconductor layer 3013 Layer containing conductive material 3014 Layer containing conductive material 3015 Insulation layer 3016 Layer containing conductive material 3020 Layer containing conductive material 7031 Case 7032 Case 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Case 7042 Display section 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Case 7052 Display section 7053 Operation key

Claims

[Claim 1] a driver circuit having a portion of a single crystal semiconductor substrate; a multilayer wiring layer provided on the drive circuit and including a plurality of wirings made of copper or a copper alloy; a memory cell array layer provided on the multi-layer wiring layer and including a plurality of memory cells arranged in a matrix; the driving circuit and each of the memory cells are electrically connected via any one of the wirings made of copper or copper alloy; Each of the memory cells includes a transistor having a channel region formed of an oxide semiconductor, and a capacitor having one electrode electrically connected to one of a source and a drain of the transistor.

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