Printed circuit board

Abstract

To provide a printed circuit board which may achieve reduced size and an increase in integration density.SOLUTION: The present invention relates to a printed circuit board which includes: a substrate; first and second through-portions penetrating between upper and lower surfaces of the substrate; a magnetic layer disposed in the first through-portion; a voltage regulator disposed in the second through-portion; a first through-hole penetrating between upper and lower surfaces of the magnetic layer; a first insulating layer disposed on the substrate, covering the magnetic layer and the voltage regulator, and filling the second through-portion and the first through-hole; a second through-hole penetrating between upper and lower surfaces of the first insulating layer in the first through-hole; a first wiring pattern disposed on an upper surface of the magnetic layer; a second wiring pattern disposed on a lower surface of the magnetic layer; and a first via pattern disposed in the second through-hole and connecting the first and second wiring patterns to each other.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Recently, in order to slim down semiconductor chips and increase power efficiency, there is a demand for embedding various passive elements such as capacitors and inductors inside package substrates. Meanwhile, in the case of inductors, there is a demand for improving inductance compared to existing chip components by changing the material and structure. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present invention is to provide a printed circuit board that can realize slimming and integration.

[0004] Another of several objects of the present invention is to provide a printed circuit board that can increase power efficiency.

[0005] Yet another of several objects of the present invention is to provide a printed circuit board capable of increasing the noise reduction effect. [Means for solving the problem]

[0006] One of the solutions provided by the present invention is to incorporate a VR (Voltage Regulator) and MCI (Magnetic Composite Inductor) into the board. If necessary, IPD (Integrated Passive Devices) can also be incorporated.

[0007] For example, a printed circuit board according to one example may include a substrate, first and second through-holes respectively penetrating between an upper surface and a lower surface of the substrate, a magnetic layer disposed in the first through-hole, a voltage regulator disposed in the second through-hole, a first through-hole penetrating between an upper surface and a lower surface of the magnetic layer, a first insulating layer disposed on the substrate, covering the magnetic layer and the voltage regulator and filling the second through-hole and the first through-hole, a second through-hole penetrating between an upper surface and a lower surface of the first insulating layer within the first through-hole, a first wiring pattern disposed on the upper surface of the magnetic layer, a second wiring pattern disposed on the lower surface of the magnetic layer, and a first via pattern disposed in the second through-hole and connecting the first and second wiring patterns to each other.

[0008] Another of several solutions provided by the present invention is to dispose a separate magnetic film in the through-hole of the substrate and form an MCI on the magnetic film.

[0009] For example, one example of a printed circuit board may include a substrate having a through portion, a magnetic layer disposed within the through portion at a distance from the substrate and having a plurality of through holes, an insulating layer covering the substrate and the magnetic layer, filling the space between a wall surface of the through portion and a side surface of the magnetic layer, and filling each of the plurality of through holes, a first wiring pattern layer disposed on an upper surface of the insulating layer, a second wiring pattern layer disposed on a lower surface of the insulating layer, and a plurality of via patterns each penetrating the insulating layer within the plurality of through holes. Effect of the Invention

[0010] Among the various effects of the present invention, one effect is that it provides a printed circuit board that can be slimmed down and integrated.

[0011] Among other advantages, the present invention provides a printed circuit board that can increase power efficiency.

[0012] Another advantage of the present invention is that it provides a printed circuit board that can enhance noise reduction effects. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4] FIG. 4 is a plan view that illustrates a cross section taken along line AA' in FIG. [Figure 5a] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5b] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5c] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5d] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 5e] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 6] FIG. 4 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. [Figure 7] 7 is a plan view that illustrates a cross section taken along line BB' in FIG. 6. FIG. [Figure 8] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 9] 9 is a plan view that illustrates a schematic cross section taken along line CC' in FIG. 8. FIG. [Figure 10a] 9A to 9C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 8. [Figure 10b] 9A to 9C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 8. [Figure 10c]9A to 9C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 8. [Figure 10d] 9A to 9C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 8. [Figure 10e] 9A to 9C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 8. [Figure 11] FIG. 9 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. [Figure 12] 12 is a plan view illustrating a cross section taken along line DD' in FIG. 11. FIG. [Figure 13] FIG. 2 is a cross-sectional view illustrating an example of a coil portion. [Figure 14] 1A to 1C are plan views each showing a schematic example of a coil portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0015] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0016] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0017] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0018] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0019] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0020] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0021] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0022] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0023] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0024] Printed Circuit Board FIG. 3 is a cross-sectional view that shows a schematic example of a printed circuit board, and FIG. 4 is a plan view that shows a schematic cross-section taken along line AA' in FIG.

[0025] Referring to the drawings, the printed circuit board 100A according to an example may include a substrate 111, first and second through-holes H1 and H2 respectively penetrating between an upper surface and a lower surface of the substrate 111, a magnetic layer 150 disposed in the first through-hole H1, a voltage regulator 141 disposed in the second through-hole H2, a first through-hole h1 penetrating between an upper surface and a lower surface of the magnetic layer 150, a first insulating layer 112 disposed on the substrate 111 to cover the magnetic layer 150 and the voltage regulator 141 and to fill the first and second through-holes H1 and H2 and the first through-hole h1, a second through-hole h2 penetrating between an upper surface and a lower surface of the first insulating layer 112 within the first through-hole h1, a first wiring pattern B1 disposed on the upper surface of the magnetic layer 150, a second wiring pattern B2 disposed on the lower surface of the magnetic layer 150, and a first via pattern M1 disposed in the second through-hole h2 to connect the first and second wiring patterns B1 and B2 to each other. An inductor 131 may be disposed on the substrate 111 via the magnetic layer 150, the first and second wiring patterns B1, B2 connected to each other in a form surrounding at least a portion of the magnetic layer 150, and the first via pattern M1. A first insulating layer 112 may be disposed between the first and second wiring patterns B1, B2 and the upper and lower surfaces of the magnetic layer 150, respectively. The first via pattern M1 may be disposed on a wall surface of the second through hole h2, and the inductor 131 may include a first filler R1 filling a space between the first via patterns M1 in the second through hole h2.

[0026] In this manner, the printed circuit board 100A according to an embodiment may include a magnetic layer 150 and a voltage regulator 141 disposed and embedded in the first and second through-holes H1 and H2 of the substrate 111 corresponding to the core layer, respectively, and may form an inductor 131 of MCI type in the magnetic layer 150. For example, a structure in which the inductor 131 and the voltage regulator 141 are both embedded may be provided. In addition, the magnetic layer 150 provided using a magnetic film or the like may be disposed apart from the wall surface of the first through-hole H1, and the first insulating layer 112 may fill the first through-hole H1, and the inductor 131 of MCI type may be formed in the magnetic layer 150. As a result, slimming and integration may be realized, and power efficiency and noise reduction effects may be improved. Also, the inductor 131 can be realized by forming a first through hole h1 in the magnetic layer 150, filling it with the first insulating layer 112, forming a second through hole h2 having a smaller diameter than the first through hole h1, and then forming a first via pattern M1 inside the second through hole h2 by plating. Therefore, the metal oxide contained in the magnetic layer 150 does not appear on the surface, and it is possible to prevent the magnetic layer 150 from dissolving in an acid solution.

[0027] Meanwhile, the printed circuit board 100A according to an example may further include a third through hole h3 penetrating between the upper and lower surfaces of the board 111 and filled with the first insulating layer 112, a fourth through hole h4 penetrating between the upper and lower surfaces of the first insulating layer 112 in the third through hole h3, a first wiring layer 121 disposed on the upper surface of the first insulating layer 112 and including a first wiring pattern B1, a second wiring layer 122 disposed on the lower surface of the first insulating layer 112 and including a second wiring pattern B2, and a second via pattern M2 disposed in the fourth through hole h4 to connect the first and second wiring layers 121 and 122 to each other. For example, the printed circuit board 100A may further include a through via 132. The second via pattern M2 may be disposed on a wall surface of the fourth through hole h4, and the through via 132 may include a second filler R2 filling a space between the second via patterns M2 in the fourth through hole h4. For example, the first and second wiring layers 121 and 122 are disposed on the upper and lower surfaces of the first insulating layer 112, allowing various wiring designs, and various materials such as metal, glass, silicon, etc., other than organic insulating materials, can be used as the material of the substrate 111. In addition, when forming the inductor 131, a through via 132 for connecting the first and second wiring layers 121 and 122 can be formed at the same time, thereby further simplifying the process and reducing costs and time.

[0028] In addition, the printed circuit board 100A according to an example may further include a third penetration portion H3 penetrating between the upper surface and the lower surface of the board 111, and a passive element 142 disposed in the third penetration portion H3. The first insulating layer 112 may cover the passive element 142 and fill the third penetration portion H3. For example, in addition to the inductor 131 and the voltage regulator 141, a passive element 142, for example, an integrated passive device, may be embedded in the printed circuit board 100A. Therefore, the noise reduction effect may be further increased along with the increase in power efficiency described above. Moreover, the printed circuit board 100A according to an example may include a first via layer 133 including connection vias penetrating the upper side of the first insulating layer 112 and connecting the first wiring layer 121 to the respective connection pads of the voltage regulator 141 and the passive element 142, and a second via layer 134 including connection vias penetrating the lower side of the first insulating layer 112 and connecting the second wiring layer 122 to the back surface of the voltage regulator 141. For example, the voltage regulator 141, the passive element 142, and the inductor 131 may be electrically connected to each other via the first via layer 133 and the first wiring layer 121. Also, heat of the voltage regulator 141 can be dissipated via the second via layer 134 and the second wiring layer 122.

[0029] Meanwhile, the printed circuit board 100A according to one example includes a second insulating layer 113 disposed on an upper surface of the first insulating layer 112, a third insulating layer 114 disposed on a lower surface of the first insulating layer 112, a third wiring layer 123 disposed on an upper surface of the second insulating layer 113, a fourth wiring layer 124 disposed on a lower surface of the third insulating layer 114, and a third via layer 125 including a connection via penetrating the second insulating layer 113 and connecting the first and third wiring layers 121 and 123 to each other. 35, a fourth via layer 136 including a connection via penetrating the third insulating layer 114 and connecting the second and fourth wiring layers 122 and 124 to each other, a first resist layer 115 disposed on the upper surface of the second insulating layer 113 and having a first opening 115h exposing the third wiring layer 123, and a second resist layer 116 disposed on the lower surface of the third insulating layer 114 and having a second opening 116h exposing the fourth wiring layer 124. For example, the substrate may have the form of a multilayer package substrate realized by a build-up process.

[0030] The components of the printed circuit board 100A according to an example will be described in more detail below with reference to the drawings.

[0031] The substrate 111 may be a core layer. For example, it may include an organic core layer, a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer. The organic core layer may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as copper clad laminate (CCL), Ajinomoto build-up film (ABF), prepreg (PPG), etc., but is not limited thereto, and other polymeric materials may be used. The glass core layer may include glass. For example, the glass may include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc. Alternative glass materials, such as, but not limited to, fluorine glass, phosphate glass, chalcogenide glass, etc., may be used as the material of the glass layer. Other additives may also be included to form glass with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of such elements and other elements. Glass may be distinguished from glass fibers, as described above. The metal core layer may include a metal. The metal may include, but is not limited to, copper (Cu), Invar, etc. The silicon core layer may include pure silicon (Si). If necessary, the silicon core layer may include an oxide layer formed on silicon (Si). It may also include a nitride layer formed on the oxide layer. The oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but is not limited to these.The ceramic core layer may include a ceramic material, such as, but not limited to, alumina (Al2O3), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si3N4), and the like.

[0032] The first to third insulating layers 112, 113, and 114 may contain an organic insulating material. As described above, the organic insulating material may contain a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as CCL (Copper Clad Laminate), ABF (Ajinomoto Build-up Film), or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The first to third insulating layers 112, 113, and 114 may contain the same or different organic insulating materials. Each of the first to third insulating layers 112, 113, and 114 may be composed of a plurality of layers as necessary.

[0033] The first and second resist layers 115 and 116 may include, but are not limited to, a liquid or film type solder resist, and may include other organic insulating materials such as ABF. The first and second resist layers 115 and 116 may have first and second openings 115h and 116h, respectively. The first and second openings 115h and 116h may each be a plurality of openings. The first and second openings 115h and 116h may be formed by solder mask defined (SMD) and / or non-solder mask defined (NSMD). The first and second openings 115h and 116h may expose the third and fourth wiring layers 123 and 124, respectively, and a surface treatment layer may be disposed on the surface of the exposed pattern. The surface treatment layer may be formed by electrolytic gold plating, electroless gold plating, OSP (Organic Solderability Preservative) or electroless tin plating, electroless silver plating, electroless nickel plating / substitution gold plating, DIG (Direct Immersion Gold) plating, HASL (Hot Air Solder Leveling), etc., but is not limited thereto.

[0034] Each of the first to fourth wiring layers 121, 122, 123, and 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first to fourth wiring layers 121, 122, 123, and 124 may perform various functions according to the design. For example, the first to fourth wiring layers 121, 122, 123, and 124 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first to fourth wiring layers 121, 122, 123, and 124 may include a seed layer and a plating layer formed on the seed layer. The seed layer may be an electroless plating layer (or chemical copper) and / or a sputtering layer, and the plating layer may be an electrolytic plating layer (or electrolytic copper), but is not limited thereto.

[0035] The first and second wiring patterns B1, B2 and the first and second via patterns M1, M2 may include a metal material. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The second via pattern M2 may perform various functions according to the design. For example, the second via pattern may include a signal via pattern, a power via pattern, a ground via pattern, and the like. The first and second wiring patterns B1, B2 and the first and second via patterns M1, M2 may include a seed layer and a plating layer formed on the seed layer, respectively. The seed layer may be an electroless plating layer (or chemical copper) and / or a sputtering layer, and the plating layer may be an electrolytic plating layer (or electrolytic copper), but is not limited thereto.

[0036] The first and second fillers R1 and R2 may include a plugging material. The plugging material may include an insulating ink including an insulating resin such as epoxy. However, the plugging material is not limited thereto and may include a conductive ink as necessary. The first and second fillers R1 and R2 may be formed through the same process, and therefore may include the same material, but is not limited thereto.

[0037] The first and second through holes h1 and h2 may each be formed in a plurality of numbers. For example, in a plane, a second through hole h2 having a smaller diameter than the first through hole h1 may be formed in each first through hole h1. Therefore, a plurality of first via patterns M1 may also be formed in the second through hole h2. In this manner, the inductor 131 may include a plurality of first via patterns M1, and the first wiring pattern B1 and the second wiring pattern B2 connected to the plurality of first via patterns M1 may also each be multiple. The plurality of first and second wiring patterns B1 and B2 may be included in the first and second wiring pattern layers, respectively, and the first and second wiring pattern layers may be included in the first and second wiring layers 121 and 122, respectively.

[0038] The third and fourth through holes h3 and h4 may also be formed in multiple numbers. For example, in a plan view, a fourth through hole h4 having a smaller diameter than the third through hole h3 may be formed in each of the third through holes h3. Therefore, the second via patterns M2 formed in the fourth through hole h4 may also be formed in multiple numbers. In this way, the number of through vias 132 may be multiple.

[0039] Each of the first to fourth via layers 133, 134, 135, and 136 may include a metal material. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first to fourth via layers 133, 134, 135, and 136 may include a filled via that fills a via hole, but may also include a conformal via that is arranged along the wall surface of the via hole. The first to fourth via layers 133, 134, 135, and 136 may perform various functions according to the design. For example, they may include a ground via, a power via, a signal via, and the like. The first and second via layers 133 and 134 may include connection vias having tapered shapes in opposite directions to each other. The third and fourth via layers 135 and 136 may include connection vias having tapered shapes in opposite directions. The first to fourth via layers 133, 134, 135 and 136 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of the electroless plating layer (or chemical copper), or both may be included as necessary.

[0040] The voltage regulator 141 may include a circuit for adjusting a voltage. The voltage regulator 141 may be a chip-type electronic component. For example, the voltage regulator 141 may be in the form of a semiconductor chip, and more specifically, may be an integrated circuit (IC) die in which hundreds to millions of elements are integrated in one chip. The integrated circuit die may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material for each body. Various circuits may be formed in the body. A connection pad may be formed on the front surface of the body, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). If necessary, a connection pad may also be formed on the back surface of the body. If necessary, there may be a plurality of voltage regulators 141, and the plurality of voltage regulators 141 may be disposed together in the second through-hole H2, or a plurality of second through-holes H2 may be formed and disposed in each of them.

[0041] The passive element 142 may be a chip-type electronic component including a resistor, a capacitor, an inductor, an impedance matching element, or a combination thereof. For example, the passive element 142 may be an integrated passive device (IPD), which may also be called an integrated passive component (IPC) or an embedded passive component (EPC). If necessary, there may be a plurality of passive elements 142, and a plurality of passive elements 142 may be disposed together in the third through-hole H3, or a plurality of third through-holes H3 may be formed and disposed in each of them.

[0042] The magnetic layer 150 may include a magnetic material. The magnetic material may include, for example, a ferrite-based material, a permalloy-based material, etc. For example, the magnetic material may include, but is not limited to, Ni-based ferrite, Ni-Zn-based ferrite, Ni-Zn-Cu-based ferrite, Fe-Si-Al (Sendust), Ni-Mo-Fe (MPP: Molypermalloy Powder Core), Ni-Fe (High Flux Core), etc., and may include other known ferrite-based materials, permalloy-based materials, etc. In addition, various types of magnetic materials including other magnetic powders may be used. The magnetic layer 150 may be hardened in the form of a magnetic film or a magnetic sheet and disposed in the first through-hole H1. Therefore, the magnetic layer 150 may be disposed apart from the substrate 111.

[0043] 5a to 5e are process diagrams that outline an example of a method for manufacturing the printed circuit board of FIG.

[0044] Referring to FIG. 5a, the first to third through-holes H1, H2, H3 and the third through-hole h3 are formed in the substrate 111. The first to third through-holes H1, H2, H3 and the third through-hole h3 can be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and blasting process depending on the material of the substrate 111. The first through-hole h1 is formed in the magnetic film or sheet-like magnetic layer 150 by mechanical drilling or the like, and cut to an appropriate size, which is then placed in the first through-hole H1. The voltage regulator 141 and the passive element 142 are placed in the second and third through-holes H2 and H3, respectively. The magnetic layer 150, the voltage regulator 141 and the passive element 142 can be placed using a tape 210.

[0045] 5b, the first insulating layer 112 is laminated by a lamination process such as PPG or ABF to cover the substrate 111, the magnetic layer 150, the voltage regulator 141 and the passive element 142, and to fill the first to third through-holes H1, H2, H3 and the first and third through-holes h1, h3. Thereafter, the laminate can be cut into unit sizes by a trimming process, if necessary.

[0046] 5c, next, second and fourth through holes h2, h4 are formed in the first and third through holes h1, h3 by a mechanical drill or the like. In addition, first and second via holes 133V, 134V for forming the first and second via layers 133, 134 are formed in the first insulating layer 112 by laser processing or the like.

[0047] 5d, the first and second via patterns M1 and M2, the first and second filling materials R1 and R2, the first and second wiring patterns B1 and B2, the first and second wiring layers 121 and 122, and the first and second via layers 133 and 134 are formed by a plating process, a plugging process, and the like. For example, the inductor 131 and the through via 132 are formed. More specifically, the inductor 131 and the through via 132 can be formed by, for example, forming a plating layer on the upper and lower surfaces of the first insulating layer 112 and the wall surfaces of the second and fourth through holes h2 and h4 in a plating process, filling the second and fourth through holes h2 and h4 with a plugging material in a plugging process, removing the plating layer and the plugging material on the upper and lower surfaces of the first insulating layer 112 in a planarization process, and then forming a plating layer on the upper and lower surfaces of the first insulating layer 112 again in a plating process. In this process, the first and second wiring layers 121 and 122 and the first and second via layers 133 and 134 can also be formed. Meanwhile, in the plating process, a plating layer patterned according to a design can be formed using a dry film exposure and development process. In addition, the planarization process can make the upper and lower surfaces of the first insulating layer 112 substantially coplanar, and rough interlayer boundaries can be formed between the plating layers.

[0048] 5e, the second and third insulating layers 113, 114, the third and fourth wiring layers 123, 124, and the third and fourth via layers 135, 136 are formed in the required number of layers by a build-up process or the like, and then the first and second resist layers 115, 116 are formed. Also, the first and second openings 115h, 116h are formed in the first and second resist layers 115, 116, respectively. Meanwhile, the second and third insulating layers 113, 114 can be formed using the above-mentioned lamination process, the third and fourth wiring layers 123, 124 and the third and fourth via layers 135, 136 can be formed using the above-mentioned plating process, and the first and second resist layers 115, 116 can be formed by a lamination process or a coating process of a liquid material, or the like.

[0049] The printed circuit board 100A according to the above-described example can be manufactured through a series of processes, and other details may be substantially the same as those described above.

[0050] FIG. 6 is a cross-sectional view that shows a schematic modification of the printed circuit board of FIG. 3, and FIG. 7 is a plan view that shows a schematic cross-section taken along line BB' of FIG.

[0051] Referring to the drawings, the printed circuit board 100B according to the modified example may be obtained by omitting the third through-hole H3 in the printed circuit board 100A according to the above-described example, and the passive element 142 may be disposed in the second through-hole H2 together with the voltage regulator 141. In this manner, only a minimum number of through-holes may be formed to incorporate components as necessary. The rest of the description may be substantially the same as that of the printed circuit board 100A according to the above-described example. Meanwhile, the printed circuit board 100B according to the modified example may be manufactured by omitting the third through-hole H3 and forming the second through-hole H2 larger in the manufacturing process of the printed circuit board 100A according to the above-described example, but a detailed description thereof will be omitted.

[0052] FIG. 8 is a cross-sectional view that shows a schematic diagram of another example of the printed circuit board, and FIG. 9 is a plan view that shows a schematic diagram of a cross section taken along line CC' in FIG.

[0053] Referring to the drawings, in the printed circuit board 100C according to another example, the magnetic layer 150 may contact the wall surface of the first through-hole H1 in the printed circuit board 100A according to the above example. For example, the magnetic layer 150 may contact the substrate 111. Therefore, the first insulating layer 112 may not fill the first through-hole H1. For example, the magnetic layer 150 may fill the first through-hole H1 with a paste or composition type, not a film or sheet type, and may then be hardened to become the magnetic layer 150. In this way, the first through-hole H1 may be filled with the magnetic layer 150 as necessary. Other explanations may be substantially the same as those described in the printed circuit board 100A according to the above example, so duplicate explanations will be omitted.

[0054] 10a to 10e are process diagrams that outline an example of a method for manufacturing the printed circuit board of FIG.

[0055] Referring to FIG. 10a, the first through third through parts H1, H2, H3 and the third through hole h3 are formed in the substrate 111. The first through third through parts H1, H2, H3 and the third through hole h3 can be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and blasting process depending on the material of the substrate 111. The first through part H1 is filled with a magnetic paste or a magnetic composition, which is hardened to form the magnetic layer 150 disposed in the first through part H1, and then the first through hole h1 is formed in the magnetic layer 150 by a mechanical drill or the like. The voltage regulator 141 and the passive element 142 are disposed in the second and third through parts H2 and H3, respectively. A tape 210 can be used to form the magnetic layer 150 and to dispose the voltage regulator 141 and the passive element 142.

[0056] 10b, a first insulating layer 112 is laminated by a lamination process such as PPG or ABF to cover the substrate 111, the magnetic layer 150, the voltage regulator 141, and the passive element 142, and to fill the first to third through-holes H1, H2, and H3 and the first and third through-holes h1 and h3. Thereafter, if necessary, the laminate can be cut into unit sizes by a trimming process.

[0057] 10c, next, second and fourth through holes h2, h4 are formed in the first and third through holes h1, h3 by a mechanical drill or the like. In addition, first and second via holes 133V, 134V for forming the first and second via layers 133, 134 in the first insulating layer 112 are formed by laser processing or the like.

[0058] 10d, the first and second via patterns M1 and M2, the first and second filling materials R1 and R2, the first and second wiring patterns B1 and B2, the first and second wiring layers 121 and 122, and the first and second via layers 133 and 134 are formed by a plating process, a plugging process, and the like. For example, an inductor 131 and a through via 132 are formed. More specifically, the inductor 131 and the through via 132 can be formed by, for example, forming a plating layer on the upper and lower surfaces of the first insulating layer 112 and the wall surfaces of the second and fourth through holes h2 and h4 in a plating process, filling the second and fourth through holes h2 and h4 with a plugging material in a plugging process, removing the plating layer and the plugging material on the upper and lower surfaces of the first insulating layer 112 in a planarization process, and then forming a plating layer on the upper and lower surfaces of the first insulating layer 112 again in a plating process. In this process, the first and second wiring layers 121 and 122 and the first and second via layers 133 and 134 can also be formed. Meanwhile, in the plating process, a plating layer patterned according to a design can be formed using a dry film exposure and development process. In addition, the planarization process can make the upper and lower surfaces of the first insulating layer 112 substantially coplanar, and rough interlayer boundaries can be formed between the plating layers.

[0059] 10e, the second and third insulating layers 113, 114, the third and fourth wiring layers 123, 124, and the third and fourth via layers 135, 136 are formed in the required number of layers by a build-up process or the like, and then the first and second resist layers 115, 116 are formed. Also, the first and second openings 115h, 116h are formed in the first and second resist layers 115, 116, respectively. Meanwhile, the second and third insulating layers 113, 114 can be formed using the above-mentioned lamination process, the third and fourth wiring layers 123, 124 and the third and fourth via layers 135, 136 can be formed using the above-mentioned plating process, and the first and second resist layers 115, 116 can be formed by a lamination process or a coating process of a liquid material, or the like.

[0060] The printed circuit board 100C according to the above-mentioned another example can be manufactured through a series of processes, and other details may be substantially the same as those described above.

[0061] FIG. 11 is a cross-sectional view that shows a schematic modification of the printed circuit board of FIG. 8, and FIG. 12 is a plan view that shows a schematic cross-section taken along line DD' of FIG.

[0062] Referring to the drawings, the printed circuit board 100D according to the modified example may be manufactured by omitting the third through-hole H3 in the printed circuit board 100C according to the other example described above, and by disposing the passive element 142 together with the voltage regulator 141 in the second through-hole H2. In this manner, only a minimum number of through-holes may be formed to incorporate components as necessary. Other explanations may be substantially the same as those described for the printed circuit board 100A according to the one example described above and the printed circuit board 100C according to the other example. Meanwhile, the printed circuit board 100D according to the modified example may be manufactured by omitting the third through-hole H3 and forming the second through-hole H2 larger in the manufacturing process of the printed circuit board 100C according to the other example described above, but a detailed explanation thereof will be omitted.

[0063] FIG. 13 is a cross-sectional view that illustrates an example of a coil portion.

[0064] Referring to the drawings, the inductor 131 included in the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D may include one or more coil parts C, and the coil part C may have a form in which a plurality of first and second wiring patterns B1, B2 and a plurality of first via patterns M1 formed in the main body 180 are alternately connected to each other. For example, the coil part C may have a coil structure in which a required number of the second wiring pattern B2, the first via pattern M1, the first wiring pattern B1, the first via pattern M1, the second wiring pattern B2, the first via pattern M1, the first wiring pattern B1, and the first via pattern M1 are connected to each other on the cross section and alternately repeated up and down. Meanwhile, the main body 180 may include the above-mentioned magnetic layer 150 and the first insulating layer 112. Also, the through holes in which the first via patterns M1 are formed may be filled with the first filler R1. In this manner, the coil unit C may have a structure in which the number of coils surrounding the magnetic layer 150 is maximized, for example, a daisy chain shape that can maximize inductance. Other explanations may be substantially the same as those described for the printed circuit boards 100A, 100B, 100C, and 100D described above, and therefore repeated explanations will be omitted.

[0065] FIG. 14 is a plan view illustrating various examples of the coil portion.

[0066] Referring to the drawings, the coil unit C may have various shapes on a plane. For example, as shown in A, it may include a plurality of coils C1 and C2 arranged in parallel in a line. Alternatively, as shown in B, it may include a coil C3 arranged in a line, bent from the right, and arranged in a line again. Alternatively, as shown in C, it may include a coil C4 arranged to be repeatedly bent up and down. Alternatively, as shown in D, it may include a coil C5 arranged repeatedly in a shape inclined in one direction. Alternatively, as shown in E, it may include a coil C6 arranged repeatedly in a shape inclined in one direction, bent from the right, and arranged repeatedly in a shape inclined in the opposite direction. Alternatively, as shown in F, it may include a coil C7 arranged repeatedly in an X-shape. In this way, the coil unit C including the coils C1, C2, C3, C4, C5, C6, and C7 of various shapes may be applied to the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D, but is not limited thereto. The rest of the description may be substantially the same as that of the printed circuit boards 100A, 100B, 100C, and 100D and the cross-sectional shape of the coil portion C described above, so a duplicated description will be omitted.

[0067] In the present invention, the expression "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and can also include not only the case of covering directly, but also the case of covering indirectly. The expression "fill" can include not only the case of filling completely, but also the case of filling at least a part, and can also include the case of filling almost entirely. For example, it can include the case where there are some gaps or voids. The expression "surround" can include not only the case of surrounding completely, but also the case of surrounding a part and the case of surrounding almost entirely. The expression "expose" can include not only the case of exposing completely, but also the case of exposing a part, and "exposure" can mean exposing from embedding the structure. For example, "the opening exposes the pad" can mean exposing the pad from the resist layer, and a surface treatment layer or the like can be further disposed on the exposed pad.

[0068] In the present invention, "disposed in a through-hole or a penetrating portion" includes not only a case where an object is completely disposed in the through-hole or a penetrating portion, but also a case where the object partially protrudes upward or downward on a cross section. For example, if the object is disposed in the through-hole or a penetrating portion on a plane, it can be judged in a broader sense.

[0069] In the present invention, the term "substantially" can be determined by taking into account process errors, positional deviations, measurement errors, and the like that occur during the manufacturing process. For example, "substantially perpendicular" can include not only a case where the two are completely perpendicular, but also a case where the two are almost perpendicular. Furthermore, "substantially coplanar" can include not only a case where the two are completely on the same plane, but also a case where the two are almost on the same plane.

[0070] In the present invention, the term "same insulating material" refers not only to completely identical insulating materials, but also to insulating materials of the same type. Thus, although the compositions of the insulating materials are substantially the same, the specific composition ratios thereof may differ slightly.

[0071] In the present invention, the term "on a cross section" may refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the term "on a plane" may refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0072] In the present invention, for convenience, terms such as "lower side, lower part, lower surface" are used to mean a downward direction based on a cross section of a drawing, and terms such as "upper side, upper part, upper surface" are used to mean the opposite direction. However, these are merely definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by such directional descriptions, and the concepts of up / down can be changed at any time.

[0073] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Also, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0074] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0075] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0076] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B, 100C, 100D: Printed circuit boards 111: Substrate 112, 113, 114: insulating layer 115, 116: resist layer 121, 122, 123, 124: Wiring layer 131: Inductor 132:Through via 133, 134, 135, 136: via layers 133V, 134V: Via holes 141: Voltage regulator 142: Passive elements 150: Magnetic layer C: Coil section c1, c2, c3, c4, c5, c6, c7: coil B1, B2: Wiring pattern M1, M2: Via patterns R1, R2: Filler material H1, H2, H3: Penetration part h1, h2, h3, h4: Through hole 210: Tape

Claims

1. A substrate; a first through portion and a second through portion that respectively penetrate between an upper surface and a lower surface of the substrate; a magnetic layer disposed in the first penetrating portion; a voltage regulator disposed in the second through-hole; a first through hole penetrating between an upper surface and a lower surface of the magnetic layer; a first insulating layer disposed on the substrate, covering the magnetic layer and the voltage regulator and filling the second through portion and the first through hole; a second through hole penetrating between an upper surface and a lower surface of the first insulating layer within the first through hole; a first wiring pattern disposed on an upper surface of the magnetic layer; a second wiring pattern disposed on a lower surface of the magnetic layer; a first via pattern disposed in the second through hole and connecting the first wiring pattern and the second wiring pattern to each other.

2. the first via pattern is disposed on a wall surface of the second through hole, The printed circuit board of claim 1 , further comprising a first filler material filling spaces between the first via patterns in the second through holes.

3. a first wiring layer disposed on an upper surface of the first insulating layer; a second wiring layer disposed on a lower surface of the first insulating layer, the first insulating layer is disposed between the first wiring pattern and an upper surface and a lower surface of the magnetic layer, and The printed circuit board according to claim 1 , wherein the first wiring layer and the second wiring layer include the first wiring pattern and the second wiring pattern, respectively.

4. a third through hole that penetrates between the upper surface and the lower surface of the substrate and is filled with the first insulating layer; a fourth through hole penetrating between an upper surface and a lower surface of the first insulating layer within the third through hole; The printed circuit board according to claim 3 , further comprising: a second via pattern disposed in the fourth through hole and connecting the first wiring layer and the second wiring layer to each other.

5. the second via pattern is disposed on a wall surface of the fourth through hole, The printed circuit board of claim 4 , further comprising a second filler material filling spaces between the second via patterns in the fourth through holes.

6. a first via layer including a first connection via penetrating an upper side of the first insulating layer and connecting the first wiring layer and the voltage regulator to each other; The printed circuit board of claim 3 , wherein the voltage regulator and the first via pattern are connected to each other through a path passing through the first connection via and the first wiring layer.

7. a second via layer including a second connection via penetrating a lower side of the first insulating layer and connecting the second wiring layer and the voltage regulator to each other; the second connection via is connected to a back surface of the voltage regulator; The printed circuit board of claim 6 , wherein the first connection via and the second connection via have tapered shapes in opposite directions.

8. a second insulating layer disposed on an upper surface of the first insulating layer; a third insulating layer disposed on a lower surface of the first insulating layer; a third wiring layer disposed on an upper surface of the second insulating layer; a fourth wiring layer disposed on a lower surface of the third insulating layer; a third via layer including a third connection via penetrating the second insulating layer and connecting the first wiring layer and the third wiring layer to each other; a fourth via layer including a fourth connection via penetrating the third insulating layer and connecting the second wiring layer and the fourth wiring layer to each other, The printed circuit board according to claim 3 , wherein the third connection via and the fourth connection via have tapered shapes in opposite directions.

9. a first resist layer disposed on an upper surface of the second insulating layer and having a first opening exposing the third wiring layer; 9. The printed circuit board according to claim 8, further comprising: a second resist layer disposed on a lower surface of the third insulating layer, the second resist layer having a second opening exposing the fourth wiring layer.

10. The semiconductor device further includes an integrated passive device disposed in the second through portion, The printed circuit board of claim 1 , wherein the first insulating layer covers the integrated passive components.

11. a third penetrating portion penetrating between the upper surface and the lower surface of the substrate; an integrated passive element disposed within the third penetration; The printed circuit board of claim 1 , wherein the first insulating layer covers the integrated passive components and fills the third via.

12. the magnetic layer is disposed apart from a wall surface of the first penetrating portion, The printed circuit board of claim 1 , wherein the first insulating layer fills the first via.

13. The printed circuit board according to claim 1 , wherein the magnetic layer is in contact with a wall surface of the first through portion.

14. The printed circuit board of claim 1 , wherein the substrate comprises an organic core layer, a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer.

15. The printed circuit board according to claim 1 , wherein the first wiring pattern, the second wiring pattern, and the first via pattern are connected to each other in a form surrounding at least a portion of the magnetic layer, thereby forming an inductor on the board.

16. A substrate having a through portion; a magnetic layer disposed in the through portion and spaced apart from the substrate, the magnetic layer having a plurality of through holes; an insulating layer that covers the substrate and the magnetic layer, fills the gap between the wall surface of the through portion and the side surface of the magnetic layer, and fills each of the through holes; a first wiring pattern layer disposed on an upper surface of the insulating layer; a second wiring pattern layer disposed on the lower surface of the insulating layer; and a plurality of via patterns each penetrating the insulating layer within the plurality of through holes.

17. the first wiring pattern layer includes a plurality of first wiring patterns; the second wiring pattern layer includes a plurality of second wiring patterns; The printed circuit board of claim 16 , further comprising a coil portion in which the first wiring patterns, the second wiring patterns and the via patterns are alternately connected to each other.

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