Solar cell, method for preparing the same, and photovoltaic module

Abstract

To provide, in the field of solar cells, a solar cell, a method for preparing the same, and a photovoltaic module.SOLUTION: The solar cell includes an N-type silicon substrate including a front surface and a rear surface opposite to each other; a passivation layer positioned on the front surface; a tunneling dielectric layer positioned on the rear surface; and a doped conductive layer positioned over the tunneling dielectric layer. The front surface includes a plurality of pyramid structures. The rear surface includes a plurality of grooves, and some of the grooves are sequentially arranged along the same direction. Embodiments of the present application are advantageous for at least improving the photoelectric conversion efficiency of the solar cell by changing the morphology of the rear surface of the N-type silicon substrate.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to the field of solar cells, and in particular to solar cells and methods of fabricating same, and photovoltaic modules. [Background technology]

[0002] At present, with the gradual depletion of fossil energy, solar cells are being used more and more widely as a new energy alternative. A solar cell is a device that converts the light energy of the sun into electrical energy. A solar cell uses the principle of photovoltaic power to generate carriers, and then uses electrodes to extract the carriers, which helps to effectively utilize electrical energy.

[0003] Current solar cells mainly include IBC (Interdigitated Back Contact) cells, TOPCON (Tunnel Oxide Passivated Contact) cells, PERC (Passivated emitter and real cell) cells, and heterojunction cells.

[0004] However, in order to improve the photoelectric conversion efficiency of solar cells, further investigation is required regarding the surface morphology of the film layer in the solar cell. Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments of the present application provide a solar cell, a manufacturing method thereof, and a photovoltaic module that are advantageous in improving the photoelectric conversion efficiency of the solar cell by changing the shape of the rear surface of at least an N-type silicon substrate. [Means for solving the problem]

[0006] According to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell is provided, the solar cell including an N-type silicon substrate having opposing front and back surfaces, a passivation layer located on the front surface, a tunnel dielectric layer located on the back surface, and a doped conductive layer located on the tunnel dielectric layer, the front surface including a plurality of pyramid structures, the back surface including a plurality of grooves, some of the grooves being arranged sequentially along the same direction.

[0007] In some embodiments, the plurality of grooves includes N groove groups, each of the groove groups including a plurality of the grooves arranged sequentially along the same direction, and the arrangement directions of the plurality of grooves in different groove groups are the same or different, and N is a positive integer greater than or equal to 2.

[0008] In some embodiments, there is a gap between adjacent grooves and / or there is an overlap region between at least some of the grooves in adjacent grooves.

[0009] In some embodiments, there is a gap between at least some of the adjacent grooves and / or there is an overlap region between at least some of the adjacent grooves.

[0010] In some embodiments, in a direction away from the back surface, the groove comprises an opposing bottom surface and a top opening, and a sidewall located between the bottom surface and the top opening, and an area of ​​an orthogonal projection of the bottom surface on the N-type silicon substrate is smaller than an area of ​​an orthogonal projection of the top opening on the N-type silicon substrate.

[0011] In some embodiments, the shape of the groove when orthogonally projected onto the N-type silicon substrate is an M-sided polygon, where M is a positive integer of 3 or more.

[0012] In some embodiments, in a direction away from the back surface, the groove has an upper opening, and a first dimension of the upper opening is between 1 μm and 20 μm.

[0013] In some embodiments, the distribution density of the grooves on the back surface is 1,000 pieces / mm 2 ~50,000 pieces / mm 2 It is.

[0014] In some embodiments, the maximum depth of the groove in a direction away from the back surface is between 50 nm and 2,000 nm.

[0015] In some embodiments, the doped conductive layer comprises an N-type doping element, and the doped conductive layer covers a surface of the tunnel dielectric layer remote from the N-type silicon substrate.

[0016] In some embodiments, the doped conductive layer comprises a P-type doping element, and the doped conductive layer covers a surface of the tunnel dielectric layer remote from the N-type silicon substrate.

[0017] In some embodiments, the doped conductive layer includes a first portion and a second portion spaced apart from one another, one of the first portion and the second portion comprising a doping element of the same conductivity type as the N-type silicon substrate and the other of the first portion and the second portion comprising a doping element of a different conductivity type than the N-type silicon substrate.

[0018] According to some embodiments of the present application, in another aspect of the embodiments of the present application, a method for manufacturing a solar cell is provided, the method for manufacturing a solar cell includes: providing an initial N-type silicon substrate, the initial N-type silicon substrate having a first surface and a second surface opposite to each other; performing a texture forming process on the initial N-type silicon substrate to form pyramid structures on both the first surface and the second surface; etching the second surface in a first etching step to form initial grooves; continuing to etch the second surface in a second etching step to increase a size of the initial grooves, thereby forming an N-type silicon substrate with grooves, and some of the grooves are sequentially arranged along the same direction, wherein an etching rate of the second surface by the first etching step is smaller than an etching rate of the second surface by the second etching step; the first surface on which the pyramid structures are formed is a front surface of the N-type silicon substrate, and the second surface processed by the first etching step and the second etching step is a back surface of the N-type silicon substrate; and sequentially forming a tunnel dielectric layer and a doping conductive layer on the back surface in a direction away from the back surface.

[0019] In some embodiments, etching the second side in the first etching step includes immersing the initial N-type silicon substrate in a first etching solution, and continuing to etch the second side in the second etching step includes immersing the initial N-type silicon substrate in a second etching solution, where a mass fraction of sodium hydroxide in the first etching solution is less than or equal to a mass fraction of sodium hydroxide in the second etching solution.

[0020] In some embodiments, both the first etching solution and the second etching solution contain a protective agent, and the mass fraction of the protective agent in the first etching solution is smaller than the mass fraction of the protective agent in the second etching solution.

[0021] In some embodiments, an ambient temperature when etching the second surface in the first etching step is a first temperature, an ambient temperature when etching the second surface in the second etching step is a second temperature, and the first temperature is lower than the second temperature.

[0022] In some embodiments, the first etching step etches the second surface for a first time, the second etching step etches the second surface for a second time, and the first time is greater than or equal to the second time.

[0023] According to some embodiments of the present application, in another aspect of the embodiments of the present application, a photovoltaic module is provided, the photovoltaic module including a cell string formed by connecting a plurality of solar cells according to any of the above embodiments or a plurality of solar cells manufactured by the manufacturing method for a solar cell according to any of the above embodiments, a sealing adhesive film for covering a surface of the cell string, and a cover plate for covering a surface of the sealing adhesive film remote from the cell string. Effect of the Invention

[0024] The technical solutions provided in the embodiments of the present application have at least the following advantages:

[0025] Unlike the typical pyramid structure on the front surface of the N-type silicon substrate, the rear surface does not have a pyramid structure protruding from the horizontal plane, but has a number of grooves recessed from the horizontal plane. In this way, the rear surface with a number of grooves is flatter than the pyramid structure with a sharp top, and contributes to improving the film layer uniformity of the tunnel dielectric layer and the doped conductive layer formed on the rear surface, thereby improving the passivation effect on the N-type silicon substrate. On the other hand, the rear surface with a number of grooves increases the specific surface area of ​​the N-type silicon substrate, improves the specific surface area of ​​the tunnel dielectric layer and the doped conductive layer, increases the contact area between the electrode and the doped conductive layer and the tunnel dielectric layer, reduces the contact resistance between the electrode and the doped conductive layer and the tunnel dielectric layer, and contributes to improving the collection efficiency of the electrode for carriers. As a result, the combination of both is helpful in improving the short-circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell. [Brief description of the drawings]

[0026] One or more embodiments are illustratively described in the figures in the corresponding attached drawings, but these illustrative descriptions are not intended to limit the embodiments, and the parts indicated with the same reference numerals in the attached drawings are similar parts, and unless otherwise specified, the figures in the attached drawings are not limited to scale. In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below, but obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative labor. [Figure 1] FIG. 1 is a diagram showing a local cross-sectional structure of a solar cell provided in one embodiment of the present application. [Diagram 2] FIG. 2 is a schematic view of the back surface of an N-type silicon substrate provided in one embodiment of the present application, taken by an electron microscope. [Diagram 3] FIG. 3 is another electron microscope schematic diagram of the back surface of the N-type silicon substrate provided in one embodiment of the present application. [Figure 4]FIG. 4 is another electron microscope schematic diagram of the back surface of the N-type silicon substrate provided in one embodiment of the present application. [Diagram 5] FIG. 5 is another electron microscope schematic diagram of the back surface of the N-type silicon substrate provided in one embodiment of the present application. [Figure 6] FIG. 6 is a diagram showing a local cross-sectional structure of an N-type silicon substrate provided in one embodiment of the present application. [Figure 7] FIG. 7 is a diagram showing a local cross-sectional structure of a single trench in an N-type silicon substrate provided in one embodiment of the present application. [Figure 8] FIG. 8 is a diagram showing a top view structure of an upper opening in a single groove provided in one embodiment of the present application. [Figure 9] FIG. 9 is a diagram showing another top view structure of an upper opening in a single groove provided in one embodiment of the present application. [Figure 10] FIG. 10 is a diagram showing another local cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 11] FIG. 11 is a diagram showing another local cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 12] FIG. 12 is a diagram showing a local cross-sectional structure of an initial N-type silicon substrate provided in another embodiment of the present application. [Figure 13] FIG. 13 is a diagram showing a local cross-sectional structure of an initial N-type silicon substrate after a texture forming process provided in another embodiment of the present application. [Figure 14] FIG. 14 is a diagram showing a local cross-sectional structure of an initial N-type silicon substrate after second surface etching by a first etching process provided in another embodiment of the present application. [Figure 15] FIG. 15 is a diagram showing the structure of a photovoltaic module provided in another embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] As can be seen from the background art, the photoelectric conversion efficiency of solar cells needs to be further improved.

[0028] Analysis shows that a tunnel oxide layer and a highly doped N-type polycrystalline silicon layer are installed on the back surface of N-type TOPCon crystalline silicon solar cells to form a tunnel oxide passivation contact structure. The passivation performance and metal electrode contact effect of the film layer structure are highly dependent on the back surface of the substrate structure. At present, the back surface of the substrate structure mainly includes textured surface, acid polished surface, alkaline polished surface and other forms, and these forms respectively have the following problems:

[0029] In the case of the textured surface, the textured surface has a large specific surface area, and due to this excellent morphology, the electrode paste is easily sintered, and the electrode and the substrate structure form a good ohmic contact, so the textured surface has a great advantage in reducing the contact resistivity between the electrode and the substrate structure. However, if the specific surface area of ​​the textured surface is large, it is likely to lead to a large number of recombination sites on the back surface of the substrate structure, that is, to provide many recombination centers for the carriers, resulting in a decrease in the carrier collection efficiency of the electrode, and the tunnel oxide layer is difficult to distribute uniformly on the textured surface, resulting in a poor passivation effect on the back surface.

[0030] In the case of acid polishing, the textured surface is treated with a mixture of hydrofluoric acid and nitric acid to form a pyramid-like structure with a polished upper portion, which reduces the specific surface area to a certain extent and improves the passivation effect. However, the contact resistivity between the electrode and substrate structure increases significantly, and the high cost of the acid limits its further use.

[0031] In the case of an alkaline polished surface, the pyramid structure on the back side of the textured surface is removed by the alkaline polishing liquid, forming a square weave structure, and the specific surface area is significantly reduced, but the ultra-high back passivation effect compensates to a certain extent for the inferiority of the reduced contact resistivity, and with the development of electrode paste for alkaline polished surfaces, the inferiority of the back contact has been further alleviated. However, how to further optimize the back surface shape and improve the contact performance between the electrode and the substrate structure while simultaneously achieving back passivation performance is an issue that needs to be resolved as soon as possible.

[0032] The present application provides a solar cell, its manufacturing method, and a photovoltaic device. In the solar cell, the back surface with multiple small grooves is flatter than the pyramid structure with a sharp top, which improves the film layer uniformity of the tunnel dielectric layer and the doped conductive layer formed on the back surface, and contributes to improving the passivation effect on the N-type silicon substrate, while the back surface with multiple grooves increases the specific surface area of ​​the N-type silicon substrate, improves the specific surface area of ​​the tunnel dielectric layer and the doped conductive layer, increases the contact area between the electrode and the doped conductive layer and the tunnel dielectric layer, reduces the contact resistance between the electrode and the doped conductive layer and the tunnel dielectric layer, and contributes to improving the collection efficiency of the electrode for carriers. This combines both to improve the short-circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell.

[0033] Hereinafter, each embodiment of the present application will be described in detail with reference to the drawings. However, as will be understood by those skilled in the art, although many technical details are proposed in each embodiment of the present application in order to allow the reader to understand the present application better, the technical solution claimed for protection by the present application can be realized without these technical details and various changes and modifications based on the following embodiments.

[0034] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present application provides a solar cell. Hereinafter, the solar cell provided in the embodiment of the present application will be described in detail with reference to the drawings.

[0035] As shown in Figures 1 to 5, the solar cell includes an N-type silicon substrate 100 having an opposing front surface a and back surface b, a passivation layer 105 located on the front surface a, a tunnel dielectric layer 101 located on the back surface b, and a doped conductive layer 102 located on the tunnel dielectric layer 101, where the front surface a has a plurality of pyramid structures 120 and the back surface b has a plurality of grooves 110, some of the grooves 110 being arranged sequentially along the same direction.

[0036] 1 is a diagram showing a local cross-sectional structure of a solar cell provided in one embodiment of the present application, and the groove 110 on the back surface b is not shown because the dimension of the groove 110 is small. Fig. 2 is an electron microscope schematic (SEM) view of the back surface of an N-type silicon substrate provided in one embodiment of the present application, Fig. 3 is another electron microscope schematic (SEM) view of the back surface of an N-type silicon substrate provided in one embodiment of the present application, Fig. 4 is another electron microscope schematic (SEM) view of the back surface of an N-type silicon substrate provided in one embodiment of the present application, and Fig. 5 is another electron microscope schematic (SEM) view of the back surface b of an N-type silicon substrate 100 provided in one embodiment of the present application.

[0037] In some cases, in the N-type silicon substrate 100, unlike the front surface a having a typical pyramid structure, the horizontal plane e (see FIG. 6) on which the back surface b is located does not have a pyramid structure protruding from the horizontal plane e, but has a plurality of grooves 110 recessed from the horizontal plane. Note that the horizontal plane e on which the back surface b is located refers to the plane on which most of the surface of the back surface b excluding the grooves 110 is located in the entire N-type silicon substrate 100, and in FIG. 6, the horizontal plane e is indicated by a dotted line, and the horizontal plane e shown in FIG. 6 is only one example.

[0038] In this way, the back surface b with the multiple grooves 110 is flatter than a pyramid structure with a sharp top, and improves the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102 formed on the back surface b, which contributes to improving the passivation effect on the N-type silicon substrate 100. On the other hand, the back surface b with the multiple grooves 110 increases the specific surface area of ​​the N-type silicon substrate 100, improves the specific surface area of ​​the tunnel dielectric layer 101 and the doped conductive layer 102, increases the contact area between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, reduces the contact resistance between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, and contributes to improving the collection efficiency of the electrode for carriers. As a result, both are combined to help improve the short-circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell.

[0039] The electrodes, the doped conductive layer 102 and the tunnel dielectric layer 101 will be described in detail later.

[0040] Hereinafter, the embodiments of the present application will be described in more detail with reference to the drawings. In some embodiments, as shown in Figures 2 to 5, the plurality of grooves 110 includes N groove groups 130, each of which includes a plurality of grooves 110 arranged sequentially along the same direction, and the arrangement directions of the plurality of grooves 110 in different groove groups 130 may be the same or different, and N is a positive integer of 2 or more.

[0041] In other words, for any groove group 130, the multiple grooves 110 belonging to the groove group 130 are sequentially arranged along the same direction, which contributes to strengthening the regularity of the morphological change of the back surface b, further improving the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102 formed on the back surface b, and helps to improve the passivation effect on the N-type silicon substrate 100.

[0042] In addition, for different groove groups 130, the arrangement directions of the grooves 110 belonging to the different groove groups 130 may be the same or different. As an example, as shown in Fig. 2, one groove group 130 is marked as A and another groove group 130 is marked as B, the arrangement direction of the grooves 110 in groove group A is X1, and the arrangement direction of the grooves 110 in groove group B is X2, and the direction X1 and the direction X2 are different, i.e., the direction X1 and the direction X2 intersect, and in actual applications, the direction X1 and the direction X2 may be the same, i.e., the direction X1 and the direction X2 may be parallel to each other.

[0043] The same groove 110 can belong to at least two different groove groups 130. For example, as shown in Figure 2, another groove group is marked C, and groove group B and groove group C comprise the same groove 110, which is marked as B1 in Figure 2.

[0044] In addition, in Figures 2 to 5, groove group 130 is shown by a plurality of grooves 110 surrounded by a dotted line frame, and although Figures 2 to 5 only show some of groove groups 130, in actual applications, the number of groove groups 130 on back surface b includes groove groups 130 shown in dotted line frames, but is not limited to this, and any of the plurality of groove groups 130 may be groove group A or groove group B.

[0045] In some embodiments, as shown in FIG. 2, there is a gap between adjacent groove groups 130, in other words, the orthogonal projections of adjacent groove groups 130 on the N-type silicon substrate 100, for example, groove group A and groove group B in FIG. 2, do not overlap. In other embodiments, continuing to refer to FIG. 2, there is an overlap region 150 (see FIG. 6) between at least some of the grooves 110 in adjacent groove groups 130, in other words, the orthogonal projections of adjacent groove groups 130 on the N-type silicon substrate 100 overlap, and the overlapping portions of the orthogonal projections of adjacent groove groups 130, i.e., the orthogonal projections of the overlap region 150 on the N-type silicon substrate 100, for example, groove B1 of groove group B and groove C1 of groove group C in FIG. 2, have the overlap region 150. In other embodiments, continuing to refer to FIG. 2, there are multiple sets of groove groups 130 on the back surface b, there is a gap between some adjacent groove groups 130, and there is an overlap region 150 between at least some of the grooves 110 of the other adjacent groove groups 130.

[0046] FIG. 6 is a diagram showing a local cross-sectional structure of an N-type silicon substrate provided in one embodiment of the present application, and in FIG. 6, the portion where two adjacent trenches 110 overlap, i.e., the overlap region 150, is shown by closely spaced dotted lines.

[0047] In one example, as shown in FIG. 2, three different groove groups 130 are marked A, B, and C, respectively, where groove groups A and B are adjacent and have a gap between them, and groove groups B and C are adjacent and have an overlap region 150 between at least some of the grooves 110 of groove groups B and C (see FIG. 6).

[0048] Any of the multiple groove groups 130 may be groove group A, groove group B, or groove group C. Although Fig. 6 shows an example in which the overlapping region 150 is one three-dimensional region, in actual applications, two adjacent groove groups 130 are adjacent to each other, and in this case, the overlapping region 150 of the two adjacent groove groups 130 is one line or one plane.

[0049] The fact that there is an overlap region 150 between at least some of the grooves 110 in the adjacent groove groups 130 will be described in detail below.

[0050] In some embodiments, of two adjacent groove groups 130, one groove 110 in one groove group 130 and one groove 110 in the other groove group 130 include an overlap region 150. As an example, as shown in Figure 2, for adjacent groove groups B and C, one groove 110 in groove group B is marked as B1 and one groove 110 in groove group C is marked as C1, where groove B1 includes an overlap region 150 (see Figure 6) with only groove C1.

[0051] In some other embodiments, of two adjacent groove groups 130, one groove 110 in one groove group 130 and at least two grooves 110 in the other groove group 130 both include overlap regions 150. In one example, as shown in Figure 3, two adjacent groove groups 130 are marked D and E, respectively, one groove 110 in groove group D is marked D1, and two grooves 110 in groove group E are marked E1 and E2, respectively, and groove B1 includes overlap regions 150 with at least both groove E1 and groove E2 (see Figure 6).

[0052] It should be noted that for any groove group 130, adjacent grooves 110 in the groove group 130 may have overlap regions 150 between them or may be spaced apart from one another. For any groove 110 in any groove group 130, this groove 110 may be spaced apart from any other groove 110 or may have an overlap region 150 with at least one other groove 110.

[0053] In some embodiments, there is a gap between at least some two adjacent grooves 110, e.g., the two grooves 110 marked F and G as shown in Figure 2. In other embodiments, there is an overlap region 150 (see Figure 6) between at least some two adjacent grooves 110, e.g., the two grooves 110 marked I and J as shown in Figure 3. In other embodiments, there is a gap between some two adjacent grooves 110 and an overlap region 150 between some other two adjacent grooves 110, e.g., a gap between grooves F and G in Figure 2 and an overlap region 150 between grooves B1 and C1.

[0054] In addition, two adjacent grooves 110 may belong to the same groove group 130, or two adjacent grooves 110 may belong to two adjacent groove groups 130, respectively. Alternatively, at least one of the two adjacent grooves 110 is an independent groove 110, and this independent groove, for example, the groove 110 marked with F in FIG. 2, does not belong to any groove group 130. In addition, in the form of the back surface b in FIGS. 2 to 5, there is a gap between some two adjacent grooves 110 and there is an overlap region 150 between other two adjacent grooves 110, but in actual applications, there is a gap between any two adjacent grooves 110 in the form of the back surface b, or there is an overlap region 150 between any two adjacent grooves 110.

[0055] In some embodiments, as shown in Fig. 7, Fig. 7 is a diagram showing a local cross-sectional structure of a single groove 110 in an N-type silicon substrate 100 provided in one embodiment of the present application, in which in a direction Y away from the back surface b, the groove 110 has a bottom surface 110a and an upper opening 110b disposed opposite to each other, and a sidewall 110c located between the bottom surface 110a and the upper opening 110b, and the area of ​​the orthogonal projection of the bottom surface 110a on the N-type silicon substrate 100 is smaller than the area of ​​the orthogonal projection of the upper opening 110b on the N-type silicon substrate 100. In other words, in a direction away from the back surface b, the groove 110 has a structure that is wider at the top and narrower at the bottom, and in a cross section perpendicular to the bottom surface 110a, the cross-sectional shape of the groove 110 is an inverted trapezoid that is wider at the top and narrower at the bottom.

[0056] In FIG. 7, the region where the upper opening 110b is approximately located is indicated by a dotted line.

[0057] As a result, the upper opening 110b, which is larger in size than the bottom surface 110a, contributes to the tunnel dielectric layer filling the groove 110 uniformly, avoiding the formation of a gap between the groove 110 and the tunnel dielectric layer 101, and further avoiding the formation of a gap between the tunnel dielectric layer 101 and the doped conductive layer 102, further improving the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102 formed on the back surface b, reducing the number of composite sites formed on the back surface b, and enhancing the passivation effect on the N-type silicon substrate 100. Meanwhile, since the groove 110 has a structure that is wide at the top and narrow at the bottom, it is possible to further increase the specific surface area of ​​the N-type silicon substrate 100, further increase the specific surface area of ​​the tunnel dielectric layer 101 and the doped conductive layer 102, increase the contact area between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, reduce the contact resistance between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, and enhance the collection efficiency of the electrode for carriers.

[0058] In some embodiments, the ratio of the area of ​​the orthogonal projection of the bottom surface 110a on the N-type silicon substrate 100 to the area of ​​the orthogonal projection of the upper opening 110b on the N-type silicon substrate 100 is 0.5 to 0.99. For example, the ratio of the area of ​​the orthogonal projection of the bottom surface 110a on the N-type silicon substrate 100 to the area of ​​the orthogonal projection of the upper opening 110b on the N-type silicon substrate 100 is 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, or 0.9.

[0059] In some embodiments, the orthogonal projection of the groove 110 onto the N-type silicon substrate 100 has an M-sided polygon, where M is 2 or greater.

[0060] 2 to 5, the shape of the orthogonal projection of the groove 110 on the N-type silicon substrate 100 is often a quadrangle, but in practical applications, the shape of the orthogonal projection of the groove 110 on the N-type silicon substrate 100 may be a polygon other than a quadrangle. In some embodiments, the quadrangle includes a rectangle, a rhombus, a square, and a trapezoid, and also includes an irregular quadrangle.

[0061] In some embodiments, as shown in Figures 7 and 8, Figure 8 is a view showing a top view structure of an upper opening 110b in a single groove 110 provided in one embodiment of the present application, in which the groove 110 has an upper opening 110b, and a one-dimensional dimension L of the upper opening 110b is 1 μm to 20 μm in a direction Y away from the back surface b, for example, the one-dimensional dimension L may be 3 μm, 5 μm, 7 μm, 10 μm, 13 μm, 16 μm, or 19 μm, etc. As shown in Figure 7, the groove 110 has a bottom surface 110a disposed opposite to the upper opening 110b, and a sidewall 110c located between the bottom surface 110a and the upper opening 110b.

[0062] As shown in Fig. 8, the one-dimensional dimension L of the upper opening 110b includes any one of the length, width, or diagonal length of the upper opening 110b. Also, Fig. 8 shows an example in which the shape of the orthogonal projection of the upper opening 110b on the N-type silicon substrate 100 is a regular rectangle, and in this case, the one-dimensional dimension L of the upper opening 110b is any one of the length, width, or diagonal length of the regular rectangle.

[0063] In practical applications, the shape of the orthogonal projection of the upper opening 110b on the N-type silicon substrate 100 may be an irregular polygon, in which case the length, width, or diagonal length of the upper opening 110b is not absolute but is artificially defined to express the one-dimensional dimension of the upper opening 110b. For example, as shown in Fig. 9, which is a diagram showing another top view structure of the upper opening 110b in a single groove 110 provided in one embodiment of the present application, the shape of the orthogonal projection of the upper opening 110b on the N-type silicon substrate 100 is an irregular rectangle, in which the length L1 of the upper opening 110b is defined as the length of the longest side of the irregular rectangle, the width L2 of the upper opening 110b is defined as the length of the shortest side of the irregular rectangle, and the length L3 of the diagonal line of the upper opening 110b is defined as the length of the longest diagonal line of the irregular rectangle. It can be understood that the above is merely an exemplary description, which in practice can be flexibly defined according to actual needs.

[0064] Furthermore, the shape of the orthogonal projection of upper opening 110b on N-type silicon substrate 100 may be a circle or an irregular shape close to a circle, in addition to an irregular polygon. In this case, the one-dimensional dimension L of upper opening 110b can be determined by selecting a plurality of regions of different specific areas in upper opening 110b, flexibly defining the specific areas according to actual needs, and then calculating the average value of the length, width, diagonal, or diameter of the plurality of different specific areas.

[0065] In some embodiments, the distribution density of the grooves 110 on the back surface b is 100 pieces / mm 2 ~200,000 pieces / mm 2 In some examples, the distribution density of the grooves 110 on the back surface b is 1,000 pieces / mm 2 ~50,000 pieces / mm 2 For example, the distribution density of the grooves 110 is 1,850 pieces / mm 2 , 3,550 pieces / mm 2 , 6,500 pieces / mm 2 , 25,000 pieces / mm 2 , 34,000 pieces / mm 2, 45,000 pieces / mm 2 or 49,000 pieces / mm 2 etc. may be used.

[0066] In some embodiments, the maximum depth of the grooves 110 in the direction away from the back surface b is 50 nm to 2,000 nm. For example, the depth of the grooves 110 may be 65 nm, 87 nm, 500 nm, 650 nm, 1,200 nm, 1,400 nm, or 1,700 nm.

[0067] In some cases, the layout area occupied by a single groove 110 relative to the entire back surface b is very small, so compared with a pyramid structure with a sharp top, the impact of the groove 110 on the back surface b on the flatness of the back surface b is very small. The groove 110 increases the specific surface area of ​​the N-type silicon substrate 100 and ensures that the back surface b has high flatness. It increases the specific surface area of ​​the tunnel dielectric layer 101 and the doped conductive layer 102, increases the contact area between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, while improving the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102, and enhances the passivation effect of the tunnel dielectric layer 101 and the doped conductive layer 102 on the N-type silicon substrate 100.

[0068] The form of the back surface b will be described in detail below with reference to four examples.

[0069] In some embodiments, as shown in FIG. 2, the linear dimension of a single groove 110 is 2 μm to 8 μm, and the distribution density of the grooves 110 is 5,000 pieces / mm 2 ~200,000 pieces / mm 2 In the direction away from the back surface b, the maximum depth of the groove 110 is 200 nm to 2,000 nm.

[0070] In some other embodiments, as shown in FIG. 3, the one-dimensional dimension of a single groove 110 is 5 μm to 13 μm, and the distribution density of the grooves 110 is 100 pieces / mm 2 ~50,000 pieces / mm 2In the direction away from the back surface b, the maximum depth of the groove 110 is 50 nm to 1,200 nm.

[0071] In some other embodiments, as shown in FIG. 4, the one-dimensional dimension of a single groove 110 is 3 μm to 15 μm, and the distribution density of the grooves 110 is 100 pieces / mm 2 ~100,000 pieces / mm 2 In the direction away from the back surface b, the maximum depth of the groove 110 is 100 nm to 2,000 nm.

[0072] In some other embodiments, as shown in FIG. 5, the one-dimensional dimension of a single groove 110 is 7 μm to 20 μm, and the distribution density of the grooves 110 is 100 pieces / mm 2 ~20,000 pieces / mm 2 In the direction away from the back surface b, the maximum depth of the groove 110 is 50 nm to 1,000 nm.

[0073] In some embodiments, the passivation layer 105 located on the front surface a, as shown in FIG. 1, FIG. 10 or FIG. 11, can be considered as a front passivation layer or a front passivation layer. The passivation layer 105 may be a single layer structure or a multi-layer structure, and in the multi-layer structure, the materials of each layer may be different from each other, or the materials of some layers may be different from each other and the materials of the remaining parts may be the same. The material of the passivation layer 105 may be at least one of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide or aluminum oxide.

[0074] In some embodiments, the solar cell further includes a back surface passivation layer 106 located on the back surface b, as shown in Figure 10 or Figure 11, and the back surface passivation layer 106 can be considered as a rear passivation layer. The back surface passivation layer 106 in Figures 10 and 11 will be described in detail later, respectively.

[0075] In some embodiments, the back surface passivation layer 106 may include a single layer structure or a laminate structure, and the material of the back surface passivation layer 106 may include at least one of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0076] In some embodiments, as shown in Figure 10 or Figure 11, the solar cell further includes a P-type emitter 170, which can be considered as a part of the thickness of the N-type silicon substrate 100, and at least a part of the front surface a is the top surface of the P-type emitter 170. In some examples, as shown in Figure 10 or Figure 11, the entire front surface a is the top surface of the P-type emitter 170. In other examples, a part of the front surface a is the top surface of the P-type emitter 170, forming a selective emitter.

[0077] The type of doping element in the P-type emitter 170 is different from the type of doping element in the N-type silicon substrate 100, and the P-type emitter 170 and the N-type silicon substrate 100 form a PN junction.

[0078] In some embodiments, as shown in FIG. 10 or 11, the passivation layer 105 is located on the surface of the P-type emitter 170 away from the N-type silicon substrate 100, and has a good passivation effect on the front surface a of the N-type silicon substrate 100, so as to reduce the defect level density on the front surface a of the N-type silicon substrate 100 and effectively suppress the carrier recombination on the front surface a of the N-type silicon substrate 100. The passivation layer 105 also has a good anti-reflection effect, so as to reduce the reflection of the front surface a of the N-type silicon substrate 100 against the incident light, and to increase the utilization rate of the N-type silicon substrate 100 against the incident light. In some cases, the solar cell provided in an embodiment of the present application may be a TOPCon cell or an IBC cell.

[0079] In some embodiments, as shown in Figure 1, the solar cell may be a TOPCon (Tunnel Oxide Passivated Contact) cell, where the doped conductive layer 102 comprises an N-type doping element, and the doped conductive layer 102 covers a surface of the tunnel dielectric layer 101 away from the N-type silicon substrate 100. In other words, the doped conductive layer 102 and the N-type silicon substrate 100 comprise doping elements of the same conductivity type, and the doping concentration of the N-type doping element in the doped conductive layer 102 is higher than that in the N-type silicon substrate 100, forming a front-contact TOPCon cell.

[0080] 1, in some other embodiments, the solar cell may be a TOPCon cell, where the doped conductive layer 102 comprises a P-type doping element, and the doped conductive layer 102 covers a surface of the tunnel dielectric layer 101 remote from the N-type silicon substrate 100. In other words, the doped conductive layer 102 and the N-type silicon substrate 100 comprise doping elements of different conductivity types, forming a back-contact TOPCon cell.

[0081] In the above two embodiments, as shown in FIG. 11, FIG. 11 is a view showing another local cross-sectional structure of the solar cell provided in one embodiment of the present application, the solar cell further includes an electrode 103, the electrode 103 and the doped conductive layer 102 form an ohmic contact, and the doped conductive layer 102 and the tunnel dielectric layer 101 form a passivation contact structure. Note that FIG. 11 shows an example in which the electrode 103 is embedded in the doped conductive layer 102, but in practical applications, the electrode 103 may penetrate the doped conductive layer 102 and contact and electrically connect with the tunnel dielectric layer 101. In some embodiments, still referring to FIG. 11, the solar cell further includes a first electrode 104 that forms an ohmic contact with the front surface a. Note that the electrode 103 located on the back surface b can be regarded as a second electrode.

[0082] In some embodiments, the electrode 103 and the first electrode 104 can be formed by sintering a metal conductive paste. In some embodiments, the material of the electrode 103 and the first electrode 104 includes at least one of metallic materials such as silver, aluminum, copper, nickel, etc.

[0083] In the above two embodiments, as shown in FIG. 11, the back surface passivation layer 106 is located on the side away from the back surface b of the doped conductive layer 102, and the electrode 103 penetrates the back surface passivation layer 106.

[0084] In some other embodiments, as shown in FIG. 10, FIG. 10 is a diagram showing another local cross-sectional structure of the solar cell provided in an embodiment of the present application, the solar cell may be an IBC cell (Interdigitated Back Contact), the doped conductive layer 102 includes a first portion 112 and a second portion 122 spaced apart from each other, one of the first portion 112 and the second portion 122 has a doping element of the same conductivity type as the N-type silicon substrate 100, and the other has a doping element of a different conductivity type from the N-type silicon substrate 100. In other words, one of the first portion 112 and the second portion 122 is an N-type doped conductive layer, and the other is a P-type doped conductive layer. In this case, the tunnel dielectric layer 101 in contact with the N-type doped conductive layer also has an N-type doping element, and the tunnel dielectric layer 101 in contact with the P-type doped conductive layer also has a P-type doping element.

[0085] In some embodiments, as shown in FIG. 10, there is a gap or isolation structure (not shown) between the second portions 122, which provides automatic isolation between the different conductivity type regions and eliminates the effect of leakage current on the cell efficiency caused by the tunnel junction formed by the heavily doped P-type and N-type doped regions on the back surface of the IBC cell.

[0086] In some embodiments, with continued reference to FIG. 10, the back surface passivation layer 106 is located on a side of the first portion 112 and the second portion 122 away from the back surface b.

[0087] In some embodiments, the solar cell includes a first sub-electrode 113 electrically connected to the first portion 112 through the rear passivation layer 106, and a second sub-electrode 123 electrically connected to the second portion 122 through the rear passivation layer 106. Note that FIG. 10 shows an example in which the first sub-electrode 113 is embedded in the first portion 112 and the second sub-electrode 123 is embedded in the second portion 122. In practical applications, the first sub-electrode 113 may be in contact with the tunnel dielectric layer 101 through the first portion 112, and the second sub-electrode 123 may be in contact with the tunnel dielectric layer 101 through the second portion 122. In some embodiments, the first sub-electrode 113 and the second sub-electrode 123 may be formed by sintering a metal conductive paste. In some embodiments, the material of the first sub-electrode 113 and the second sub-electrode 123 includes at least one of metal materials such as silver, aluminum, copper, and nickel.

[0088] As described above, the back surface b with the multiple grooves 110 is flatter than the pyramid structure with a sharp top, and improves the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102 formed on the back surface b, which contributes to improving the passivation effect on the N-type silicon substrate 100. Meanwhile, the back surface b with the multiple grooves 110 increases the specific surface area of ​​the N-type silicon substrate 100, thereby improving the specific surface area of ​​the tunnel dielectric layer 101 and the doped conductive layer 102, increasing the contact area between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, reducing the contact resistance between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, and also contributing to improving the collection efficiency of the electrode for carriers. As a result, both are combined to help improve the short-circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell.

[0089] In another embodiment of the present application, a solar cell manufacturing method for forming the solar cell provided in the above embodiment is provided. Hereinafter, the solar cell manufacturing method provided in another embodiment of the present application will be described in detail with reference to the drawings. FIGS. 12 to 14 are diagrams showing cross-sectional structures corresponding to each step in the solar cell manufacturing method provided in another embodiment of the present application. Here, FIG. 12 is a diagram showing a local cross-sectional structure of an initial N-type silicon substrate provided in another embodiment of the present application, FIG. 13 is a diagram showing a local cross-sectional structure of an initial N-type silicon substrate after a texture forming process provided in another embodiment of the present application, and FIG. 14 is a diagram showing a local cross-sectional structure of an initial N-type silicon substrate after a second surface etching by a first etching step provided in another embodiment of the present application. Note that for the same or corresponding parts as those in the above embodiment, the corresponding explanations in the above embodiment can be referred to, and will not be repeated here.

[0090] As shown in FIGS. 1 to 14, the method for manufacturing a solar cell includes the following steps.

[0091] 12, an initial N-type silicon substrate 140 is provided, and the initial N-type silicon substrate 140 has a first surface c and a second surface d opposite to each other. In some embodiments, the initial N-type silicon substrate 140 is formed after a dicing process of a silicon wafer.

[0092] 13, a texture forming process is performed on the initial N-type silicon substrate 140 so as to form pyramid structures 120 on both the first surface c and the second surface d. This allows the first surface c on which the pyramid structures 120 are formed to become the front surface a of the N-type silicon substrate 100.

[0093] 13 and 14, the second surface d is etched in a first etching process to form an initial groove 160. Note that in other embodiments of the present application, the cross-sectional shape of the initial groove 160 is not limited, and FIG.

[0094] Step S104: As shown in any one of FIG. 14 and FIG. 2 to FIG. 5, in the second etching process, the second surface d is continuously etched to increase the dimension of the initial groove 160, thereby forming an N-type silicon substrate 100 having a groove 110, and some of the grooves 110 are sequentially arranged along the same direction, where the etching rate of the second surface d by the first etching process is smaller than the etching rate of the second surface d by the second etching process, and the first surface c on which the pyramid structure 120 is formed is the front surface a of the N-type silicon substrate 100, and the second surface d processed by the first etching process and the second etching process is the back surface b of the N-type silicon substrate 100.

[0095] Step S105: As shown in FIG. 1, a tunnel dielectric layer 101 and a doped conductive layer 102 are sequentially formed on the back surface b in a direction away from the back surface b.

[0096] In some cases, compared with the front surface a having the pyramid structure 120 with a sharp top, the back surface b having the multiple grooves 110 is flatter, which improves the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102 formed on the back surface b, and thus contributes to improving the passivation effect on the N-type silicon substrate 100. On the other hand, the back surface b having the multiple grooves 110 increases the specific surface area of ​​the N-type silicon substrate 100, which in turn improves the specific surface area of ​​the tunnel dielectric layer 101 and the doped conductive layer 102, increases the contact area between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, reduces the contact resistance between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, and also contributes to improving the collection efficiency of the electrode for carriers. This combines both to help improve the short-circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell.

[0097] Steps S101 to S105 will be described in detail below.

[0098] In some embodiments, as shown in FIG. 12, the material of the initial N-type silicon substrate 140 provided in step S101 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0099] In some embodiments, as shown in FIG. 13, performing a texture forming process on the initial N-type silicon substrate 140 in step S102 includes performing a double-sided texture forming process on the initial N-type silicon substrate 140. For example, the pyramid structure 120 is manufactured by wet chemical etching, and the pyramid structure 120 can reduce the reflection of light on the surface of the initial N-type silicon substrate 140, increase the light absorption utilization rate of the initial N-type silicon substrate 140, and improve the conversion efficiency of the solar cell. In addition, in another embodiment of the present application, the specific operation method of the texture forming is not limited. For example, the texture forming process can be performed by selecting a wet texture forming process, but is not limited thereto, and the texture forming process can be performed using an alkaline solution such as a sodium hydroxide solution. The corrosion of the sodium hydroxide solution is anisotropic, which contributes to the manufacture of a pyramidal microstructure. The pyramidal microstructure may be a structure such as a tetrahedron, an approximate tetrahedron, a pentahedron, or an approximate pentahedron. In addition, the texture forming process may be chemical etching, laser etching, a mechanical method, or plasma etching.

[0100] In some cases, when a metal paste is screen-printed to form the first electrode 104 (see FIG. 11 ), the pyramid structure 120 can allow the metal paste to be better filled into the pyramid structure 120, obtain better electrode contact, and effectively reduce the series resistance of the solar cell and increase the backing factor.

[0101] In some embodiments, after step S102 and before step S103, the manufacturing method further includes performing a doping process, such as a boron diffusion process, of P-type doping ions on the first surface c, thereby forming a P-type emitter 170 (see FIG. 10 ) on the first surface c, the P-type emitter 170 occupying a portion of the surface space toward the sun side of the initial N-type silicon substrate 140.

[0102] In some cases, the P-type emitter 170 may be a P-type doping layer formed by diffusing boron atoms to a certain depth in the first face c by a diffusion process using a boron source. For example, the boron source may be liquid boron tribromide. The microcrystalline silicon phase of the boron-diffused substrate is transformed into a polycrystalline silicon phase. Since the surface of the semiconductor substrate has a relatively high concentration of boron, a borosilicate glass layer (BSG) is usually formed on both the first face c and the second face d.

[0103] In some embodiments, from forming the P-type emitter 170 until before step S103, the manufacturing method further includes removing the borosilicate glass layer formed on the second surface d with a mixed acid, where the mixed acid can include a hydrofluoric acid solution having a mass fraction of 0.1% to 10%, a sulfuric acid solution having a mass fraction of 10% to 20%, and a nitric acid solution having a mass fraction of 25% to 50%, and washing and drying the second surface d after the acid cleaning.

[0104] In some cases, during the boron diffusion process, some borosilicate glass may be plated on the second surface d of the initial N-type silicon substrate 140, and it is this partial borosilicate glass layer that needs to be removed with the mixed acid.

[0105] In some embodiments, it takes 10 s to 180 s to remove the borosilicate glass layer formed on the second surface d with the prepared mixed acid, and the reaction temperature is 7°C to 20°C, i.e., the borosilicate glass layer on the second surface d is removed by acid cleaning at room temperature.

[0106] In some embodiments, as shown in FIGS. 13 and 14 , in step S103, the step of etching the second face d in a first etching process includes immersing the initial N-type silicon substrate 140 in a first etching solution, and with combined reference to FIGS. 14 and 15 , in step S104, the step of continuing to etch the second face d in a second etching process includes immersing the initial N-type silicon substrate 140 in a second etching solution, where the mass fraction of sodium hydroxide in the first etching solution is less than or equal to the mass fraction of sodium hydroxide in the second etching solution.

[0107] In some cases, the first etching step is performed to etch the second surface d mainly to reduce the size of the pyramid structures 120 on the second surface d, or to remove at least a part of the pyramid structures 120 to form the initial grooves 160. Note that, when the initial N-type silicon substrate 140 is textured on both sides to form the pyramid structures 120, the adjacent pyramid structures 120 are adjacent to each other or have a pitch. When the first etching step is performed to reduce the size of the pyramid structures 120 on the second surface d, the adjacent pyramid structures 120 are made to have a pitch, and the pitch is gradually increased until it is transformed into the initial grooves 160, thereby improving the shape of the second surface d.

[0108] Furthermore, the reason why the second surface d is continued to be etched in the second etching process is mainly to increase the size of the initial groove 160, to form the N-type silicon substrate 100 having the grooves 110, and to sequentially arrange a portion of the grooves 110 along the same direction. In other words, by continuing to etch the second surface d in the second etching process, the size of the pyramid structures 120 on the second surface d is further reduced, or at least a portion of the pyramid structures 120 is removed, to form more grooves 110, and to further increase the pitch between the adjacent pyramid structures 120, to increase the depth of the initial groove 160, and to contribute to forming a larger groove 110.

[0109] In some cases, some areas around the groove 110 have not changed from the pitch between adjacent pyramid structures 120, but rather the areas corresponding to the removed pyramid structures 120 have been further etched and changed, so the central area of ​​the groove 110 is exposed to the etching environment for a longer period of time, i.e., the area corresponding to the pitch between adjacent pyramid structures 120 is etched to a deeper degree, and some areas around the groove 110 are exposed to the etching environment for a shorter period of time, i.e., the area corresponding to the removed pyramid structures 120 is etched to a shallower degree, which contributes to forming the groove 110 having an inverted trapezoidal cross-sectional shape as shown in FIG. 7.

[0110] Furthermore, the mass fraction of sodium hydroxide in the first etching liquid is equal to or less than the mass fraction of sodium hydroxide in the second etching liquid, i.e., the alkalinity of the first etching liquid is lower than that of the second etching liquid, which contributes to the etching rate of the second surface d in the first etching step being lower than the etching rate of the second surface d in the second etching step. Note that means for making the etching rate of the second surface d in the first etching step lower than the etching rate of the second surface d in the second etching step include, but are not limited to, controlling the alkalinity of the first etching liquid to be lower than that of the second etching liquid.

[0111] In some embodiments, the mass fraction of sodium hydroxide in the first etching solution may be between 0.5% and 2%, and the mass fraction of sodium hydroxide in the second etching solution may be between 2% and 4%.

[0112] In some embodiments, both the first etching solution and the second etching solution contain a protective agent, and the mass fraction of the protective agent in the first etching solution is smaller than the mass fraction of the protective agent in the second etching solution. In some cases, the protective agent and the borosilicate glass layer can be mixed so that the borosilicate glass layer formed on the first surface c is not treated during the boron diffusion treatment, and the first etching solution and the second etching solution do not etch the pyramid structure 120 formed on the first surface c. In addition, the mass fraction of sodium hydroxide in the second etching solution is equal to or greater than the mass fraction of sodium hydroxide in the first etching solution, i.e., the second etching solution is more alkaline, and the mass fraction of the protective agent in the first etching solution is smaller than the mass fraction of the protective agent in the second etching solution, i.e., the mass fraction of the protective agent in the second etching solution is increased, which contributes to avoiding the etching of the pyramid structure 120 formed on the first surface by the second etching solution.

[0113] In some embodiments, the protective agent is an oxide layer protective agent.

[0114] In some embodiments, the mass fraction of the protective agent in the first etching solution is between 0.5% and 0.8%, and the mass fraction of the protective agent in the second etching solution is between 1% and 1.5%.

[0115] In some embodiments, the ambient temperature when etching the second surface d in the first etching step is a first temperature Temp1, the ambient temperature when etching the second surface d in the second etching step is a second temperature Temp2, and the first temperature Temp1 is lower than the second temperature Temp2. ​​In some cases, the higher the ambient temperature when etching the second surface d, the higher the etching rate of the second surface d in the etching step, so that the first temperature Temp1 being lower than the second temperature Temp2 contributes to the etching rate of the second surface d in the first etching step being lower than the etching rate of the second surface d in the second etching step.

[0116] In some embodiments, the first temperature Temp1 may be between 30°C and 45°C, and the second temperature Temp2 may be between 70°C and 85°C.

[0117] In addition, by adjusting the alkalinity of the first etching liquid and the alkalinity of the second etching liquid, or by adjusting the difference between the ambient temperature in the first etching step and the ambient temperature in the second etching step, the etching rate of the second surface d in the first etching step can be made smaller than the etching rate of the second surface d in the second etching step. In another embodiment of the present application, the adjustment of the etching rates in the first etching step and the second etching step includes, but is not limited to, the above two ideas.

[0118] In some embodiments, the etching time of the second surface d by the first etching step is a first time Time1, the etching time of the second surface d by the second etching step is a second time Time2, and the first time Time1 is equal to or greater than the second time Time2. In some cases, the etching time of the second surface d by the first etching step is longer and is mainly used to perform low-speed alkaline polishing on the second surface, remove most of the pyramid structures 120 on the second surface d, and form the grooves 110. The etching time of the second surface d by the second etching step is shorter and is mainly used to increase the depth of the initial grooves 160.

[0119] In some embodiments, the first time Time1 may be between 300s and 600s, and the second time Time2 may be between 50s and 300s.

[0120] The morphology of surface b after production will be described in detail below using four examples.

[0121] In some embodiments, to form the back surface b as shown in FIG. 2, the mass fraction of sodium hydroxide in the first etching solution is 0.5% to 2%, the mass fraction of sodium hydroxide in the second etching solution is 2% to 5%, the mass fraction of the protective agent in the first etching solution is 0.5% to 0.8%, the mass fraction of the protective agent in the second etching solution is 1% to 1.5%, the first temperature is 30° C. to 45° C., the second temperature is 70° C. to 85° C., the first time is 300 s to 400 s, and the second time is 150 s to 300 s.

[0122] In some other embodiments, to form rear surface b as shown in FIG. 3, the mass fraction of sodium hydroxide in the first etching solution is 0.5% to 2%, the mass fraction of sodium hydroxide in the second etching solution is 2% to 5%, the mass fraction of the protective agent in the first etching solution is 0.5% to 0.8%, and the mass fraction of the protective agent in the second etching solution is 1% to 1.5%, the first temperature is 30° C. to 45° C., the second temperature is 70° C. to 85° C., the first time is 400 s to 550 s, and the second time is 50 s to 200 s.

[0123] In some other embodiments, to form rear surface b as shown in FIG. 4, the mass fraction of sodium hydroxide in the first etching solution is 0.5% to 2%, the mass fraction of sodium hydroxide in the second etching solution is 2% to 5%, the mass fraction of the protective agent in the first etching solution is 0.5% to 0.8%, and the mass fraction of the protective agent in the second etching solution is 1% to 1.5%, the first temperature is 30° C. to 45° C., the second temperature is 70° C. to 85° C., the first time is 400 s to 550 s, and the second time is 100 s to 300 s.

[0124] In some other embodiments, to form rear surface b as shown in FIG. 5, the mass fraction of sodium hydroxide in the first etching solution is 0.5% to 2%, the mass fraction of sodium hydroxide in the second etching solution is 2% to 5%, the mass fraction of the protective agent in the first etching solution is 0.5% to 0.8%, and the mass fraction of the protective agent in the second etching solution is 1% to 1.5%, the first temperature is 30° C. to 45° C., the second temperature is 70° C. to 85° C., the first time is 450 s to 600 s, and the second time is 50 s to 200 s.

[0125] In addition, in the four examples of forming the four types of back surface b shown in Figures 2 to 5, the mass fraction of sodium hydroxide in the first etching solution, the mass fraction of sodium hydroxide in the second etching solution, the mass fraction of the protective agent in the first etching solution, the mass fraction of the protective agent in the second etching solution, the first temperature, and the second temperature may all be determined based on a unified standard, that is, the numerical values ​​of the above parameters in the four examples may be the same or may take numerical values ​​within the same numerical range, and only the etching time in the four examples may be differentiated, that is, the first time and the second time in the four examples may take different numerical values ​​or numerical ranges. In practical applications, in order to form the four different types of back surface b shown in Figures 2 to 5, the numerical values ​​and numerical ranges of the mass fraction of sodium hydroxide in the first etching solution, the mass fraction of sodium hydroxide in the second etching solution, the mass fraction of the protective agent in the first etching solution, the mass fraction of the protective agent in the second etching solution, the first temperature, the second temperature, the first time, and the second time can be flexibly adjusted according to actual needs.

[0126] In some embodiments, in step S105, forming the tunnel dielectric layer 101 and the doped conductive layer 102, as shown in FIG. 1, may include the following steps.

[0127] In some embodiments, the tunnel dielectric layer 101 is formed by a deposition process. Specifically, the material of the tunnel dielectric layer 101 includes silicon oxide, and the deposition process includes a chemical vapor deposition process. In other embodiments, the tunnel dielectric layer may be formed by an in situ generation process. Specifically, the tunnel dielectric layer 101 can be generated in situ on the basis of an N-type silicon substrate 100 by a thermal oxidation process, a nitric acid oxidation process, or the like.

[0128] In some embodiments, after forming the tunnel dielectric layer 101, intrinsic polysilicon is deposited to form a polysilicon layer, and phosphorus ions are doped by ion implantation and heat source diffusion to form an N-type doped polysilicon layer, and the N-type doped polysilicon layer is the doped conductive layer 102. In the direction X, the thickness of the doped conductive layer 102 can be set to 50 nm to 200 nm, for example, 100 nm, 120 nm, or 140 nm.

[0129] It should be noted that the above describes the manufacturing process of forming the tunnel dielectric layer 101 and the doped conductive layer 102 by taking the front-contact TOPCon cell as an example. In practical applications, the back-contact TOPCon cell or IBC cell can also be formed. In another embodiment of the present application, the manufacturing process of forming the tunnel dielectric layer 101 and the doped conductive layer 102 in the back-contact TOPCon cell or IBC cell is not limited.

[0130] In some embodiments, as shown in FIG. 10, the manufacturing method further includes forming a first sub-electrode 113 that forms an ohmic contact with the first portion 112, and forming a second sub-electrode 123 that forms an ohmic contact with the second portion 122. In another embodiment of the present application, the manufacturing process for forming the first sub-electrode 113 and the second sub-electrode 123 is not limited. In some other embodiments, as shown in FIG. 11, the manufacturing method further includes forming an electrode 103 that forms an ohmic contact with the doped conductive layer 102, and forming a first electrode 104 that forms an ohmic contact with the front surface a. In another embodiment of the present application, the manufacturing process for forming the electrode 103 and the first electrode 104 is not limited.

[0131] In some embodiments, as shown in FIG. 10 or 11, the manufacturing method further includes forming a passivation layer 105 located on the front surface a, and forming a back surface passivation layer 106 located on the side away from the back surface b of the doped conductive layer 102. In another embodiment of the present application, the manufacturing process of forming the passivation layer 105 and the back surface passivation layer 106 is not limited. As described above, the first etching process and the second etching process are sequentially performed on the second surface d of the initial N-type silicon substrate 140, and the etching rate of the second surface d by the first etching process is smaller than the etching rate of the second surface d by the second etching process, which contributes to forming the back surface b with a plurality of grooves 110, and the back surface b with the plurality of grooves 110 is flatter than the pyramid structure 120 with a sharp top, which contributes to improving the film layer uniformity of the tunnel dielectric layer 101 and the doped conductive layer 102 formed on the back surface b, and improving the passivation effect on the N-type silicon substrate 100. In addition, the back surface b having the multiple grooves 110 increases the specific surface area of ​​the N-type silicon substrate 100, which in turn increases the specific surface area of ​​the tunnel dielectric layer 101 and the doped conductive layer 102, increases the contact area between the electrode 103 and the doped conductive layer 102 and the tunnel dielectric layer 101, reduces the contact resistance between the electrode and the doped conductive layer 102 and the tunnel dielectric layer 101, and contributes to increasing the collection efficiency of the electrode for carriers. As a result, both of these are combined to contribute to improving the short-circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell.

[0132] Another embodiment of the present application further provides a photovoltaic module for converting received light energy into electrical energy. Figure 15 is a diagram showing the structure of a photovoltaic module provided in another embodiment of the present application. Note that for the same or corresponding parts as those in the above embodiment, reference can be made to the relevant description in the above embodiment. Here, the description will not be repeated.

[0133] 15, the photovoltaic module includes a cell string formed by connecting a plurality of solar cells 40 according to any of the above-mentioned embodiments or a plurality of solar cells 40 manufactured by the manufacturing method for a solar cell according to any of the above-mentioned embodiments, a sealing adhesive film 41 for covering a surface of the cell string, and a cover plate 42 for covering a surface of the sealing adhesive film 41 remote from the cell string. The solar cells 40 are electrically connected as a whole or in a form of a plurality of divisions to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or parallel.

[0134] Specifically, in some embodiments, the cell strings are electrically connected to each other by the conductive band 402. FIG. 15 shows only one type of positional relationship between solar cells, i.e., the electrodes of the battery cells with the same polarity are arranged in the same direction, or the electrodes with positive polarity of each battery cell are arranged on the same side, and the conductive band connects the different sides of two adjacent battery cells. In some embodiments, the battery cells can have electrodes with different polarities facing the same side, i.e., the electrodes of adjacent battery cells can be arranged in the order of first polarity, second polarity, first polarity, and the conductive band connects the two adjacent battery cells on the same side.

[0135] In some embodiments, there is no space between the battery cells, i.e., the battery cells overlap.

[0136] In some embodiments, the sealing adhesive film 41 includes a first sealing layer covering one of the front and back sides of the solar cell 40, and a second sealing layer covering the other of the front and back sides of the solar cell 40. Specifically, at least one of the first sealing layer or the second sealing layer may be an organic sealing adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0137] In some cases, the first sealing layer and the second sealing layer have a boundary line before lamination, but when forming a photovoltaic module after the lamination process, there is no concept of a first sealing layer and a second sealing layer, i.e., the first sealing layer and the second sealing layer form an integrated sealing adhesive film 41.

[0138] In some embodiments, the cover plate 42 may be a cover plate with a light-transmitting function, such as a glass cover plate, a plastic cover plate, etc. Specifically, the surface of the cover plate 42 facing the sealing adhesive film 41 may be an uneven surface to improve the utilization rate of the incident light. The cover plate 42 includes a first cover plate and a second cover plate, where the first cover plate faces the first sealing layer, and the second cover plate faces the second sealing layer.

[0139] Those skilled in the art will understand that the above embodiments are specific examples for implementing the present application, but that in practice, various changes in form and details are possible without departing from the spirit and scope of the embodiments of the present application. Since any person skilled in the art can make changes and modifications without departing from the spirit and scope of the embodiments of the present application, the scope of protection of the embodiments of the present application should be based on the scope limited by the claims.

Claims

1. an N-type silicon substrate having opposing front and back surfaces; a passivation layer located on said front surface; a tunnel dielectric layer located on the back surface; a doped conductive layer located in the tunnel dielectric layer; the front surface comprises a plurality of pyramid structures, the back surface comprises a plurality of grooves, some of the grooves are sequentially arranged along the same direction, a plane on which most of the surface of the entire back surface excluding the grooves is located is a horizontal plane, and the grooves are recessed with respect to the horizontal plane, wherein the plurality of grooves include N groove groups, each of the groove groups includes a plurality of the grooves sequentially arranged along the same direction, and there is an overlapping region between at least some of the grooves of the adjacent groove groups; A solar cell characterized by:

2. The arrangement directions of the grooves in the different groove groups are the same or different, and N is a positive integer of 2 or more. The solar cell according to claim 1 .

3. There is a space between adjacent grooves. The solar cell according to claim 2 .

4. At least two first grooves of the plurality of grooves are adjacent and spaced apart, and there is an overlap region between at least two second grooves of the plurality of grooves. The solar cell according to claim 1 .

5. In a direction away from the back surface, the groove has a bottom surface and an upper opening that are disposed opposite to each other, and a sidewall located between the bottom surface and the upper opening, and an area of ​​the bottom surface as an orthogonal projection on the N-type silicon substrate is smaller than an area of ​​the upper opening as an orthogonal projection on the N-type silicon substrate. The solar cell according to claim 1 .

6. The shape of the groove when orthogonally projected on the N-type silicon substrate is an M-sided polygon, where M is a positive integer of 3 or more. The solar cell according to claim 1 .

7. In a direction away from the back surface, the groove has an upper opening, and a one-dimensional dimension of the upper opening is 1 μm to 20 μm, and the one-dimensional dimension is an average value of a length, a width, a diagonal, or a diameter of a plurality of different specific areas of the upper opening. The solar cell according to claim 1 .

8. The distribution density of the grooves on the back surface is 1,000 pieces / mm ２ ~50,000 pieces / mm ２ That is, The solar cell according to claim 1 .

9. In a direction away from the back surface, the maximum depth of the groove is 50 nm to 2,000 nm. The solar cell according to claim 1 .

10. the doped conductive layer comprises an N-type doping element, and the doped conductive layer covers a surface of the tunnel dielectric layer remote from the N-type silicon substrate; The solar cell according to claim 1 .

11. the doped conductive layer comprises a P-type doping element, and the doped conductive layer covers a surface of the tunnel dielectric layer remote from the N-type silicon substrate; The solar cell according to claim 1 .

12. the doped conductive layer includes a first portion and a second portion spaced apart from each other, one of the first portion and the second portion comprising a doping element of the same conductivity type as the N-type silicon substrate, and the other of the first portion and the second portion comprising a doping element of a conductivity type different from that of the N-type silicon substrate; The solar cell according to claim 1 .

13. A cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 12; a sealing adhesive film for covering a surface of the cell string; and a cover plate for covering a surface of the sealing adhesive film away from the cell string. A photovoltaic module comprising:

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