Heat dissipation substrate for power semiconductor module, power semiconductor module including the heat dissipation substrate, and power converter including the power semiconductor module

Abstract

To provide a ceramic substrate for a heat dissipation substrate, capable of preventing an occurrence of warpage of the heat dissipation substrate due to a difference in each coefficient of thermal expansion of an insulating substrate, an upper metal plate, and a lower metal plate that make up the heat dissipation substrate, a heat dissipation substrate for a power semiconductor module, a power semiconductor module including the same, a power converter including the power semiconductor module, and a method of manufacturing the same.SOLUTION: In a power semiconductor module 502, a heat dissipation substrate 410B includes a first metal plate MP1, an insulating substrate SS bonded onto the first metal plate, and a second metal plate MP2 bonded onto the insulating substrate. A first thickness T1 of the first metal plate may be different from a second thickness T2 of the second metal plate. The first thickness of the first metal plate may be thinner than the second thickness of the second metal plate. The first metal plate includes a circuit pattern CP1 electrically connected to a predetermined power semiconductor element 100, and the second metal plate includes a marked unique code.SELECTED DRAWING: Figure 2c

Description

[Technical field]

[0001] The embodiments relate to a ceramic substrate for a heat dissipation substrate, a heat dissipation substrate for a power semiconductor module, a power semiconductor module including the same, a power conversion device including the same, and a method for manufacturing the same. [Background technology]

[0002] A power conversion module is a device that performs the functions of power conversion (AC → DC, DC → AC), power transformation (step-down, step-up), power distribution, or power control. It is a core component that improves energy efficiency during the power transmission and control process, controls voltage changes, and provides system stability and reliability. It is also called a power module or power system.

[0003] The power conversion module includes various components such as a power semiconductor element, a heat dissipation substrate, a base plate, molding silicon, a case and cover, and a terminal.

[0004] Recently, electric or hydrogen-based eco-friendly vehicles have been gaining attention as an alternative to fossil fuel-based internal combustion engine vehicles, and many power semiconductor elements are used in these eco-friendly vehicles. Eco-friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), fuel cell electric vehicles (PCEVs), etc.

[0005] In addition to eco-friendly cars, power semiconductors are also used in a variety of electric and electronic devices, such as electric car chargers, energy storage devices, power supply devices, and trains.

[0006] Silicon (Si) power semiconductor elements have been widely used in the past, but as Si power semiconductors have reached their physical limits, active research is being conducted into WBG (Wide Bandgap) power semiconductors such as Silicon Carbide (SiC) or Gallium Nitride (GaN) to address these limitations.

[0007] WBG power semiconductor elements have about three times the band gap energy of Si power semiconductor elements, about ten times higher dielectric breakdown field than Si power semiconductor elements, and about three times higher thermal conductivity than Si power semiconductor elements. These excellent characteristics allow them to operate in high temperature and high voltage environments, and they have the advantages of high switching speed and low switching loss.

[0008] For example, conventional Si-based power semiconductor modules used for power conversion (DC⇔motor drive switching, control, etc.) in electric vehicles, hybrid electric vehicles, etc. have been operated in a temperature environment of around 150°C. However, due to the recent demand for increased switching performance and power density, active research is being conducted on wide bandgap (WBG)-based power semiconductor elements such as SiC or GaN that can operate at temperatures of around 300°C or higher, for example, around 300~700°C.

[0009] Meanwhile, heat generated in the power semiconductor generates thermo-mechanical stress in each part of the power semiconductor module, and thermal fatigue of the junctions reduces the life span of the junctions and the power semiconductor elements. Therefore, it is very important to design the reliability of the power semiconductor module to properly dissipate the heat generated in the power semiconductor elements through the heat dissipation board and maintain the junction temperature of the power semiconductor elements below an appropriate temperature.

[0010] Meanwhile, a heat dissipation substrate for a power semiconductor not only transfers heat generated during the operation of the power semiconductor device to the outside, but also has an important function of electrically connecting the power semiconductor device by forming a circuit pattern on one side of the heat dissipation substrate.

[0011] Conventionally, heat dissipation substrates for power semiconductors can be classified into DBC (direct bonded copper) method and AMB (active metal brazing) method depending on the bonding method. The DBC method is a method in which an oxide film is formed on the copper (Cu) layer and then directly bonded to the ceramic. The AMB method is a method in which a paste containing metal particles with a relatively low melting point is placed between the base metal and ceramic as an intermediate material and then brazed.

[0012] Recently, high voltage / high power SiC power conversion modules of 1200V, 200A class have been used to improve the performance of hybrid and electric vehicles and autonomous vehicles. During the operation of such high performance electric vehicles, the operating temperature of power semiconductor devices is required to be 300°C or more on average, and they are facing ultra-high temperature usage conditions with momentary maximum operating temperatures of 350°C or more.

[0013] In such an operating environment of ultra-high temperature, high voltage and high current, the existing bonding material itself re-melts and pores in the bonding area cause a heat trap phenomenon, rapidly shortening the lifespan of the power semiconductor module.

[0014] For example, cracks occur due to defects induced at the interface between the ceramic substrate of the heat dissipation board and the copper (Cu) sheet, and such cracks induced in the heat dissipation board can cause thermal runaway, leading to the destruction of the power semiconductor device.

[0015] For example, if the heat dissipation performance of the heat dissipation board is reduced due to cracks or other reasons, the temperature of the case and surroundings of the power semiconductor module will rise. At this time, if the heat generated by the sudden temperature rise exceeds the heat dissipation performance (heat generation state > heat dissipation performance), the thermal design will no longer be able to maintain a state of thermal equilibrium (heat generation state < heat dissipation performance), and the heat generation will continue to increase. As a result, the leakage current will continue to increase, eventually destroying the power semiconductor module itself.

[0016] In particular, when degradation of the power semiconductor module occurs in an ultra-high operating temperature environment, the destruction of the power semiconductor elements due to malfunction of the power semiconductor module installed in the vehicle can have a serious impact on the safety of the driver.

[0017] Meanwhile, in the field of heat dissipation boards, the delivery thickness of substrates including ceramic substrates is not uniform, and the delivery thickness of metal plates, such as copper plates, is also not uniform. In this situation, the final heat dissipation board must meet strict delivery standards for heat dissipation boards, but it is difficult to produce heat dissipation boards that meet strict thickness specifications.

[0018] Meanwhile, FIG. 1 is a photograph showing that warpage WP occurs after the AMB heat dissipation substrate according to the prior art is bonded to a base plate BP.

[0019] The thermal expansion coefficients (CTE) of the insulating substrate, copper plate, and SiC that make up the heat dissipation substrate are significantly different. For example, the thermal expansion coefficient of the AlN insulating substrate SS is 4.5×10 -6 / ℃, and the thermal expansion coefficient of copper (T-Cu, B-Cu) is 16.0×10 -6 / ℃, and the thermal expansion coefficient of SiC is 4.0×10 -6 / ℃.

[0020] When warpage WP occurs due to differences in thermal expansion coefficients of components constituting a power semiconductor module in an ultra-high operating temperature environment of 300° C. or more, the power semiconductor module may malfunction.

[0021] In the prior art, the only approach to prevent warpage caused by the difference in thermal expansion coefficient was to design a heat sink or control the temperature of the cooling water.

[0022] In terms of internal technology, research had been conducted into the selection of materials for the insulating substrate and metal plate that make up the heat dissipation board, but the thickness ratios of the insulating substrate, upper metal plate, and lower metal plate that make up the heat dissipation board had not been considered or researched.

[0023] Meanwhile, internal research has found that the thicker the metal plate on the heat dissipation board, the greater the distance between circuit patterns. For example, if the Cu plate is about 0.2 mm thick, the separation distance between circuit patterns is about 0.4 mm, but if the Cu plate is about 0.4 mm thick, the separation distance between circuit patterns is about 0.6 mm.

[0024] In the internal technology, the thickness of the metal plates bonded to the top and bottom of the heat dissipation board was controlled within a certain range, and the metal plates were etched to ensure an average separation distance.

[0025] Meanwhile, in order to realize a high-performance power semiconductor element, multiple SiC power semiconductors are mounted on a heat dissipation substrate, which requires a complex circuit pattern. If the separation distance between the circuit patterns is increased more than necessary, it may be difficult to realize a high-density power semiconductor module.

[0026] In addition, internal research has revealed that when performing Transient Liquid Phase Bonding (TLP), the metal plate material of the heatsink substrate is consumed to form an IMC (intermetallic compound), which results in an insufficient IMC bonding layer, resulting in reduced bonding strength and the occurrence of pores.

[0027] In a power semiconductor module that operates at extremely high temperatures, a decrease in the adhesive strength between a power semiconductor element and a heat dissipation substrate or the presence of pores at the bonding interface significantly affects the performance degradation and reliability of the power semiconductor module.

[0028] Furthermore, in the conventional heat dissipation board industry, overall production information and quality information and history, such as thickness information of insulating substrates such as ceramic substrates, inspection information, thickness information of copper plates, surface information, and interface information after the bonding process, are not accurately aligned and managed for each "individual heat dissipation board."

[0029] On the other hand, particularly in cases where the present invention is applied to an insulating substrate such as a ceramic substrate, which is an internal technology in which metal sputtering is performed on the insulating substrate, followed by a copper plate and hot pressing process, even if a predetermined code is marked on the insulating substrate, the code is blocked by the sputtering process and the subsequent hot pressing process, and therefore it is not possible to attempt to mark a separate code on each of the "individual heat dissipation substrates."

[0030] On the other hand, the internal technology relied on manual labor for the lamination process of insulating substrates and metal plates. However, when the lamination process is done manually, it is difficult to consider the consistency of the thickness between each insulating substrate and metal plate, and even the placement of the metal plates on the upper and lower sides of the insulating substrates is not easy to control.

[0031] In particular, in the internal technology, the stacked set of the heat dissipation board includes an insulating substrate and metal plates arranged above and below, and in order to realize a high degree of stacking, with the number of stacked sets reaching tens to 100, the alignment of the insulating substrate and the metal plate has been studied as a very difficult technical challenge. Summary of the Invention [Problem to be solved by the invention]

[0032] One of the technical objectives of the embodiment is to solve the problem that it is difficult to meet the strict thickness specifications of the final heat dissipation substrate when the delivered thickness of insulating substrates such as ceramic substrates is not constant and the delivered thickness of metal plates is also not constant.

[0033] In addition, one of the technical objectives of the embodiment is to solve the problem of warpage of the heat dissipation substrate caused by the difference in thermal expansion coefficients of the insulating substrate, the upper metal plate, and the lower metal plate that make up the heat dissipation substrate.

[0034] In addition, one of the technical objectives of the embodiment is to solve the problem that it is difficult to realize a high-density power semiconductor module when the separation distance between circuit patterns is wider than necessary in a situation where a complex circuit pattern is required due to multiple SiC power semiconductors being mounted on a heat dissipation substrate to realize a high-performance power semiconductor element.

[0035] In addition, one of the technical objectives of the embodiment is to solve the problem that the metal plate material of the heat dissipation substrate is consumed to form an IMC (intermetallic compound) when performing Transient Liquid Phase Bonding (TLP), resulting in an insufficient IMC bonding layer, resulting in reduced bonding strength and the occurrence of pores.

[0036] Also, one of the technical objectives of the embodiment is to solve the problem of cracks occurring at the bonding interface of the heat dissipation substrate.

[0037] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]

[0038] A heat dissipation substrate for a power semiconductor module according to an embodiment includes a first metal plate, an insulating substrate bonded onto the first metal plate, and a second metal plate bonded onto the insulating substrate, and a first thickness of the first metal plate may be different from a second thickness of the second metal plate.

[0039] The first thickness of the first metal plate may be less than the second thickness of the second metal plate.

[0040] The first metal plate may include a circuit pattern electrically connected to a predetermined power semiconductor element, and the second metal plate may include a unique code marked thereon.

[0041] In addition, the heat dissipation substrate for a power semiconductor module in the embodiment includes a second metal plate, an insulating substrate joined onto the second metal plate, and a third metal plate joined onto the insulating substrate, and the third thickness of the third metal plate may be thicker than the second thickness of the second metal plate.

[0042] The third metal plate may include a circuit pattern electrically connected to a predetermined power semiconductor element, and the second metal plate may include a unique code marked thereon.

[0043] The unique code may include thickness information of at least one of the insulating substrate or the first and second metal plates.

[0044] The device may further include a unique ID marked on the first metal plate or the second metal plate.

[0045] A power semiconductor module according to an embodiment includes a first heat dissipation substrate, a power semiconductor element arranged on the first heat dissipation substrate, and a second heat dissipation substrate arranged on the power semiconductor element, and the first heat dissipation substrate or the second heat dissipation substrate may include any one of the heat dissipation substrates for a power semiconductor module described above.

[0046] The first heat dissipation substrate or the second heat dissipation substrate may include any one of the heat dissipation substrates for a power semiconductor module described above, and the embodiment may further include a power semiconductor element bonded to the circuit pattern of the first metal plate.

[0047] Also, the embodiment may include a bonding layer bonded between the circuit pattern of the first metal plate and the power semiconductor element by any one of sintering, soldering, and ultrasonic bonding.

[0048] The first heat dissipation substrate or the second heat dissipation substrate may include any one of the heat dissipation substrates for a power semiconductor module described above, and the embodiment may further include a power semiconductor element bonded to the circuit pattern of the third metal plate.

[0049] The embodiment may also include a bonding layer bonded between the circuit pattern of the third metal plate and the power semiconductor element by a phase change bonding method.

[0050] Moreover, a power conversion device according to the embodiment may include any one of the power semiconductor modules described above.

[0051] In addition, the insulating substrate for heat dissipation substrate of the embodiment may include an effective area AA of the insulating substrate, a dummy area DA of the insulating substrate arranged on the periphery of the effective area AA, and a unique code UC marked on the dummy area DA of the insulating substrate.

[0052] The embodiment may further include a unique ID marked on the dummy area DA of the insulating substrate.

[0053] The unique ID may include a combination of numbers, a combination of letters, or a combination of numbers and letters.

[0054] The unique code UC may include a rectangular or square shape.

[0055] The apex of the unique code and the apex of the effective area may be disposed so as to face each other.

[0056] The minimum distance between the unique code and the effective area AA of the insulating substrate may be the distance between the apex of the unique code and the apex of the effective area.

[0057] The unique code UC may be disposed such that a corner of the unique code UC faces a vertex of the effective area that is most adjacent to the unique code.

[0058] A heat dissipation substrate for a power semiconductor module according to an embodiment may include a first metal plate, an insulating substrate bonded onto the first metal plate, and a second metal plate bonded onto the insulating substrate.

[0059] A unique code may be included marked on the first metal plate or the second metal plate.

[0060] The second metal plate is electrically connected to a predetermined power semiconductor element.

[0061] A unique code may be provided on the first metal plate.

[0062] The first metal plate and the second metal plate may have different thicknesses.

[0063] Also, a power semiconductor module according to the embodiment can include a first heat dissipation substrate, a power semiconductor element disposed on the first heat dissipation substrate, and a second heat dissipation substrate disposed on the power semiconductor element.

[0064] The first heat dissipation substrate or the second heat dissipation substrate may include any one of the heat dissipation substrates for power semiconductors described above.

[0065] The second metal plate is electrically connected to the power semiconductor device, and a unique code is provided on the first metal plate.

[0066] The first metal plate and the second metal plate may have different thicknesses.

[0067] Moreover, a power conversion device according to the embodiment may include any one of the power semiconductor modules described above. Effect of the Invention

[0068] According to the embodiment, there is a technical effect that the occurrence of warpage of the heat dissipation board can be prevented by taking into consideration the thickness ratio of the insulating board, the upper metal plate, and the lower metal plate that constitute the heat dissipation board.

[0069] Furthermore, according to the first heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded onto the first surface of the insulating substrate SS facing the power semiconductor element 100 can be controlled to be equal to or smaller than the second thickness T2 of the second metal plate MP2 bonded onto the second surface of the insulating substrate.

[0070] According to the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor element 100 can be controlled to be thin, thereby ensuring a small separation distance PD between the first circuit patterns CP1 of the first metal plate MP1, thereby providing a high-density power semiconductor module.

[0071] In addition, according to the third embodiment, the third thickness T3 of the third metal plate MP3 to be bonded to the power semiconductor element 100 can be controlled to be thick, and the third thickness T3 of the third circuit pattern CP3 of the third metal plate MP3 can also be controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2. This provides a special technical effect of preventing the problem of the metal plate material of the heat dissipation substrate being consumed during the formation of the IMC when performing transient liquid phase bonding between the power semiconductor element 100 and the third metal plate MP3, improving the bonding strength, and solving the problem of pores being generated at the bonding interface.

[0072] In addition, according to the embodiment, there is a technical effect that overall production and quality information and history in the manufacture of heat dissipation substrates, such as thickness information of insulating substrates such as ceramic substrates, inspection information, thickness information of copper plates, surface information, and bonding interface information after the bonding process, can be accurately matched, updated, and managed for each "individual heat dissipation substrate."

[0073] For example, according to an embodiment, unique information is marked on a dummy area of ​​an insulating substrate such as an initial ceramic substrate during the manufacturing process of a heat dissipation substrate, and the unique information is stored and managed in a central server, thereby providing a special technical effect that overall production information, quality information, and history in the manufacturing process of a heat dissipation substrate can be accurately matched, updated, and managed for each of the "individual insulating substrates," "individual metal plates," and "individual heat dissipation substrates."

[0074] In addition, according to the embodiment, even if the position or arrangement of the insulating substrate changes due to an operator's error during the manufacturing process, the application of the embodiment has a technical effect that the history of all processes, from the initial receipt of each insulating substrate, such as the cleaning stage and hot pressing, can be perfectly updated and managed by checking the unique information of each insulating substrate.

[0075] In addition, according to the embodiment, the unique information that can confirm the information on the history of all processes from the initial storage stage of the product is perfectly matched with the final product and delivered to the customer, and the customer can accurately understand and use the quality and production history of the product from the unique information and can quickly and accurately request after-sales service when necessary.

[0076] On the other hand, simply marking product information on the heat dissipation substrate of the final product does not allow for perfect consistency and management of film formation information such as thickness information of the insulating substrate, thickness information of the metal plate, and bonding interface information that make up the product.

[0077] In addition, according to the embodiment, there is a technical effect that the thickness distribution can be minimized by classifying the individual insulating substrates and metal plates according to thickness and matching each thickness grade.

[0078] For example, according to the embodiment, insulating substrates are classified and loaded into first to third substrate magazines CM1, CM2, and CM3 according to thickness, and thickness and classification loading information for each insulating substrate and each substrate magazine is stored and managed in the upper server. Also, information about which substrate magazine each insulating substrate SS is loaded in is accurately updated and managed in the unique information UC of each insulating substrate SS.

[0079] This has the technical effect of optimizing the quality of the thickness of the heat dissipation substrate by reading the unique IDs of the first to third substrate magazines CM1, CM2, and CM3 in the lamination process performed after the sputtering process, and aligning the lamination and bonding processes with the metal plate for each thickness.

[0080] In addition, the embodiment closely measures and manages the thicknesses of the insulating substrate and the copper plate, which are delivered in various thicknesses, and perfectly manages such thickness information, so that each product can be matched through unique information. Therefore, there is a technical effect that thickness distribution can be minimized based on such unique information.

[0081] For example, according to the embodiment, the thicknesses of insulating substrates and metal plates delivered in various thicknesses are carefully measured and managed, and each thickness information is completely updated and managed so as to match the product specifications required by each customer company using unique information UC. Based on the unique information UC, an optimal lamination set combination of insulating substrates and metal plates is calculated and laminated, and then hot press fixing is performed, thereby providing a special technical effect of providing a heat dissipation substrate that is perfectly compatible with strict thickness specifications, and a power semiconductor module, insulating substrate and copper substrate lamination system having the same.

[0082] Furthermore, the embodiment has a technical effect of providing an automatic alignment lamination apparatus capable of automatically laminating and aligning an insulating substrate and a metal plate.

[0083] For example, the "automatic alignment stacking system 800" according to the embodiment can perform automatic stacking and hot press bonding processes for several tens to more than 100 sets.

[0084] In particular, according to the embodiment, the bottom surface of the lamination unit 850 has a tilted structure, which provides a special technical effect of enabling precise automatic alignment of corners of the spacer, metal plate, and insulating substrate that are sequentially laminated. For example, according to the embodiment, the tilted lamination provides a special technical effect of innovatively improving the accuracy of vertical alignment by utilizing gravity.

[0085] This allows for precise automatic alignment when tens to over 100 sets are automatically stacked, and even in the hot press bonding process that weighs over tens of tons, accurate alignment is maintained and there is no misalignment in the stacked sets, resulting in a special technical effect of enabling the realization of a high-quality heat dissipation substrate.

[0086] In addition, the embodiments have a technical effect of solving the problem of cracks occurring at the bonding interface of the heat dissipation substrate. For example, the embodiments can prevent cracks from occurring at the interface between the insulating substrate and the copper sheet of the heat dissipation substrate, thereby improving the reliability of the power semiconductor device.

[0087] The technical effects of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Brief description of the drawings]

[0088] [Figure 1] FIG. 1 is a photograph showing warpage that occurred after the AMB heat dissipation substrate according to the prior art was bonded to a base plate BP. [Figure 2a] FIG. 2a is a cross-sectional view of a power semiconductor module 500 including a heat dissipation substrate for a power semiconductor according to an embodiment. [Figure 2b]FIG. 2b is a manufacturing process diagram of a power semiconductor module 501 including a heat dissipation substrate for a power semiconductor according to the first embodiment. [Figure 2c] FIG. 2c is a manufacturing process diagram of a power semiconductor module 502 including a heat dissipation substrate for a power semiconductor according to the second embodiment. [Figure 2d] FIG. 2d is a manufacturing process diagram of a power semiconductor module 503 including a heat dissipation substrate for a power semiconductor according to the third embodiment. [Figure 3a] FIG. 3a is a first cross-sectional view of a power semiconductor device 100 according to an embodiment. [Figure 3b] FIG. 3b is a second cross-sectional view of the power semiconductor device 100 according to the embodiment. [Figure 4] FIG. 4 is a flow chart of a process for manufacturing a heat dissipation substrate for power semiconductors according to the embodiment. [Figure 5a] FIG. 5a is a diagram relating to the pretreatment process of the insulating substrate. [Figure 5b] FIG. 5b is a diagram relating to the pretreatment process of the insulating substrate. [Figure 6] FIG. 6 is a diagram relating to a pretreatment process for an insulating substrate. [Figure 7] FIG. 7 is a diagram relating to a pretreatment process for an insulating substrate. [Figure 8] FIG. 8 is a diagram relating to a pretreatment process for an insulating substrate. [Figure 9] FIG. 9 is a diagram showing a sputtering process for an insulating substrate according to an embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing a sputtering process for an insulating substrate according to the embodiment. [Figure 11] FIG. 11 is a diagram showing a sputtering process for an insulating substrate according to an embodiment of the present invention. [Figure 12] FIG. 12 is a diagram showing a sputtering process for an insulating substrate according to the embodiment. [Figure 13] FIG. 13 is a diagram of a metal magazine MM into which metal plates classified according to thickness are loaded. [Figure 14] FIG. 14 is a schematic diagram of an automatic alignment and lamination system 800 for insulating substrates and metal plates according to an embodiment. [Figure 15] FIG. 15 is a schematic diagram of an automatic alignment and lamination system 800 for insulating substrates and metal plates according to an embodiment. [Figure 16] FIG. 16 is a flow chart of the lamination process of an insulating substrate and a metal plate. [Figure 17] FIG. 17 is a conceptual diagram of a stack set stacked in a stack unit. [Figure 18] FIG. 18 is a diagram relating to the hot press joining process of the embodiment. [Figure 19a] FIG. 19a is a diagram relating to the hot press joining process of the embodiment. [Figure 19b] FIG. 19b is a diagram relating to the hot press joining process of the embodiment. [Figure 20] FIG. 20 is a diagram relating to the inspection process and etching process of the heat dissipation board. [Figure 21] FIG. 21 is a diagram relating to a laser scribing process, an inspection process, and a cutting process for a heat dissipation substrate. [Figure 22] FIG. 22 is a diagram relating to a laser scribing process, an inspection process, and a cutting process for a heat dissipation substrate. [Diagram 23] FIG. 23 is a circuit diagram of a power conversion device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0089] Hereinafter, the invention according to the embodiment for solving the above problems will be described in more detail with reference to the drawings.

[0090] The suffixes "module" and "section" for components used in the following description are merely given to facilitate the writing of the specification and do not impart any particular significance or role to them. Therefore, the terms "module" and "section" can be used interchangeably.

[0091] Although terms including ordinal numbers such as first, second, etc. may be used to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from another component.

[0092] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0093] In this application, the terms "including," "having," or "comprising" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but are not to be understood as precluding the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0094] In the embodiment, the power semiconductor module can be used in inverters, converters, etc. of automobiles, computers, home appliances, solar power, smart grids, etc. In addition, the power semiconductor module according to the embodiment can be applied to various electric and electronic devices such as electric vehicle chargers, power supply devices, and railways in addition to eco-friendly automobiles.

[0095] In addition, the heat dissipation substrate for power semiconductors according to the embodiments can be mounted and used in power semiconductor modules employed in inverters and converters for automobiles, computers, home appliances, solar power, smart grids, etc. In addition, the heat dissipation substrate for power semiconductors according to the embodiments can be mounted and used in power semiconductor modules mounted in various electric and electronic devices such as electric vehicle chargers, power supply devices, and railways other than eco-friendly automobiles.

[0096] In an embodiment, the power semiconductor device may include one power semiconductor module or multiple power semiconductor modules, and the power semiconductor module may include multiple power semiconductor elements.

[0097] In the following embodiments, the power semiconductor device is described as an inverter for an automobile for driving a motor, but the power semiconductor device of the embodiments can be applied to inverters, converters, etc. in the various technical fields mentioned above. Here, the automobile includes a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vehicle (EV), a fuel cell electric vehicle (PCEV), etc. In the following description of the embodiments, the switching element and the power semiconductor element may be used interchangeably.

[0098] <Power semiconductor module including heat dissipation substrate> FIG. 2a is a cross-sectional view of a power semiconductor module 500 including a heat dissipation substrate for a power semiconductor according to an embodiment, and FIG. 2b is a manufacturing process diagram of a power semiconductor module 501 including a heat dissipation substrate for a power semiconductor according to a first embodiment.

[0099] 2a, a power semiconductor module 500 according to the embodiment may include a first heat dissipation substrate 410, a second heat dissipation substrate 420, a power semiconductor device 100, a first lead frame 310, and a second lead frame 320, and is packaged by a mold 201. The mold 201 may include, but is not limited to, EMC (Epoxy Molding Compound). The power semiconductor device 100 may include a first power semiconductor device 100a and a second power semiconductor device 100b.

[0100] For example, referring to FIG. 2b, a first lead frame 310, a second lead frame 320, and one or more power semiconductor elements 100a, 100b may be arranged between a first heat dissipation substrate 410 and a second heat dissipation substrate 420, and then compressed to manufacture a power semiconductor module 501 according to the first embodiment.

[0101] The power semiconductor device 100 and the first and second heat dissipation substrates 410 and 420 may be bonded together by a predetermined adhesive member (not shown).

[0102] For example, the first and second heat dissipation substrates 410 and 420 may be attached to the power semiconductor device 100 by soldering, sintering bonding, transient liquid phase bonding (TLP bonding), ultrasonic bonding, or the like.

[0103] For example, the power semiconductor device 100 may be bonded to the first and second heat dissipation substrates 410 and 120 by sintering bonding.

[0104] For example, the first and second heat dissipation substrates 410 and 420 are bonded to the power semiconductor element 100 by screen printing a conductive paste such as Ag paste and then sintering the conductive paste at a temperature of about 150 to 300° C. The conductive paste may include conductive powder such as Ag, a solvent, and a binder.

[0105] Prior to the sinter-bonding, the heat dissipation substrate is subjected to a Cu or Ag surface treatment. In addition, in the sinter-bonding process, pressure bonding using a predetermined bonding jig can be performed to improve the bonding strength.

[0106] Alternatively, the power semiconductor device 100 of the embodiment may be bonded to the first and second heat dissipation substrates 410 and 120 by transient liquid phase bonding (TLP bonding).

[0107] The phase change bonding of the embodiment is a bonding technique in which a thin metal piece is inserted between metal layers and an IMC (intermetallic compound) is formed by diffusion at a predetermined temperature.

[0108] In the embodiment, the material for forming the IMC joint may include Cu-based, Ni-based, etc. For example, in the embodiment, the IMC joint may include any one of Cu-Sn, Ni-Sn, and Cu-Ni-Sn-based materials.

[0109] Alternatively, the power semiconductor element 100 of the embodiment may be bonded to the first and second heat dissipation substrates 410 and 220 by ultrasonic bonding technology.

[0110] The ultrasonic bonding technique of the embodiment is a technique in which the power semiconductor element and the heat dissipation substrate to be bonded are butted together and a constant pressure is applied, while vibrating with a predetermined ultrasonic wave, for example an ultrasonic wave of about 20 kHz or more, to cause friction between the bonding surfaces, inducing contact between the metals, and forming a bond by frictional heat, etc.

[0111] The ultrasonic bonding technique of the embodiment may include a vertical vibration method and a horizontal vibration method depending on the vibration direction.

[0112] 2a again, in the power semiconductor module 500 according to the embodiment, the first power semiconductor device 100a and the second power semiconductor device 100b may form one arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may be connected in series with the electrodes arranged in opposite directions, but are not limited thereto. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may be electrically connected in parallel.

[0113] In the embodiment, the first and second heat dissipation substrates 410 and 420 may be disposed on the upper and lower sides of the power semiconductor module 500, respectively, but are not limited thereto.

[0114] The first heat dissipation substrate 410 may include a first metal plate MP1, an insulating substrate SS, and a second metal plate MP2.

[0115] The insulating substrate SS can electrically insulate the first metal plate MP1 and the second metal plate MP2. The insulating substrate SS can include a polycrystalline insulating substrate made of a ceramic material having high thermal conductivity. For example, the insulating substrate SS can be one of AlN or Si3N4, but is not limited thereto, and can be Al2O3, etc. Also, the insulating substrate SS can include a single crystal substrate such as a sapphire substrate.

[0116] Hereinafter, the insulating substrate SS will be described as a polycrystalline substrate made of a ceramic material as an embodiment, but the insulating substrate SS is not limited thereto and may include a single crystal substrate.

[0117] The first metal plate MP1 and the second metal plate MP2 may include, but are not limited to, a Cu-based metal.

[0118] The second metal plate MP2 has one side in contact with the insulating substrate SS and can dissipate heat to the other side thereof. A heat dissipation means including a cooling medium is disposed adjacent to the other side of the second metal plate MP2.

[0119] Referring to FIG. 2b, a first metal plate MP1 disposed under the power semiconductor device 100 may include a first circuit pattern CP1 formed by a patterning process such as etching, and the first circuit pattern CP1 is electrically connected to an electrode of the power semiconductor device 100.

[0120] For example, the first circuit pattern CP1 may include a 1-1 circuit pattern p11, a 1-2 circuit pattern p12, and a 1-3 circuit pattern p13 that are electrically isolated and are electrically connected to the first power semiconductor device 100a and the second power semiconductor device 100b, respectively, as shown in FIG. 2a.

[0121] In addition, the second heat dissipation substrate 420 may also include a first metal plate MP1, an insulating substrate SS, and a second metal plate MP2. The second heat dissipation substrate 420 may adopt the technical features of the first heat dissipation substrate 410.

[0122] For example, the first metal plate MP1 disposed on the upper side of the power semiconductor device 100 may include an electrically isolated second circuit pattern CP2 formed by a patterning process such as etching. The second circuit pattern CP2 may include a 2-1 circuit pattern p21, a 2-2 circuit pattern p22, and a 2-3 circuit pattern p23, and is electrically connected to the first power semiconductor device 100a and the second power semiconductor device 100b, respectively, as shown in FIG. 2a.

[0123] 2a, one side of each of the first lead frame 310 and the second lead frame 320 is electrically connected to the power semiconductor device 100, and the other side of each is connected to an external connection terminal. The external connection terminal may include an input power source, a motor, an inverter controller, etc.

[0124] For example, the first lead frame 310 and the second lead frame 320 are electrically connected to the power semiconductor device 100 via the first heat dissipation substrate 410 and the second heat dissipation substrate 420 .

[0125] For example, the first lead frame 310 may include a 1-1 lead frame 310a electrically connected to the 1-1 circuit pattern p11 of the lower first metal plate MP1, and a 1-2 lead frame 310B electrically connected to the 2-1 circuit pattern p21 of the upper first metal plate MP1.

[0126] In addition, the second lead frame 320 may include a 2-1 lead frame 320a electrically connected to the 1-3 circuit pattern p13 of the lower first metal plate MP1, and a 2-2 lead frame 320b electrically connected to the 2-3 circuit pattern p23 of the upper first metal plate MP1.

[0127] Next, FIG. 2c is a manufacturing process diagram of a power semiconductor module 502 including a heat dissipation substrate for a power semiconductor according to the second embodiment.

[0128] A power semiconductor module 502 including a heat dissipation substrate for power semiconductors according to the second embodiment can adopt the technical features of the power semiconductor module 501 including a heat dissipation substrate for power semiconductors according to the first embodiment described above, and the following description will focus on the technical features of the second embodiment.

[0129] According to an internal study, the problem of the distance between circuit patterns increasing as the metal plate on the heat dissipation board gets thicker was investigated.

[0130] For example, when the thickness of the Cu plate is about 0.2 mm, the separation distance between the circuit patterns is about 0.4 mm, whereas when the thickness of the Cu plate is about 0.4 mm, the separation distance between the circuit patterns is about 0.6 mm.

[0131] In the internal technology, the thickness of the metal plates bonded to the top and bottom of the heat dissipation board was controlled within a certain range, and the metal plates were etched to ensure an average separation distance.

[0132] Meanwhile, in order to realize a high-performance power semiconductor element, multiple SiC power semiconductors are mounted on a heat dissipation substrate, which requires a complex circuit pattern. If the separation distance between the circuit patterns is increased more than necessary, it may be difficult to realize a high-density power semiconductor module.

[0133] Therefore, the inventors of the present application may control the thickness of the metal plate on one side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side. The control of the thickness of the metal plate will be described in detail later.

[0134] Referring to FIG. 2c, in the power semiconductor module 502 according to the second embodiment, the first heat dissipation substrate 410B of the second embodiment may include a first metal plate MP1 of a first thickness T1 on a first surface of the insulating substrate SS facing the power semiconductor element 100, and a second metal plate MP2 of a second thickness T2 on a second surface of the insulating substrate.

[0135] In the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than or equal to the second thickness T2 of the second metal plate MP2.

[0136] For example, in the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than the second thickness T2 of the second metal plate MP2.

[0137] According to the first heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded onto the first surface of the insulating substrate SS facing the power semiconductor element 100 can be controlled to be equal to or less than the second thickness T2 of the second metal plate MP2 bonded onto the second surface of the insulating substrate.

[0138] In addition, the second heat dissipation substrate 420b of the second embodiment can also adopt the technical features of the first heat dissipation substrate 410B of the second embodiment.

[0139] According to the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor element 100 can be controlled to be thin, thereby ensuring a small separation distance PD between the first circuit patterns CP1 of the first metal plate MP1, thereby providing a high-density power semiconductor module.

[0140] Next, FIG. 2d is a manufacturing process diagram of a power semiconductor module 503 including a heat dissipation substrate for power semiconductors according to the third embodiment.

[0141] A power semiconductor module 503 including a heat dissipation substrate for power semiconductors according to the third embodiment can adopt the technical features of the power semiconductor module 501 including a heat dissipation substrate for power semiconductors according to the first embodiment described above, and the following description will focus on the technical features of the third embodiment.

[0142] According to an internal study, when performing Transient Liquid Phase Bonding (TLP), the metal plate material of the heatsink substrate is consumed to form an IMC (intermetallic compound), which results in an insufficient IMC bonding layer, resulting in reduced bonding strength and the occurrence of pores.

[0143] In a power semiconductor module that operates at extremely high temperatures, a decrease in the adhesive strength between a power semiconductor element and a heat dissipation substrate or the presence of pores at the bonding interface significantly affects the performance degradation and reliability of the power semiconductor module.

[0144] Therefore, the inventors of the present application can control the thickness of the metal plate on one side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side.

[0145] For example, referring to FIG. 2d, in a power semiconductor module 503 according to the third embodiment, a third heat dissipation substrate 430 may include a third metal plate MP3 of a third thickness T3 bonded onto a first surface of an insulating substrate SS facing the power semiconductor element 100, and a second metal plate MP2 of a second thickness T2 bonded onto a second surface of the insulating substrate.

[0146] In the third embodiment, the third thickness T3 of the third metal plate MP3 may be greater than or equal to the second thickness T2 of the second metal plate MP2.

[0147] For example, in the third embodiment, the third thickness T3 of the third metal plate MP3 may be greater than the second thickness T2 of the second metal plate MP2.

[0148] According to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded onto the first surface of the insulating substrate SS facing the power semiconductor element 100 can be controlled to be greater than or equal to the second thickness T2 of the second metal plate MP2 bonded onto the second surface of the insulating substrate.

[0149] According to the third embodiment, the third thickness T3 of the third metal plate MP3 to be bonded to the power semiconductor element 100 can be controlled to be thick, and the third thickness T3 of the third circuit pattern CP3 of the third metal plate MP3 is also controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2. This provides a special technical effect of preventing the problem of the metal plate material of the heat dissipation substrate being consumed during the formation of the IMC when performing phase change bonding (Transient Liquid Phase Bonding) between the power semiconductor element 100 and the third metal plate MP3, improving the bonding strength, and solving the problem of pores being generated at the bonding interface.

[0150] Next, FIG. 3a is a first cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0151] 3a, the power semiconductor device 100 according to the embodiment may include a substrate 110, a first conductive type epitaxial layer 120, a second conductive type well 130, a first conductive type source region 140, a gate insulating layer 150, a gate electrode 160, and a drain electrode 105. The first conductive type may be an N type, and the second conductive type may be a P type, but is not limited thereto.

[0152] For example, the power semiconductor device 100 may include a first conductive type epitaxial layer 120 formed on a predetermined substrate 110, a second conductive type well 130 formed in the first conductive type epitaxial layer 120, a first conductive type source region 140 formed in the second conductive type well 130, a gate insulating layer 150 and a gate electrode 160 formed on the first conductive type source region 140, and a drain electrode 105 disposed under the substrate 110.

[0153] The substrate 110 and the first conductive type epitaxial layer 120 may include, but are not limited to, silicon carbide (SiC).

[0154] Next, FIG. 3b is a second cross-sectional view of the power semiconductor device 100 according to the embodiment, which is a schematic diagram based on the first cross-sectional view shown in FIG. 3a.

[0155] The power semiconductor device 100 according to the embodiment may include a source electrode 145s and a gate electrode 165g disposed on a given semiconductor epitaxial layer 120, and a drain electrode 105 disposed on a lower side of the semiconductor epitaxial layer 120.

[0156] In the form of a MOSFET, the source electrode 145s or the gate electrode 165g may include an Al-based metal, and the drain electrode 105 may include, but is not limited to, Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V (vanadium) / Ni / Ag, etc.

[0157] <Manufacturing process of heat dissipation substrates for power semiconductors> FIG. 4 is a schematic flow chart of a manufacturing process of a heat dissipation substrate for power semiconductors according to an embodiment.

[0158] The manufacturing process of the heat dissipation substrate for power semiconductors in the embodiment can broadly include (1) a pretreatment process of the insulating substrate, (2) a sputtering process, (3) a pretreatment process of the metal plate, (4) a lamination process of the insulating substrate and the metal plate, (5) a hot pressing process of the insulating substrate and the metal plate, (6) an etching process of the heat dissipation substrate, and (7) an inspection and cutting process of the heat dissipation substrate, etc.

[0159] The entire manufacturing process of the heat dissipation substrate for power semiconductors according to the embodiment is controlled by a control unit (not shown) of a central server, and the central server may include a data storage unit (not shown).

[0160] Hereinafter, the main manufacturing process of the heat dissipation board for power semiconductors according to the embodiment will be described with reference to the drawings.

[0161] (Pretreatment process for insulating substrates) Hereinafter, an insulating substrate for manufacturing a heat dissipation substrate according to an embodiment will be described by way of example with respect to a polycrystalline ceramic substrate, but the insulating substrate is not limited thereto and may include a single crystal substrate such as a sapphire substrate.

[0162] Hereinafter, the pretreatment process of the insulating substrate will be described with reference to FIGS. 5a to 8. FIG.

[0163] In this embodiment, a "pre-treatment process for the insulating substrate" is performed in a substrate cleaning device (not shown) before a "lamination process" of the insulating substrate and the metal plate.

[0164] The pretreatment process of the insulating substrate may include (1) a step of loading the insulating substrate, (2) a step of marking the unique code UC, (3) a step of cleaning the insulating substrate, (4) a step of measuring the thickness of the insulating substrate, and (5) a step of loading the insulating substrate into a thickness-specific magazine.

[0165] (1) Loading stage of insulating substrate First, as shown in Fig. 5a, a predetermined insulating substrate SS is prepared and loaded into a substrate cleaning device (not shown). The insulating substrate SS may be, but is not limited to, AlN, Si3N4, Al2O3, etc., and may also include a single crystal substrate such as a sapphire substrate.

[0166] On the other hand, FIG. 5b is a photograph showing the unevenness R present on the surface of the insulating substrate SS in the internal technique.

[0167] The surface of the insulating substrate SS may have irregularities R of several μm to several hundred μm in size. When the conventional technology is applied, such irregularities R may induce the generation of pores during the bonding process.

[0168] 5b, in the conventional technology and internal technology, the occurrence of pores was considered to be inevitable due to the unevenness R of several μm to several hundred μm on the surface of the insulating substrate. However, considering the ultra-high operating temperature environment of the power semiconductor module, a solution to this problem must be found.

[0169] (2) Unique code UC marking process In the conventional heat dissipation board industry, it was difficult to accurately match various production and quality histories such as the thickness information of the insulating board, the thickness information of the copper plate, and product information after the bonding process to each "heat dissipation board."

[0170] In particular, when the insulating substrate to which the present invention is applied is subjected to a copper plate and hot press process after metal sputtering, even if a code is marked on the insulating substrate, the code is blocked by the sputtering process and the subsequent hot press process, so it is impossible to attempt to mark a separate code for each "individual heat dissipation substrate."

[0171] 6, a unique code UC is marked on the insulating substrate SS loaded into the substrate cleaning device. After that, the unique code UC is read and transmitted to and stored in a data storage unit of a server via wired or wireless communication, and detailed information on each "individual heat dissipating substrate" including each "individual insulating substrate" in the subsequent processes is precisely updated and managed.

[0172] 6, the insulating substrate SS may include an effective area AA and a dummy area DA. The outermost edge of the effective area AA is a boundary B between the effective area AA and the dummy area DA.

[0173] The effective area AA is an area that will become a final heat dissipation substrate product, and the dummy area DA is an area that will be removed. The unique code UC may be marked in the dummy area DA of the insulating substrate SS.

[0174] The unique code UC may include, but is not limited to, a DMC (Digital Matrix Code), a QR code, a barcode, etc. For example, the unique code UC may include a unique code marked or labeled by a unique code technology that may appear through technological development after the filing of the present invention.

[0175] Also, the unique code UC may be marked by a laser marking (LM) technique, but is not limited thereto.

[0176] According to the embodiment, after marking the entire insulating substrate SS with a unique code UC and a unique ID, the data can be transmitted to and managed in the data storage unit of the upper server, and detailed information on "individual insulating substrates" and "individual heat dissipation substrates" including the insulating substrate can be precisely updated and managed, and there is a special technical effect that post-event management between processes is possible.

[0177] Meanwhile, in the heat dissipation substrate industry, there has been no concern or attempt to manage the process history of the heat dissipation substrate manufacturing process for each insulating substrate.

[0178] Meanwhile, the inventors of the present application, in the course of new research into process history management of the manufacturing process for "individual insulating substrates" in the field of heat dissipation substrates, discovered a unique problem in which soot is generated when marking the unique code UCr on the insulating substrate, and the soot can spread beyond the dummy area DA to the effective area AA.

[0179] Such soot can cause sputtering defects in the subsequent sputtering process, which directly affects the quality of the heat dissipation substrate itself, and furthermore, specific technical problems that can cause bonding defects in the hot press process with the metal plate have been studied.

[0180] Therefore, marking a specific unique code on the insulating substrate itself is incredibly difficult, and there are considerable technical challenges to overcome in order to realize this.

[0181] Nevertheless, the inventors of the present application have independently researched the point where soot does not affect the active area when marking the unique code UC, and have been able to precisely mark the unique code UC in the dummy area DA without soot, as shown in FIG. 5.

[0182] In addition, in the present invention, the insulating substrate is subjected to a copper plate and hot pressing process after sputtering, but if a unique code is marked on the insulating substrate, the unique code will be blocked during the sputtering and hot pressing processes, so attempts to mark a unique code on each insulating substrate have been technically difficult.

[0183] (3) A process for cleaning the insulating substrate, and (4) A process for measuring the thickness Next, referring to FIG. 7, a cleaning process and a thickness measurement process are performed on the insulating substrate SS.

[0184] For example, a CDA (Clean Dried Air) cleaning process CL is performed on the insulating substrate SS.

[0185] In addition, in the embodiment, after cleaning the insulating substrate SS, the thickness of the insulating substrate SS can be measured at nine points using a displacement sensor (TM), but the present invention is not limited to this.

[0186] The insulating substrate SS may have a thickness of 200 μm to 1,000 μm, but is not limited to this range. Preferably, the insulating substrate SS may have a thickness of 300 μm to 800 μm, but is not limited to this range.

[0187] The insulating substrates SS can be classified into a number of groups according to their thickness, for example, ceramic substrates can be classified into first to third groups according to their thickness, but are not limited thereto.

[0188] (5) Loading process for different insulating substrate thicknesses FIG. 8 is a diagram of a substrate magazine CM into which insulating substrates classified according to thickness after cleaning are loaded according to an embodiment.

[0189] For example, the insulating substrates can be classified into first to third groups of ceramic substrates SS1, SS2, and SS3 according to the first to third thicknesses T1, T2, and T3.

[0190] For example, the first group of insulating substrates SS1, the second group of insulating substrates SS2, and the third group of insulating substrates SS3 may have increasing thicknesses in this order, but this is not limited thereto.

[0191] The first to third groups of insulating substrates SS1, SS2, and SS3 are loaded into first to third substrate magazines CM1, CM2, and CM3, respectively, and then transferred to a predetermined stacking device. The first to third groups of insulating substrates can also be referred to as first to third lots.

[0192] In the embodiment, each of the first to third substrate magazines CM1, CM2, and CM3 may also be marked with a predetermined unique ID or unique code.

[0193] According to the embodiment, insulating substrates are classified and loaded into first to third substrate magazines CM1, CM2, and CM3 according to thickness, and thickness and classification loading information for each insulating substrate and each substrate magazine is stored and managed in an upper server.

[0194] In addition, the unique information UC of each insulating substrate SS is precisely updated and managed with information about which substrate magazine it is loaded in.

[0195] As a result, in the lamination process that is performed after the sputtering process, the unique IDs of the first to third substrate magazines CM1, CM2, and CM3 can be read, and the thickness quality of the heat dissipation substrate can be optimized in the matching lamination and bonding process with the metal plate according to thickness.

[0196] According to the embodiment, there is a technical effect that the thickness distribution can be minimized by classifying the individual insulating substrates and metal plates according to thickness and matching them according to thickness grades.

[0197] Currently, in the field of heat dissipation substrates, the supplied thickness of insulating substrates is not uniform, and the supplied thickness of metal plates, such as copper plates, is also not uniform.

[0198] In this situation, the final heat dissipation board must meet strict specifications for the delivery of the heat dissipation board, but it is difficult to produce a heat dissipation board that can meet the strict thickness specifications.

[0199] Therefore, the inventors of the present invention have invented a lamination system for insulating substrates and copper substrates that can carefully measure and manage the thicknesses of insulating substrates and copper plates, which are delivered in various thicknesses, and perfectly manage such thickness information to be consistent for each product using unique information UC, and minimize thickness distribution based on such unique information UC.

[0200] (Sputtering process) As mentioned above, the insulating substrates classified according to thickness are transported to the sputtering device while being loaded into the first to third substrate magazines CM1, CM2, and CM3, and then the individual insulating substrates are unloaded and mounted in the sputtering device for the sputtering process.

[0201] Hereinafter, the "sputtering step for an insulating substrate" of the embodiment will be described with reference to Figs.

[0202] Referring to FIG. 9, a bonding metal layer 411 having a first thickness is formed on one surface of an insulating substrate SS by sputtering.

[0203] At this time, sputtering can be prevented from occurring in the unique code UC and unique ID area. For example, in the sputtering process, the unique code UC and unique ID area are protected by the sprayed parts PS, etc., so that sputtering can be controlled not to occur in the unique code UC and unique ID area.

[0204] Also, in this embodiment, unlike the illustration in FIG. 9, it is possible to control so that sputtering does not occur on the part PS that has been thermally sprayed.

[0205] Referring to FIG. 10, an insulating substrate SS is mounted on an anode electrode plate of a predetermined PVD apparatus 700, and a bonding metal layer 411 including Ti or TiW is formed to a first thickness of about 2000 Å to 4000 Å in an inert atmosphere such as Ar gas.

[0206] For example, the bonding metal layer 411 may be formed to a thickness of about 2500 Å to 3500 Å, but is not limited thereto.

[0207] 11, a diffusion metal layer 412 is formed by sputtering on the bonding metal layer 411. The diffusion metal layer 412 is formed by sputtering to a second thickness that is thinner than the first thickness of the bonding metal layer 411.

[0208] For example, the second thickness of the diffusion metal layer 412 may be in the range of ¼ to ½ of the first thickness of the bonding metal layer 411 .

[0209] For example, the second thickness of the diffusion metal layer 412 may be about 1000 Å to about 2000 Å. Preferably, the second thickness of the diffusion metal layer 412 may be about 1500 Å to about 1900 Å, but is not limited thereto.

[0210] The diffusion metal layer 412 may have a melting point lower than the temperature of a hot pressing process for subsequent bonding. For example, the hot pressing temperature may be in the range of about 900° C. to 1100° C., and the diffusion metal layer 412 may be a material having a melting point lower than 900° C. and excellent diffusion. For example, the diffusion metal layer 412 may be made of one or more of Al, Ag, Au, and Sn, but is not limited thereto.

[0211] In addition, in the embodiment, sputtering can be performed with the anode electrode plate in Fig. 10 tilted, so that the diffusion metal regions 412a can be controlled to be formed in the form of islands separated from each other while first filling the bottom and side surfaces of the concave portions of the surface unevenness of the bonding metal layer 411.

[0212] The diffusion metal region 412a is formed to a third thickness that is very thin, 1 / 10 to 1 / 4 the thickness of the first thickness of the bonding metal layer 411. For example, the third thickness of the diffusion metal region 412a may be about 200 Å to 1000 Å. Preferably, the third thickness of the diffusion metal region 412a may be about 500 Å to 900 Å, but is not limited thereto.

[0213] Next, referring to FIG. 12, the insulating substrate SS having the diffusion metal layer 412 formed on one surface is turned over, and then the bonding metal layer 411 and the diffusion metal layer 412 can be sequentially formed on the other surface by sputtering.

[0214] In the embodiment, after sputtering, the thicknesses of the bonding metal layer 411 and the diffusion metal layer 412 are measured for each insulating substrate SS, and the thickness data for each unique code UC can be transmitted to a server for update management.

[0215] For example, in the embodiment, the sheet resistance of each insulating substrate SS can be measured to measure the thickness of the formed bonding metal layer 411 and diffusion metal layer 412, but the present invention is not limited to this.

[0216] After the thicknesses of the bonding metal layer 411 and the diffusion metal layer 412 have been measured, the individual insulating substrates are reloaded into the first to third substrate magazines CM1, CM2, and CM3 and transferred to a stacking device, where the thicknesses of each insulating substrate and each metal plate are aligned and stacked in the stacking device.

[0217] (Pretreatment process for metal plates) FIG. 13 is a diagram showing a metal magazine MM into which metal plates sorted by thickness after cleaning are loaded according to an embodiment.

[0218] The pretreatment process of the metal plate is performed separately from the pretreatment process of the insulating substrate, for example, the pretreatment process of the metal plate may be performed before, after, or simultaneously with the pretreatment process of the insulating substrate.

[0219] The metal plate may be a metal plate having excellent electrical conductivity and thermal conductivity. For example, the metal plate may be a Cu plate, a Cu alloy plate, etc., but is not limited thereto. The metal plate may also be referred to as a metal substrate.

[0220] The pre-treatment process of the metal plates may include a cleaning process and a thickness measurement process for the metal plates, and then the metal plates classified according to thickness are sorted and loaded into a metal magazine.

[0221] For example, a CDA (Clean Dried Air) cleaning process and a particle exhaust process are performed on the metal plate.

[0222] In addition, in the embodiment, after cleaning the metal plate, the thickness of the upper and lower parts of the metal plate can be measured using a displacement sensor, etc. For example, the thickness of the metal plate can be measured at nine points, but is not limited thereto.

[0223] In this case, the embodiment transmits information on the thickness of the metal plate to a higher-level server, and can precisely update and manage information on each metal plate.

[0224] Additionally, the embodiment may include, but is not limited to, a metal specific information (not shown) marking procedure on the dummy areas of the metal plate prior to the cleaning process.

[0225] In the embodiment, the thickness of the metal plate may be, but is not limited to, 200 μm to 500 μm, and preferably, the thickness of the metal plate may be, but is not limited to, 250 μm to 350 μm.

[0226] The metal plates can be classified into a plurality of groups according to their thickness. For example, the metal plates can be classified into first to third metal plates MP1, MP2, and MP3 according to their thickness, but are not limited thereto. The first metal plate MP1, the second metal plate MP2, and the third metal plate MP3 can be classified in this order of thickness, but are not limited thereto.

[0227] 13, first to third groups of metal plates MP1, MP2, MP3 classified into first to third thicknesses T1, T2, T3 are loaded into first to third metal magazines MM1, MM2, MM3, respectively, and then transferred to a predetermined stacking device. The first to third groups of metal plates can also be called first to third lots.

[0228] In an embodiment, each of the first to third metal magazines MM1, MM2, and MM3 may be marked with a predetermined unique ID or unique code.

[0229] According to the embodiment, metal plates are classified and loaded into first to third metal magazines MM1, MM2, and MM3 according to their thickness, and thickness and classification loading information for each metal plate and metal magazine is stored and managed in an upper server.

[0230] In addition, the unique information of each metal plate, including information on which metal magazine it was loaded in, is precisely updated and managed.

[0231] As a result, in the subsequent lamination process, the unique IDs of the first to third metal magazines MM1, MM2, and MM3 can be read, and the bonding can be matched to the insulating substrate according to each thickness, thereby optimizing the thickness quality.

[0232] According to the embodiment, there is a technical effect that the thickness distribution can be minimized by classifying not only the individual insulating substrates but also the metal plates according to their thickness and matching them according to the thickness grade.

[0233] Currently, in the field of heat dissipation boards, not only the delivered thickness of insulating boards but also the delivered thickness of metal plates, such as copper plates, is not consistent. In this situation, the final heat dissipation board must meet strict specifications for the delivery standard of the heat dissipation board, but it is difficult to produce a heat dissipation board that meets the strict thickness specifications.

[0234] Therefore, the inventors of the present invention carefully measure and manage the thicknesses of insulating substrates and copper plates, which are delivered in various thicknesses, and perfectly manage the thickness information, so that it can be matched to each product through unique information. Based on this unique information, the inventors have invented a lamination system for insulating substrates and copper substrates that can minimize thickness distribution.

[0235] For example, according to the embodiment, a second insulating substrate SS2 of a second thickness T2, a second metal plate MP2 of a second thickness T2 as an upper plate, and a second metal plate MP2 of a second thickness T2 as a lower plate are laminated together to form one laminate set, thereby complying with the strict specifications of the delivery standards for heat dissipation substrates.

[0236] For example, according to the embodiment, a second insulating substrate SS2 having a second thickness T2, a first metal plate MP1 having a first thickness T1 as an upper plate, and a second metal plate MP2 having a second thickness T2 as a lower plate are laminated together to form one laminate set, thereby complying with the strict specifications of the delivery standards for heat dissipation substrates.

[0237] For example, according to the embodiment, a second insulating substrate SS2 having a second thickness T2, a first metal plate MP1 having a first thickness T1 as an upper plate, and a third metal plate MP3 having a third thickness T3 as a lower plate are laminated together to form one laminate set, thereby complying with the strict specifications of the delivery standards for heat dissipation substrates.

[0238] In addition, according to the embodiment, the first insulating substrate SS1 having the first thickness T1, the first metal plate MP1 having the first thickness T1 as the upper plate, and the third metal plate MP3 having the third thickness T3 as the lower plate are laminated together to form one laminate set, thereby making it possible to meet the delivery standards for heat dissipation substrates with strict specifications.

[0239] Alternatively, according to an embodiment, a first insulating substrate SS1 having a first thickness T1, a second metal plate MP2 having a second thickness T2 as an upper plate, and a third metal plate MP3 having a third thickness T3 as a lower plate are laminated together to form a single laminate set, thereby complying with the strict specifications of the delivery standards for heat dissipation substrates.

[0240] Alternatively, according to an embodiment, a third insulating substrate SS3 having a third thickness T3, a first metal plate MP1 having a first thickness T1 as an upper plate, and a first metal plate MP1 having a first thickness T1 as a lower plate are laminated together to form a single laminate set, thereby complying with the strict specifications of the delivery standards for heat dissipation substrates.

[0241] Alternatively, according to an embodiment, a third insulating substrate SS3 having a third thickness T3, a first metal plate MP1 having a first thickness T1 as an upper plate, and a second metal plate MP2 having a second thickness T2 as a lower plate are laminated together to form a single laminate set, thereby complying with the strict specifications of the delivery standards for heat dissipation substrates.

[0242] According to the embodiment, the thicknesses of insulating substrates and metal plates delivered in various thicknesses are measured and managed carefully, and each thickness information is updated and managed completely to match the product specifications required by each customer using unique information UC. Based on the unique information UC, an optimal combination of lamination sets of insulating substrates and metal plates is calculated and laminated, and then hot press fixing is performed, thereby providing a special technical effect of providing a heat dissipation substrate that is perfectly compatible with strict thickness specifications, and a power semiconductor module, insulating substrate and copper substrate lamination system having the same.

[0243] (Lamination process of insulating substrate and metal plate) Next, the process of laminating the insulating substrate and the metal plate will be described with reference to FIGS.

[0244] 14 and 15 are schematic diagrams of an automatic alignment lamination apparatus 800 for an insulating substrate and a metal plate in the embodiment, and FIG. 16 is a flow chart of a lamination process for an insulating substrate and a metal plate.

[0245] In the internal technology, the lamination process of insulating substrates and metal plates was done manually. However, when the lamination process is done manually, it is difficult to consider the consistency of the thickness of each insulating substrate and metal plate, and even the placement of the metal plates on the upper and lower sides of the insulating substrate is not easy to control.

[0246] In particular, in the internal technology, the stacking set of the heat dissipation board includes an insulating substrate and metal plates arranged above and below, and in order to realize a high degree of stacking, with the number of stacking sets reaching tens to hundreds, the alignment of the insulating substrate and the metal plate was studied as a very difficult technical challenge.

[0247] That is, if there is even a slight misalignment between the ceramic and metal plates, there is a problem that poor bonding occurs in the subsequent hot pressing process which is performed under a pressure of several tens of tons.

[0248] This led the inventors of the present application to invent an "automatic alignment lamination system 800" that is capable of automatic lamination and automatic alignment of an insulating substrate and a metal plate.

[0249] Referring now to FIG. 16, the lamination process of the insulating substrate and the metal plate may include (1) a carbon spacer loading process, (2) a lower metal plate loading process, (3) an insulating substrate loading process, (4) an upper metal plate loading process, (5) a carbon spacer loading process, and (6) a graphite loading process.

[0250] First, an "automatic alignment lamination system 800" for an insulating substrate and a metal plate will be described with reference to FIGS.

[0251] Referring to FIG. 14, in an embodiment, the automatic alignment stacking system 800 may include at least one of a spacer port 805, a first substrate port 800P1, a second metal port 800P2, a third metal port 800P3, a graphite port 840, and a stacking unit 850.

[0252] Additionally, the automated alignment stacking system 800 of the embodiment may include a first conveyor 800C1 and a particle applicator 807 above the first rack 800B1, and a second conveyor 800C2 above the second rack 800B2.

[0253] Hereinafter, the features of each device will be described in detail with reference to FIG.

[0254] The automatic alignment stacking system 800 according to the embodiment may implement automatic transfer or stacking of each insulating substrate, metal plate, etc., using an automatic transfer device. For example, the automatic transfer device may include first to seventh transfer devices 800R1, 800R2, 800R3, 800R4, 800R5, 800R6, and 800R7, which may include, but are not limited to, a robot equipped with a transfer arm and a servo motor, etc.

[0255] First, a predetermined spacer 415 (see FIG. 17) is loaded into the spacer port 805. The spacer 415 may be, but is not limited to, a carbon spacer or a ceramic spacer.

[0256] In addition, the embodiment may include a particle applicator 807 on the first conveyor 800C1. The operation of the particle applicator 807 will be described later.

[0257] Next, the first substrate port 800P1 may include a substrate magazine CM in which the sputtered insulating substrates are classified according to thickness and loaded. For example, the first substrate port 800P1 may include first to third substrate magazines CM1, CM2, and CM3 in which the sputtered insulating substrates are classified according to thickness and loaded.

[0258] Next, the second metal port 800P2 may include a metal magazine MM in which metal plates are classified according to thickness and loaded. For example, the second metal port 800P2 may include first to third metal magazines MM1, MM2, and MM3 in which metal plates are classified according to thickness and loaded.

[0259] A lower metal plate, which is disposed under an insulating substrate during a lamination process, is loaded on the second metal port 800P2.

[0260] Next, the third metal port 800P3 may also include a metal magazine MM in which metal plates are classified according to thickness and loaded. For example, the third metal port 800P3 may include first to third metal magazines MM1, MM2, and MM3 in which metal plates are classified according to thickness and loaded.

[0261] An upper metal plate, which is to be disposed on the upper side of the insulating substrate during a lamination process, is loaded on the third metal port 800P3.

[0262] Next, a predetermined graphite 480 (see FIG. 17) is loaded into the graphite port 840. The graphite 480 can function as an anti-adhesion sheet.

[0263] Hereinafter, a stacking process using the automatic alignment stacking system 800 according to the embodiment will be described with reference to FIGS.

[0264] First, the first spacer 415a is loaded onto the first conveyor 800C1 by the first transfer device 800R1 and then moved to the particle coating device 807.

[0265] Before entering the particle coating device 807, the first spacer 415a is subjected to a predetermined cleaning process such as CDA.

[0266] After the cleaning process, a particle coating device 807 sprays predetermined particles onto one side of the first spacer 415a, and the first spacer is coated with particles by a roller. The spacer is then turned over and the other side is coated with particles.

[0267] The particles may include boron nitride (B / N) or the like, in order to facilitate separation of the heat dissipation substrate after the hot press bonding process.

[0268] The first spacer 415a moved by the first conveyor 800C1 is stacked in a stacking unit 850 by the sixth transfer device 800R6.

[0269] According to the embodiment, the particle application process is automated and uniformed, thereby improving the quality of the heat dissipation substrate and shortening the process time.

[0270] Next, the metal plates loaded on the second metal port 800P2 can be unloaded onto the second conveyor 800C2 of the second rack 800B2 by the second transfer device 800R2.

[0271] For example, the second metal plate MP2 loaded in the second metal magazine MM2 of the second metal port 800P2 can be unloaded onto the second conveyor 800C2 of the second rack 800B2 by the second transfer device 800R2.

[0272] Thereafter, the second metal plate MP2 moved by the second conveyor 800C2 is stacked in the stacking unit 850 by the fifth transfer device 800R5. The second metal plate MP2 is stacked on the first spacer 415a.

[0273] Next, the insulating substrate loaded on the first substrate port 800P1 can be unloaded onto the second conveyor 800C2 of the second rack 800B2 by the third transfer device 800R3.

[0274] For example, the second insulating substrate SS2 loaded in the second substrate magazine CM2 of the second metal port 800P2 can be unloaded onto the second conveyor 800C2 by the third transfer device 800R3.

[0275] Thereafter, the second insulating substrate SS2 moved by the second conveyor 800C2 is stacked in the stacking unit 850 by the fifth transfer device 800R5. The second insulating substrate SS2 is stacked on the second metal plate MP2.

[0276] Next, the metal plates loaded on the third metal port 800P3 can be unloaded onto the second conveyor 800C2 of the second rack 800B2 by the fourth transfer device 800R4.

[0277] For example, the second metal plate MP2 loaded in the second metal magazine MM2 of the third metal port 800P3 can be unloaded onto the second conveyor 800C2 of the second rack 800B2 by the fourth transfer device 800R4.

[0278] Thereafter, the second metal plate MP2 moved by the second conveyor 800C2 is stacked in the stacking unit 850 by the fifth transfer device 800R5. The second metal plate MP2 is stacked on the second insulating substrate SS2.

[0279] Next, the second spacer 415b is loaded onto the first conveyor 800C1 by the first transfer device 800R1 and then moved to the particle coating device 807.

[0280] Before entering the particle coating device 807, a predetermined cleaning process such as CDA is performed.

[0281] After the cleaning process, a particle coating device 807 sprays predetermined particles onto one side of the second spacer 415b using air and coats it with a roller.Then, the spacer is turned over and the other side is coated with particles.

[0282] The particles may include boron nitride (B / N) or the like, in order to facilitate separation of the heat dissipation substrate after the hot press bonding process.

[0283] The second spacer 415b moved by the first conveyor 800C1 is stacked by the sixth transfer device 800R6 onto the stacking unit 850. The second spacer 415b is stacked on the second metal plate MP2.

[0284] In this way, a first laminate set ST1 that becomes the heat dissipation substrate 410a (see FIG. 19a) of the first embodiment is prepared (see FIG. 17).

[0285] Thereafter, a lamination process of a second lamination set ST2 which becomes the heat dissipation substrate 410B (see FIG. 19a) of the second embodiment is performed (see FIG. 17). For example, referring to FIG. 17, a second metal plate MP2, a first insulating substrate SS1, a first metal plate MP1, and a third spacer 415c are sequentially laminated on the second spacer 415b.

[0286] In a non-limiting example, graphite 480 may be layered after a set of 10 stacks has been performed.

[0287] As mentioned above, internal research has found that the thicker the metal plate on the heat dissipation board, the greater the distance between circuit patterns. For example, if the Cu plate is about 0.2mm thick, the separation distance between circuit patterns is about 0.4mm, but if the Cu plate is about 0.4mm thick, the separation distance between circuit patterns is about 0.6mm.

[0288] The internal technology was at a level where the thickness of the metal plates bonded to the top and bottom of the heat dissipation board was controlled within a certain range, and the metal plates were etched to ensure an average separation distance.

[0289] Meanwhile, in order to realize a high-performance power semiconductor element, multiple SiC power semiconductors are mounted on a heat dissipation substrate, which requires a complex circuit pattern. If the separation distance between the circuit patterns is increased more than necessary, it will be difficult to realize a high-density power semiconductor module.

[0290] Therefore, the inventors of the present application can control the thickness of the metal plate on one side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side.

[0291] According to the embodiment, the thicknesses of insulating substrates and metal plates delivered in various thicknesses are carefully measured and managed, and each thickness information can be perfectly updated and managed to match the product specifications required by each customer using unique information UC.

[0292] For example, since the upper surface of the insulating substrate is marked with a specific unique code UC, the surface marked with the unique code UC during the lamination process can be managed as the upper surface of the insulating substrate.

[0293] As a result, the unique code UC not only records the product history of each insulating substrate, but also serves as an alignment function to distinguish the upper and lower surfaces during the lamination process, resulting in a special technical effect in which metal plates with optimal thickness combinations are laminated on the upper and lower surfaces of the insulating substrate, controlling the hot pressing process.

[0294] For example, referring to FIG. 17, the second stack set ST2 constituting the heat dissipation substrate 410B of the second embodiment has a first metal plate MP1 of a first thickness T1 stacked on a first surface of a first insulating substrate SS1 facing a specified power semiconductor element 100, and a second metal plate MP2 of a second thickness T2 stacked on a second surface of the first insulating substrate SS1.

[0295] In the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than or equal to the second thickness T2 of the second metal plate MP2. For example, in the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than the second thickness T2 of the second metal plate MP2.

[0296] In the embodiment, the first thickness T1 of the first metal plate MP1 may be in the range of 50% to 100% of the second thickness T2 of the second metal plate MP2, or may be in the range of 60% to 90% of the second thickness T2 of the second metal plate MP2, but is not limited thereto.

[0297] According to the heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor element 100 can be controlled to be thin, thereby ensuring a small separation distance PD between the first circuit patterns CP1 of the first metal plate MP1, thereby providing a high-density power semiconductor module.

[0298] Next, FIG. 19b is a manufacturing process diagram including a heat dissipation substrate 410C according to the third embodiment.

[0299] The manufacturing process of the heat dissipation substrate 410C of the third embodiment may adopt the technical features of the heat dissipation substrate 410a of the first embodiment or the heat dissipation substrate 410B of the second embodiment described above, and the following description will focus on the technical features of the third embodiment.

[0300] As mentioned above, according to internal research, when performing Transient Liquid Phase Bonding (TLP), the metal plate material of the heat dissipation substrate is consumed to form the IMC, which results in the IMC bonding layer not being formed sufficiently, resulting in reduced bonding strength and the occurrence of pores.

[0301] In power semiconductor modules that operate at extremely high temperatures, a decrease in adhesive strength between a power semiconductor element and a heat dissipation substrate or the presence of pores at the bonding interface significantly affects the performance degradation and reliability of the power semiconductor module.

[0302] Therefore, the inventors of the present application can control the thickness of the metal plate on one side of the heat dissipation substrate on which the circuit pattern is formed to be different from the thickness of the metal plate on the other side.

[0303] For example, referring to FIG. 19b, the heat dissipation substrate 410C of the third embodiment may include a third metal plate MP3 of a third thickness T3 bonded onto a first surface of the first insulating substrate SS1 and a second metal plate MP2 of a second thickness T2 bonded onto a second surface of the second insulating substrate SS2.

[0304] A predetermined power semiconductor element 100 is bonded onto the third metal plate MP3.

[0305] In the heat dissipation substrate 410C of the third embodiment, the third thickness T3 of the third metal plate MP3 may be greater than or equal to the second thickness T2 of the second metal plate MP2. For example, in the third embodiment, the third thickness T3 of the third metal plate MP3 may exceed the second thickness T2 of the second metal plate MP2.

[0306] In the third embodiment, the third thickness T3 of the third metal plate MP2 may be in the range of 100% to 200% of the second thickness T2 of the second metal plate MP2, or may be in the range of 120% to 150% of the second thickness T2 of the second metal plate MP2, but is not limited thereto.

[0307] According to the heat dissipation substrate 410C of the third embodiment, the third thickness T3 of the third metal plate MP3 facing the power semiconductor element 100 can be controlled to be greater than or equal to the second thickness T2 of the second metal plate MP2 bonded onto the opposite surface of the insulating substrate.

[0308] According to the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the power semiconductor element 100 can be controlled to be thick, and the third thickness T3 of the third circuit pattern of the third metal plate MP3 is also controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2. This provides a special technical effect of preventing the problem of the metal plate material of the heat dissipation substrate being consumed during the formation of the IMC when performing transient liquid phase bonding between the power semiconductor element 100 and the third metal plate MP3, improving the bonding strength, and solving the problem of pores being generated at the bonding interface.

[0309] Referring again to FIG. 15, automatic lamination and alignment of an insulating substrate and a metal plate can be realized using the automatic alignment lamination system 800 according to the embodiment.

[0310] According to the "automatic alignment stacking system 800" of the embodiment, automatic stacking and hot press bonding processes of several tens to more than 100 sets are possible.

[0311] In particular, according to the embodiment, the bottom surface of the stacking unit 850 has a tilted structure, which has a special technical effect of enabling precise automatic alignment of the corners of the spacer, metal plate, and insulating substrate that are stacked in sequence.

[0312] For example, according to the embodiment, there is a special technical effect that the tilt stacking can utilize gravity to innovatively increase the vertical alignment accuracy.

[0313] As a result, precise automatic alignment is possible when tens to over 100 sets are automatically laminated, and even in a hot press bonding process exceeding tens of tons, accurate alignment is maintained and there is no deviation of the laminated set, resulting in a special technical effect of realizing a high-quality heat dissipation substrate.

[0314] In addition, according to the embodiment, since a predetermined unique code UC is marked on one side edge of the insulating substrate, the insulating substrates can be stacked in such a manner that the unique code UC coincides with the lowest corner of the tilted structure of the stacked unit 850 during the stacking process.

[0315] As a result, the unique code UC has a special technical effect of being able to perform not only the product history of each insulating substrate but also the alignment function of the stacking position with respect to the stacking unit 850 during the stacking process.

[0316] According to the embodiment, when the unique code is opened for the inspection and history management process of the bonded heat dissipation substrate after the hot pressing process, the hot pressing process is performed with the unique code positioned at a fixed position, which has the special technical effect of allowing the unique code opening process to be performed quickly and accurately.

[0317] According to the embodiment, there is a special technical effect that the laminate set laminated by the automatic alignment lamination system device can be fastened to a predetermined carrier clamp, and a predetermined guide transport device can be inserted into the lamination carrier to feed the precisely aligned laminate set into the hot press while maintaining the alignment.

[0318] (Hot press process) Next, the hot press bonding process of the embodiment will be described with reference to Figs. 18 to 19b.

[0319] Referring to FIG. 18, a hot press process is performed in a vacuum on the laminate set placed in a hot press device (not shown) to manufacture the heat dissipation substrates 410A and 410B of the first and second embodiments as shown in FIG. 19a.

[0320] For example, a first stack set ST1 including a second metal plate MP2, a second insulating substrate SS2, and a second metal plate MP2 is manufactured as the heat dissipation substrate 410A of the first embodiment.

[0321] Moreover, a second stack set ST2 including the second metal plate MP2, the first insulating substrate SS1, and the first metal plate MP1 is manufactured as a heat dissipation substrate 410B of the second embodiment.

[0322] Also, referring to FIG. 19b, a third stack set including a second metal plate MP2, a first insulating substrate SS1 and a third metal plate MP3 is fabricated as a heat dissipation substrate 410C of a third embodiment.

[0323] The temperature of the hot pressing step may be about 900° C. to 1100° C. Preferably, the temperature of the hot pressing step may be about 950° C. to 1000° C., but is not limited thereto.

[0324] The degree of vacuum in the hot pressing process was 1.0×10 -1 The degree of vacuum may be, but is not limited to, torr or more, and the pressure in the hot pressing step may be, but is not limited to, about 10 MPa to about 100 MPa.

[0325] (Heat dissipation board inspection and etching process) Hereinafter, the inspection process and the etching process of the heat dissipation substrate will be described with reference to Fig. 20. Referring to Fig. 20, each heat dissipation substrate manufactured by the hot press bonding process is subjected to a cleaning process, an inspection process, and an etching process.

[0326] The heat dissipation substrate 410B of the second embodiment shown in FIG. 20 may have a structure including a second metal plate MP2, a first insulating substrate SS1, and a first metal plate MP1, but is not limited thereto.

[0327] For example, a cleaning process is performed on the heat dissipation substrate 410B of the second embodiment manufactured by the hot press bonding process. For example, the heat dissipation substrate 410B of the second embodiment is subjected to brush cleaning, water rinsing, and drying processes, but is not limited thereto.

[0328] In addition, in the embodiment, ultrasonic inspection is performed on the bonding interface of the heat dissipation substrate manufactured by hot pressing.

[0329] For example, according to the embodiment, the first bonding interface of each heat dissipation substrate can be inspected for interface thickness, presence of voids, and presence of cracks using ultrasonic inspection equipment.

[0330] According to the embodiment, after the hot press bonding process, the metal plate of each dummy region of the heat dissipation substrate can be partially removed to open the unique code UC formed in the dummy region.

[0331] This provides a special technical effect in that after the hot pressing process, inspection information regarding the interface thickness, the presence or absence of voids, and the presence or absence of cracks for the bonding interface of each heat dissipation substrate can be precisely updated and managed.

[0332] Next, referring to FIG. 20, an etching process is performed to form a circuit pattern on the heat dissipation board that has been determined to be a non-defective product in the inspection process.

[0333] For example, the first circuit pattern CP1 can be formed by etching the heat dissipation substrate 410B of the second embodiment that has been subjected to the hot pressing process. For example, the first metal plate MP1 of the heat dissipation substrate 410B of the second embodiment is partially removed to form the first circuit pattern CP1. The bonding metal layer 411 and the bonding layer 413 on the second insulating substrate SS2 are also removed.

[0334] The embodiment has a special technical effect that etching information (etchant, etching process conditions, etc.) for each heat dissipation substrate can be precisely updated and managed after the hot pressing process.

[0335] Also, referring to FIG. 20, the heat dissipation substrate 410B of the second embodiment can have a first metal plate MP1 of a first thickness T1 laminated on a first surface of a first insulating substrate SS1 facing a specified power semiconductor element 100, and a second metal plate MP2 of a second thickness T2 laminated on a second surface of the first insulating substrate SS1.

[0336] In the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than or equal to the second thickness T2 of the second metal plate MP2. For example, in the second embodiment, the first thickness T1 of the first metal plate MP1 may be less than the second thickness T2 of the second metal plate MP2.

[0337] A first circuit pattern CP1 including a 1-1 pattern p11, a 1-2 pattern p12, and a 1-3 pattern p13 is formed on the first metal plate MP1 by etching.

[0338] According to the heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor element 100 can be controlled to be thin, thereby ensuring a small separation distance between the first circuit patterns CP1 of the first metal plate MP1, thereby providing a high-density power semiconductor module.

[0339] (Inspection and cutting process) Next, a laser scribing process, an inspection process and a cutting process for the heat dissipation substrate will be described with reference to FIGS.

[0340] Referring to FIG. 21, an etching inspection is performed on the heat dissipation substrate after the etching process is completed.

[0341] For heat dissipation boards that pass the etching test, a unique code UC is marked on the metal plate. For example, if one heat dissipation board includes nine snap areas, unique information UC can be marked on each snap area of ​​a metal plate that does not have a circuit pattern formed thereon, for example, the second metal plate MP2.

[0342] The unique information UC marking on each snap area of ​​the second metal plate MP2 may be performed after laser scribing.

[0343] Next, the laser scribing step and the breaking step are carried out.

[0344] In the embodiment, an inspection process is performed after the laser scribing process and before the breaking process. The inspection process may include a scanning ultrasonic test (SAT) for secondarily inspecting voids and cracks at the bonding interface by ultrasonic waves.

[0345] In addition, in the inspection process after the laser scribing process, an automatic appearance inspection process is performed to analyze surface information such as surface roughness, surface pinhole inspection, protrusion inspection, and foreign matter inspection.

[0346] The embodiment has a special technical effect of being able to precisely update and manage secondary bonding interface inspection information and automatic appearance inspection information for each heat dissipation substrate after the etching process.

[0347] Thereafter, the final non-defective product is cut and separated to produce individual heat dissipation substrates as shown in Fig. 22. The second metal plate MP2 of the heat dissipation substrate 410B of the second embodiment shown in Fig. 22 is marked with a unique code UC before delivery.

[0348] As a result, according to the embodiment, the unique information that can confirm information on the history of all processes from the initial storage stage of the product is perfectly integrated with the final product and delivered to the customer, and the customer can accurately understand and use the quality, production history, etc. of the product based on the unique information and can quickly and accurately request after-sales service when necessary.

[0349] On the other hand, simply marking product information on the heat dissipation substrate of the final product does not allow for perfect consistency and management of film formation information such as thickness information of the insulating substrate that constitutes the product, thickness information of the metal plate, and bonding interface information.

[0350] In addition, according to the heat dissipation substrate 410B of the second embodiment, the first thickness T1 of the first metal plate MP1 bonded to the power semiconductor element 100 can be controlled to be thin, thereby ensuring a small separation distance PD between the first circuit patterns CP1 of the first metal plate MP1, thereby providing a high-density power semiconductor module.

[0351] Also, according to the heat dissipation substrate 410C (see FIG. 19b) of the third embodiment, the third thickness T3 of the third metal plate MP3 bonded to the power semiconductor device 100 can be controlled to be thick. As a result, the third thickness T3 of the third circuit pattern CP3 of the third metal plate MP3 is also controlled to be equal to or greater than the second thickness T2 of the second metal plate MP2, thereby preventing the problem of the metal plate material of the heat dissipation substrate being consumed during the formation of an IMC when performing transient liquid phase bonding between the power semiconductor device 100 and the third metal plate MP3, improving the bonding strength, and solving the problem of voids being generated at the bonding interface.

[0352] <Power conversion device including heat dissipation substrate> FIG. 23 is a circuit diagram illustrating a power conversion device 1000 to which the power semiconductor module according to the embodiment is applied.

[0353] The power conversion device 1000 according to the embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor M, and the motor M can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0354] The power conversion device 1000 according to the embodiment may include a power semiconductor device 100. The power semiconductor device 100 may be, but is not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and may include an Insulated Gate Bipolar Transistor (IGBT).

[0355] For example, the power conversion device 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f and may include a plurality of diodes (not shown). Each of the plurality of diodes may be included in the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto and may be disposed separately.

[0356] The embodiment can convert DC power into AC power by controlling the on / off of the multiple power semiconductor elements 100a to 100f. For example, the power conversion device 1000 according to the embodiment can supply positive power to the motor M by turning on the first power semiconductor element 100a and turning off the second power semiconductor element 100b in a first time interval of one cycle, and supply negative power to the motor M by turning off the first power semiconductor element 100a and turning on the second power semiconductor element 100b in a second time interval of one cycle.

[0357] In the embodiment, a group of power semiconductor elements arranged in series on the high voltage line and low voltage line on the input side may be referred to as an arm. For example, the first and second power semiconductor elements 100a and 100b may form a first arm 12a, the third and fourth power semiconductor elements 100c and 100d may form a second arm 12b, and the fifth and sixth power semiconductor elements 100e and 100f may form a third arm 12c.

[0358] The multiple power semiconductor elements 100a to 100f shown in FIG. 23 are packaged as one power semiconductor module, or the power semiconductor elements constituting each arm are packaged as one power semiconductor module.

[0359] In each arm, the upper and lower power semiconductor devices are controlled so as not to be turned on at the same time. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b are not turned on at the same time but can be turned on and off alternately.

[0360] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which is capable of operating in a high temperature and high voltage environment and has a high switching speed while having low switching loss.

[0361] According to the embodiment, there is a technical effect that overall production and quality information and history in the manufacture of heat dissipation substrates, such as thickness information of the insulating substrate, inspection information, thickness information of the copper plate, surface information, and bonding interface information after the bonding process, can be accurately matched, updated, and managed for each "individual heat dissipation substrate."

[0362] In addition, according to the embodiment, even if the position or arrangement of the insulating substrate changes due to an operator's error during the manufacturing process, the application of the embodiment has a technical effect that the history of all processes, from the initial receipt of each insulating substrate, such as the cleaning stage and hot pressing, can be perfectly updated and managed by checking the unique information of each insulating substrate.

[0363] In addition, according to the embodiment, the unique information that can confirm the information on the history of all processes from the initial storage stage of the product is perfectly integrated with the final product and delivered to the customer, and the customer can accurately understand and use the quality, production history, etc. of the product based on the unique information and can quickly and accurately request after-sales service when necessary.

[0364] In addition, according to the embodiment, there is a technical effect that the thickness distribution can be minimized by classifying the individual insulating substrates and metal plates according to their thickness and matching them according to the thickness grade.

[0365] As a result, in the lamination process performed after the sputtering process, the unique IDs of the first to third substrate magazines CM1, CM2, and CM3 are read, and the ceramic substrates and metal plates are matched according to their thickness to perform the lamination and bonding process, thereby achieving the technical effect of optimizing the thickness and quality of the heat dissipation substrate.

[0366] In addition, the embodiment has a technical effect that the thickness of the insulating substrate and the copper plate, which are delivered in various thicknesses, are carefully measured and managed, so that the thickness can be perfectly managed to match each product through unique information, and the thickness distribution can be minimized based on this unique information.

[0367] Furthermore, the embodiment has a technical effect of providing an automatic alignment lamination apparatus capable of automatically laminating and aligning an insulating substrate and a metal plate.

[0368] In particular, according to the embodiment, the bottom surface of the lamination unit 850 has a tilted structure, which provides a special technical effect of enabling precise automatic alignment of corners of the spacer, metal plate, and insulating substrate that are sequentially laminated. For example, according to the embodiment, there is a special technical effect that the tilted lamination can innovatively increase the vertical alignment accuracy by utilizing gravity.

[0369] As a result, precise automatic alignment is possible when tens to over 100 sets are automatically laminated, and even in a hot press bonding process exceeding tens of tons, accurate alignment is maintained and there is no deviation of the laminated set, resulting in a special technical effect of realizing a high-quality heat dissipation substrate.

[0370] Although the present invention has been described above with reference to an embodiment thereof, it should be readily apparent to a person skilled in the art that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A first metal plate; an insulating substrate bonded onto the first metal plate; a second metal plate bonded onto the insulating substrate; A heat dissipation substrate for a power semiconductor module, wherein a first thickness of the first metal plate is different from a second thickness of the second metal plate.

2. 2. The heat dissipation substrate for a power semiconductor module according to claim 1, wherein the first thickness of the first metal plate is smaller than the second thickness of the second metal plate.

3. the first metal plate includes a circuit pattern electrically connected to a predetermined power semiconductor device, The heat dissipation substrate for a power semiconductor module according to claim 1 , wherein the second metal plate includes a unique code marked thereon.

4. A second metal plate; an insulating substrate bonded onto the second metal plate; a third metal plate bonded onto the insulating substrate; A heat dissipation substrate for a power semiconductor module, wherein a third thickness of the third metal plate is greater than a second thickness of the second metal plate.

5. the third metal plate includes a circuit pattern electrically connected to a predetermined power semiconductor device, The heat dissipation substrate for a power semiconductor module according to claim 4 , wherein the second metal plate includes a unique code marked thereon.

6. The heat dissipation substrate for a power semiconductor module according to claim 3 or 5, wherein the unique code includes thickness information of at least one of the insulating substrate, the first metal plate, and the second metal plate.

7. A first heat dissipation substrate; a power semiconductor element disposed on the first heat dissipation substrate; a second heat dissipation substrate disposed on the power semiconductor element; The power semiconductor module, wherein the first heat dissipation substrate or the second heat dissipation substrate comprises the heat dissipation substrate for a power semiconductor module according to claim 1 .

8. The first heat dissipation substrate or the second heat dissipation substrate includes a heat dissipation substrate for a power semiconductor module according to any one of claims 1 to 3, The power semiconductor element is bonded to the circuit pattern of the first metal plate. The power semiconductor module according to claim 7 , further comprising a bonding layer bonded between the circuit pattern of the first metal plate and the power semiconductor element by any one of sintering, soldering, and ultrasonic bonding.

9. The first heat dissipation substrate or the second heat dissipation substrate includes a heat dissipation substrate for a power semiconductor module according to claim 4 or 5, The power semiconductor element is bonded to the circuit pattern of the third metal plate, The power semiconductor module according to claim 7 , further comprising a bonding layer bonded between the circuit pattern of the third metal plate and the power semiconductor element by a phase change bonding method.

10. A power conversion device comprising the power semiconductor module according to claim 7.

Images