Double data rate circuit implementing precise duty cycle control and data generation method

Abstract

To provide a double data rate circuit that implements precise duty cycle control, and a data generation method.SOLUTION: A data generation method is performed by a double data rate circuit including a clock generator, a clock divider, and a multiplexer. The clock generator receives a source clock signal for generating a pair of complementary clock signals, and the clock divider is coupled to the clock generator and generates four multi-phase clock signals that are sequentially out of phase by 90° using only single edge transitions of the pair of complementary clock signals. The multiplexer is coupled to the clock divider and multiplexes multiple data bits into an output data stream by sequentially selecting each data bit of the multiple data bits at each of first and second edge transitions of two of the four multi-phase clock signals, cancelling the selection, and making each selected data bit into the output data stream.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to high speed data processing, and in particular to a double data rate circuit and data generation method that implements precise duty cycle control. [Background technology]

[0002] A double data rate (DDR) system transfers data on both the rising and falling edges of a clock signal. Therefore, the output data from the DDR circuit is aligned with the rising and falling edges of the clock signal, so the duty cycle of the clock signal has a direct effect on the data window of the output data, and a low jitter clock with a 50% duty cycle is essential to optimize the timing behavior of the output signal.

[0003] In the prior art, conventional DDR circuits often suffer from low duty cycle of output data due to imbalance in pull-up and pull-down drive strengths to select the output data. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, a need has arisen for a double data rate circuit and data generation method that implements precise duty cycle control to meet timing requirements, reduce data skew, lower error rates, and enhance system performance. [Means for solving the problem]

[0005] In one embodiment of the present invention, a double data rate circuit is provided, including a clock generator, a clock divider, and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator and used to generate four multi-phase clock signals using only single edge transitions of the pair of complementary clock signals. The four multi-phase clock signals are sequentially out of phase by 90°. The multiplexer is coupled to the clock divider and used to multiplex the multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits at a first edge transition and a second edge transition of two of the four multi-phase clock signals, respectively, and outputting each selected data bit as an output data stream.

[0006] In another embodiment of the present invention, a data generation method is disclosed which is employed by a double data rate circuit including a clock generator, a clock divider, and a multiplexer, the data generation method including the steps of: a clock generator receiving a source clock signal to generate a pair of complementary clock signals, a clock divider generating four multi-phase clock signals using only single edge transitions of the pair of complementary clock signals, the four multi-phase clock signals being 90° out of phase with each other, and a multiplexer multiplexing the multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits at a first edge transition and a second edge transition of two of the four multi-phase clock signals, respectively, and outputting each selected data bit as an output data stream.

[0007] These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, further assist in explaining the principles of the disclosure and in enabling those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram of a double data rate circuit according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a timing diagram of the DDR circuit of FIG. [Diagram 3] FIG. 2 is a block diagram of the clock generator of FIG. [Figure 4] FIG. 2 is a block diagram of the clock divider of FIG. [Diagram 5] FIG. 2 is a block diagram of the multiplexer of FIG. 1. [Figure 6] FIG. 6 is a schematic diagram of matched 3-input NAND gates of the multiplexer of FIG. 5. [Figure 7] FIG. 6 is a schematic diagram of matched 4-input NAND gates of the multiplexer of FIG. [Figure 8] 2 is a flow chart of a data generation method employed by the double data rate circuit of FIG. 1. [Figure 9] FIG. 2 is a diagram showing a simulation of the DDR circuit of FIG. [Figure 10] FIG. 1 illustrates a simulation of a conventional memory controller. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] 1 is a block diagram of a double data rate (DDR) circuit 1 according to an embodiment of the present invention, comprising a clock generator 10, a clock divider 12, and a multiplexer 14. The clock generator 10 is coupled to the clock divider 12, which is then coupled to the multiplexer 14. The double data rate circuit 1 may receive four data bits Dr0, Df0, Dr1, Df1 from a baseband circuit, receive a source clock signal CKs from an external clock source, and multiplex the data bits Dr0, Df0, Dr1, Df1 into one data stream DQ at twice the clock rate of the source clock signal CKs. In particular, the start and end of multiplexing of each of the data bits Dr0, Df0, Dr1, Df1 are controlled by equal numbers of signal edges, respectively, thereby reducing or eliminating timing mismatches between the start and end of multiplexing due to unbalanced pull-up and pull-down drive strengths and / or process variations. The double data rate circuit 1 may be a DDR memory controller that sends the output data stream DQ to a DDR memory. The external clock source refers to a clock generator external to the double data rate circuit 1, and may be a crystal oscillator circuit.

[0011] More specifically, the clock generator 10 may receive a source clock signal CKs to generate a pair of complementary clock signals CK, CKc. The pair of complementary clock signals CK, CKc have a phase difference of about 180° with respect to each other and substantially equal timing delays with respect to the source clock signal CKs. In particular, the clock generator 10 may employ an even number of inverters coupled in series to generate the complementary clock signal CK, and an odd number of inverters coupled in series to generate the complementary clock signal CKc. The sum of the fan-outs of the even number of inverters and the sum of the fan-outs of the odd number of inverters are configured to be substantially the same to ensure substantially equal timing delays of the pair of complementary clock signals CK, CKc.

[0012] The clock divider 12 can generate four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 using only single-edge transitions of a pair of complementary clock signals CK and CKc. The four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 are sequentially out of phase with each other by 90°. The single-edge transitions may be rising edges or falling edges of the pair of complementary clock signals CK and CKc.

[0013] The multiplexer 14 may multiplex the data bits Dr0, Df0, Dr1, Df1 into the output data stream DQ by sequentially selecting and deselecting each of the data bits Dr0, Df0, Dr1, Df1 at the first edge transitions and second edge transitions of two of the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, respectively, and outputting each selected data bit as the output data stream DQ. For example, the multiplexer 14 may select the first data bit Dr0 of the data bits Dr0, Df0, Dr1, Df1 as the output data stream DQ at a first edge transition of a first multi-phase clock signal CKsel_L0 of the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, and deselect the first data bit Dr0 of the data bits Dr0, Df0, Dr1, Df1 as the output data stream DQ at a second edge transition of a second multi-phase clock signal CKsel_L1 of the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1. The first multi-phase clock signal CKsel_L0 and the second multi-phase clock signal CKsel_L1 are out of phase by 90°. The first edge transition and the second edge transition may be opposite clock edges. For example, the first edge transition may be a rising edge and the second edge transition may be a falling edge. The other three data bits Df0, Dr1, Df1 may be selected and / or deselected based on the same principle using other combinations of two multi-phase clock signals of the multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, where the two multi-phase clock signals are also out of phase by 90°.

[0014] 2 is a timing diagram of a DDR circuit 1 including a source clock signal CKs, complementary clock signals CK, CKc, multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, and an output data stream DQ. The source clock signal CKs is used to generate a pair of complementary clock signals CK, CKc having substantially identical delays. The complementary clock signals CK are then used to generate multi-phase clock signals CKsel_L1, CKsel_U1 using the rising edges of the complementary clock signal CK, and similarly, the complementary clock signal CKc is used to generate multi-phase clock signals CKsel_L0, CKsel_U0 using the rising edges of the complementary clock signal CKc. Since only the rising edges are used, the timing skew between any two of the multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1 is reduced or minimized. The multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1 are then used to multiplex the data bits Dr0, Df0, Dr1, Df1. In particular, four pairs of multi-phase clock signals may be selected from the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, respectively, to combine the data bits Dr0, Df0, Dr1, Df1 into the output data stream DQ, and each pair of multi-phase clock signals is out of phase by 90°. For example, when the pair of multi-phase clock signals CKsel_L0, CKsel_L1 are both in logic state “HIGH”, the data bit Dr0 may be selected as the output data bit Q0 of the output data stream DQ, and otherwise the data bit Dr0 may be deselected. To this end, the selection of the data bit Dr0 is triggered by a rising edge of the multi-phase clock signal CKsel_L1, and the deselection of the data bit Dr0 is triggered by a falling edge of the multi-phase clock signal CKsel_L0. Similarly, the data bits Df0, Dr1, Df1 can be sequentially selected as the output data bits Q1, Q2, Q3 of the output data stream DQ.

[0015] Thus, the start of an output data bit in the output data stream DQ depends on the rising edge of one of the first multi-phase clock signals among the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, and the end of an output data bit in the output data stream DQ depends on the falling edge of one of the second multi-phase clock signals among the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1; therefore, the start and end of an output data bit are driven with substantially equal drive strength, which can reduce or eliminate mismatch due to timing and process variations between the start and end delays, thereby generating an output data stream DQ with enhanced duty cycle control.

[0016] The double data rate circuit 1 uses matched circuit components to further control the duty cycle of the output data stream DQ at approximately 50%. More specifically, the clock generator 10, the clock divider 12, and the multiplexer 14 all adopt matched structures, which are described in detail as follows.

[0017] 3 is a block diagram of the clock generator 10 of FIG. 1. The clock generator 10 includes inverters 300, 302, 320, 322, and 324. The inverters 300 and 302 are coupled in series to form a first clock path and receive a source clock CKs to generate a complementary clock signal CK. Similarly, the inverters 320, 322, and 324 are coupled in series to form a second clock path and receive a source clock CKs to generate a complementary clock signal CKc. The fan-out of the inverter 300 is equal to the sum of the fan-outs of the inverters 320 and 322, and can be expressed by the equation Eq(1). FO(inverter 300)=FO(inverter 320)+FO(inverter 322) Eq(1) where FO() is the fanout of the inverter.

[0018] Since the fan-out sums of the inverters on the first clock path and the second clock path are matched, the timing delays of the complementary clock signals CK, CKc are substantially equal. The circuit configuration ensures low or no timing skew while providing a 180° phase difference between the complementary clock signals CK, CKc.

[0019] 4 is a block diagram of the clock divider 12 of FIG. 1. The clock divider 12 comprises first and second pairs of cross-coupled flip-flops. The first pair of cross-coupled flip-flops includes flip-flop 40a and flip-flop 40b that are cross-coupled to each other and receive complementary clock signal CK to generate multi-phase clock signals CKsel_L1, CKsel_U1 by switching multi-phase clock signals CKsel_L1, CKsel_U1 on every rising edge of complementary clock signal CK. Similarly, the second pair of cross-coupled flip-flops includes flip-flop 40c and flip-flop 40d that are cross-coupled to each other and receive complementary clock signal CKc to generate multi-phase clock signals CKsel_L0, CKsel_U0 by switching multi-phase clock signals CKsel_L0, CKsel_U0 on every rising edge of complementary clock signal CKc. The multi-phase clock signals CKsel_L1 and CKsel_U1 have opposite phases, and the multi-phase clock signals CKsel_L0 and CKsel_U0 have opposite phases.

[0020] 5 is a block diagram of the multiplexer 14 of FIG. 1. The multiplexer 14 includes four 3-input NAND gates 50a-50d and a 4-input NAND gate 52 coupled thereto. Each of the four 3-input NAND gates 50a-50d is configured to receive one of the data bits Dr0, Df0, Dr1, Df1 and two of the four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, and to start outputting the received data bit at a first edge transition of one of the two received multi-phase clock signals and to stop outputting the received data bit at a second edge transition of the other one of the two received multi-phase clock signals. The two received multi-phase clock signals are out of phase by 90°. For example, the three-input NAND gate 50b may receive the data bit Df0 and the multi-phase clock signals CKsel_L1, CKsel_U0, and at the rising edge of the multi-phase clock signal CKsel_U0, the three-input NAND gate 50b may start outputting the data bit Df0, and at the falling edge of the multi-phase clock signal CKsel_L1, the three-input NAND gate 50b may stop outputting the data bit Df0. The same operation principle is applied to the other three-input NAND gates 50a, 50c, 50d. Since the received multi-phase clock signals are out of phase by 90°, each data bit may be valid for a period of about a quarter clock cycle and may be coupled to the output data stream DQ by the four-input NAND gate 52. When not outputting a data bit, the three-input NAND gates 50a-50d may output a logic state "HIGH". A four-input NAND gate 52 may receive respective output signals from the four three-input NAND gates 50a-50d to generate an output data stream DQ.Thus, the three-input NAND gates 50a-50d may output valid data bits Dr0, Df0, Dr1, Df1 for a period of one-quarter clock cycle and output a logic state “HIGH” for the remaining time, after which the four-input NAND gate 52 may receive only one valid data bit and the three logic states “HIGH” in any one-quarter clock cycle and combine the data bits Dr0, Df0, Dr1, Df1 into the output data stream DQ. The multiplexer 14 may further comprise a keeper circuit configured to keep the output data stream DQ at a steady state during the standby mode.

[0021] Furthermore, the three-input NAND gates 50a-50d and the four-input NAND gate 52 may be implemented in a matched structure, as shown in FIG. 6 and FIG. 7, to offset the difference in output response speed due to the input connections. In FIG. 6, the input signals A, B, and C of the three-input NAND gate 50 are matched in pull-up and pull-down paths. The three-input NAND gate 50 comprises three P-type metal-oxide-semiconductor field-effect transistors (MOSFETs) Q600-Q604 and nine N-type MOSFETs Q606-Q622. The three P-type MOSFETs Q600-Q604 are coupled in parallel, each receiving a respective input signal A, B, or C. The nine N-type MOSFETs Q606-Q622 are grouped into three groups coupled in parallel. Each group of N-type MOSFETs includes three N-type MOSFETs coupled in series, respectively referred to as the top N-type MOSFET, the middle N-type MOSFET, and the bottom N-type MOSFET. The three groups of N-type MOSFETs may receive input signals A, B, and C in a matched manner, or each of the input signals A, B, and C may be input to the top N-type MOSFET, the middle N-type MOSFET, and the bottom N-type MOSFET of a different group of N-type MOSFETs. Using the matched structure, the output signal Sout3 may respond to the input signals A, B, and C at approximately the same speed. Similarly, in FIG. 7, the four-input NAND gate 52 comprises four P-type MOSFETs Q700-Q706 and sixteen N-type MOSFETs Q710-Q740. The inputs of the four-input NAND gate are matched with pull-up and pull-down paths so that the output signal Sout4 may respond to the input signals A, B, C, and D at approximately the same speed.

[0022] 8 is a flow chart of a data generation method 8 employed by the DDR circuit 1 of FIG. 1. The data generation method 8 includes steps S800-S804 and is used to implement precise duty cycle control for the output data stream DQ. Any reasonable technical changes or step adjustments are within the scope of this disclosure. Steps S800-S804 are detailed as follows: Step S800: The clock generator 10 receives a source clock signal CKs to generate a pair of complementary clock signals CK, CKc. Step S802: The clock divider 12 generates four multi-phase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 using only single-edge transitions of the pair of complementary clock signals CK and CKc. Step S804: The multiplexer 14 multiplexes the multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits at the first edge transitions and the second edge transitions of two of the four multi-phase clock signals, respectively, and outputting each selected data bit as the output data stream.

[0023] Steps S800-S804 have been described in detail in the previous paragraphs, and the description thereof will be omitted for the sake of brevity.

[0024] 9 and 10 respectively show simulations of the DDR circuit 1 of FIG. 1 and a conventional memory controller. It can be seen that the DDR circuit 1 of the present invention can produce a duty cycle of 47.5%, while the conventional memory controller produces a duty cycle of 36.4%.

[0025] As such, the DDR circuit 1 and data generation method 8 can provide enhanced duty cycle control, thereby meeting timing requirements, reducing data skew, lowering error rates, and enhancing system performance.

[0026] Those skilled in the art will readily recognize that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [Explanation of symbols]

[0027] 1 Double Data Rate (DDR) circuit 8 Data Generation Method 10 Clock Generator 12 Clock Dividers 14 Multiplexer 40. Flip-flop 50a~50d 3-input NAND gate 52 4-input NAND gate 300 Inverter 302 Inverter 320 Inverter 322 Inverter 324 Inverter Q600~Q604 P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Q606~Q622 N-type MOSFET Q700~Q706 P-type MOSFET Q710~Q740 N-type MOSFET

Claims

1. 1. A double data rate circuit, comprising: a clock generator configured to receive a source clock signal to generate a pair of complementary clock signals; a clock divider coupled to the clock generator and configured to generate four multi-phase clock signals using only single edge transitions of the pair of complementary clock signals, the four multi-phase clock signals being sequentially out of phase with each other by 90°; a multiplexer coupled to the clock divider and configured to multiplex the plurality of data bits into the output data stream by sequentially selecting and deselecting each data bit of the plurality of data bits at first and second edge transitions, respectively, of two of the four multi-phase clock signals and outputting each selected data bit as an output data stream; A circuit comprising:

2. the multiplexer is configured to select a first data bit of the plurality of data bits for the output data stream upon the first edge transition of a first multi-phase clock signal of the four multi-phase clock signals and to deselect the first data bit of the plurality of data bits for the output data stream upon the second edge transition of a second multi-phase clock signal of the four multi-phase clock signals; the first multi-phase clock signal and the second multi-phase clock signal are out of phase with each other by 90°; The circuit of claim 1 .

3. The circuit of claim 1 , wherein the first edge transition and the second edge transition are opposing clock edges.

4. 2. The circuit of claim 1, wherein the first edge transition is a rising edge and the second edge transition is a falling edge.

5. the multiplexer comprises four 3-input NAND gates and one 4-input NAND gate coupled thereto; each of the four 3-input NAND gates is configured to receive one of four plurality of data bits and two of the four multi-phase clock signals, and to start outputting the received data bit at the first edge transition of one of the two received multi-phase clock signals and to stop outputting the received data bit at the second edge transition of the other one of the two received multi-phase clock signals, the two received multi-phase clock signals being 90° out of phase; the four-input NAND gate configured to receive respective output signals from the four three-input NAND gates to generate the output data stream. The circuit of claim 1 .

6. 6. The circuit of claim 5, wherein the inputs of the three-input NAND gate are matched with pull-up and pull-down paths, and the inputs of the four-input NAND gate are matched with pull-up and pull-down paths.

7. The clock generator includes: an even number of inverters coupled in series to generate one of said complementary clock signals; an odd number of inverters coupled in series to generate another one of said complementary clock signals; Equipped with 2. The circuit of claim 1, wherein a sum of the fan-outs of the even number of inverters is equal to a sum of the fan-outs of the odd number of inverters.

8. The clock divider comprises: a first pair of cross-coupled flip-flops configured to receive one of the complementary clock signals to generate two of the four multi-phase clock signals that are opposite in phase; a second pair of cross-coupled flip-flops configured to receive another one of the complementary clock signals to generate other two of the four multi-phase clock signals that are opposite in phase; and The circuit of claim 1 , comprising:

9. The circuit of claim 1 , wherein the multiplexer further comprises a keeper circuit configured to keep the output data stream in a steady state during a standby mode.

10. A data generation method employed by a double data rate circuit comprising a clock generator, a clock divider, and a multiplexer, comprising: the clock generator receiving a source clock signal for generating a pair of complementary clock signals; using only single edge transitions of the pair of complementary clock signals, the clock divider generates four multi-phase clock signals, the four multi-phase clock signals being 90° out of phase with each other; the multiplexer multiplexing the plurality of data bits into the output data stream by sequentially selecting and deselecting each data bit of the plurality of data bits at a first edge transition and a second edge transition, respectively, of two of the four multi-phase clock signals, and outputting each selected data bit as an output data stream; A method comprising:

11. the multiplexer selecting a first data bit of the plurality of data bits as the output data stream upon the first edge transition of a first multi-phase clock signal of the four multi-phase clock signals; the multiplexer deselecting the first data bit of the plurality of data bits as the output data stream upon the second edge transition of a second multi-phase clock signal of the four multi-phase clock signals; Further comprising:

11. The method of claim 10, wherein the first multi-phase clock signal and the second multi-phase clock signal are 90 degrees out of phase.

12. The method of claim 10 , wherein the first edge transition and the second edge transition are opposing clock edges.

13. The method of claim 10 , wherein the first edge transition is a rising edge and the second edge transition is a falling edge.

14. the multiplexer comprises four 3-input NAND gates and one 4-input NAND gate coupled thereto; The method comprises: each of the four 3-input NAND gates receiving one of four plurality of data bits and two of the four multi-phase clock signals, starting outputting the received data bit at the first edge transition of one of the two received multi-phase clock signals and stopping outputting the received data bit at the second edge transition of the other one of the two received multi-phase clock signals, the two received multi-phase clock signals being 90° out of phase; said four-input NAND gate receiving respective output signals from said four three-input NAND gates to generate said output data stream; The method of claim 10 further comprising:

15. 15. The method of claim 14, wherein the inputs of the three-input NAND gate are matched with pull-up and pull-down paths, and the inputs of the four-input NAND gate are matched with pull-up and pull-down paths.

16. The clock generator includes: an even number of inverters coupled in series to generate one of the pair of complementary clock signals; an odd number of inverters coupled in series to generate another one of the pair of complementary clock signals; Equipped with The method of claim 10 , wherein a sum of the fan-outs of the even number of inverters is equal to a sum of the fan-outs of the odd number of inverters.

17. the clock divider comprises a first pair of cross-coupled flip-flops and a second pair of cross-coupled flip-flops; The method comprises: receiving one of the pair of complementary clock signals by the first pair of cross-coupled flip-flops to generate two of the four multi-phase clock signals that are opposite in phase; receiving another one of the pair of complementary clock signals by a second pair of cross-coupled flip-flops to generate other two of the four multi-phase clock signals that are opposite in phase; The method of claim 10 further comprising:

18. 11. The method of claim 10, wherein the multiplexer further comprises a keeper circuit, the method further comprising the step of the keeper circuit keeping the output data stream at a steady state during a standby mode.

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