Display device and mother board for display device

Abstract

To suppress decrease in reliability.SOLUTION: In an embodiment, a display device includes an organic insulating layer disposed in a display region to display images and a peripheral region outside the display region, a lower electrode disposed on the organic insulating layer in the display region, an inorganic insulating layer disposed on the organic insulating layer and covering the peripheral part of the lower electrode, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, and a plurality of peripheral partition walls disposed in the peripheral region. Each of the peripheral partition walls includes a first lower part existing on the inorganic insulating layer, and a first upper part existing on the first lower part and projecting from the side surface of the first lower part. In the peripheral region, the organic insulating layer includes a flat upper surface and a concave part that is depressed relative to the upper surface. The peripheral partition walls include a first partition wall overlapping with the concave part. The distance from the first upper part of the first partition wall to the edge part of the concave part is 50 μm or more.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device and a mother substrate for the display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer that covers the lower electrode, and an upper electrode that covers the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a motherboard for the display device, which are capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: a substrate; an organic insulating layer disposed above the substrate over a display region for displaying an image and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a flat upper surface and a recess recessed relative to the upper surface in the peripheral region, the plurality of peripheral partitions including a first partition overlapping the recess, and a distance from the first upper portion of the first partition to an edge of the recess is 50 μm or more.

[0006] According to one embodiment, the display device comprises: a substrate; an organic insulating layer disposed above the substrate over a display region for displaying an image and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a flat upper surface in the peripheral region, a recess recessed relative to the upper surface, and a slope surrounding the recess, the plurality of peripheral partitions including a first partition overlapping the recess and a second partition overlapping the upper surface, and the inorganic insulating layer has a missing portion overlapping the slope.

[0007] According to one embodiment, a mother substrate for a display device includes: a display region for displaying an image and a peripheral region outside the display region; a margin portion outside the panel portion; and an organic insulating layer disposed across the panel portion and the margin portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral region and the margin portion, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the inorganic insulating layer having a flat upper surface and a recess recessed relative to the upper surface in the peripheral region or the margin portion, the plurality of peripheral partitions including a first partition overlapping the recess, and a distance from the first upper portion of the first partition to an edge of the recess is 50 μm or more.

[0008] According to one embodiment, a mother substrate for a display device includes: A panel section having a display area for displaying an image and a peripheral area outside the display area, a margin area outside the panel section, and an organic insulating layer disposed across the panel section and the margin area, a lower electrode disposed on the organic insulating layer in the display area, an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral area of ​​the lower electrode, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, and a plurality of peripheral electrodes disposed in the peripheral area and the margin area. and a peripheral partition, each of the plurality of peripheral partitions having a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a flat upper surface, a recess recessed relative to the upper surface, and a slope surrounding the recess in the peripheral region or the margin portion, the plurality of peripheral partitions including a first partition overlapping the recess and a second partition overlapping the upper surface, and the inorganic insulating layer having a missing portion overlapping the slope. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a diagram for explaining a manufacturing method of the display device DSP. [Diagram 5] FIG. 5 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 7] FIG. 7 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a plan view showing an example of the mother substrate 100. As shown in FIG. [Figure 11] FIG. 11 is a plan view showing a configuration example of the pad PD or the terminal TE. [Figure 12] FIG. 12 is a cross-sectional view showing an example of the configuration of the motherboard 100. As shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 19] FIG. 19 is a plan view showing an example of the configuration of the region 100A of the mother substrate 100 shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view showing an example of the configuration of the motherboard 100. As shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 24] FIG. 24 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 25] FIG. 25 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 26] FIG. 26 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 27] FIG. 27 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 28] FIG. 28 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 29] FIG. 29 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 30] FIG. 30 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 31] FIG. 31 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 32] FIG. 32 is a diagram for explaining one of the effects of this embodiment. [Diagram 33] FIG. 33 is a plan view showing an example of the peripheral partition 7 disposed in the recess DP of the organic insulating layer IL. [Diagram 34] FIG. 34 is a plan view showing another configuration example of the pad PD or the terminal TE. [Diagram 35] FIG. 35 is a cross-sectional view showing an example of a configuration of the motherboard 100. As shown in FIG. [Diagram 36]FIG. 36 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 37] FIG. 37 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 38] FIG. 38 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 39] FIG. 39 is a cross-sectional view showing another example of the configuration of the mother substrate 100. As shown in FIG. [Diagram 40] FIG. 40 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 41] FIG. 41 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 42] FIG. 42 is a plan view showing another configuration example of the region 100A shown in FIG. [Diagram 43] FIG. 43 is a cross-sectional view showing an example of a configuration of the motherboard 100. As shown in FIG. [Diagram 44] FIG. 44 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Diagram 45] FIG. 45 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 46] FIG. 46 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 47] FIG. 47 is a cross-sectional view showing another example of the configuration of the mother substrate 100. As shown in FIG. [Figure 48] FIG. 48 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 49] FIG. 49 is a cross-sectional view showing another example of the configuration of the mother substrate 100. As shown in FIG. [Figure 50] FIG. 50 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 51] FIG. 51 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 52] FIG. 52 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 53] FIG. 53 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 54]FIG. 54 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. [Figure 55] FIG. 55 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in a region including the missing portion LP shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0011] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0012] The display device according to this embodiment is an organic electroluminescence display device having an organic light emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0013] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0014] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0015] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0016] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, the second color, and the third color are different from each other. The pixel PX may include a subpixel SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0017] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0018] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0019] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0020] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0021] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limited thereto. For example, some of the plurality of terminals TE may extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0022] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0023] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0024] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0025] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0026] In the display region DA, an inorganic insulating layer 5 and a partition wall 6 are disposed. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0027] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and is electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1.

[0028] The sub-pixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0029] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The periphery of each of the organic layer OR1 and the upper electrode UE1 overlaps the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0030] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The periphery of each of the organic layer OR2 and the upper electrode UE2 overlaps the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0031] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The periphery of each of the organic layer OR3 and the upper electrode UE3 overlaps the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in, for example, a red wavelength region.

[0032] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes illustrated in the drawings do not necessarily reflect the exact shapes.

[0033] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode, and are in contact with the partition walls 6.

[0034] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0035] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another. The area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0036] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0037] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0038] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. The contact holes in the insulating layer 12 are omitted in FIG. 3.

[0039] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0040] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed to be thinner than the second conductive layer 64. In addition, in the illustrated example, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64. The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both end portions of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the second conductive layer 64.

[0041] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61.

[0042] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower portion 61.

[0043] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has a peripheral portion located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0044] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. The cap layers CP1, CP2, and CP3 may be omitted.

[0045] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0046] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0047] In the illustrated example, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are separated from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located in the aperture AP1 (parts constituting the display element DE1).

[0048] Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition 6 surrounding the subpixel SP2, and these portions are spaced apart from portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (portions that constitute the display element DE2).

[0049] Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition 6 surrounding the subpixel SP3, and these portions are spaced apart from portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (portions that constitute the display element DE3).

[0050] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is referred to as a laminate film FL3.

[0051] Ends of the sealing layers SE1, SE2, and SE3 and ends of the stacked films FL1, FL2, and FL3 are located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0052] The partition 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0053] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0054] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0055] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0056] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers. The lower transparent layer functions as an adhesive layer that adheres to the insulating layer 12.

[0057] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the emitting layer EM3 is formed of a material that emits light in a red wavelength range. In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0058] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0059] The cap layers CP1, CP2, and CP3 are multilayer structures made up of a plurality of thin films, all of which are transparent and have different refractive indices.

[0060] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0061] Next, a method for manufacturing the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the insulating layer 12 is omitted.

[0062] First, a circuit layer 11 and an insulating layer 12 are formed on a substrate 10 across the display area DA and the peripheral area SA, and then, as shown in FIG. 4, a lower electrode LE1 of subpixel SP1, a lower electrode LE2 of subpixel SP2, and a lower electrode LE3 of subpixel SP3 are formed on the insulating layer 12. Thereafter, an inorganic insulating layer 5 is formed to cover the peripheries of the lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 5 is made of silicon oxide, silicon nitride, silicon oxynitride, or the like. Thereafter, a partition wall 6 is formed having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from a side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a conductive material such as a titanium-based material, and the second conductive layer 64 is formed of a conductive material such as an aluminum-based material. The step of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after the partition wall 6 is formed.

[0063] Next, the display element DE1 is formed.

[0064] First, as shown in FIG. 5, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes a process of forming an organic layer OR1 that contacts the lower electrode LE1 at the opening AP1, a process of forming an upper electrode UE1 that covers the organic layer OR1 and contacts the lower portion 61 of the partition wall 6, and a process of forming a cap layer CP1 located on the upper electrode UE1. The process of forming the organic layer OR1 also includes a process of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by deposition using the partition wall 6 as a mask. The laminated film FL1 is divided into a plurality of parts by the overhanging partition wall 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0065] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each of the divided portions of the laminated film FL1 and the partition walls 6.

[0066] 6, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0067] 7, etching is performed using the resist RS as a mask to sequentially remove the sealing layer SE1 and stacked film FL1 exposed from the resist RS. In this etching, after removing the sealing layer SE1 exposed from the resist RS, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after removing the upper electrode UE1 exposed from the cap layer CP1, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed. Thereafter, the resist RS is removed, thereby forming a display element DE1 in the subpixel SP1.

[0068] Next, as shown in FIG. 8, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0069] Next, as shown in FIG. 9, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. As a result, a display element DE3 is formed in the subpixel SP3.

[0070] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 are formed in this order, thereby completing the display device DSP.

[0071] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order of formation of display elements DE1, DE2, and DE3 is not limited to this example.

[0072] Next, a display device mother substrate (hereinafter simply referred to as a mother substrate) 100 for collectively manufacturing a plurality of display devices DSP will be described.

[0073] FIG. 10 is a plan view showing an example of the mother substrate 100. As shown in FIG.

[0074] The mother substrate 100 includes a plurality of panel portions PP and a margin portion MP on the outer side of the panel portions PP on a large substrate 10. The large substrate 10 is formed, for example, in a rectangular shape. The plurality of panel portions PP are arranged in a matrix in a first direction X and a second direction Y. Each of the panel portions PP is extracted by cutting the mother substrate 100 along a cut line. Each of the extracted panel portions PP corresponds to the display panel PNL shown in FIG. 1 and includes a display area DA and a peripheral area SA. The blank portion MP has, for example, a plurality of pads PD electrically connected to a test element group or the like.

[0075] FIG. 11 is a plan view showing a configuration example of the pad PD or the terminal TE.

[0076] The pads PD correspond to, for example, the pads PD in the marginal portion MP shown in Fig. 10. The terminals TE correspond to, for example, the terminals TE in the peripheral area SA shown in Fig. 1.

[0077] The organic insulating layer IL includes, for example, the insulating layer 12 shown in FIG. 3. As will be described later, the organic insulating layer IL may be a single layer of the insulating layer 12 or another insulating layer, or may be a multilayer of the insulating layer 12 and another insulating layer. The organic insulating layer IL is disposed on each of the panel portions PP and also on the margin portion MP. Note that the inorganic insulating layer 5, not shown here, is also disposed not only on the panel portion PP but also on the margin portion MP.

[0078] The metal layer MT indicated by the dashed line corresponds to, for example, the pad PD or the electrode of the terminal TE. The metal layer MT overlaps the recess DP of the organic insulating layer IL in a plan view. The recess DP corresponds to a through portion of the organic insulating layer IL and exposes a part of the metal layer MT. The peripheral portion of the metal layer MT is covered with the organic insulating layer IL or the inorganic insulating layer 5.

[0079] Next, several configuration examples will be described regarding the cross-sectional structure of the motherboard 100 taken along line CD in FIG.

[0080] FIG. 12 is a cross-sectional view showing an example of the configuration of the motherboard 100. As shown in FIG.

[0081] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The wiring layer 112 is disposed on the insulating layer 111. The insulating layer 113 is an inorganic insulating layer and is disposed on the wiring layer 112. The insulating layer 113 exposes a part of the wiring layer 112. The insulating layer 114 is an organic insulating layer and is disposed on the insulating layer 113. The metal layer MT is in contact with the wiring layer 112. The peripheral portion of the metal layer MT is disposed on the insulating layer 114. As a result, the metal layer MT is electrically connected to the wiring layer 112. The insulating layer 111, the wiring layer 112, the insulating layer 113, the insulating layer 114, and the metal layer MT are included in the circuit layer 11 shown in FIG. 3. The circuit layer 11 may include an insulating layer and a conductive layer in addition to the layers shown in the figure.

[0082] The insulating layer 12 is an organic insulating layer, and is disposed on the insulating layer 114 and the metal layer MT. The insulating layer 114 is recessed from the insulating layer 12 and is covered with the insulating layer 12. The peripheral portion of the metal layer MT is covered with the insulating layer 12.

[0083] The organic insulating layer IL has an insulating layer 114 and an insulating layer 12. The organic insulating layer IL has a flat upper surface TS, a recess DP recessed relative to the upper surface TS, and a slope SS surrounding the recess DP. The recess DP is a penetration portion of the insulating layer 12 formed to expose the metal layer MT. The upper surface TS is the upper surface of the insulating layer 12. The slope SS is a slope connected to the upper surface of the insulating layer 12. An edge DPE of the recess DP is defined as an edge of the insulating layer 12. An edge TSE of the upper surface TS is defined as an intersection of the upper surface TS and the slope SS.

[0084] The inorganic insulating layer 5 covers the insulating layer 12 and contacts the metal layer MT at a recess DP. The inorganic insulating layer 5 has an opening OP overlapping the recess DP. The opening OP is a through-portion of the inorganic insulating layer 5 formed so as to expose the metal layer MT. The area of ​​the opening OP is smaller than the area of ​​the recess DP.

[0085] The multiple peripheral partitions 7 are arranged so as to overlap the upper surface TS and recesses DP of the organic insulating layer IL. Each of the peripheral partitions 7 has a lower portion 71 arranged on the inorganic insulating layer 5 and an upper portion 72 arranged on the lower portion 71. The upper portion 72 has a width greater than that of the lower portion 71. Both end portions of the upper portion 72 protrude beyond the side surfaces of the lower portion 71.

[0086] In this manner, the peripheral partition wall 7 has an overhanging shape similar to the partition wall 6 shown in Fig. 3. The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the lower portion 71 is formed of the same material as the lower portion 61, and the upper portion 72 is formed of the same material as the upper portion 62.

[0087] Focusing on the peripheral partition (first partition) 7 located in the recess DP, the distance D1 from the edge of the upper portion 72 to the edge DPE of the recess DP is 50 μm or more.

[0088] Focusing on the peripheral partition (second partition) 7 located above the upper surface TS, the distance D2 from the edge of the upper portion 72 to the edge TSE of the upper surface TS is 20 μm or more.

[0089] FIG. 13 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0090] The configuration example shown in FIG. 13 differs from the configuration example shown in FIG. 12 in that the organic insulating layer IL is a single layer of the insulating layer 114 at least around the recess DP.

[0091] The recess DP of the organic insulating layer IL is a penetration of the insulating layer 114 formed to expose the metal layer MT. The top surface TS is the top surface of the insulating layer 114. The slope SS is a slope connected to the top surface of the insulating layer 114. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the top surface TS is defined as the intersection of the top surface TS and the slope SS.

[0092] The inorganic insulating layer 5 is disposed on the insulating layer 114 and the metal layer MT. The peripheral edge of the metal layer MT is covered with the inorganic insulating layer 5. An opening OP in the inorganic insulating layer 5 exposes the metal layer MT.

[0093] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0094] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0095] FIG. 14 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0096] The configuration example shown in FIG. 14 differs from the configuration example shown in FIG. 12 in that the organic insulating layer IL is a single layer of the insulating layer 12 at least around the recess DP.

[0097] The recess DP in the organic insulating layer IL is a penetration in the insulating layer 12 formed to expose the metal layer MT. The top surface TS is the top surface of the insulating layer 12. The slope SS is a slope connected to the top surface of the insulating layer 12. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the top surface TS is defined as the intersection of the top surface TS and the slope SS.

[0098] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the metal layer MT. The peripheral edge of the metal layer MT is covered with the inorganic insulating layer 5. An opening OP in the inorganic insulating layer 5 exposes the metal layer MT.

[0099] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0100] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0101] FIG. 15 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0102] The configuration example shown in FIG. 15 differs from the configuration example shown in FIG. 12 in that the organic insulating layer IL has a stepped cross section.

[0103] The insulating layer 114 extends further toward the recess DP than the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114. The peripheral edge of the metal layer MT is located between the insulating layer 114 and the insulating layer 12.

[0104] The organic insulating layer IL has an upper surface TS1 located at the topmost position around the recess DP, an upper surface TS2 located below the upper surface TS1, and a slope SS between the upper surface TS1 and the upper surface TS2. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0105] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 114 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0106] The inorganic insulating layer 5 is disposed on the insulating layer 12, the metal layer MT, and the insulating layer 114. An opening OP in the inorganic insulating layer 5 exposes the metal layer MT.

[0107] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0108] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0109] FIG. 16 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0110] The configuration example shown in FIG. 16 differs from the configuration example shown in FIG. 12 in that the organic insulating layer IL has a stepped cross section.

[0111] The insulating layer 114 is recessed from the insulating layer 12 and is covered with the insulating layer 12. The peripheral edge of the metal layer MT is located between the insulating layer 114 and the insulating layer 12.

[0112] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slope SS around the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0113] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 12 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0114] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the metal layer MT. An opening OP in the inorganic insulating layer 5 exposes the metal layer MT.

[0115] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0116] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0117] FIG. 17 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0118] The configuration example shown in FIG. 17 differs from the configuration example shown in FIG. 12 in that the organic insulating layer IL has a stepped cross section.

[0119] The insulating layer 114 extends further toward the recess DP than the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114. The peripheral edge of the metal layer MT is located between the insulating layer 114 and the insulating layer 12.

[0120] The organic insulating layer IL has an upper surface TS and a sloped surface SS. The upper surface TS is the upper surface of the insulating layer 12. The sloped surface SS is a sloped surface of the insulating layer 12.

[0121] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 114 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the top surface TS is defined as the intersection of the top surface TS and the beveled surface SS.

[0122] The inorganic insulating layer 5 is disposed on the insulating layer 12, the metal layer MT, and the insulating layer 114. An opening OP in the inorganic insulating layer 5 exposes the metal layer MT.

[0123] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0124] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0125] FIG. 18 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0126] The configuration example shown in FIG. 18 differs from the configuration example shown in FIG. 12 in that the organic insulating layer IL is a single layer and has a stepped cross section at least around the recess DP.

[0127] The insulating layer 12 is disposed on the insulating layer 113. The peripheral edge of the metal layer MT is located between the insulating layer 113 and the insulating layer 12.

[0128] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slope SS around the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0129] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 12 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0130] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the metal layer MT. An opening OP in the inorganic insulating layer 5 exposes the metal layer MT.

[0131] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0132] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0133] FIG. 19 is a plan view showing an example of the configuration of the region 100A of the mother substrate 100 shown in FIG.

[0134] The region 100A includes one panel portion PP. Cut lines CL shown by dashed lines in the figure extend, for example, along the first direction X and the second direction Y. These cut lines CL may form the outline of the display panel PNL shown in Fig. 1. Each panel portion PP includes a display area DA and a peripheral area SA.

[0135] The organic insulating layer IL is disposed on each panel portion PP and also on the margin portion MP. The organic insulating layer IL has a recess DP that follows the outer shape of the panel portion PP. The cut line CL overlaps the recess DP. The recess DP may be a through portion of the organic insulating layer IL or a thin portion of the organic insulating layer IL. The recess DP is formed in a lattice shape surrounding each panel portion PP. In the illustrated example, the recess DP extends in the first direction X and the second direction Y, respectively.

[0136] Focusing on one panel unit PP, the recess DP is formed in a loop shape surrounding the panel unit PP. In the panel unit PP, the display area DA overlaps the organic insulating layer IL. In addition, a part of the peripheral area SA also overlaps the organic insulating layer IL.

[0137] Next, several configuration examples will be described regarding the cross-sectional structure of the motherboard 100 taken along line EF in FIG.

[0138] FIG. 20 is a cross-sectional view showing an example of the configuration of the motherboard 100. As shown in FIG.

[0139] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The insulating layer 113 is an inorganic insulating layer and is disposed on the insulating layer 111. The insulating layer 114 is an organic insulating layer and is disposed on the insulating layer 113. The insulating layers 111, 113, and 114 are included in the circuit layer 11 shown in Fig. 3. Note that the circuit layer 11 may include an insulating layer and a conductive layer in addition to the layers shown in the figure.

[0140] The insulating layer 12 is an organic insulating layer, and is disposed on the insulating layers 113 and 114. The insulating layer 114 is recessed from the insulating layer 12 and is covered with the insulating layer 12.

[0141] The organic insulating layer IL has an insulating layer 114 and an insulating layer 12. The organic insulating layer IL has a flat upper surface TS, a recess DP recessed relative to the upper surface TS, and a slope SS surrounding the recess DP. The recess DP is a penetration portion of the insulating layer 12 formed to expose the insulating layer 113. The upper surface TS is the upper surface of the insulating layer 12. The slope SS is a slope connected to the upper surface of the insulating layer 12. An edge DPE of the recess DP is defined as the edge of the insulating layer 12. An edge TSE of the upper surface TS is defined as the intersection of the upper surface TS and the slope SS.

[0142] The inorganic insulating layer 5 covers the insulating layer 12, and also covers the insulating layer 113 in the recess DP.

[0143] The multiple peripheral partitions 7 are arranged so as to overlap the upper surface TS and recesses DP of the organic insulating layer IL. Each of the peripheral partitions 7 has a lower portion 71 arranged on the inorganic insulating layer 5 and an upper portion 72 arranged on the lower portion 71. The peripheral partitions 7 have an overhang shape similar to the partitions 6 shown in FIG. 3. The peripheral partitions 7 can be formed in the same process as the partitions 6.

[0144] Focusing on the peripheral partition (first partition) 7 located in the recess DP, the distance D1 from the edge of the upper portion 72 to the edge DPE of the recess DP is 50 μm or more.

[0145] Focusing on the peripheral partition (second partition) 7 located above the upper surface TS, the distance D2 from the edge of the upper portion 72 to the edge TSE of the upper surface TS is 20 μm or more.

[0146] FIG. 21 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0147] The configuration example shown in FIG. 21 differs from the configuration example shown in FIG. 20 in that the organic insulating layer IL is a single layer of the insulating layer 114 at least around the recess DP.

[0148] The recess DP of the organic insulating layer IL is a penetration of the insulating layer 114 formed to expose the insulating layer 113. The top surface TS is the top surface of the insulating layer 114. The slope SS is a slope connected to the top surface of the insulating layer 114. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the top surface TS is defined as the intersection of the top surface TS and the slope SS.

[0149] The inorganic insulating layer 5 covers the insulating layer 114, and covers the insulating layer 113 in the recess DP.

[0150] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0151] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0152] FIG. 22 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0153] The configuration example shown in FIG. 22 differs from the configuration example shown in FIG. 20 in that the organic insulating layer IL is a single layer of the insulating layer 12 at least around the recess DP.

[0154] The recess DP of the organic insulating layer IL is a penetration of the insulating layer 12 formed to expose the insulating layer 113. The top surface TS is the top surface of the insulating layer 12. The slope SS is a slope connected to the top surface of the insulating layer 12. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the top surface TS is defined as the intersection of the top surface TS and the slope SS.

[0155] The inorganic insulating layer 5 covers the insulating layer 12, and also covers the insulating layer 113 in the recess DP.

[0156] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0157] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0158] FIG. 23 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0159] The configuration example shown in FIG. 23 differs from the configuration example shown in FIG. 20 in that the organic insulating layer IL has a stepped cross section.

[0160] The insulating layer 114 extends toward the recess DP further than the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114, exposing the insulating layer 114 adjacent to the recess DP.

[0161] The organic insulating layer IL has an upper surface TS1 located at the topmost position around the recess DP, an upper surface TS2 located below the upper surface TS1, and a slope SS between the upper surface TS1 and the upper surface TS2. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0162] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 114 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0163] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114, and covers the insulating layer 113 in the recess DP.

[0164] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0165] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0166] FIG. 24 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0167] The configuration example shown in FIG. 24 differs from the configuration example shown in FIG. 20 in that the organic insulating layer IL has a stepped cross section.

[0168] The insulating layer 114 is recessed from the insulating layer 12 and is covered with the insulating layer 12 .

[0169] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slope SS around the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0170] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 12 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0171] The inorganic insulating layer 5 covers the insulating layer 12, and also covers the insulating layer 113 in the recess DP.

[0172] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0173] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0174] FIG. 25 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0175] The configuration example shown in FIG. 25 differs from the configuration example shown in FIG. 20 in that the organic insulating layer IL has a stepped cross section.

[0176] The insulating layer 114 extends toward the recess DP further than the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114.

[0177] The organic insulating layer IL has an upper surface TS and a sloped surface SS. The upper surface TS is the upper surface of the insulating layer 12. The sloped surface SS is a sloped surface of the insulating layer 12.

[0178] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 114 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the top surface TS is defined as the intersection of the top surface TS and the slope SS.

[0179] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114, and covers the insulating layer 113 in the recess DP.

[0180] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0181] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0182] FIG. 26 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0183] The configuration example shown in FIG. 26 differs from the configuration example shown in FIG. 20 in that the organic insulating layer IL is a single layer and has a stepped cross section at least around the recess DP.

[0184] Insulating layer 12 is disposed on insulating layer 113 .

[0185] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slope SS around the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0186] The recess DP in the organic insulating layer IL is a penetration through the insulating layer 12 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0187] The inorganic insulating layer 5 covers the insulating layer 12, and also covers the insulating layer 113 in the recess DP.

[0188] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0189] The distance D1 with respect to the peripheral partition 7 located in the recess DP and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0190] FIG. 27 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0191] The configuration example shown in FIG. 27 differs from the configuration example shown in FIG. 20 in that the recess DP of the organic insulating layer IL is a thin portion.

[0192] The insulating layer 114 is disposed on the insulating layer 113. The insulating layer 12 covers the insulating layer 113 and the insulating layer 114.

[0193] The organic insulating layer IL has an insulating layer 114 and an insulating layer 12. The organic insulating layer IL has a flat upper surface TS1, a recess DP recessed relative to the upper surface TS1, a flat upper surface TS2 located below the upper surface TS1, and a slope SS located between the upper surfaces TS1 and TS2 and surrounding the recess DP. The upper surface TS2 corresponds to the bottom surface of the recess DP. The recess DP corresponds to a thin portion of the organic insulating layer IL formed only by the insulating layer 12. In the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL.

[0194] The thickness T0 of the organic insulating layer IL is the sum of the thicknesses of the insulating layer 114 and the insulating layer 12, and corresponds to the length along the third direction Z from the upper surface of the insulating layer 113 to the upper surface TS1. The thickness T2 of the organic insulating layer IL corresponds to the thickness of the thin portion of the organic insulating layer IL that forms the recess DP, and corresponds to the thickness of only the insulating layer 12, not including the insulating layer 114. In other words, the thickness T2 corresponds to the length along the third direction Z from the upper surface of the insulating layer 113 to the upper surface TS2. The thickness T2 is smaller than the thickness T0 (T0>T2). Moreover, the thickness T1 of the insulating layer 12 that overlaps the insulating layer 114 is approximately equal to the thickness T2 (T1≒T2).

[0195] The top surfaces TS1 and TS2 are the top surfaces of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The edge DPE of the recess DP is defined as the intersection of the top surface TS2 and the slope SS. The edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 and the slope SS.

[0196] The inorganic insulating layer 5 covers the insulating layer 12 .

[0197] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0198] The distance D1 with respect to the peripheral partition 7 located above the top surface TS2 or in the recess DP, and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0199] FIG. 28 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0200] The configuration example shown in FIG. 28 differs from the configuration example shown in FIG. 27 in that the organic insulating layer IL has a stepped cross section and the recess DP of the organic insulating layer IL is a thin portion.

[0201] Insulating layer 114 is disposed on insulating layer 113. Insulating layer 12 is disposed on insulating layer 114.

[0202] The organic insulating layer IL has an upper surface TS1 located at the topmost position around the recess DP, an upper surface TS2 located below the upper surface TS1, and a slope SS between the upper surface TS1 and the upper surface TS2. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure amount for each portion.

[0203] The recess DP of the organic insulating layer IL is a penetration portion of the insulating layer 12 formed to expose the insulating layer 114, and corresponds to a thin portion of the organic insulating layer IL formed only of the insulating layer 114. In addition, in the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL. An edge portion DPE of the recess DP is defined as an edge portion of the insulating layer 12. An edge portion TSE of the upper surface TS1 is defined as an intersection portion between the upper surface TS1 and the slope SS.

[0204] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114 .

[0205] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0206] The distance D1 with respect to the peripheral partition 7 located above the insulating layer 114 or in the recess DP, and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0207] FIG. 29 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0208] The configuration example shown in FIG. 29 is different from the configuration example shown in FIG. 20 in that the recess DP of the organic insulating layer IL is a thin portion.

[0209] The insulating layer 114 and the insulating layer 113 are covered with the insulating layer 12 .

[0210] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a sloped surface SS. The upper surface TS2 corresponds to the bottom surface of the recess DP. The recess DP corresponds to a thin portion of the organic insulating layer IL that is formed only by the insulating layer 12. In the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL.

[0211] Thickness T2 is smaller than thickness T0 (T0>T2). Thickness T2 is smaller than thickness T1 (T1>T2). Top surfaces TS1 and TS2 are top surfaces of insulating layer 12. Slope SS is a slope of insulating layer 12. Insulating layer 12 having such a stepped cross section is formed by adjusting the exposure dose for each portion.

[0212] An edge DPE of the recess DP is defined as the intersection of the top surface TS2 with the beveled surface SS. An edge TSE of the top surface TS1 is defined as the intersection of the top surface TS1 with the beveled surface SS.

[0213] The inorganic insulating layer 5 covers the insulating layer 12 .

[0214] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0215] The distance D1 with respect to the peripheral partition 7 located above the top surface TS2 or in the recess DP, and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0216] FIG. 30 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0217] The configuration example shown in FIG. 30 differs from the configuration example shown in FIG. 20 in that the recess DP of the organic insulating layer IL is a thin portion.

[0218] Insulating layer 114 is disposed on insulating layer 113. Insulating layer 12 is disposed on insulating layer 114.

[0219] The organic insulating layer IL has an upper surface TS and a sloped surface SS. The upper surface TS is the upper surface of the insulating layer 12. The sloped surface SS is a sloped surface of the insulating layer 12.

[0220] The recess DP of the organic insulating layer IL is a penetration portion of the insulating layer 12 formed to expose the insulating layer 114, and corresponds to a thin portion of the organic insulating layer IL formed only of the insulating layer 114. In addition, in the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL. An edge portion DPE of the recess DP is defined as an edge portion of the insulating layer 12. An edge portion TSE of the top surface TS is defined as an intersection portion between the top surface TS and the slope SS.

[0221] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114 .

[0222] The peripheral partition walls 7 are arranged so as to overlap the upper surface TS and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0223] The distance D1 with respect to the peripheral partition 7 located above the insulating layer 114 or in the recess DP, and the distance D2 with respect to the peripheral partition 7 located above the top surface TS are as described above.

[0224] FIG. 31 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG.

[0225] The configuration example shown in Figure 31 differs from the configuration example shown in Figure 20 in that the recess DP of the organic insulating layer IL is a thin-walled portion, and at least around the recess DP, the organic insulating layer IL is a single layer body and has a stepped cross-section.

[0226] Insulating layer 12 is disposed on insulating layer 113 .

[0227] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a sloped surface SS. The upper surface TS2 corresponds to the bottom surface of the recess DP. The recess DP corresponds to a thin portion of the organic insulating layer IL that is formed only by the insulating layer 12. In the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL.

[0228] The thickness T0 of the organic insulating layer IL corresponds to the thickness of the insulating layer 12 along the third direction Z from the upper surface of the insulating layer 113 to the upper surface TS1. The thickness T2 of the organic insulating layer IL is the thickness of the thin portion of the organic insulating layer IL that forms the recess DP, and corresponds to the thickness of the insulating layer 12 along the third direction Z from the upper surface of the insulating layer 113 to the upper surface TS2. The thickness T2 is smaller than the thickness T0 (T0>T2).

[0229] The upper surfaces TS1 and TS2 are the upper surface of the insulating layer 12. The slope SS is a slope of the insulating layer 12. The insulating layer 12 having such a stepped cross section is formed by adjusting the exposure dose for each part. The edge DPE of the recess DP is defined as the intersection of the upper surface TS2 and the slope SS. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slope SS.

[0230] The inorganic insulating layer 5 covers the insulating layer 12 .

[0231] The multiple peripheral partition walls 7 are arranged so as to overlap the upper surface TS1 and the recesses DP of the organic insulating layer IL, and each has an overhanging shape.

[0232] The distance D1 with respect to the peripheral partition 7 located above the top surface TS2 or in the recess DP, and the distance D2 with respect to the peripheral partition 7 located above the top surface TS1 are as described above.

[0233] In each of the configuration examples shown in FIGS. 20 to 31, the inorganic insulating layer 5 may have an opening OP overlapping the recess DP, similar to the configuration example shown in FIG.

[0234] FIG. 32 is a diagram for explaining one of the effects of this embodiment.

[0235] The mother substrate 100 has, as recesses DP in the organic insulating layer IL, portions where the insulating layer 114 and the insulating layer 12 are missing, portions where the insulating layer 12 is missing but the insulating layer 114 remains, and portions where the insulating layer 114 is missing but the insulating layer 12 remains. Note that in the figure, elements other than the organic insulating layer IL, the peripheral partition 7, and the resist RS are omitted.

[0236] For example, the process of forming the resist RS shown in Fig. 6 includes a step of applying the liquid resist RS. The arrow AD in the figure indicates the application direction of the resist RS.

[0237] In the recess DP of the organic insulating layer IL, the peripheral partition 7 is disposed at a position of distance D1 from the edge DPE of the recess DP. As described above, the distance D1 is 50 μm or more. As a result, when the resist RS is applied to the recess DP, the resist RS flows into the region between the peripheral partition 7 and the slope of the organic insulating layer IL (the region near the edge DPE), and spreads while contacting the peripheral partition 7. This prevents undesired voids from being formed in the resist RS. In other words, as shown in FIG. 7, the region to be protected during subsequent etching can be reliably covered with the resist RS.

[0238] In addition, when the distance D1 is less than 50 μm, the inventors have confirmed that when the resist RS flows into the recess DP, it is difficult for the resist RS to fill below the upper part 72 of the peripheral partition 7, and voids are likely to form around the peripheral partition 7.

[0239] On the upper surface TS of the organic insulating layer IL, the peripheral partition 7 is disposed at a position of a distance D2 from the edge portion TSE of the upper surface TS. As described above, the distance D2 is 20 μm or more. This allows the resist RS, when applied, to flow into the recess DP and spread while also contacting the peripheral partition 7 on the upper surface TS. This prevents undesired voids from being formed in the resist RS.

[0240] Furthermore, when the distance D2 is less than 20 μm, the inventors' investigations have confirmed that a large step is formed between the recess DP of the organic insulating layer IL and the peripheral partition 7 arranged on the upper surface TS, making it easy for gaps to form near the edge DPE of the recess DP or around the peripheral partition 7.

[0241] If voids are formed in the resist RS, there is a risk that the voids will expand and burst when the resist RS is dried under reduced pressure. In such a case, a part of the resist RS will be damaged, and the area that should be protected will be exposed from the resist RS. This causes excessive etching, making it impossible to achieve the desired patterning.

[0242] According to this embodiment, when forming the display element DE1, the loss of the resist RS is suppressed, and the sealing layer SE1 and the laminated film FL1 can be patterned into a desired shape. When forming the display element DE2, the sealing layer SE2 and the laminated film FL2 can be patterned into a desired shape, and when forming the display element DE3, the sealing layer SE3 and the laminated film FL3 can be patterned into a desired shape. Therefore, the deterioration of reliability can be suppressed.

[0243] FIG. 33 is a plan view showing an example of the peripheral partition 7 disposed in the recess DP of the organic insulating layer IL.

[0244] A plurality of peripheral partitions 7 are disposed in the recess DP. In a plan view, each of the peripheral partitions 7 is formed in a lattice pattern. In one example, the peripheral partitions 7 are formed in the same pattern as the lattice-shaped partitions 6 shown in FIG. 2. The peripheral partitions 7 are aligned in the first direction X and the second direction Y and spaced apart from each other. Although not described in detail here, the peripheral partitions 7 are disposed at a distance D1 from the edge portion DPE of the recess DP, as described above.

[0245] In the drawing, an arrow ADX indicates the coating direction of the resist RS along a first direction X, and an arrow ADY indicates the coating direction of the resist RS along a second direction Y.

[0246] When the resist RS is applied in the first direction X, the resist RS flows into the recesses DP. At this time, the resist RS is not blocked by the peripheral partitions 7, but passes between the peripheral partitions 7 arranged in the second direction Y and spreads while contacting the peripheral partitions 7. The resist RS also fills the regions surrounded by the peripheral partitions 7. This suppresses the formation of undesired voids in the resist RS.

[0247] Even when the resist RS is applied along the second direction Y, the resist RS is not blocked by the peripheral partition walls 7, but passes between the peripheral partition walls 7 arranged in the first direction X and spreads while contacting the peripheral partition walls 7. The resist RS is filled in the regions surrounded by the peripheral partition walls 7. This suppresses the formation of undesired voids in the resist RS.

[0248] Therefore, damage to the resist RS is suppressed, and deterioration of reliability can be suppressed.

[0249] In this manner, the technique of arranging the multiple peripheral partitions 7 so as to be spaced apart from each other in the recess DP can be applied to all configuration examples disclosed in this specification.

[0250] FIG. 34 is a plan view showing another configuration example of the pad PD or the terminal TE.

[0251] The configuration example shown in Fig. 34 differs from the configuration example shown in Fig. 11 in that the inorganic insulating layer 5 has a missing portion LP outside the opening OP. The missing portion LP is a through portion of the inorganic insulating layer 5, and is formed in a loop shape in a plan view. Such a missing portion LP can be formed in the same process as the opening AP1 shown in Fig. 2, for example.

[0252] A portion of the organic insulating layer IL adjacent to the recess DP overlaps the missing portion LP. In the illustrated example, the organic insulating layer IL overlapping the missing portion LP is exposed from the inorganic insulating layer 5. Note that in the missing portion LP, there may be cases where the overlapping organic insulating layer IL is not exposed and the metal layer MT is exposed from the inorganic insulating layer 5.

[0253] The recess DP corresponds to a through portion of the organic insulating layer IL, and exposes a part of the metal layer MT. The peripheral edge of the metal layer MT is covered with the organic insulating layer IL or the inorganic insulating layer 5.

[0254] Next, several configuration examples will be described with respect to the cross-sectional structure of the motherboard 100 taken along line CD in Fig. 34. Note that main differences between the following configuration examples will be described.

[0255] FIG. 35 is a cross-sectional view showing an example of a configuration of the motherboard 100. As shown in FIG.

[0256] The configuration example shown in FIG. 35 differs from the configuration example shown in FIG. 12 in that the inorganic insulating layer 5 has a missing portion LP that overlaps the slope SS of the organic insulating layer IL.

[0257] The organic insulating layer IL has a flat upper surface TS, a recess DP recessed from the upper surface TS, and a slope SS surrounding the recess DP. The recess DP is a through-hole in the organic insulating layer IL. The slope SS is a slope of the insulating layer 12.

[0258] The inorganic insulating layer 5 is disposed on the upper surface TS, and is disposed on the metal layer MT at the recess DP. The inorganic insulating layer 5 has an opening OP overlapping the recess DP. The opening OP is a through-portion of the inorganic insulating layer 5 formed to expose the metal layer MT. The notch LP exposes the slope SS. In the illustrated example, the notch LP further exposes a part of the upper surface TS, an edge portion TSE, and an edge portion DPE, and exposes the metal layer MT between the edge portion DPE and the inorganic insulating layer 5 at the recess DP. It is sufficient that the notch LP overlaps at least a part of the slope SS.

[0259] FIG. 36 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 36 differs from the configuration example shown in Fig. 13 in that the inorganic insulating layer 5 has a missing portion LP overlapping a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 114. The missing portion LP exposes the metal layer MT overlapping the slope SS.

[0260] FIG. 37 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. The configuration example shown in Fig. 37 differs from the configuration example shown in Fig. 14 in that the inorganic insulating layer 5 has a missing portion LP that overlaps the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the metal layer MT that overlaps the slope SS.

[0261] FIG. 38 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 38 differs from the configuration example shown in FIG 15 in that the inorganic insulating layer 5 has a missing portion LP that overlaps the slope SS1, slope SS2, and slope SS3 of the organic insulating layer IL. The slope SS1 and slope SS2 are slopes of the insulating layer 12. The slope SS3 is a slope of the insulating layer 114. The missing portion LP exposes the slope SS1, slope SS2, and upper surface TS2, as well as the metal layer MT that overlaps the slope SS3.

[0262] FIG. 39 is a cross-sectional view showing another example of the configuration of the mother substrate 100. As shown in FIG. 39 differs from the configuration example shown in Fig. 16 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS1 and slope SS2 of the organic insulating layer IL. The slope SS1 and slope SS2 are slopes of the insulating layer 12. The missing portion LP exposes the slope SS1, slope SS2, and upper surface TS2.

[0263] FIG. 40 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 40 differs from the configuration example shown in Fig. 17 in that the inorganic insulating layer 5 has a missing portion LP that overlaps the slope SS1 and slope SS3 of the organic insulating layer IL. The slope SS1 is a slope of the insulating layer 12. The slope SS3 is a slope of the insulating layer 114. The missing portion LP exposes the slope SS1 as well as the metal layer MT that overlaps the slope SS3.

[0264] FIG. 41 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 41 differs from the configuration example shown in Fig. 18 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS1 and slope SS2 of the organic insulating layer IL. The slope SS1 and slope SS2 are slopes of the insulating layer 12. The missing portion LP exposes the slope SS1, slope SS2, and upper surface TS2.

[0265] 35 to 41, the peripheral partitions 7 are arranged so as to overlap the upper surface TS or the upper surface TS1 of the organic insulating layer IL and also overlap the recesses DP, and each has an overhanging shape. In each configuration example, the distance D1 is 50 μm or more, and the distance D2 is 20 μm or more.

[0266] Fig. 42 is a plan view showing another configuration example of the region 100A shown in Fig. 19. Here, a region including the recessed portion DP formed in the peripheral region SA or the marginal portion MP in the region 100A is shown in an enlarged manner.

[0267] The recess DP may be a through-hole in the organic insulating layer IL, or may be a thin-walled portion of the organic insulating layer IL. The missing portion LP is a through portion of the inorganic insulating layer 5. A portion of the organic insulating layer IL adjacent to the recess DP overlaps the missing portion LP. The organic insulating layer IL overlapping the missing portion LP is exposed from the inorganic insulating layer 5.

[0268] Next, several configuration examples will be described with respect to the cross-sectional structure of the motherboard 100 taken along line EF in Fig. 42. Note that main differences between the following configuration examples will be described.

[0269] FIG. 43 is a cross-sectional view showing an example of a configuration of the motherboard 100. As shown in FIG.

[0270] The configuration example shown in FIG. 43 differs from the configuration example shown in FIG. 20 in that the inorganic insulating layer 5 has a missing portion LP that overlaps the slope SS of the organic insulating layer IL.

[0271] The organic insulating layer IL has a flat upper surface TS, a recess DP recessed from the upper surface TS, and a slope SS surrounding the recess DP. The recess DP is a through-hole in the organic insulating layer IL. The slope SS is a slope of the insulating layer 12.

[0272] The inorganic insulating layer 5 is disposed on the upper surface TS, and is also disposed on the insulating layer 113 at the recess DP. The notch LP exposes the slope SS. In the illustrated example, the notch LP further exposes a part of the upper surface TS, the edge portion TSE, and the edge portion DPE, and exposes the insulating layer 113 between the edge portion DPE and the inorganic insulating layer 5 at the recess DP. It is sufficient that the notch LP overlaps at least a part of the slope SS.

[0273] FIG. 44 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 44 differs from the configuration example shown in Fig. 21 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 114. The missing portion LP exposes the slope SS.

[0274] FIG. 45 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 45 differs from the configuration example shown in Fig. 22 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0275] FIG. 46 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. The configuration example shown in Fig. 46 differs from the configuration example shown in Fig. 23 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS1, slope SS2, and slope SS3 of the organic insulating layer IL. The slope SS1 and slope SS2 are slopes of the insulating layer 12. The slope SS3 is a slope of the insulating layer 114. The missing portion LP exposes the slope SS1, slope SS2, upper surface TS2, and slope SS3.

[0276] FIG. 47 is a cross-sectional view showing another example of the configuration of the mother substrate 100. As shown in FIG. 47 differs from the configuration example shown in Fig. 24 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS1 and slope SS2 of the organic insulating layer IL. The slope SS1 and slope SS2 are slopes of the insulating layer 12. The missing portion LP exposes the slope SS1, slope SS2, and upper surface TS2.

[0277] FIG. 48 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. The configuration example shown in Fig. 48 differs from the configuration example shown in Fig. 25 in that the inorganic insulating layer 5 has a missing portion LP that overlaps the slope SS1 and slope SS3 of the organic insulating layer IL. The slope SS1 is a slope of the insulating layer 12. The slope SS3 is a slope of the insulating layer 114. The missing portion LP exposes the slope SS1 and slope SS3.

[0278] FIG. 49 is a cross-sectional view showing another example of the configuration of the mother substrate 100. As shown in FIG. 49 differs from the configuration example shown in Fig. 26 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS1 and slope SS2 of the organic insulating layer IL. The slope SS1 and slope SS2 are slopes of the insulating layer 12. The missing portion LP exposes the slope SS1, slope SS2, and upper surface TS2.

[0279] FIG. 50 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 50 differs from the configuration example shown in Fig. 27 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The inorganic insulating layer 5 is disposed on the upper surface TS1, and is also disposed on the upper surface TS2 at the recess DP. The notch LP exposes the slope SS. In the illustrated example, the notch LP further exposes a part of the upper surface TS1, the edge portion TSE, and the edge portion DPE, and exposes the upper surface TS2 at the recess DP between the edge portion DPE and the inorganic insulating layer 5. It is sufficient that the notch LP overlaps at least a part of the slope SS.

[0280] FIG. 51 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. 51 differs from the configuration example shown in Fig. 28 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slopes SS1 and SS2 of the organic insulating layer IL. The slopes SS1 and SS2 are slopes of the insulating layer 12. The inorganic insulating layer 5 is disposed on the upper surface TS1, and is disposed in the recess DP on the insulating layer 114. The notch portion LP exposes the slope SS1, the upper surface TS2, and the slope SS2.

[0281] FIG. 52 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. The configuration example shown in Fig. 52 differs from the configuration example shown in Fig. 29 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0282] FIG. 53 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. The configuration example shown in Fig. 53 differs from the configuration example shown in Fig. 30 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0283] FIG. 54 is a cross-sectional view showing another example of the configuration of the motherboard 100. As shown in FIG. The configuration example shown in Fig. 54 differs from the configuration example shown in Fig. 31 in that the inorganic insulating layer 5 has a missing portion LP that overlaps with a slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0284] In each of the configuration examples shown in FIGS. 43 to 54, the inorganic insulating layer 5 may have an opening OP overlapping the recess DP, similar to the configuration example shown in FIG.

[0285] 43 to 54, the peripheral partitions 7 are arranged so as to overlap the upper surface TS or the upper surface TS1 of the organic insulating layer IL and also to overlap the recesses DP, and each has an overhanging shape. In each configuration example, the distance D1 is preferably 50 μm or more, and the distance D2 is preferably 20 μm or more.

[0286] As described above, by having the missing portion LP of the inorganic insulating layer 5 overlapping the slope SS, it is possible to suppress local stress concentration near the edge portion DPE of the recess DP, thereby suppressing lifting of the inorganic insulating layer 5 from the organic insulating layer IL.

[0287] Furthermore, when a laminated film is formed in the vicinity of the missing portion LP, the laminated film can be prevented from lifting up. This point will be described below.

[0288] FIG. 55 is a cross-sectional view for explaining a state in which the laminated film FL1 is formed in a region including the missing portion LP shown in FIG.

[0289] For example, in the process of forming the display element DE1, the laminated film FL1 is formed not only in the display region but also in the marginal portion MP and the peripheral region SA. The laminated film FL1 here includes, for example, an organic layer OR1, an upper electrode UE1, and a cap layer CP1 for forming the display element DE1. The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition wall 7, and is also formed on the slope SS of the organic insulating layer IL.

[0290] The laminated film FL1 is divided by the overhanging peripheral partition 7. That is, when the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition, the material emitted from the deposition source is blocked by the upper part 72 of the peripheral partition 7. Therefore, a part of each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is laminated on the upper part 72. Each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the upper part 72 is separated from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located around the peripheral partition 7. As a result, the laminated film FL1 is partially divided.

[0291] Compared with the case where the laminated film FL1 is not divided by the peripheral partition 7, the area of ​​the continuous laminated film FL1 is reduced, and stress that may occur in the laminated film FL1 is dispersed. In addition, the inorganic insulating layer 5 and the laminated film FL1 are held down by the peripheral partition 7. Therefore, it is possible to suppress the inorganic insulating layer 5 from lifting up from the organic insulating layer IL and the laminated film FL1 from the inorganic insulating layer 5. In addition, since stress concentration in the vicinity of the edge portion DPE of the recess DP is suppressed, it is possible to suppress the laminated film FL1 from lifting up from the slope SS. Furthermore, when the sealing layer SE1 is formed on the laminated film FL1, the sealing layer SE1, together with the peripheral partition 7, holds down the laminated film FL1. Therefore, it is possible to suppress the detachment of the laminated film FL1 and the sealing layer SE1 from the inorganic insulating layer 5.

[0292] Furthermore, when the organic insulating layer IL has a stepped cross section in which the thickness decreases toward the recess DP, the formation of a steep step is suppressed. The thinner the organic insulating layer IL is, the less it stretches. Therefore, when the laminated film FL1 is formed on the organic insulating layer IL, the distortion of the laminated film FL1 is small, and localized stress concentration in the laminated film FL1 can be suppressed. This makes it possible to suppress the detachment of the laminated film FL1 from the inorganic insulating layer 5 or the slope SS.

[0293] Here, a description will be given of problems that may occur when the laminated film FL1 floats up from the inorganic insulating layer 5 and breaks. The inorganic insulating layer 5 that has detached from the organic insulating layer IL and the laminated film FL1 that has detached from the inorganic insulating layer 5 become foreign matter and float within the manufacturing equipment, and may become a source of contamination. Furthermore, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0294] In contrast, according to the present embodiment, the inorganic insulating layer 5 and the laminated film FL1 can be prevented from being detached. This prevents contamination of the manufacturing equipment and the generation of undesired foreign matter. Therefore, the deterioration of reliability is prevented.

[0295] The same effect can be obtained even when the laminated film FL1 is replaced with a laminated film FL2 including an organic layer OR2 for forming the display element DE2, an upper electrode UE2, and a cap layer CP2. Moreover, even if the laminated film FL1 is replaced with a laminated film FL3 including an organic layer OR3 for forming a display element DE3, an upper electrode UE3, and a cap layer CP3, the same effect can be obtained.

[0296] Here, the effect of suppressing separation of the inorganic insulating layer 5 and the laminated film FL1 has been described for the configuration example shown in FIG. 35, but the same effect can be obtained for each of the other configuration examples.

[0297] In the above embodiment, for example, in the peripheral partition 7, the lower part 71 corresponds to the first lower part, and the upper part 72 corresponds to the first upper part. In the partition 6, the lower part 61 corresponds to the second lower part, and the upper part 62 corresponds to the second upper part. In the organic insulating layer IL, the insulating layer 114 corresponds to the first layer, and the insulating layer 12 corresponds to the second layer.

[0298] As described above, according to the present embodiment, it is possible to provide a display device and a motherboard capable of suppressing a decrease in reliability.

[0299] All display devices and motherboards that can be implemented by a person skilled in the art through appropriate design modifications based on the display device and motherboard described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0300] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0301] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0302] DSP…display device 10…board 5...Inorganic insulating layer AP1, AP2, AP3...Openings LP...Notch 6...Bulkhead 61...Lower 62...Upper 7...Peripheral bulkhead 71...Lower part 72...Upper part SP1, SP2, SP3...Subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3...lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer DA: Display area SA: Surrounding area 100... Motherboard for display device PP... Panel part MP... Margin part CL... Cut line IL...organic insulating layer 12...insulating layer 114...insulating layer DP…Concave TS, TS1, TS2…Top surface SS, SS1, SS2, SS3…Slope

Claims

1. A substrate; an organic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; each of the plurality of peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the organic insulating layer has a flat upper surface and a recess recessed relative to the upper surface in the peripheral region, the plurality of peripheral partition walls include a first partition wall overlapping the recess, a distance from the first upper portion of the first partition to an edge of the recess is 50 μm or more; Display device.

2. the plurality of peripheral partition walls include a second partition wall overlapping the upper surface, a distance from the first upper portion of the second partition wall to an edge of the upper surface is 20 μm or more; The display device according to claim 1 .

3. A substrate; an organic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region; each of the plurality of peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the organic insulating layer has, in the peripheral region, a flat upper surface, a recessed portion recessed relative to the upper surface, and a slope surrounding the recessed portion; the plurality of peripheral partition walls include a first partition wall overlapping the recess and a second partition wall overlapping the upper surface, the inorganic insulating layer has a missing portion overlapping the inclined surface, Display device.

4. a distance from the first upper portion of the first partition to an edge of the recess is 50 μm or more; a distance from the first upper portion of the second partition wall to an edge of the upper surface is 20 μm or more; The display device according to claim 3 .

5. The recess is a through-hole in the organic insulating layer. The display device according to claim 1 .

6. Further, a metal layer is provided in the recess, The inorganic insulating layer has an opening exposing the metal layer. The display device according to claim 5 .

7. The recess is a thin portion of the organic insulating layer. The display device according to claim 1 .

8. The first partition is formed in a lattice shape in a plan view, The first partition walls are spaced apart from each other. The display device according to claim 1 .

9. a partition wall including a second lower portion disposed on the inorganic insulating layer in the display region and made of a conductive material, and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion, the lower electrode, the organic layer, and the upper electrode are surrounded by the partition wall, the upper electrode is in contact with the second lower portion of the partition wall; The display device according to claim 1 .

10. The organic insulating layer has a stepped cross section whose thickness decreases toward the recess. The display device according to claim 1 .

11. The organic insulating layer has a first layer and a second layer covering the first layer. The display device according to claim 1 .

12. the organic insulating layer has a first layer and a second layer disposed on the first layer and exposing the first layer adjacent to the recess; The display device according to claim 1 .

13. The organic insulating layer is a single layer. The display device according to claim 1 .

14. a panel section having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region and the marginal portion; each of the plurality of peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the inorganic insulating layer has a flat upper surface and a recessed portion recessed relative to the upper surface in the peripheral region or the marginal portion, the plurality of peripheral partition walls include a first partition wall overlapping the recess, a distance from the first upper portion of the first partition to an edge of the recess is 50 μm or more; Motherboard for display devices.

15. the plurality of peripheral partition walls include a second partition wall overlapping the upper surface, a distance from the first upper portion of the second partition wall to an edge of the upper surface is 20 μm or more; The mother substrate for a display device according to claim 14.

16. a panel section having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed over the organic layer; a plurality of peripheral partitions disposed in the peripheral region and the marginal portion; each of the plurality of peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion; the organic insulating layer has, in the peripheral region or the marginal portion, a flat upper surface, a recessed portion recessed relative to the upper surface, and a slope surrounding the recessed portion; the plurality of peripheral partition walls include a first partition wall overlapping the recess and a second partition wall overlapping the upper surface, the inorganic insulating layer has a missing portion overlapping the inclined surface, Motherboard for display devices.

17. a distance from the first upper portion of the first partition to an edge of the recess is 50 μm or more; a distance from the first upper portion of the second partition wall to an edge of the upper surface is 20 μm or more; The mother substrate for a display device according to claim 16.

18. The recess is a through-hole in the organic insulating layer.

17. The mother substrate for a display device according to claim 14 or 16.

19. Further, a metal layer is provided in the recess, The inorganic insulating layer has an opening exposing the metal layer.

20. The mother substrate for a display device according to claim 18.

20. The recess is a thin portion of the organic insulating layer.

17. The mother substrate for a display device according to claim 14 or 16.

21. The first partition is formed in a lattice shape in a plan view, The first partition walls are spaced apart from each other.

17. The mother substrate for a display device according to claim 14 or 16.

22. a partition wall including a second lower portion disposed on the inorganic insulating layer in the display region and made of a conductive material, and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion, the lower electrode, the organic layer, and the upper electrode are surrounded by the partition wall, the upper electrode is in contact with the second lower portion of the partition wall; 17. The mother substrate for a display device according to claim 14 or 16.

23. The organic insulating layer has a stepped cross section whose thickness decreases toward the recess.

17. The mother substrate for a display device according to claim 14 or 16.

24. The organic insulating layer has a first layer and a second layer covering the first layer.

17. The mother substrate for a display device according to claim 14 or 16.

25. the organic insulating layer has a first layer and a second layer disposed on the first layer and exposing the first layer adjacent to the recess; 17. The mother substrate for a display device according to claim 14 or 16.

26. The organic insulating layer is a single layer.

17. The mother substrate for a display device according to claim 14 or 16.

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