Pattern generating device and method, and error rate measuring device and method

Abstract

To visually recognize and set the allocation of the leading bit of a multi-level modulated signal pattern generated by bit interleaving a PRBS in a multi-level modulated signal having four or more values of a power of two (2n: n is an integer equal to or greater than two) of a desired pattern.SOLUTION: A pattern generating device 2 generates a multi-level modulation signal with four or more values of a power of two using patterns corresponding to various transmission standards, and includes: display means 15 for displaying a setting screen 15a for selecting and setting a pattern of the multi-level modulation signal from a pattern list; control means 14 controls displaying of a circuit configuration diagram 25 on the transmitting side or receiving side according to the standard of the pattern of the multi-level modulation signal selected and set on the setting screen 15a; and switching means 16 that selectively switches a position, to which the first bit is allocated, with the LSB being the lowest position, 0th position, for a division circuit 25b that divides the PRBS pattern in a manner that enables identification in the circuit configuration diagram 25.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a pattern generating device and method, and an error rate measuring device and method, for generating a multi-level modulated signal having a value equal to or greater than a power of two of a desired pattern defined by standards organizations or standard names in various transmission standards. [Background technology]

[0002] Normally, when generating a PAM4 (Pulse Amplitude Modulation 4) symbol pattern from a PRBS (Pseudo Random Bit Sequence) pattern, the PRBS pattern is generated by bit interleaving the MSB (Most Significant Bit) and LSB (Least Significant Bit). Hereafter, the PAM4 symbol pattern generated in this way is referred to as PRBSxQ, where x is a number representing the number of PRBS stages. For example, a PAM4 symbol pattern generated from a PRBS13 pattern is referred to as PRBS13Q.

[0003] Incidentally, when bit interleaving a PRBS pattern, the generated PAM4 symbol pattern will differ depending on whether the first bit is assigned to the MSB or the LSB. Hereafter, a pattern that assigns the first bit to the MSB will be denoted as PRBSxQ, and a pattern that assigns the first bit to the LSB will be denoted as / PRBSxQ.

[0004] The PRBSxQ and / PRBSxQ patterns thus generated have the following characteristics (1) to (3).

[0005] (1) The MSB bit string also has the original PRBS pattern. (2) The LSB bit string also has the original PRBS pattern. (3) There is a phase difference between the MSB bit string and the LSB bit string, and this phase difference is 2^(number of PRBS stages-1). If the first bit is assigned to the MSB, the phase on the LSB side will be advanced by 2^(number of PRBS stages-1) bits. Conversely, if the first bit is assigned to the LSB, the phase on the MSB side will be advanced by 2^(number of PRBS stages-1) bits.

[0006] Here, the phase difference when PRBS7Q is generated will be described with reference to Figures 7(a) and (b). In the case of PRBS7Q, the phase difference is 2^(7-1) = 64 bits. Therefore, when the first bit of PRBS7Q is assigned to the MSB, the phase on the LSB side will be advanced by 64 bits, as shown in Figure 7(a). On the other hand, when the first bit of PRBS7Q is assigned to the LSB, the phase on the MSB side will be advanced by 64 bits, as shown in Figure 7(b).

[0007] Due to these characteristics, in the setting for error measurement of PRBSxQ PAM4 symbols, error measurement of / PRBSxQ PAM4 symbols cannot be performed. This is because, when measuring symbol errors as PAM4 symbols, it is necessary to confirm that the set of MSB and LSB bits is the same as the phase at the time of transmission. As shown in FIG. 8, the MSB bit string of PRBS7Q indicated by the downward slanting line and the LSB bit string of / PRBS7Q indicated by the upward slanting line are the same bit string, and even if a PAM4 symbol string is generated from the same PRBS7, PRBS7Q and / PRBS7Q as PAM4 symbols have different patterns. Therefore, if the combination of MSB and LSB is misaligned, the PAM4 symbol will have an error even if there is no error in the PRBS pattern of MSB and LSB.

[0008] Incidentally, for example, the conventional error rate measurement device disclosed in the following Patent Document 1 handles error measurement of PAM4 symbols, but the PAM4 symbol error measurement using PRBSxQ up to now has a specification for 400G Ethernet (registered trademark) that assigns the first bit to the MSB. However, the newly formulated PCIe Gen6 adopts the PAM4 symbol, and the specification assigns the first bit to the LSB. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2022-158216 A Summary of the Invention [Problem to be solved by the invention]

[0010] However, conventional PRBSxQ PAM4 symbol error measurements for 400G Ethernet (registered trademark), including the error rate measurement device disclosed in the above-mentioned Patent Document 1, cannot measure errors in PCIe Gen6 / PRBSxQ PAM4 symbols, and in order to perform measurements, it is necessary to clarify whether the first bit of the PRBS is assigned to the MSB or LSB. In other words, as a test signal of a known pattern to be input to the device under test (DUT), a desired pattern including the PAM4 PRBS specified by the standards organizations and standard names in various transmission standards, which is a power of two value of 4 or more (2 n When measuring an error rate by inputting a multi-level modulation signal pattern generated by bit-interleaving a PRBS in a multi-level modulation signal (n = an integer equal to or greater than 2), it was necessary to clarify the allocation of the first bit of the PRBS to the multi-level modulation signal (the 0th digit, which is the lowest digit, to which the LSB is assigned).

[0011] In view of the above problems, the present invention is directed to a method for determining whether a desired pattern has four or more power-of-two values ​​(2 nThe present invention aims to provide a pattern generating device and method, and an error rate measuring device and method, which allow visual recognition and setting of the allocation of the first bit when generating a multi-level modulated signal by bit interleaving a PRBS in a multi-level modulated signal (n=an integer equal to or greater than 2). [Means for solving the problem]

[0012] In order to achieve the above object, the pattern generator according to claim 1 of the present invention is a pattern generator 2 that generates a multi-value modulation signal having four or more power-of-two values ​​according to a pattern corresponding to various transmission standards, a display means 15 for displaying a setting screen 15a for selecting and setting a pattern of the multi-level modulation signal from a pattern list; A control means 14 for displaying and controlling a circuit configuration diagram 25 of a transmitting side or a receiving side according to a standard of a pattern of the multi-level modulation signal which is generated by bit interleaving the PRBS selected and set on the setting screen; The circuit configuration diagram is characterized by including a switching means 16 for selectively switching the position to which the first bit is assigned, with the LSB being the lowest position, 0th position, in a manner that makes it possible to distinguish between the positions of the first bit and the LSB, with the LSB being the lowest position.

[0013] The pattern generating device according to claim 2 is the pattern generating device according to claim 1, The switching means 16 is characterized in that, when the standard is Ethernet (registered trademark), it displays the MSB and disables switching.

[0014] The pattern generating device according to claim 3 is the pattern generating device according to claim 1, The switching means (16) is characterized in that, when the standard is at least PCI Express 6.0, it displays the LSB and disables switching.

[0015] The pattern generator according to claim 4 is any one of the pattern generators according to claims 1 to 3, The switching means 16 is provided outside or inside the dividing circuit 25b.

[0016] The pattern generation method described in claim 5 is a pattern generation method for generating a multi-value modulated signal having four or more power-of-two values ​​according to a pattern corresponding to various transmission standards, displaying a setting screen 15a for selecting and setting a pattern of the multi-level modulation signal from a pattern list; A step of displaying and controlling a circuit configuration diagram 25 of a transmitting side or a receiving side according to a standard of a pattern of the multi-level modulation signal generated by bit interleaving the PRBS selected and set on the setting screen; a step of selectively switching a switching means 16 so that it is possible to identify to which place the first bit is assigned, with the LSB being the lowest place, 0th place, for a division circuit (25b) that divides the PRBS pattern in the circuit configuration diagram; The present invention is characterized by comprising:

[0017] The pattern generating method according to claim 6 is the pattern generating method according to claim 5, The method is characterized in that it includes a step of displaying the MSB and disabling the switching of the switching means 16 when the standard is Ethernet (registered trademark).

[0018] The pattern generating method according to claim 7 is the pattern generating method according to claim 5, When the standard is at least PCI Express 6.0, the method includes a step of displaying the LSB and disabling the switching of the switching means 16.

[0019] The pattern generating method according to claim 8 is the pattern generating method according to any one of claims 5 to 7, The method includes a step of providing the switching means 16 outside or inside the division circuit 25b.

[0020] The error rate measuring device according to claim 9 comprises the pattern generating device 2 according to claim 1, an error detection device 3 that receives a signal from the device under test W associated with an input of a multi-level modulated signal generated by the pattern generation device to the device under test W and measures a symbol error rate; The present invention is characterized by comprising:

[0021] The error rate measuring method according to claim 10 includes the steps of: inputting a multi-level modulated signal generated by the pattern generating method according to claim 5 to a device under test W; receiving a signal from the device under test associated with inputting the multi-level modulated signal to the device under test and measuring a symbol error rate; The present invention is characterized by comprising: Effect of the Invention

[0022] According to the present invention, it is possible to visually see to which position, starting with the LSB being the lowest position, 0th position, the first bit of a multi-level modulated signal generated by bit-interleaving a PRBS is assigned, and this makes it easy to set the assignment of the first bit of the multi-level modulated signal. [Brief description of the drawings]

[0023] [Figure 1] 1 is a block diagram showing a schematic configuration of an error rate measuring device including a pattern generating device according to the present invention; [Diagram 2] FIG. 13 is a diagram showing an example of a setting screen displaying a circuit configuration diagram on the transmission side including a switching means which is a main part of the present invention. [Diagram 3] FIG. 13 is a diagram showing an example of a setting screen displaying a circuit configuration diagram on the receiving side including a switching means which is a main part of the present invention. [Figure 4] 13(a) to 13(d) are diagrams showing modified examples of the switching means. [Diagram 5] 13(a) to (d) are diagrams showing other modified examples of the switching means. [Figure 6] 13(a) and 13(b) are diagrams showing another modified example of the switching means. [Figure 7]FIG. 1A shows an example of a bit phase difference when the first bit of PRBS7Q is assigned to the MSB, and FIG. 1B shows an example of a bit phase difference when the first bit of PRBS7Q is assigned to the LSB. [Figure 8] FIG. 11 is an explanatory diagram showing the difference between the patterns PRBS7Q and / PRBS7Q. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] In the present invention, a test signal having a known pattern to be input to a device under test (DUT) is a power of two (2 n The present invention relates to a pattern generating device and a pattern generating method for generating a multi-level modulated signal pattern generated by bit interleaving a PRBS in a multi-level modulated signal (n=an integer equal to or greater than 2), and an error rate measuring device and an error rate measuring method for receiving a signal from a device under test in response to inputting a test signal to the device under test and measuring a symbol error rate.

[0026] In the following, in this embodiment, four or more powers of two (2 n Here, an example will be described in which a four-level PAM4 signal is generated as a multi-level modulated signal (n=an integer equal to or greater than 2) and a PAM4 symbol error rate is measured.

[0027] As shown in FIG. 1, an error rate measuring device 1 of this embodiment is roughly configured to include a pattern generator 2 on the transmitting side and an error detection device 3 on the receiving side. The pattern generator 2 generates a PAM4 signal of a desired pattern defined by standards organizations or standard names in various transmission standards, transmits the generated PAM4 signal as a test signal to a device under test W, and receives a signal from the device under test W accompanying the transmission of this test signal to measure the PAM4 symbol error rate.

[0028] As shown in FIG. 1, the pattern generating device 2 comprises a setting means 11, a signal generating means 12, a storage means 13, a control means 14, a display means 15, and a switching means 16.

[0029] The setting means 11 functions as a user interface for selecting and setting the standard name, pattern, and pattern length on the display screen of the display means 15 in order to select and set a PAM4 signal pattern corresponding to the standard.

[0030] 2 and 3, for example, two items, "Test Pattern" and "Length," are displayed on the setting screen 15a of the display means 15. The input box 21 for "Test Pattern" is configured as a pull-down menu and displays a standard name selected from a list of standard names (e.g., IEEE, infiniband, PCIe6, etc.) that the error rate measurement device 1 is compatible with. The examples in FIGS. 2 and 3 show a state in which "All List," which includes all standard names that the error rate measurement device 1 is compatible with, is selected from the list of standard names and displayed in the input box 21.

[0031] Then, when a standard name is selected from the pull-down menu in input box 21 for "Test Pattern," and a pattern selectable for that standard name is selected from the pattern list in the pull-down menu, the selected pattern is displayed in input box 22. For example, when "IEEE" is selected as the standard name, a pattern selected from PRBS9Q, PRBS13Q, QPRBS13, PRBS31Q, SSPRQ, JP03A, ​​JP03B, Transmitter linearity, and Square Wave is displayed in input box 22 as a pattern list corresponding to "IEEE." The examples in FIGS. 2 and 3 show a state in which "PRBS" is selected and displayed in input box 22.

[0032] The "Summary" button 23 on the right side of the input box 22 is pressed to display a pop-up summary of the pattern selected from the pull-down menu of the input box 22.

[0033] Furthermore, in the "Length" input box 24, the pattern length of the pattern of the standard name selected in the "Test Pattern" input boxes 21 and 22 is selected from a list of pattern lengths in a pull-down menu and displayed. In the examples of Figs. 2 and 3, "2 15-1 " is selected and displayed.

[0034] In addition, as shown in Figures 2 and 3, the setting means 11 also functions as a user interface for setting a specific circuit in the circuit configuration diagram 25 (25A, 25B) based on the generation procedure of the selected and set pattern on the display screen (setting screen 15a) of the display means 15.

[0035] For example, as shown in FIG. 2, when a PAM4 signal pattern corresponding to a standard is selected and set on the setting screen 15a of the display means 15, a circuit configuration diagram 25 (25A) is displayed in which the circuitry required to generate this selected and set pattern is organized into circuit blocks according to the generation procedure of the standard.

[0036] In Fig. 2, a circuit configuration diagram 25A is constructed by an oscillator 25a, a division circuit 25b, an MSB and LSB PRBS logic inversion circuit 25c, a gray coder 25d, a precoder 25e, an MSB and LSB logic inversion circuit 25f, a bit shift circuit 25g, and an addition circuit 25h. Note that specific circuits in the circuit configuration diagram 25A (for example, the "ON / OFF" of the MSB and LSB PRBS logic inversion circuit 25c in Fig. 2, the "POS (through) / NEG (inversion)" of the MSB and LSB logic inversion circuit 25f, the "ON / OFF" of the gray coder 25d, the "ON / OFF" of the precoder 25e, the shift amount of the bit shift circuit 25g, etc.) can be appropriately set as necessary.

[0037] In Fig. 3, a circuit configuration diagram 25B is constructed by an oscillator 25a, a division circuit 25b, an MSB and LSB PRBS logic inversion circuit 25c, a gray coder 25d, a precoder 25e, a PAM4 decoder 25i, an MSB and LSB logic inversion circuit 25j, and an error detector 25k. Note that specific circuits in the circuit configuration diagram 25B (e.g., "ON / OFF" of the MSB and LSB inversion circuit 25c in Fig. 3, "ON / OFF" of the gray coder 25d, "ON / OFF" of the precoder 25e, "ON / OFF" of the MSB and LSB logic inversion circuit 25j, etc.) can be set appropriately as necessary.

[0038] The signal generating means 12 generates a PAM4 signal of the pattern selected and set by the setting means 11, in accordance with a circuit configuration diagram 25 of the selected and set pattern. For example, as shown in FIG. 2, when “All List” is selected and set in the input box 21 of the Test Pattern, “PRBS” is selected and set in the input box 22 of the pattern, and “2 15-1 When " is selected and set, the signal generating means 12 generates the selected and set pattern: PRBS, pattern length: 2 15-1 The PAM4 signal is generated using the circuit configuration shown in FIG.

[0039] The storage means 13 stores, for multiple types of PAM4 signal patterns that can be generated by the pattern generating device 2, information linking each pattern to the standards organization or standard name, circuit information required to construct a circuit configuration diagram 25 of the selected and set pattern, and the like.

[0040] The control means 14 generally controls each section when generating a PAM4 signal of a desired pattern defined by a standards organization or standard name in various transmission standards and performing various measurements including a PAM4 symbol error rate, and includes a display control means 14a.

[0041] The display control means 14a displays a setting screen 15a for selecting and setting the pattern of the PAM4 signal generated by the signal generating means 12 on the display screen.

[0042] As shown in Figures 2 and 3, the display control means 14a selectively switches and displays, on the display screen (setting screen 15a), a transmitting side circuit configuration diagram 25A in which the procedure for generating a pattern selected and set on the setting screen 15a is represented as circuit blocks in accordance with a standard, or a receiving side circuit configuration diagram 25B in which the procedure for comparing an expected value of the pattern selected and set on the setting screen 15a with data from outside (including the object to be measured W) is represented as circuit blocks in accordance with a standard.

[0043] When the "Summary" button 23 on the setting screen 15a is pressed, the display control means 14a displays a pop-up summary of the pattern selected and set on the setting screen 15a in a desired language on the display screen (setting screen 15a).

[0044] The display control means 14a controls the display of various setting screens relating to measurement, measurement screens, etc. on the display screen of the display means 15 in addition to the above-mentioned display control.

[0045] The display means 15 is constituted by a display device such as a liquid crystal display provided in the main body of the device, and displays, for example, a setting screen 15a shown in FIG. 2 or FIG. 3 under the control of the display control means 14a.

[0046] When the "Summary" button 23 on the setting screen 15a is pressed, the display means 15, under the control of the display control means 14a, pops up a summary explanation of the pattern selected and set on the setting screen 15a on the display screen (setting screen 15a) in the desired language suited to the user and the usage environment.

[0047] Under the control of the display control means 14a, the display means 15 displays the above-mentioned displays as well as various setting screens, compliance test (a test to see whether the device under test W complies with a standard) and bit error rate measurement screens.

[0048] The switching means 16, which is a main part of this embodiment, is composed of a toggle button (toggle switch) that is incorporated and displayed in the circuit configuration diagrams 25 (25A, 25B) of Fig. 2 and Fig. 3. The switching means 16, under the control of the control means 14, selects and switches the toggle button so that it is possible to distinguish whether the first bit of the PRBS is assigned to the MSB or the LSB for the division circuit 25b that divides the PRBS by bit interleaving in the circuit configuration diagrams 25A, 25B of Fig. 2 and Fig. 3.

[0049] To explain further, as shown in Figures 2 and 3, the switching means 16 is configured to display an MSB toggle button 16a and an LSB toggle button 16b side-by-side inside the divided circuit 25b of the circuit configuration diagrams 25A and 25B, and to identifiably display (highlight in a specific color (e.g., green)) one of the toggle buttons (16a or 16b) that has been pressed.

[0050] In the examples of FIG. 2 and FIG. 3, the LSB toggle button 16b is identifiable (displayed with a diagonal line slanting upwards to the right) to indicate that the first bit of the PRBS is assigned to the LSB.

[0051] The arrangement of the MSB toggle button 16a and the LSB toggle button 16b is not limited to the horizontal arrangement as in Figures 2 and 3, but may be vertical arrangement, and can be arranged according to the layout of the circuit configuration diagram 25 and the display space of the setting screen 15a.

[0052] The switching means 16 in Fig. 4(a) has a configuration in which one toggle button 16c is arranged inside a dividing circuit 25b. The toggle button 16c of the switching means 16 in Fig. 4(a) initially displays the MSB, and alternates between the MSB and LSB each time it is pressed.

[0053] The switching means 16 in FIG. 4(b) is configured in the same way as in FIG. 4(a), with one toggle button 16c arranged inside the division circuit 25b, but it displays the initial LSB, and each time the toggle button 16c is pressed, the display of the LSB and MSB alternates.

[0054] The switching means 16 in FIG. 4(c) has a configuration in which one toggle button 16c is arranged inside a dividing circuit 25b, similar to that in FIG. 4(a), but disables pressing of the toggle button 16c when the MSB is displayed.

[0055] The switching means 16 in FIG. 4(d) has a configuration in which one toggle button 16c is arranged inside a dividing circuit 25b, similar to that in FIG. 4(a), but disables pressing of the toggle button 16c when the LSB is displayed.

[0056] The switching means 16 in Fig. 5(a) has a configuration in which one toggle button 16c is arranged outside the dividing circuit 25b. The toggle button 16c of the switching means in Fig. 5(a) initially displays the MSB, and alternates between the MSB and LSB each time it is pressed.

[0057] The switching means 16 in Figure 5(b) is configured in the same way as in Figure 5(a), with one toggle button 16c arranged outside the division circuit 25b, but the LSB is displayed initially, and each time the toggle button 16c is pressed, the display of the LSB and MSB is alternated.

[0058] The switching means 16 in FIG. 5(c) has a configuration in which one toggle button 16c is arranged outside the dividing circuit 25b, similar to that in FIG. 5(a), but disables pressing of the toggle button 16c when the MSB is displayed.

[0059] The switching means 16 in FIG. 5(d) has a configuration in which one toggle button 16c is arranged outside the dividing circuit 25b, similar to that in FIG. 5(a), but disables pressing of the toggle button 16c when the LSB is displayed.

[0060] The switching means 16 in Figures 6(a) and (b) is configured to display an MSB toggle button 16a and an LSB toggle button 16b side by side outside the divided circuit 25b of the circuit configuration diagrams 25A and 25B, and to distinguishably display (highlight in a specific color, for example green) one of the toggle buttons (16a or 16b) that has been pressed.

[0061] FIG. 6(a) shows a state in which the MSB toggle button 16a is pressed and displayed distinctively, and FIG. 6(b) shows a state in which the LSB toggle button 16b is pressed and displayed distinctively.

[0062] In the configuration of the switching means 16 in Figures 4(c) and (d) and Figures 5(c) and (d), disabling pressing of the toggle button 16c means that the display control means 14a displays the toggle button 16c in a grayed-out state so that it cannot be pressed, or that even if the toggle button 16c is pressed, the control means 14 does not accept the signal.

[0063] When a PAM4 signal is input to the device under test W as a test signal of a known pattern from the above-mentioned pattern generating device 2, the error detecting device 3 receives a signal from the device under test W accompanying the input of this PAM4 signal and measures the PAM4 symbol error rate.

[0064] When using the error rate measurement apparatus 1 configured as described above to generate a PAM4 signal of a desired pattern and measure the PAM4 symbol error rate, first, a pattern corresponding to the desired standard is selected and set on the setting screen 15a of the display means 15.

[0065] Next, when a pattern corresponding to the desired standard is selected and set on the setting screen 15a, a transmitting side circuit configuration diagram 25A in which the procedure for generating the pattern selected and set on this setting screen 15a is represented by circuit blocks in accordance with the standard, or a receiving side circuit configuration diagram 25B in which the procedure for comparing the expected value of the pattern selected and set on the setting screen 15a with data from outside (including the object to be measured W) is represented by circuit blocks in accordance with the standard, is displayed.

[0066] Then, in the displayed circuit configuration diagram 25A or 25B, the user selects whether the first bit of the PRBS is to be assigned to the MSB or LSB by pressing one of the toggle buttons of the switching means 16 (the MSB toggle button 16a or the LSB toggle button 16b). At that time, the selected toggle button (the MSB toggle button 16a or the LSB toggle button 16b) is identifiably displayed. After that, a PAM4 signal of the selected pattern is generated by the signal generating means 12 and transmitted to the device under test W.

[0067] The error detection device 3 receives a signal from the device under test W accompanying the transmission of the PAM4 signal from the signal generating means 12 of the pattern generator 2, and measures the PAM4 symbol error rate.

[0068] In the above embodiment, a PAM4 signal is generated as a multi-level modulated signal having a pattern corresponding to a desired transmission standard, and the switching means 16 is used to select and switch between the MSB and the LSB so that the first bit of the PRBS is assigned to the MSB or the LSB. However, the present invention is not limited to this. The multi-level modulated signal may be a power of 2 value (2 n :n=an integer of 2 or greater).

[0069] For example, when generating a PAM8 signal (a multi-level modulation signal with a value of 2 to the power of 3), the switching means 16 sequentially assigns the digits 0 (0th digit), 1 (1st digit), and 2 (2nd digit) from the lowest digit, and selectively switches between 0, 1, and 2 so that it is possible to distinguish whether the first bit of the PRBS is assigned to that digit.

[0070] Specifically, instead of the "MSB" and "LSB" toggle buttons (toggle switches) 16a1, 16b of the switching means 16 shown in Figures 2, 3 and 6, three toggle buttons (toggle switches) are provided, indicating the digits with numbers, "0", "1", and "2", and the toggle button (toggle switch) for the digit to which the first bit of the PRBS is assigned is identifiably displayed (highlighted in a specific color (e.g., green)). Furthermore, when the switching means 16 of Figures 4 and 5 is employed, the digit to which the first bit of the PRBS is assigned (any number from 0, 1, or 2) is identifiably displayed on toggle button (toggle switch) 16c.

[0071] In this manner, in this embodiment, the desired pattern is a power of 2 (2 n In a multi-level modulated signal (n=an integer equal to or greater than 2), when a multi-level modulated signal pattern generated by bit-interleaving a PRBS is input to a device under test as a test signal, a configuration / method is adopted in which a switching means is used to select and switch to which bit of the PRBS the first bit is assigned, with the LSB being the lowest bit being 0th. This makes it possible to visually see which bit the first bit of the multi-level modulated signal generated by bit-interleaving a PRBS is assigned, and makes it easy to set the assignment of the first bit of the multi-level modulated signal generated by bit-interleaving a PRBS. Specifically, if the multi-level modulated signal is a PAM4 PRBS, it is possible to visually recognize whether the first bit of the PRBS is assigned to the MSB or the LSB.

[0072] Although the best mode of the pattern generating device and method, and the error rate measuring device and method according to the present invention have been described above, the present invention is not limited by the description and drawings according to the mode. In other words, other modes, embodiments, and operation techniques made by those skilled in the art based on the mode are all naturally included in the scope of the present invention. [Explanation of symbols]

[0073] 1. Error rate measurement device 2 Pattern Generator 3. Error detection device 11 Setting methods 12 Signal Generating Means 13 Memory means 14 Control Means 14a Display control means 15 Display means 16 Switching Method 16a MSB Toggle Button 16b LSB toggle button 16c Toggle Button 21, 22, 24 Input box 23 Button 25(25A,25B) Circuit diagram 25a Oscillator 25b split circuit 25c MSB and LSB PRBS logic inversion circuit 25d Gray Coder 25e Precoder 25f MSB and LSB Logic Inverter 25g bit shift circuit 25h Addition circuit 25i PAM4 Decoder 25j MSB and LSB logic inversion circuit 25k error detector W Object to be measured

Claims

1. A pattern generator (2) for generating a multi-value modulation signal having four or more power-of-two values ​​using a pattern corresponding to various transmission standards, a display means (15) for displaying a setting screen (15a) for selecting and setting a pattern of the multi-level modulation signal from a pattern list; A control means (14) for displaying and controlling a circuit configuration diagram (25) on the transmitting side or receiving side according to a standard of the pattern of the multi-level modulation signal generated by bit interleaving the PRBS selected and set on the setting screen; and a switching means (16) for selectively switching the position to which the first bit is assigned, with the LSB being the lowest position, for a division circuit (25b) that divides the PRBS pattern in the circuit diagram.

2. 2. The pattern generator according to claim 1, wherein the switching means (16) displays the MSB and disables switching when the standard is Ethernet (registered trademark).

3. 2. The pattern generator according to claim 1, wherein the switching means (16) displays the LSB and disables switching when the standard is at least PCI Express 6.

0.

4. 4. The pattern generating device according to claim 1, wherein the switching means (16) is provided outside or inside the dividing circuit (25b).

5. A pattern generation method for generating a multi-value modulated signal having four or more power-of-two values ​​using a pattern corresponding to various transmission standards, comprising the steps of: displaying a setting screen (15a) for selecting and setting a pattern of the multi-level modulation signal from a pattern list; A step of displaying and controlling a circuit configuration diagram (25) on the transmitting side or receiving side according to a standard of the pattern of the multi-level modulation signal generated by bit interleaving the PRBS selected and set on the setting screen; a step of selectively switching a switching means (16) so that it is possible to identify to which place the first bit is assigned, with the LSB being the lowest 0th place, for a division circuit (25b) that divides the PRBS pattern in the circuit configuration diagram; 13. A pattern generating method comprising:

6. 6. The pattern generating method according to claim 5, further comprising the step of displaying an MSB and disabling switching of the switching means (16) when the standard is Ethernet (registered trademark).

7. 6. The pattern generating method according to claim 5, further comprising the step of displaying an LSB and disabling switching of the switching means (16) when the standard is at least PCI Express 6.

0.

8. 8. The pattern generating method according to claim 5, further comprising the step of providing the switching means (16) outside or inside the dividing circuit (25b).

9. A pattern generator (2) according to claim 1; an error detection device (3) for measuring a symbol error rate by receiving a signal from the device under test (W) associated with an input of a multi-level modulated signal generated by the pattern generation device to the device under test (W); An error rate measuring device comprising:

10. A step of inputting a multi-level modulated signal generated by the pattern generating method of claim 5 to a device under test (W); receiving a signal from the device under test associated with inputting the multi-level modulated signal to the device under test and measuring a symbol error rate; 13. A method for measuring an error rate comprising:

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