Display device and display system

Abstract

To provide a display device and a display system for improving the transmissivity even if the pixels are increased in definition.SOLUTION: A display device includes an array substrate, a counter substrate, and a liquid crystal layer. The array substrate includes a signal line, a scan line, a plurality of pixel electrodes disposed for every opening of a pixel surrounded by two adjacent signal lines and two adjacent scan lines, a plurality of semiconductors disposed for every pixel, and a common electrode overlapping with the pixel electrodes through an insulating film. An end part of the pixel electrode overlaps with the opening of the pixel. A slit of the common electrode is polygonal in shape. In the opening of the pixel, a part of the slit of the common electrode overlaps with the pixel electrode and the other part of the slit of the common electrode overlaps with a region without the pixel electrode.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present disclosure relates to a display device and a display system. [Background technology]

[0002] Patent Documents 1 and 2 disclose display devices that improve the response speed and transmittance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-232136 A [Patent Document 2] JP 2019-113584 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, as pixels become finer, it becomes difficult to form the comb teeth of the electrodes. In Patent Document 2, four liquid crystal domains of the same size are generated around two openings (slits), improving the response speed. However, in Patent Document 2, as pixels become finer, all four liquid crystal domains around the two openings (slits) become equally small, which may result in a decrease in transmittance.

[0005] An object of the present disclosure is to provide a display device and a display system that improve the transmittance even when pixels have high resolution. [Means for solving the problem]

[0006] A display device according to one embodiment includes an array substrate, an opposing substrate opposed to the array substrate, and a liquid crystal layer including liquid crystal molecules between the array substrate and the opposing substrate, the array substrate including a plurality of signal lines spaced apart in a first direction, a plurality of scanning lines spaced apart in a second direction, a plurality of pixel electrodes arranged at each pixel opening surrounded by two adjacent signal lines and two adjacent scanning lines, a plurality of semiconductors arranged at each pixel, and a common electrode overlapping the pixel electrodes via an insulating film, an end of the pixel electrode overlapping the pixel opening, The slit in the common electrode is polygonal, and within the pixel opening, a portion of the slit in the common electrode overlaps with the pixel electrode, and another portion of the slit in the common electrode overlaps with an area where there is no pixel electrode.

[0007] A display system according to one aspect includes the display device described above and a control device that outputs an image to the display device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram showing an example of a display system according to the first embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing an example of the relative relationship between the display device and the user's eyes. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of the display system according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a pixel arrangement in a display region according to the first embodiment. [Diagram 5] FIG. 5 is a schematic diagram illustrating an example of the display panel according to the first embodiment. [Figure 6] FIG. 6 is a schematic enlarged view of a part of the display area in the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view that diagrammatically shows a cross section taken along line VII-VII' in FIG. [Figure 8] FIG. 8 is a cross-sectional view illustrating a schematic boundary between the display region and the peripheral region according to the first embodiment. [Figure 9]FIG. 9 is a cross-sectional view showing a schematic cross section taken along line IX-IX' in FIG. [Figure 10] FIG. 10 is a plan view illustrating a schematic relationship between the slits and the liquid crystal domains in the first embodiment. [Figure 11] FIG. 11 is a plan view showing a schematic relationship between slits and liquid crystal domains in a comparative example. [Figure 12] FIG. 12 is a plan view illustrating a schematic relationship between slits and liquid crystal domains in a modification of the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view illustrating a schematic cross section taken along line VII-VII' of FIG. 6 in the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view illustrating a schematic cross section taken along line IX-IX' of FIG. 8 in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The form (embodiment) for carrying out the invention will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiment. In addition, the components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present disclosure. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present disclosure. In addition, in this specification and each figure, elements similar to those described above with respect to the previously mentioned figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] (Embodiment 1) Fig. 1 is a configuration diagram showing an example of a display system according to embodiment 1. Fig. 2 is a schematic diagram showing an example of the relative relationship between a display device and a user's eyes.

[0011] In this embodiment, the display system 1 is a display system that changes the display in accordance with the movement of the user. For example, the display system 1 is a VR system that stereoscopically displays a VR (Virtual Reality) image showing a three-dimensional object or the like in a virtual space and changes the stereoscopic display in accordance with the direction (position) of the user's head, thereby generating a sense of virtual reality for the user.

[0012] The display system 1 includes, for example, a display device 100 and a control device 200. The display device 100 and the control device 200 are configured to be capable of inputting and outputting information (signals) via a cable 300. The cable 300 includes, for example, a cable such as a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)). The display device 100 and the control device 200 may be configured to be capable of inputting and outputting information via wireless communication.

[0013] Moreover, the display device 100 is supplied with power from the control device 200 via a cable 300. For example, the display device 100 may have a power receiving unit to which power is supplied from a power supply unit of the control device 200 via the cable 300, and each component of the display device 100, such as the display panel 110 and the sensor 120, may be driven using power supplied from the control device 200. In this way, a battery or the like can be removed from the display device 100, and a cheaper and lighter display device 100 can be provided. Note that a battery may be provided in the mounting member 400 or the display device 100, and the battery may be supplied to the display device.

[0014] The display device 100 includes a display panel. The display panel is, for example, a liquid crystal display.

[0015] The display device 100 is fixed to a wearing member 400. The wearing member 400 includes, for example, a headset, goggles, a helmet and a mask that cover both eyes of the user, and the like. The wearing member 400 is worn on the user's head. When worn, the wearing member 400 is disposed in front of the user so as to cover both eyes of the user. The wearing member 400 functions as an immersive wearing member by positioning the display device 100 fixed inside in front of both eyes of the user. The wearing member 400 may have an output unit that outputs sound signals and the like output from the control device 200. The wearing member 400 may also have a structure that incorporates the functions of the control device 200.

[0016] 1 shows a case where the display device 100 is slotted into the mounting member 400, but it may also be fixed to the mounting member 400. In other words, the display system may be composed of the mounting member 400, a wearable display device including the display device 100, and the control device 200.

[0017] As shown in FIG. 2, the wearing member 400 has, for example, lenses 410 corresponding to both eyes of the user. The lenses 410 are magnifying lenses for forming an image on the user's eyes. When the wearing member 400 is worn on the user's head, the lenses 410 are positioned in front of the user's eyes E. The user visually recognizes the display area of ​​the display device 100 magnified by the lenses 410. Therefore, the display device 100 needs to have high resolution in order to clearly display an image (screen). Note that, although the present disclosure has been described with one lens as an example, the display device 100 may have multiple lenses and be positioned at a position other than in front of the eyes.

[0018] The control device 200, for example, causes an image to be displayed on the display device 100. For example, the control device 200 may be an electronic device such as a personal computer or a game device. The virtual image includes, for example, images such as computer graphic images and 360-degree live-action images. The control device 200 outputs a three-dimensional image that utilizes the parallax between the user's eyes to the display device 100. The control device 200 outputs images for the right eye and the left eye that follow the direction of the user's head to the display device 100.

[0019] 3 is a block diagram showing an example of the configuration of the display system according to embodiment 1. As shown in FIG. 3, the display device 100 includes two display panels 110, a sensor 120, an image separation circuit 150, and an interface 160.

[0020] The display device 100 is composed of two display panels 110, one of which is used as the display panel 110 for the left eye and the other is used as the display panel 110 for the right eye.

[0021] Each of the two display panels 110 has a display area AA and a display control circuit 112. The display panel 110 has a light source device (not shown) that illuminates the display area AA from behind.

[0022] In the display area AA, P0×Q0 pixels Pix (P0 in the row direction and Q0 in the column direction) are arranged in a two-dimensional matrix (row and column shape). In this embodiment, P0=2880 and Q0=1700. FIG. 3 shows the arrangement of a plurality of pixels Pix in a schematic manner, and the detailed arrangement of the pixels Pix will be described later. Since the pixels of the display device are viewed through a lens, the pixel pitch is, for example, between 3 μm and 10 μm, and the display area AA is an arrangement of high-definition pixels Pix. The display area AA is surrounded by a peripheral area GA.

[0023] The display panel 110 has scanning lines extending in the X direction and signal lines extending in the Y direction intersecting the X direction. For example, the display panel 110 has 2880 signal lines SL and 1700 scanning lines GL. In the display panel 110, pixels Pix are arranged in an area surrounded by the signal lines SL and the scanning lines GL. Each pixel Pix has a switching element SW (TFT: thin film transistor) connected to the signal line SL and the scanning line GL, and a pixel electrode connected to the switching element SW. A plurality of pixels Pix arranged along the extension direction of the scanning line GL are connected to one scanning line GL. Also, a plurality of pixels Pix arranged along the extension direction of the signal line SL are connected to one signal line SL.

[0024] Of the two display panels 110, a display area AA of one display panel 110 is for the right eye, and a display area AA of the other display panel 110 is for the left eye. In the first embodiment, a case will be described in which the display panel 110 has two display panels 110, one for the left eye and one for the right eye. However, the display device 100 is not limited to the structure using two display panels 110 as described above. For example, there may be one display panel 110, and the display area of ​​the single display panel 110 may be divided into two so that an image for the right eye is displayed in the right half area and an image for the left eye is displayed in the left half area.

[0025] The display control circuit 112 includes a driver IC (Integrated Circuit) 115, a signal line connection circuit 113, and a scanning line driving circuit 114. The signal line connection circuit 113 is electrically connected to the signal lines SL. The driver IC 115 controls the ON / OFF of switching elements (e.g., TFTs) for controlling the operation (light transmittance) of the pixels Pix by the scanning line driving circuit 114. The scanning line driving circuit 114 is electrically connected to the scanning lines GL.

[0026] The sensor 120 detects information that allows the orientation of the user's head to be estimated. For example, the sensor 120 detects information indicating the movement of the display device 100 or the wearing member 400, and the display system 1 estimates the orientation of the head of the user wearing the display device 100 on his / her head based on the information indicating the movement of the display device 100 or the wearing member 400.

[0027] The sensor 120 detects information that can estimate the direction of the line of sight by using at least one of the angle, acceleration, angular velocity, direction, and distance of the display device 100 or the mounting member 400. The sensor 120 can use, for example, a gyro sensor, an acceleration sensor, an orientation sensor, or the like. The sensor 120 can detect, for example, the angle and angular velocity of the display device 100 or the mounting member 400 by a gyro sensor. The sensor 120 can detect, for example, the direction and magnitude of the acceleration acting on the display device 100 or the mounting member 400 by an acceleration sensor. The sensor 120 can detect, for example, the orientation of the display device 100 by an orientation sensor. The sensor 120 can detect the movement of the display device 100 or the mounting member 400 by, for example, a distance sensor, a GPS (Global Positioning System) receiver, or the like. The sensor 120 can be another sensor such as an optical sensor, or a combination of multiple sensors, as long as it is a sensor for detecting the direction of the user's head, a change in the line of sight, a movement, or the like. The sensor 120 is electrically connected to an image separation circuit 150 via an interface 160, which will be described later.

[0028] The image separation circuit 150 receives image data for the left eye and image data for the right eye sent from the control device 200 via a cable 300, and sends the image data for the left eye to the display panel 110 which displays the image for the left eye, and sends the image data for the right eye to the display panel 110 which displays the image for the right eye.

[0029] The interface 160 includes a connector to which a cable 300 (FIG. 1) is connected. A signal from the control device 200 is input to the interface 160 via the connected cable 300. The image separation circuit 150 outputs a signal input from the sensor 120 to the control device 200 via the interface 160 and the interface 240. Here, the signal input from the sensor 120 includes information that allows the above-mentioned line of sight direction to be estimated. Alternatively, the signal input from the sensor 120 may be output directly to the control unit 230 of the control device 200 via the interface 160. The interface 160 may be, for example, a wireless communication device, and may transmit and receive information to and from the control device 200 via wireless communication.

[0030] The control device 200 includes an operation unit 210, a storage unit 220, a control unit 230, and an interface 240.

[0031] The operation unit 210 accepts operations by a user. For example, the operation unit 210 can use an input device such as a keyboard, a button, or a touch screen. The operation unit 210 is electrically connected to the control unit 230. The operation unit 210 outputs information according to the operation to the control unit 230.

[0032] The storage unit 220 stores programs and data. The storage unit 220 temporarily stores processing results of the control unit 230. The storage unit 220 includes a storage medium. The storage medium includes, for example, a ROM, a RAM, a memory card, an optical disk, or a magneto-optical disk. The storage unit 220 may store data of an image to be displayed on the display device 100.

[0033] The storage unit 220 stores, for example, a control program 211, a VR application 212, and the like. The control program 211 can provide, for example, functions related to various controls for operating the control device 200. The VR application 212 can provide a function for displaying a virtual reality image on the display device 100. The storage unit 220 can store, for example, various information input from the display device 100, such as data indicating the detection result of the sensor 120.

[0034] The control unit 230 includes, for example, a micro control unit (MCU) and a central processing unit (CPU). The control unit 230 can comprehensively control the operation of the control device 200. Various functions of the control unit 230 are realized based on the control of the control unit 230.

[0035] The control unit 230 includes, for example, a GPU (Graphics Processing Unit) that generates an image to be displayed. The GPU generates an image to be displayed on the display device 100. The control unit 230 outputs the image generated by the GPU to the display device 100 via the interface 240. In this embodiment, the control unit 230 of the control device 200 includes a GPU, but is not limited to this. For example, the GPU may be provided in the display device 100 or the image separation circuit 150 of the display device 100. In this case, the display device 100 may acquire data from, for example, the control device 200, an external electronic device, etc., and the GPU may generate an image based on the data.

[0036] The interface 240 includes a connector to which a cable 300 (see FIG. 1) is connected. A signal from the display device 100 is input to the interface 240 via the cable 300. The interface 240 outputs a signal input from the control unit 230 to the display device 100 via the cable 300. The interface 240 may be, for example, a wireless communication device, and may transmit and receive information to and from the display device 100 via wireless communication.

[0037] When the control unit 230 executes the VR application 212, it causes the display device 100 to display an image according to the movement of the user (display device 100). When the control unit 230 detects a change in the user (display device 100) while an image is being displayed on the display device 100, it changes the image displayed on the display device 100 to an image in the changed direction. When starting to create an image, the control unit 230 creates an image based on a reference viewpoint and reference line of sight in the virtual space, and when it detects a change in the user (display device 100), it changes the viewpoint or line of sight when creating the displayed image from the reference viewpoint or reference line of sight direction according to the movement of the user (display device 100), and causes the display device 100 to display an image based on the changed viewpoint or line of sight.

[0038] For example, the control unit 230 detects a movement of the user's head to the right based on the detection result of the sensor 120. In this case, the control unit 230 changes the currently displayed image to an image in which the line of sight is changed to the right. The user can visually recognize an image to the right of the image displayed on the display device 100.

[0039] For example, when the control unit 230 detects the movement of the display device 100 based on the detection result of the sensor 120, it changes the image according to the detected movement. When the control unit 230 detects that the display device 100 has moved forward, it changes the image to an image in which the display device 100 has moved forward from the currently displayed image. When the control unit 230 detects that the display device 100 has moved backward, it changes the image to an image in which the display device 100 has moved backward from the currently displayed image. The user can visually recognize an image in the direction of his / her own movement from the image displayed on the display device 100.

[0040] Fig. 4 is a circuit diagram showing a pixel array in a display region according to embodiment 1. Fig. 5 is a schematic diagram showing an example of a display panel according to embodiment 1. In the present disclosure, the scanning lines GL and the signal lines SL do not necessarily intersect at right angles, but for convenience of explanation, in Fig. 4, the scanning lines GL and the signal lines SL are perpendicular to each other.

[0041] In the display area AA, switching elements SW, signal lines SL, scanning lines GL, etc. of the pixels PixR, PixG, and PixB shown in Fig. 4 are formed. The signal lines SL are wiring for supplying pixel signals to the pixel electrodes PE (see Fig. 6). The scanning lines GL are wiring for supplying gate signals that drive the switching elements SW.

[0042] As shown in Fig. 4, each of the pixels PixR, PixG, and PixB has a switching element SW and a capacitance of a liquid crystal layer LC. The switching element SW is composed of a thin film transistor, and in this example, is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT. An insulating film is provided between the pixel electrode PE and the common electrode CE, which will be described later, and a storage capacitance Cs shown in Fig. 4 is formed between the pixel electrode PE and the common electrode CE.

[0043] The color filters CFR1, CFG1, and CFB1 shown in FIG. 5 have color regions periodically arranged in three colors, for example, red (first color: R), green (second color: G), and blue (third color: B). The pixels PixR, PixG, and PixB shown in FIG. 4 above are associated with three color regions of R, G, and B. A set of pixels PixR, PixG, and PixB corresponding to the three color regions constitutes a pixel. The color filter may include color regions of four or more colors. The pixels PixR, PixG, and PixB may each be called a subpixel.

[0044] The color filters CFR1, CFG1, and CFB1 shown in FIG. 5 are disposed in an opening surrounded by two signal lines SL and two scanning lines GL.

[0045] As shown in FIGS. 4 and 5, in the direction Vx (first direction), the pixel PixR is sandwiched between the pixels PixB and PixG, and in the direction Vy (second direction), the pixel PixR is sandwiched between the pixels PixB and PixG.

[0046] Furthermore, in the direction Vx, the pixel PixG is sandwiched between the pixels PixR and PixB, and in the direction Vy, the pixel PixG is sandwiched between the pixels PixR and PixB.

[0047] Furthermore, in the direction Vx, the pixel PixB is sandwiched between the pixels PixG and PixR, and in the direction Vy, the pixel PixB is sandwiched between the pixels PixG and PixR.

[0048] In the direction Vx, the pixels PixR, PixG, and PixB are repeatedly arranged in this order. In the direction Vy, the pixels PixR, PixB, and PixG are repeatedly arranged in this order. Note that the arrangement in the direction Vy may be such that the pixels PixR, PixG, and PixB are repeatedly arranged in this order.

[0049] The color filters CFR1 are connected to each other by the same red color filter CFR2, and when the color filters CFR1 and CFR2 are connected, color filters of the same color are arranged in diagonal directions that intersect with the directions Vx and Vy. Similarly, the color filters CFG1 are connected to each other by the same green color filter CFG2, and the color filters CFB1 are connected to each other by the same blue color filter CFB2.

[0050] Since color filters CFR1 and CFR2 are integrally formed, for convenience of explanation, when color filters CFR1 and CFR2 are not distinguished from each other, they are hereinafter referred to as color filters CFR. Similarly, when color filters CFG1 and CFG2 are not distinguished from each other, they are hereinafter referred to as color filters CFG. When color filters CFB1 and CFB2 are not distinguished from each other, they are hereinafter referred to as color filters CFB. Furthermore, when color filters CFR, CFG, and CFB are not distinguished from each other, color filters CFR, CFG, and CFB are hereinafter referred to as color filters CF.

[0051] The spacer SP shown in FIG. 5 is a member that regulates the distance between the array substrate SUB1 and the counter substrate SUB2. The material of the spacer SP is, for example, acrylic resin. The spacer SP is cylindrical, and FIG. 5 shows the maximum diameter of the spacer SP. The shape of the spacer SP is not limited to a cylindrical shape, and it may be formed as a spacer of, for example, a rectangular column. FIG. 5 shows one spacer as an example, but in reality, a plurality of spacers are arranged.

[0052] Fig. 6 is a schematic diagram showing an enlarged view of a part of the display area in embodiment 1. The pixel Pix shown in Fig. 6 is any one of pixel PixR, pixel PixG, and pixel PixB. Hereinafter, when there is no need to distinguish between pixel PixR, pixel PixG, and pixel PixB, pixel PixR, pixel PixG, and pixel PixB will be referred to as pixel Pix.

[0053] The multiple signal lines SL are arranged at intervals in the direction Vx. The multiple scanning lines GL are arranged at intervals in the direction Vy. The conductive layer TL overlaps with the multiple signal lines SL and multiple scanning lines GL in a planar view, forming a lattice shape. Since the conductive layer TL has a lower resistance than the common electrode CE, variations in voltage distribution in the surface of the common electrode CE due to voltage drop are suppressed. The width of the conductive layer TL in the direction Vx is larger than the width of the signal lines SL. The width of the scanning lines GL in the direction Vy is larger than the width of the conductive layer TL in the direction Vy. As a result, the transparent region of the opening of the pixel Pix is ​​the region surrounded by the scanning lines GL and the conductive layer TL.

[0054] In the pixel Pix, a pixel electrode PE and a switching element SW are arranged at each opening surrounded by two signal lines SL and two scanning lines GL. The common electrode CE is an electrode common to a plurality of pixels Pix. The common electrode CE has a slit CES at each opening surrounded by two signal lines SL and two scanning lines GL.

[0055] The slit CES is a portion of the common electrode CE that is not covered with the light-transmitting conductive material. The slit CES overlaps with the pixel electrode PE. The slit CES has a quadrangular shape, and specifically includes a trapezoid shape having a pair of opposing sides that are different in length.

[0056] As shown in Fig. 6, the semiconductor SC is formed in a U-shape. The signal line SL and the semiconductor SC are electrically connected via a contact hole CH1. The semiconductor SC and the relay electrode RE are electrically connected via a contact hole CH2. The relay electrode RE and the pixel electrode PE are electrically connected via a contact hole CH3.

[0057] Fig. 7 is a cross-sectional view showing a schematic cross section taken along line VII-VII' in Fig. 6. In the first embodiment, as shown in Fig. 5, a color filter CF is provided on an array substrate SUB1. The display device 100 has a so-called COA (Color Filter On Array) structure in which the color filter CF, pixel electrodes PE, and common electrode CE are arranged on the array substrate SUB1.

[0058] 7, the array substrate SUB1 is based on a first insulating substrate 10 having light transmission properties, such as a glass substrate or a resin substrate. The array substrate SUB1 includes a first layer GL1 of the scanning line GL, a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a color filter CF, a fifth insulating film 15, a pixel electrode PE, a sixth insulating film 16, a seventh insulating film 17, a conductive layer TL, a common electrode CE, a first alignment film AL1, and the like, on the side of the first insulating substrate 10 facing the counter substrate SUB2. In the following description, the direction from the array substrate SUB1 toward the counter substrate SUB2 is referred to as the upper side, or simply as the upper side.

[0059] The first layer GL1 of the scanning line GL is located on the first insulating substrate 10. The first insulating film 11 is located on the first layer GL1 of the scanning line GL and the inner side surface 10A of the first insulating substrate 10. The second insulating film 12 is located on the first insulating film 11. The semiconductor SC is located on the second insulating film 12. The third insulating film 13 is located on the semiconductor SC and the second insulating film 12. The second layer GL2 of the scanning line GL is located on the third insulating film 13. Note that the portions of the first layer GL1 and the second layer GL2 of the scanning line GL that overlap the semiconductor SC act as gate electrodes.

[0060] The fourth insulating film 14 is located on the second layer GL2 of the scanning line GL and the third insulating film 13. A contact hole CH1 is formed in the third insulating film 13 and the fourth insulating film 14 at a position overlapping the semiconductor SC, and the signal line SL formed on the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact hole CH1.

[0061] A contact hole CH2 is formed by drilling a hole in the third insulating film 13 and the fourth insulating film 14 at a position overlapping the semiconductor SC, and a relay electrode RE formed on the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact hole CH2.

[0062] The fifth insulating film 15 is located on the signal line SL, the relay electrode RE, and the fourth insulating film 14. The color filter CF is located on the fifth insulating film 15. The sixth insulating film 16 is located on the color filter CF and the fifth insulating film 15.

[0063] A pixel electrode PE is electrically connected to the relay electrode RE through a contact hole CH3 formed in the fifth insulating film 15 and the sixth insulating film 16 at a position overlapping the relay electrode RE. The pixel electrode PE is formed of a conductive material having light transmission, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGO (Indium Gallium Oxide).

[0064] The common electrode CE is located on the seventh insulating film 17. The common electrode CE is formed of a light-transmitting conductive material such as ITO, IZO, or IGO.

[0065] The conductive layer TL is located on the seventh insulating film 17. The conductive layer TL is a conductor and is electrically connected to the common electrode CE, so that the resistance value per unit area of ​​the common electrode CE and the conductive layer TL is small. The conductive layer TL may be a single layer of a metal such as aluminum (Al), but may also be formed of multiple metal layers such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum by disposing titanium (Ti) and molybdenum (Mo) on the upper and lower layers of aluminum.

[0066] The common electrode CE and the slits CES are covered with a first alignment film AL1.

[0067] The counter substrate SUB2 is based on a second insulating substrate 20 having light-transmitting properties, such as a glass substrate or a resin substrate. The counter substrate SUB2 includes an overcoat layer 21 and a second alignment film AL2 on the side of the second insulating substrate 20 facing the array substrate SUB1.

[0068] The array substrate SUB1 and the counter substrate SUB2 are arranged such that the first alignment film AL1 and the second alignment film AL2 face each other. The liquid crystal layer LC is sealed between the first alignment film AL1 and the second alignment film AL2. The first alignment film AL1 and the second alignment film AL2 align the long axes of the liquid crystal molecules so as to be perpendicular or parallel to the initial alignment direction AD shown in FIG. 6. The liquid crystal layer LC is made of a negative type liquid crystal material having a negative dielectric anisotropy, or a positive type liquid crystal material having a positive dielectric anisotropy. The liquid crystal layer LC is stable in orientation when a voltage is applied to the liquid crystal layer LC, and it is easy to maintain a high-speed response of the liquid crystal molecules. If the liquid crystal layer LC is made of a positive type liquid crystal material, the long axes of the liquid crystal molecules are aligned in a direction parallel to the initial alignment direction AD shown in FIG. 6. If the liquid crystal layer LC is made of a negative type liquid crystal material, the long axes of the liquid crystal molecules are aligned in a direction perpendicular to the initial alignment direction AD shown in FIG. 6.

[0069] The array substrate SUB1 faces the backlight unit, and the counter substrate SUB2 is located on the display surface side. Various types of backlight units are applicable, but detailed explanations of their structures will be omitted.

[0070] The first optical element OD1 including the first polarizing plate PL1 is disposed on the outer surface 10B of the first insulating substrate 10 or on the surface facing the backlight unit. The second optical element OD2 including the second polarizing plate PL2 is disposed on the outer surface 20B of the second insulating substrate 20 or on the surface on the observation position side. The first polarization axis of the first polarizing plate PL1 and the second polarization axis of the second polarizing plate PL2 are in a crossed Nicol positional relationship in the Vx-Vy plane, for example. The first optical element OD1 and the second optical element OD2 may include other optical functional elements such as retardation plates.

[0071] Fig. 8 is a cross-sectional view showing a schematic view of the boundary between the display region and the peripheral region according to embodiment 1. Fig. 9 is a cross-sectional view showing a schematic view of the cross section taken along line IX-IX' in Fig. 8.

[0072] 8 and 9, in the peripheral area GA, a wiring COM for supplying a common potential is disposed on the fourth insulating film 14. The fifth insulating film 15 covers and protects the wiring COM. A contact hole CHG is provided in a part of the fifth insulating film 15, and the wiring COM is electrically connected to the conductive layer TL and the common electrode CE that are led out from the display area AA via the contact hole CHG.

[0073] As shown in Figures 8 and 9, in the peripheral area GA, a light-shielding layer BM is provided on the counter substrate SUB2, and the light-shielding layer BM can hide the peripheral area GA of the array substrate SUB1. As shown in Figures 7 and 9, in the display area AA, the light-shielding layer BM is not provided on the counter substrate SUB2. The light-shielding layer BM is made of a black resin material.

[0074] Unlike the first embodiment, if the counter substrate SUB2 is provided with a color filter and a light-shielding layer on the boundary between the colors of the color filter, the smaller the pixel Pix is, the more likely it is that the opening of the pixel Pix on the array substrate will overlap with the position of the light-shielding layer in the display area AA of the counter substrate SUB2. In contrast, in the COA structure of the first embodiment shown in Figures 8 and 9, the display area AA of the counter substrate SUB2 does not have a color filter CF and a light-shielding layer on the boundary between the colors of the color filter CF, so that even if the pixel Pix is ​​small, the opening of the pixel Pix is ​​not shielded from light.

[0075] FIG. 10 is a plan view showing a schematic relationship between the slit and the liquid crystal domain. As shown in FIG. 6 and FIG. 10, the slit CES is a polygonal shape having a trapezoidal region CESA and a rectangular region CESB. The trapezoidal region CESA has a first side Qa, a second side Qb, a third side Qt1, and a fourth side Qt2. The first side Qa and the second side Qb face each other and are parallel. The third side Qt1 and the fourth side Qt2 face each other and are non-parallel. The distance between the third side Qt1 and the fourth side Qt2 becomes smaller as they approach the first side Qa. The second side Qb constitutes one side of the rectangular region CESB, and the third side Qt1 and the fourth side Qt2 intersect with the second side Qb at intersections Qbp1 and Qbp2, respectively. The straight line connecting the intersection points Qbp1 and Qbp2 can be said to be the second side of the trapezoidal area CESA, and the distance Db is greater than the distance Da of the first side Qa. As described above, the slit CES includes a trapezoid in the aperture portion of the pixel Pix.

[0076] The first side Qa overlaps the scanning line GL. In order to suppress the influence of the leakage electric field from the scanning line GL, it is preferable that the first side Qa overlaps the scanning line GL within a range of 0 μm to 0.3 μm from the edge of the scanning line GL. Since the first side Qa does not overlap the conductive layer TL, it is less likely to be influenced by the contact hole CH3.

[0077] The distance of the third side Qt1 is equal to the distance of the fourth side Qt2. This makes the trapezoidal region CESA an isosceles trapezoid. The distance Db of the second side Qb is about 2 μm or more and 3 μm or less. The distance Da of the first side Qa is 2 μm or less. When the distance Da of the first side Qa is substantially zero and the third side Qt1 and the fourth side Qt2 intersect, the trapezoidal region CESA becomes a triangle. The trapezoidal region CESA may be a polygonal shape having a triangle or more, and may be a pentagon, hexagon, octagon, or the like. The trapezoidal region CESA may be an asymmetric trapezoid in which the distance of the third side Qt1 and the distance of the fourth side Qt2 are different.

[0078] The distance Lc from the first side Qa to the second side Qb is greater than the distance of the opening between the scanning lines GL in the direction Vy. The distance Db of the second side Qb is less than the distance of the opening between the conductive layers TL in the direction Vx. The distance Lc1 from the end PEe of the pixel electrode PE to the second side Qb is less than the distance Lc. The region CESC between the end PEe of the pixel electrode PE and the scanning line GL has a length in the direction Vy that is less than the distance Lc2 from the end PEe of the pixel electrode PE to the first side Qa.

[0079] As described above, the slit CES of the common electrode CE has a first side Qa, a second side Qb, a third side Qt1, and a fourth side Qt2. In a plan view, the first side Qa overlaps with the scanning line GL, and the distance between the third side Qt1 and the fourth side Qt2 becomes smaller toward the first side Qa. When the distance between the third side Qt1 and the fourth side Qt2 becomes smaller toward the first side Qa, the stability of the liquid crystal alignment in the vicinity of the third side Qt1 and the fourth side Qt2 is improved and the behavior of the liquid crystal molecule Lcm is stabilized, compared to when the third side Qt1 and the fourth side Qt2 are parallel.

[0080] For example, when no voltage is applied to the liquid crystal layer LC, the liquid crystal molecules Lcm are initially aligned such that their major axes are parallel to the initial alignment direction AD on each of the third side Qt1 and the fourth side Qt2 of the slit CES. The liquid crystal molecules Lcm in the vicinity of each of the adjacent third side Qt1 and fourth side Qt2 are tilted in the opposite direction to the direction Vy. On the other hand, when a voltage is applied to the liquid crystal layer LC, that is, during the ON state when an electric field is formed between the pixel electrode PE and the common electrode CE, the alignment state of the liquid crystal molecules Lcm is changed by the influence of the electric field.

[0081] In the display device of the first embodiment, a dark region NDM where the alignment of the liquid crystal molecules Lcm hardly changes is formed at a position midway between the third side Qt1 and the fourth side Qt2. Note that a dark region NDM is also formed in the vicinity of the first side Qa, but the existence of the dark region NDM is not visible due to the scanning line GL.

[0082] 10, liquid crystal domains DM11 and DM21 are formed at the third side Qt1 and the fourth side Qt2. In the liquid crystal domains DM11 and DM21, when a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules Lcm near the third side Qt1 and near the fourth side Qt2 rotate in opposite directions.

[0083] In this way, when a voltage is applied between the pixel electrode PE and the common electrode CE, the long axis direction of the liquid crystal molecules Lcm rotates clockwise in the region near the third side Qt1 and counterclockwise in the region near the fourth side Qt2. In the vicinity of the region CESC, when a voltage is applied between the pixel electrode PE and the common electrode CE, the long axis direction of the liquid crystal molecules Lcm rotates clockwise in the region near the third side Qt1 and counterclockwise in the region near the fourth side Qt2. In this way, when a voltage is applied between the pixel electrode PE and the common electrode CE, the polarization state of the incident linearly polarized light changes according to the alignment state of the liquid crystal molecules Lcm as it passes through the liquid crystal layer LC.

[0084] The liquid crystal molecules Lcm in the liquid crystal domains DM11 and DM12 respond faster than those in horizontal electric field type liquid crystal display devices such as FFS (Fringe Field Switching) and IPS (In Plane Switching).

[0085] The rectangular region CESB stabilizes the liquid crystal domains DM11 and DM21. As a result, in the display device of the first embodiment, even if the pixel Pix becomes smaller due to high resolution, the area ratio of the liquid crystal domains DM11 and DM21 in the pixel Pix increases, and the transmittance improves.

[0086] As shown in Fig. 6, when the pixel Pix becomes smaller due to high definition, it is necessary to avoid short-circuiting between two adjacent pixels Pix due to the influence of the contact hole CH3 of the adjacent pixel Pix. To avoid short-circuiting between two adjacent pixels Pix, it is necessary to move the end PEe of the pixel electrode PE away from the contact hole CH3 of the adjacent pixel Pix. For example, the distance in the direction Vy from the end PEe of the pixel electrode PE to the conductive layer TL is 2 μm or more. Therefore, the end PEe of the pixel electrode PE crosses the light-transmitting region of the opening of the pixel Pix.

[0087] FIG. 11 is a plan view showing a schematic relationship between the slit and the liquid crystal domain in the comparative example. As shown in the comparative example in FIG. 11, if the end PEe of the pixel electrode PE and the first side Qa of the slit CES are positioned at the same position in a plan view, a dark region NDM may occur in the region CESC between the end PEe of the pixel electrode PE and the scanning line GL, and the luminance of the pixel Pix may decrease. In contrast, in the first embodiment, the end PEe of the pixel electrode PE and the first side Qa of the slit CES are at different positions in a plan view. As shown in FIG. 7, the end PEe of the pixel electrode PE overlaps with the slit CEA of the common electrode CE. Although the region CESC is a region without the conductive material of the common electrode CE and the pixel electrode PE, the liquid crystal domains DM11 and DM21 are also generated in the region CESC due to the fringe electric field. As a result, the display device 100 of the first embodiment can increase the normalized liquid crystal mode efficiency by 1.37 times compared to the comparative example described above, and can improve the maximum luminance of the pixel Pix.

[0088] In addition, there is no light-shielding layer in the display area AA of the counter substrate SUB2, which reduces the influence of misalignment between the array substrate SUB1 and the counter substrate SUB2.

[0089] As described above, the display device 100 of the first embodiment includes an array substrate SUB1, a counter substrate SUB2 opposed to the array substrate SUB1, and a liquid crystal layer LC including liquid crystal molecules Lcm between the array substrate SUB1 and the counter substrate SUB2. The array substrate SUB1 includes a plurality of signal lines SL spaced apart in the direction Vx, a plurality of scanning lines GL spaced apart in the direction Vy, a plurality of pixel electrodes PE arranged at each opening of a pixel Pix surrounded by two adjacent signal lines SL and two adjacent scanning lines GL, a plurality of semiconductors SC arranged at each pixel Pix, and a common electrode CE overlapping the plurality of pixel electrodes PE via a seventh insulating film 17.

[0090] The end PEe of the pixel electrode PE overlaps the opening of the pixel Pix. As a result, the opening of the pixel Pix has a portion where the pixel electrode PE is present and a portion where the pixel electrode PE is not present, as shown in FIG. 10. As shown in FIG. 10, when the distance Lc1 from the second side Qb to the end PEe of the pixel electrode PE is greater than the distance Lc2 from the first side Qa to the end PEe of the pixel electrode PE, the light transmittance is further improved. The slit CES of the common electrode CE is polygonal, and in the opening of the pixel Pix, a portion of the slit CES of the common electrode CE overlaps with the pixel electrode PE, and the region CESC of the other portion of the slit CES of the common electrode CE overlaps with the region where the pixel electrode is not present. As a result, even if the pixel Pix is ​​highly fine, a short circuit between adjacent pixel electrodes PE is suppressed. Even in the highly fine pixel Pix, the liquid crystal domains DM11 and DM21 appear near the region CESC, improving the light transmittance.

[0091] (Modification of the first embodiment) 12 is a plan view showing a schematic relationship between a slit and a liquid crystal domain in a modification of the first embodiment. In the following description, the same components as those in the first embodiment may be denoted by the same reference numerals. Furthermore, duplicated descriptions will be omitted. The modification of the first embodiment differs from the first embodiment in that the slit CES is trapezoidal and there is no rectangular region CESB.

[0092] As shown in FIG. 12, the slit CES is a polygon having a trapezoidal region CESA. The trapezoidal region CESA has a first side Qa, a second side Qb, a third side Qt1, and a fourth side Qt2. The first side Qa and the second side Qb face each other and are parallel. The third side Qt1 and the fourth side Qt2 face each other and are non-parallel. The distance between the third side Qt1 and the fourth side Qt2 becomes smaller as it approaches the first side Qa. The second side Qb constitutes one side of the rectangular region CESB, and the third side Qt1 and the fourth side Qt2 intersect with the second side Qb at intersections Qbp1 and Qbp2, respectively. The straight line connecting the intersections Qbp1 and Qbp2 is the second side of the trapezoidal region CESA, and this distance Db is greater than the distance Da of the first side Qa. As described above, the slit CES includes a trapezoid in the opening portion of the pixel Pix.

[0093] 12, liquid crystal domains DM11, DM12, DM21, and DM22 are formed between the dark regions NDM. In the liquid crystal domains DM11 and DM21, when a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules Lcm near the third side Qt1 and near the fourth side Qt2 rotate in opposite directions. In the liquid crystal domains DM12 and DM22, when a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules Lcm near the third side Qt1 and near the fourth side Qt2 rotate in opposite directions.

[0094] In the display device of the modified example of the first embodiment, a dark region NDM where almost no change in alignment of the liquid crystal molecules Lcm occurs is formed in the central position of the third side Qt1 and the fourth side Qt2.

[0095] A dark region NDM is sandwiched between the liquid crystal domains DM11 and DM12, and in the liquid crystal domains DM11 and DM12, when a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules Lcm in the vicinity of the third side Qt1 rotate in the opposite directions to each other. A dark region NDM is sandwiched between the liquid crystal domains DM21 and DM22, and in the liquid crystal domains DM21 and DM22, when a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules Lcm in the vicinity of the fourth side Qt2 rotate in the opposite directions to each other.

[0096] Although the region CESC is an area where the conductive materials of the common electrode CE and the pixel electrode PE are absent, liquid crystal domains DM11 and DM21 are generated due to the fringe electric field, so that the display device 100 of the modification of embodiment 1 has improved light transmittance.

[0097] The liquid crystal domain DM11 of the embodiment 1 can be said to be in a state where the rotation directions of the liquid crystal domains DM11 and DM12 in the modification of the embodiment 1 are aligned, and therefore has a larger area ratio in the pixel Pix than the modification of the embodiment 1. Similarly, the liquid crystal domain DM21 of the embodiment 1 can be said to be in a state where the rotation directions of the liquid crystal domains DM21 and DM22 in the modification of the embodiment 1 are aligned, and therefore has a larger area ratio in the pixel Pix than the modification of the embodiment 1.

[0098] (Embodiment 2) Fig. 13 is a cross-sectional view showing a schematic cross section of VII-VII' in Fig. 6 in embodiment 2. Fig. 14 is a cross-sectional view showing a schematic cross section of IX-IX' in Fig. 8 in embodiment 2. In the following description, the same components as those in embodiment 1 may be denoted by the same reference numerals. Furthermore, duplicated descriptions will be omitted. Embodiment 2 differs from embodiment 1 in that the common electrode CE is multi-layered and the pixel electrode is multi-layered.

[0099] As shown in Fig. 13, the array substrate SUB1 is based on a first insulating substrate 10 having translucency, such as a glass substrate or a resin substrate. The array substrate SUB1 includes a first layer GL1 of the scanning line GL, a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a color filter CF, a fifth insulating film 15, a pixel electrode PE1, a sixth insulating film 16, a shield electrode CE1, a first intermediate insulating film 17A, a second intermediate insulating film 17B, a third intermediate insulating film 17C, a pixel electrode PE2, a conductive layer TL, a common electrode CE2, a first alignment film AL1, and the like, on the side of the first insulating substrate 10 facing the counter substrate SUB2. In the following description, the direction from the array substrate SUB1 toward the counter substrate SUB2 is referred to as the upper side, or simply as the upper side.

[0100] The first layer GL1 of the scanning line GL is located on the first insulating substrate 10. The first insulating film 11 is located on the first layer GL1 of the scanning line GL and the inner side surface 10A of the first insulating substrate 10. The second insulating film 12 is located on the first insulating film 11. The semiconductor SC is located on the second insulating film 12. The third insulating film 13 is located on the semiconductor SC and the second insulating film 12. The second layer GL2 of the scanning line GL is located on the third insulating film 13. Note that the portions of the first layer GL1 and the second layer GL2 of the scanning line GL that overlap the semiconductor SC act as gate electrodes.

[0101] The fourth insulating film 14 is located on the second layer GL2 of the scanning line GL and the third insulating film 13. A contact hole CH1 is formed in the third insulating film 13 and the fourth insulating film 14 at a position overlapping the semiconductor SC, and the signal line SL formed on the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact hole CH1.

[0102] A contact hole CH2 is formed by drilling a hole in the third insulating film 13 and the fourth insulating film 14 at a position overlapping the semiconductor SC, and a relay electrode RE formed on the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact hole CH2.

[0103] The fifth insulating film 15 is located on the signal line SL, the relay electrode RE, and the fourth insulating film 14. The color filter CF is located on the fifth insulating film 15. The sixth insulating film 16 is located on the color filter CF and the fifth insulating film 15.

[0104] The pixel electrode PE1 is electrically connected to the relay electrode RE through a contact hole CH3 formed in the fifth insulating film 15 and the sixth insulating film 16 at a position overlapping the relay electrode RE. The first intermediate insulating film 17A is located on the sixth insulating film 16 and the pixel electrode PE1. The pixel electrode PE1 is formed of a conductive material having light transmission, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGO (Indium Gallium Oxide).

[0105] The shield electrode CE1 is located on the first intermediate insulating film 17A. The shield electrode CE1 is made of a conductive material having light transmission, such as ITO, IZO, or IGO. The second intermediate insulating film 17B is located on the shield electrode CE1 and the first intermediate insulating film 17A. The pixel electrode PE2 is located on the second intermediate insulating film 17B. The pixel electrode PE2 is made of a conductive material having light transmission, such as ITO, IZO, or IGO. The second intermediate insulating film 17B has a contact hole CH4. The second intermediate insulating film 17B electrically insulates the pixel electrode PE2 from the shield electrode CE1, and the pixel electrode PE2 is electrically connected to the pixel electrode PE1 through the contact hole CH4.

[0106] The third intermediate insulating film 17C is located on the pixel electrode PE2 and the second intermediate insulating film 17B. The first intermediate insulating film 17A, the second intermediate insulating film 17B, and the third intermediate insulating film 17C are the seventh insulating film.

[0107] The conductive layer TL is located on the third intermediate insulating film 17C. The conductive layer TL is a conductor and is electrically connected to the common electrode CE, so that the resistance value per unit area of ​​the common electrode CE and the conductive layer TL is small. The conductive layer TL may be a single layer of a metal such as aluminum (Al), but may also be formed of multiple metal layers such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum by disposing titanium (Ti) and molybdenum (Mo) on the upper and lower layers of aluminum.

[0108] The common electrode CE2 is located on the conductive layer TL and the third intermediate insulating film 17 C. The common electrode CE2 and the slits CES are covered with the first alignment film AL1.

[0109] The counter substrate SUB2 is based on a second insulating substrate 20 having light-transmitting properties, such as a glass substrate or a resin substrate. The counter substrate SUB2 includes an overcoat layer 21 and a second alignment film AL2 on the side of the second insulating substrate 20 facing the array substrate SUB1.

[0110] As shown in Figures 8 and 14, in the peripheral area GA, a wiring COM for supplying a common potential is disposed on the fourth insulating film 14. The fifth insulating film 15 covers and protects the wiring COM. A contact hole CHG is provided in a part of the fifth insulating film 15, and the wiring COM is electrically connected to the shield electrode CE1, the conductive layer TL, and the common electrode CE2, which are led out from the display area AA, via the contact hole CHG. This makes the shield electrode CE1 have the same potential as the common electrode CE2. The shield electrode CE1, together with the common electrode CE2, also functions as the common electrode CE.

[0111] 13, an end PEe1 of the pixel electrode PE1 overlaps with the shield electrode CE1. An end PEe2 of the pixel electrode PE2 overlaps with the shield electrode CE1. The shield electrode CE1 overlaps with the region CESC. This suppresses capacitive coupling between the pixel electrodes PE2 of the adjacent pixels Pix. Also, similar to the first embodiment, an end PEe2 of the pixel electrode PE2 overlaps with the slit CEA of the common electrode CE2.

[0112] As shown in FIG. 13, the pixel Pix includes a common electrode CE2 overlapping with a plurality of pixel electrodes PE2 via a third intermediate insulating film 17C. In the second embodiment, the end PEe2 of the pixel electrode PE2 overlaps with the opening of the pixel Pix. As a result, the opening of the pixel Pix has a portion where the pixel electrode PE2 is present and a portion where the pixel electrode PE2 is not present. The slit CES of the common electrode CE is polygonal, and in the opening of the pixel Pix, a portion of the slit CES of the common electrode CE2 overlaps with the pixel electrode PE2, and the region CESC of the other portion of the slit CES of the common electrode CE2 overlaps with the region where the pixel electrode is not present. As a result, even if the pixel Pix is ​​highly fine, a short circuit between adjacent pixel electrodes PE2 is suppressed. Even in the highly fine pixel Pix, the liquid crystal domains DM11 and DM21 appear near the region CESC in the same manner as in the first embodiment, and thus the light transmittance is improved.

[0113] Although the preferred embodiment has been described above, the present disclosure is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally belong to the technical scope of the present disclosure. [Explanation of symbols]

[0114] 1 Display System 10 First insulating substrate 11 First insulating film 12 Second insulating film 13 Third insulating film 14 Fourth insulating film 15 Fifth insulating film 16 6th insulating film 17 Seventh insulating film 17A First intermediate insulating film 17B Second intermediate insulating film 17C 3rd intermediate insulating film 20 Second insulating substrate 20B Outer surface 21 Overcoat layer 100 display device 110 Display Panel 112 Display control circuit 200 Control device 410 Lens AA display area BM light shielding layer CE, CE1, CE2 common electrode CES Slit CESA isosceles trapezoid region CESB rectangular area CESC area CF Color Filter GA Peripheral Areas GL scanline LS light shielding layer PE, PE1, PE2 pixel electrodes SL signal line SUB1 Array board SUB2 Opposite board TL Conductive layer

Claims

1. An array substrate; a counter substrate facing the array substrate, and a liquid crystal layer including liquid crystal molecules between the array substrate and the counter substrate; The array substrate includes: A plurality of signal lines arranged at intervals in a first direction; a plurality of scan lines spaced apart in a second direction; A plurality of pixel electrodes arranged for each pixel aperture surrounded by two adjacent signal lines and two adjacent scanning lines; A plurality of semiconductors arranged for each pixel; a common electrode overlapping the plurality of pixel electrodes via an insulating film; an end of the pixel electrode overlaps an opening of the pixel; The slit of the common electrode is polygonal, Within the pixel aperture, a portion of the slit of the common electrode overlaps with the pixel electrode, and another portion of the slit of the common electrode overlaps with an area where the pixel electrode is not present. Display device.

2. 2. The display device of claim 1, wherein the slit in the common electrode has a first side, a second side, a third side and a fourth side, and in a planar view, the first side overlaps the scanning line, and the distance between the third side and the fourth side becomes smaller toward the first side.

3. 3. The display device of claim 2, wherein when a voltage is applied between the pixel electrode and the common electrode, the long axis direction of the liquid crystal molecules rotates clockwise in a region near the third side and rotates counterclockwise in a region near the fourth side.

4. 3. The display device of claim 2, wherein in other portions of the slits of the common electrode, when a voltage is applied between the pixel electrode and the common electrode, the long axis direction of the liquid crystal molecules rotates clockwise in a region near the third side and counterclockwise in a region near the fourth side.

5. The display device according to claim 1 , further comprising a shield electrode having the same potential as the common electrode, the shield electrode overlapping an area where no pixel electrode is present in a plan view.

6. The display device according to claim 1 , wherein within the pixel aperture, the slit in the common electrode comprises a trapezoidal shape.

7. Lenses and A display device according to any one of claims 1 to 6, A control device that outputs an image to the display device. Display system.

Images