Semiconductor device

Abstract

To provide a semiconductor device which can be improved in electric characteristics.SOLUTION: A semiconductor device 1A comprises: a chip 2 which has a first principal surface 3; trench electrode type capacitor structure 85 which is formed on the first principal surface 3 and which is given a first potential; a dielectric film 46 which covers the capacitor structure 85 on the first principal surface 3; and a pad electrode 91 which is arranged on the dielectric film 46 in such a manner that the pad electrode 91 and the capacitor structure 85 form capacity connection through the dielectric film 46 and to which second potential being different from the first potential is given. The dielectric film 46 comprises: a first film 53 which covers the capacitor structure 85; and a second film 54 which is arranged on the first film 53 in such a manner that the second film 54 covers the capacitor structure 85 by sandwiching the first film 53, and is made of a dielectric material being different from the first film 53.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a trench gate structure, an interlayer insulating film, a source electrode, an isolation insulating film, and a gate pad. The trench gate structure is formed in the semiconductor substrate. The interlayer insulating film is formed on the trench gate structure. The source electrode is formed on the interlayer insulating film. The isolation insulating film is formed on the source electrode. The gate pad is disposed on the source electrode via the isolation insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0106733

[0004] [overview] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type capacitor structure formed on the main surface and applied with a first potential; a dielectric film covering the capacitor structure on the main surface; and a pad electrode arranged on the dielectric film to form a capacitive connection with the capacitor structure via the dielectric film, and to which a second potential different from the first potential is applied, the dielectric film including a first film covering the capacitor structure, and a second film arranged on the first film to cover the capacitor structure with the first film in between, the second film being made of a dielectric material different from the first film. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a circuit diagram showing an example of an electrical configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view of the semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a plan view showing an example of the layout of the first main surface. [Figure 4] FIG. 4 is an enlarged plan view showing a main part of the active region. [Diagram 5] FIG. 5 is an enlarged plan view showing another main part of the active region. [Figure 6] FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is an enlarged plan view showing a main part of the monitor area. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG. [Figure 12] FIG. 12 is an enlarged plan view showing the temperature measuring area. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is an enlarged plan view showing the configuration in the pad region together with the capacitor structure according to the first layout example. [Figure 15] FIG. 15 is an enlarged plan view showing a main part of the pad region. [Figure 16] FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18A] FIG. 18A is a diagram showing a part of a manufacturing process of the semiconductor device according to the first embodiment. [Figure 18B] FIG. 18B is a diagram showing a step subsequent to that of FIG. 18A. [Figure 18C] FIG. 18C is a diagram showing a step subsequent to that of FIG. 18B. [Figure 18D]FIG. 18D is a diagram showing a step subsequent to that of FIG. 18C. [Figure 19A] FIG. 19A is a plan view showing a capacitor structure according to the second layout example. [Figure 19B] FIG. 19B is a plan view showing a capacitor structure according to the third layout example. [Figure 19C] FIG. 19C is a plan view showing a capacitor structure according to the fourth layout example. [Figure 19D] FIG. 19D is a plan view showing a capacitor structure according to the fifth layout example. [Figure 19E] FIG. 19E is a plan view showing a capacitor structure according to the sixth layout example. [Figure 19F] FIG. 19F is a plan view showing a capacitor structure according to the seventh layout example. [Figure 19G] FIG. 19G is a plan view showing a capacitor structure according to the eighth layout example. [Figure 19H] FIG. 19H is a plan view showing a capacitor structure according to the ninth layout example. [Figure 19I] FIG. 19I is a plan view showing a capacitor structure according to the tenth layout example. [Figure 19J] FIG. 19J is a plan view showing a capacitor structure according to the eleventh layout example. [Figure 19K] FIG. 19K is a plan view showing a capacitor structure according to the twelfth layout example. [Figure 19L] FIG. 19L is a plan view showing a capacitor structure according to the thirteenth layout example. [Figure 19M] FIG. 19M is a plan view showing a capacitor structure according to the fourteenth layout example. [Figure 20] FIG. 20 is a plan view for explaining an electrical test on the gate pad electrode side. [Figure 21] FIG. 21 is a plan view for explaining an electrical test on the monitor pad electrode side. [Figure 22] FIG. 22 is a plan view for explaining an electrical test on the anode pad electrode side. [Figure 23] FIG. 23 is a plan view for explaining an electrical test on the cathode pad electrode side. [Figure 24] FIG. 24 is a cross-sectional view of a semiconductor device according to the second embodiment. [Diagram 25] FIG. 25 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 26A] FIG. 26A is a diagram showing a part of a manufacturing process of the semiconductor device according to the second embodiment. [Figure 26B] FIG. 26B is a diagram showing a step subsequent to that of FIG. 26A. [Figure 26C] FIG. 26C is a diagram showing a step subsequent to that of FIG. 26B. [Figure 26D] FIG. 26D is a diagram showing a step subsequent to that of FIG. 26C. [Figure 27] FIG. 27 is a plan view showing a main part of a pad region of a semiconductor device according to the third embodiment. [Figure 28] FIG. 28 is an enlarged plan view showing a main part of a pad region of a semiconductor device according to the third embodiment. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX shown in FIG. [Diagram 30] FIG. 30 is a cross-sectional view taken along the line XXX-XXX shown in FIG. [Figure 31A] FIG. 31A is a diagram showing a part of a manufacturing process of the semiconductor device according to the third embodiment. [Figure 31B] FIG. 31B is a diagram showing a step subsequent to that of FIG. 31A. [Figure 31C] FIG. 31C is a diagram showing a step subsequent to that of FIG. 31B. [Diagram 32] FIG. 32 is a cross-sectional view showing a main part of a semiconductor device according to the fourth embodiment. [Diagram 33] FIG. 33 is a cross-sectional view showing a main part of a semiconductor device according to a fifth embodiment. [Diagram 34] FIG. 34 is a cross-sectional view showing a main part of a semiconductor device according to the sixth embodiment. [Diagram 35] FIG. 35 is a plan view showing an example of the layout of a first main surface of a semiconductor device according to the seventh embodiment. [Diagram 36] FIG. 36 is an enlarged plan view showing a main part of the active region of the semiconductor device shown in FIG. [Figure 37] FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in FIG. [Figure 38] FIG. 38 is a cross-sectional view showing a main part of a semiconductor device according to the eighth embodiment. [Figure 39] FIG. 39 is a cross-sectional view showing a main part of a semiconductor device according to a ninth embodiment. [Diagram 40] FIG. 40 is a cross-sectional view showing a main part of a semiconductor device according to the tenth embodiment. [Diagram 41] FIG. 41 is a cross-sectional view showing a main part of a semiconductor device according to the eleventh embodiment. [Diagram 42] FIG. 42 is a cross-sectional view showing a main part of a semiconductor device according to the twelfth embodiment. [Diagram 43] FIG. 43 is a plan view showing a first modified example of the semiconductor device according to the first to twelfth embodiments. [Diagram 44] FIG. 44 is a plan view showing a second modified example of the semiconductor device according to the first to twelfth modes. [Diagram 45] FIG. 45 is a plan view showing a third modified example of the semiconductor device according to the first to twelfth modes. [Figure 46] FIG. 46 is a plan view showing a fourth modified example of the semiconductor device according to the first to twelfth modes.

[0006] [Detailed Description] Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams, and are not strictly illustrated, and the relative positional relationship, scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanations given before the omission or simplification apply.

[0007] When the term "substantially" is used in this specification, this term includes a numerical value (shape) equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison target. In the following description, the terms "first," "second," "third," and the like are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0008] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type", but "p-type" may also be called "first conductivity type" and "n-type" may also be called "second conductivity type". Of course, "n-type" may also be called "first conductivity type" and "p-type" may also be called "second conductivity type". "p-type" is a conductivity type caused by a trivalent element, and "n-type" is a conductivity type caused by a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0009] 1 is a circuit diagram showing an example of an electrical configuration of a semiconductor device 1A according to the first embodiment. The semiconductor device 1A includes a gate pad GP, an emitter pad EP, a monitor pad MP, a collector pad CoP, an anode pad AP, a cathode pad CaP, an insulated gate type main transistor structure T1, an insulated gate type monitor transistor structure T2, and a temperature sensitive diode structure D. In other words, the semiconductor device 1A is a semiconductor switching device.

[0010] The main transistor structure T1 is composed of one or more transistor structures T3. In this embodiment, the main transistor structure T1 includes a parallel circuit composed of a plurality of (four in this embodiment) transistor structures T3. The transistor structure T3 includes either or both of a MISFET structure and an IGBT structure. In this embodiment, the transistor structure T3 has a trench gate vertical IGBT structure.

[0011] The main transistor structure T1 (transistor structure T3) includes a gate electrically connected to the gate pad GP, an emitter electrically connected to the emitter pad EP, and a collector electrically connected to the collector pad CoP. The main transistor structure T1 is controlled to be turned on and off in response to a gate potential applied from the gate pad GP, and generates an output current Ice between the emitter pad EP and the collector pad CoP. The output current Ice is an emitter-collector current of the main transistor structure T1.

[0012] In this embodiment, the monitor transistor structure T2 is connected in parallel to the main transistor structure T1. In this embodiment, the monitor transistor structure T2 has a trench-gate vertical IGBT structure. The monitor transistor structure T2 includes a monitor gate electrically connected to the gate pad GP, a monitor emitter electrically connected to the monitor pad MP, and a monitor collector electrically connected to the collector pad CoP.

[0013] The monitor transistor structure T2 is controlled to be turned on and off at the same timing as the main transistor structure T1 in response to a gate potential applied from the gate pad GP, and generates a monitor current Im for monitoring the output current Ice between the monitor pad MP and the collector pad CoP. The monitor current Im is an emitter-collector current of the monitor transistor structure T2.

[0014] The monitor current Im is less than the output current Ice. The current ratio Im / Ice of the monitor current Im to the output current Ice may be 1 / 2000 or more and 1 / 10 or less. The current ratio Im / Ice may have a value belonging to at least one of the ranges of 1 / 2000 or more and 1 / 1750 or less, 1 / 1750 or more and 1 / 1500 or less, 1 / 1500 or more and 1 / 1250 or less, 1 / 1250 or more and 1 / 1000 or less, 1 / 1000 or more and 1 / 750 or less, 1 / 750 or more and 1 / 500 or less, 1 / 500 or more and 1 / 250 or less, 1 / 250 or more and 1 / 100 or less, 1 / 100 or more and 1 / 75 or less, 1 / 75 or more and 1 / 50 or less, 1 / 50 or more and 1 / 25 or less, and 1 / 25 or more and 1 / 10 or less.

[0015] The temperature sensitive diode structure D has a parallel circuit PC including one or more (four in this embodiment) first diodes D1 and one or more (four in this embodiment) second diodes D2. The number of the second diodes D2 is the same as the number of the first diodes D1. Of course, the number of the second diodes D2 may be more than the number of the first diodes D1, or may be less than the number of the first diodes D1.

[0016] The first diodes D1 are connected in series in the forward direction to form a first series circuit SC1. The anode of the first series circuit SC1 is electrically connected to the anode pad AP. The cathode of the first series circuit SC1 is electrically connected to the cathode pad CaP.

[0017] The second diodes D2 are connected in series in the forward direction to form a second series circuit SC2. The cathode of the second series circuit SC2 is electrically connected to the anode pad AP. The anode of the second series circuit SC2 is electrically connected to the cathode pad CaP. In other words, the second series circuit SC2 is connected in parallel with the first series circuit SC1 in a reverse bias state, and forms a parallel circuit PC with the first series circuit SC1.

[0018] The first series circuit SC1 functions as a temperature sensor, and the second series circuit SC2 functions as a protection circuit. The first series circuit SC1 (the plurality of first diodes D1) has a temperature characteristic (for example, a positive temperature characteristic) that varies with temperature change with respect to a forward voltage, and outputs a forward current according to the temperature of the chip 2.

[0019] The second series circuit SC2 provides immunity to noise signals. It is preferable that the second series circuit SC2 has electrical characteristics (high frequency impedance characteristics) substantially equal to those of the first series circuit SC1. If the protection function provided by the second series circuit SC2 is not required, the second series circuit SC2 may be omitted.

[0020] The semiconductor device 1A includes a monitor capacitor structure CM electrically interposed between the emitter pad EP and the monitor pad MP. The monitor capacitor structure CM functions as a capacitor between the emitter pad EP and the monitor pad MP when a voltage is applied between the emitter pad EP and the monitor pad MP. The monitor capacitor structure CM also functions as a capacitor between the gate pad GP and the monitor pad MP when a voltage is applied between the gate pad GP and the monitor pad MP.

[0021] The semiconductor device 1A includes an anode capacitor structure CA electrically interposed between the emitter pad EP and the anode pad AP. When a voltage is applied between the emitter pad EP and the anode pad AP, the anode capacitor structure CA functions as a capacitor between the emitter pad EP and the anode pad AP. When a voltage is applied between the gate pad GP and the anode pad AP, the anode capacitor structure CA also functions as a capacitor between the gate pad GP and the anode pad AP.

[0022] The semiconductor device 1A includes a cathode capacitor structure CC electrically interposed between the emitter pad EP and the cathode pad CaP. When a voltage is applied between the emitter pad EP and the cathode pad CaP, the cathode capacitor structure CC functions as a capacitor between the emitter pad EP and the cathode pad CaP. When a voltage is applied between the gate pad GP and the cathode pad CaP, the cathode capacitor structure CC also functions as a capacitor between the gate pad GP and the cathode pad CaP.

[0023] FIG. 2 is a plan view of the semiconductor device 1A shown in FIG. 1. FIG. 3 is a plan view showing an example of the layout of the first main surface 3. FIG. 4 is an enlarged plan view showing a main part of the active region 6. FIG. 5 is an enlarged plan view showing another main part of the active region 6. FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along the line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along the line VIII-VIII shown in FIG. 5.

[0024] 2 to 8, the semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 includes either one or both of a silicon single crystal and a wide band gap semiconductor single crystal. A wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon. Examples of wide band gap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). The chip 2 may be called a "semiconductor chip", a "silicon chip", a "wide band gap semiconductor chip", or the like.

[0025] When SiC single crystal is used as the wide band gap semiconductor single crystal, the chip 2 is preferably made of hexagonal SiC single crystal. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. The chip 2 preferably includes 4H-SiC single crystal. Of course, the chip 2 may include other polytypes. In this embodiment, the chip 2 has a single-layer structure made of silicon single crystal.

[0026] The chip 2 may have a thickness of 50 μm or more and 500 μm or less. The thickness of the chip 2 may have a value belonging to at least one of the ranges of 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0027] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0028] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face (oppose) a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face (oppose) the first direction X.

[0029] Hereinafter, the direction extending along the first main surface 3 may be referred to as the “horizontal direction.” The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0030] The semiconductor device 1A includes one or more active regions 6 provided on the first main surface 3. The active regions 6 are regions having a transistor structure T3. The number of active regions 6 is arbitrary and is appropriately adjusted according to the size of the chip 2 (first main surface 3).

[0031] In this embodiment, the semiconductor device 1A includes a plurality (four in this embodiment) of active regions 6. The plurality of active regions 6 include a first active region 6A, a second active region 6B, a third active region 6C, and a fourth active region 6D arranged from the third side surface 5C side toward the fourth side surface 5D side.

[0032] The multiple active regions 6 are provided in an inner portion of the first main surface 3 and spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The multiple active regions 6 are arranged at intervals in the first direction X and extend in strip shapes in the second direction Y. The multiple active regions 6 are biased toward the second side surface 5B relative to the first side surface 5A.

[0033] The multiple active regions 6 may have any planar shape. In this embodiment, the multiple active regions 6 are partitioned into a polygonal shape having four sides parallel to the periphery of the chip 2. The multiple active regions 6 may have different widths in the first direction X, lengths in the second direction Y, planar areas, etc. At least two of the multiple active regions 6 may be partially connected.

[0034] The semiconductor device 1A includes a monitor region 7 provided on the first main surface 3. The monitor region 7 is a region having a monitor transistor structure T2. The monitor region 7 is provided in a region outside the multiple active regions 6. The layout location of the monitor region 7 is arbitrary. In this embodiment, the monitor region 7 is arranged on the first side surface 5A side with respect to the multiple active regions 6.

[0035] In this embodiment, the monitor region 7 is disposed near a corner connecting the first side surface 5A and the fourth side surface 5D. The monitor region 7 may face at least one active region 6 in the second direction Y. The monitor region 7 has a planar area smaller than the planar area of ​​the multiple active regions 6. The planar area of ​​the monitor region 7 is arbitrary and is appropriately adjusted according to the size of the chip 2 (first main surface 3) and the monitor current Im.

[0036] The semiconductor device 1A includes a peripheral region 8 provided on the periphery of the first main surface 3. The peripheral region 8 is a region that does not have a monitor transistor structure T2 and a transistor structure T3. The peripheral region 8 is provided in a region outside the multiple active regions 6 and the monitor region 7 on the periphery of the first main surface 3. The peripheral region 8 is formed in an annular shape extending along the periphery of the first main surface 3, and surrounds the multiple active regions 6 and the monitor region 7.

[0037] The semiconductor device 1A includes one or more (multiple in this embodiment) street regions 9 provided on the first main surface 3. The street regions 9 are regions that do not have a monitor transistor structure T2 and a transistor structure T3.

[0038] The multiple street regions 9 are provided in an area outside the multiple active regions 6 and the monitor area 7. The multiple street regions 9 are partitioned into regions between adjacent multiple active regions 6, and extend in a strip shape along the second direction Y following the extension direction of the multiple active regions 6.

[0039] The semiconductor device 1A includes a temperature detection region 10 provided on the first main surface 3. The temperature detection region 10 is a region including a temperature sensing diode structure D for detecting the temperature of the chip 2. The temperature detection region 10 may be referred to as a "diode region", a "temperature sensing diode region", or the like. The temperature detection region 10 is provided in a region outside the multiple active regions 6 and the monitor region 7.

[0040] In this embodiment, the temperature detection region 10 is formed in a region between the plurality of active regions 6 by utilizing a part of the street region 9, and faces the plurality of active regions 6 in the first direction X. In this embodiment, the temperature detection region 10 is formed in the second active region 6B. The temperature detection region 10 has a planar area less than the planar area of ​​the multiple active regions 6. The layout location of the temperature detection region 10 is arbitrary. The temperature rises relatively easily in the inner part of the first main surface 3 (chip 2). Therefore, it is preferable that the temperature detection region 10 is provided in the inner part of the first main surface 3 (for example, near the center).

[0041] In this case, the temperature of the chip 2 is appropriately detected. When a first virtual line passing through the center of the first main surface 3 in the first direction X and a second virtual line passing through the center of the first main surface 3 in the second direction Y are set, a part of the temperature measurement region 10 may overlap either or both of the first virtual line and the second virtual line.

[0042] The semiconductor device 1A includes a plurality of pad regions 11 provided on the first main surface 3. The plurality of pad regions 11 are regions in which external terminals for external connection are arranged. The plurality of pad regions 11 are provided in regions outside the plurality of active regions 6, the monitor region 7, and the temperature measurement region 10. The layout locations of the plurality of pad regions 11 are arbitrary. In this embodiment, the plurality of pad regions 11 are formed by utilizing a part of the outer periphery region 8 in a region on the first side surface 5A side of the plurality of active regions 6.

[0043] The multiple pad regions 11 include a gate pad region 11G, a monitor pad region 11M, an anode pad region 11A, and a cathode pad region 11C. The gate pad region 11G is a region where a gate pad GP is arranged. The monitor pad region 11M is a region where a monitor pad MP is arranged. The anode pad region 11A is a region where an anode pad AP is arranged. The cathode pad region 11C is a region where a cathode pad CaP is arranged.

[0044] The gate pad region 11G is provided in a region on the first side surface 5A side with respect to the multiple active regions 6. Specifically, the gate pad region 11G may be provided in the vicinity of the center of the first side surface 5A and face one or multiple active regions 6 in either or both of the first direction X and the second direction Y. In this embodiment, the gate pad region 11G faces the temperature measurement region 10 in the second direction Y.

[0045] The monitor pad region 11M is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the monitor pad region 11M is provided in a region on the fourth side surface 5D side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X. In this embodiment, the monitor pad region 11M faces the gate pad region 11G across a part of at least one active region 6 (in this embodiment, the third active region 6C).

[0046] The monitor pad region 11M is provided in a region on the first side surface 5A side of the monitor region 7, and faces the monitor region 7 in the second direction Y. The monitor pad region 11M faces one or more active regions 6 (the third active region 6C in this embodiment) in the second direction Y, with the monitor region 7 in between.

[0047] The anode pad region 11A is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the anode pad region 11A is provided in a region on the third side surface 5C side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X. The anode pad region 11A may face one or more active regions 6 in the second direction Y.

[0048] The cathode pad region 11C is provided in a region on the first side surface 5A side with respect to the multiple active regions 6. Specifically, the cathode pad region 11C is provided in a region on the third side surface 5C side with respect to the gate pad region 11G, and faces the gate pad region 11G in the first direction X.

[0049] More specifically, the cathode pad region 11C is interposed in a region between the gate pad region 11G and the anode pad region 11A, and faces both the gate pad region 11G and the anode pad region 11A in the first direction X. The cathode pad region 11C may face one or more active regions 6 in the second direction Y.

[0050] The semiconductor device 1A includes an n-type drift region 12 formed inside the chip 2. The drift region 12 may be referred to as a "semiconductor region." The drift region 12 is formed throughout the thickness range between the first main surface 3 and the second main surface 4, and extends in a layered manner along the first main surface 3 (second main surface 4).

[0051] In this embodiment, drift region 12 is formed throughout the entire interior of chip 2, and is exposed from first main surface 3 and first to fourth side surfaces 5A to 5D. In this embodiment, chip 2 is made of an n-type semiconductor substrate (n-type chip 2), and drift region 12 is formed by utilizing n-type chip 2.

[0052] The semiconductor device 1A includes an n-type buffer region 13 formed in a surface layer portion of the second main surface 4. The buffer region 13 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. In this embodiment, the buffer region 13 is formed in a layer shape extending along the second main surface 4 over the entire area of ​​the second main surface 4, and is exposed from the first to fourth side surfaces 5A to 5D. The presence or absence of the buffer region 13 is optional, and a configuration not including the buffer region 13 may be adopted.

[0053] The semiconductor device 1A includes a p-type collector region 14 formed in a surface layer portion of the second main surface 4. The collector region 14 forms the collector of the main transistor structure T1 (transistor structure T3). The collector region 14 is formed in a region on the second main surface 4 side with respect to the buffer region 13. The collector region 14 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and replaces the conductivity type of the drift region 12 from n-type to p-type.

[0054] Collector region 14 has a p-type impurity concentration higher than the n-type impurity concentration of buffer region 13, and replaces the conductivity type of buffer region 13 from n-type to p-type. Collector region 14 is formed in a layer shape extending along second main surface 4 over the entire area of ​​second main surface 4, and is exposed from second main surface 4 and first to fourth side surfaces 5A to 5D.

[0055] The configurations of the active regions 6, the monitor region 7, the peripheral region 8, the street regions 9, the temperature detection region 10, and the pad regions 11 will be described below. FIG. 4 is an enlarged plan view showing a main part of the active region 6. FIG. 5 is an enlarged plan view showing another main part of the active region 6. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.

[0056] The semiconductor device 1A includes a plurality of transistor structures T3 formed in the respective active regions 6. The plurality of transistor structures T3 are connected in parallel to each other to form one main transistor structure T1. Since the plurality of transistor structures T3 have the same configuration, the configuration of one transistor structure T3 as one component of the semiconductor device 1A will be described below.

[0057] The transistor structure T3 includes a p-type base region 15 formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The base region 15 may also be referred to as a "body region", a "channel region", or the like. The base region 15 is formed in a surface layer portion of the drift region 12. In this embodiment, the base region 15 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and replaces the conductivity type of the drift region 12 from n-type to p-type.

[0058] The base regions 15 are each formed in a layer shape extending along the first main surface 3 in the corresponding active region 6. The base regions 15 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with the drift region 12 interposed therebetween.

[0059] The transistor structure T3 includes a plurality of trench electrode type gate structures 20 formed on the first main surface 3 of the corresponding active region 6. The plurality of gate structures 20 form the gate of the main transistor structure T1 (transistor structure T3). The gate structures 20 may be referred to as a "first trench structure", a "trench gate structure", etc. A gate potential is applied to the gate structures 20.

[0060] The multiple gate structures 20 each extend in a band shape in the first direction X and are arranged at intervals in the second direction Y. That is, the multiple gate structures 20 are arranged in a stripe shape extending in the first direction X. Each of the multiple gate structures 20 has one end on one side (the third side surface 5C side) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X).

[0061] The multiple gate structures 20 may each have a width less than the width of the multiple street regions 9. The width of the gate structure 20 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the gate structure 20.

[0062] The width of the gate structure 20 may be 0.5 μm or more and 5 μm or less. The width of the gate structure 20 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The width of the gate structure 20 is preferably 1 μm to 2.5 μm.

[0063] The multiple gate structures 20 penetrate the base region 15 to reach the drift region 12. The multiple gate structures 20 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with a part of the drift region 12 therebetween in the thickness direction.

[0064] The multiple gate structures 20 may be formed in a tapered shape toward the bottom wall. Of course, the multiple gate structures 20 may be formed approximately perpendicular to the first main surface 3. The multiple gate structures 20 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the multiple gate structures 20 may be formed approximately parallel to the first main surface 3. In this case, corners of the bottom walls of the multiple gate structures 20 may be formed in a curved shape.

[0065] Each of the gate structures 20 may have a depth of 1 μm to 10 μm. The depth of the gate structures 20 may have a value that belongs to at least one of the following ranges: 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the gate structures 20 is preferably 4 μm to 8 μm.

[0066] Each of the multiple gate structures 20 includes a gate trench 21, a gate insulating film 22, and a buried gate electrode 23. The gate trench 21 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the gate structure 20.

[0067] The gate insulating film 22 covers the wall surface of the gate trench 21. The gate insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.

[0068] The gate insulating film 22 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the gate insulating film 22 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the gate insulating film 22 is preferably 100 nm or more and 150 nm or less.

[0069] The buried gate electrode 23 is buried in the gate trench 21 with the gate insulating film 22 sandwiched therebetween. The buried gate electrode 23 faces the drift region 12 and the base region 15 with the gate insulating film 22 sandwiched therebetween. An electrode surface of the buried gate electrode 23 may be located on the bottom wall side of the gate trench 21 with respect to the first main surface 3. The buried gate electrode 23 may include either one or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0070] The transistor structure T3 includes a plurality of trench electrode type gate connection structures 25 formed on the first main surface 3 to be connected to the plurality of gate structures 20 in the corresponding active regions 6. A gate potential is applied to the plurality of gate connection structures 25. The gate connection structures 25 may be referred to as "first trench connection structures", "trench gate connection structures", etc.

[0071] The multiple gate connection structures 25 are arranged on both end sides of the multiple gate structures 20 in the first direction X so as to be connected to one end and the other end of the multiple gate structures 20, and together with the outermost multiple gate structures 20, define corresponding active regions 6.

[0072] The multiple gate connection structures 25 include a gate connection structure 25 on one end side of the multiple gate structures 20 and a gate connection structure 25 on the other end side of the multiple gate structures 20. The gate connection structure 25 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple gate structures 20. The gate connection structure 25 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple gate structures 20.

[0073] The multiple gate connection structures 25 may each have a width approximately equal to the width of the gate structure 20. Of course, the width of the gate connection structures 25 may be greater than or smaller than the width of the gate structure 20.

[0074] The width of the gate connection structure 25 may be 0.5 μm or more and 5 μm or less. The width of the gate connection structure 25 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The width of the gate connection structure 25 is preferably 1 μm to 2.5 μm.

[0075] The multiple gate connection structures 25 penetrate the base region 15 to reach the drift region 12. The multiple gate connection structures 25 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with a part of the drift region 12 therebetween in the thickness direction.

[0076] The gate connection structures 25 may be formed in a tapered shape toward the bottom wall. Of course, the gate connection structures 25 may be formed substantially perpendicular to the first main surface 3. The gate connection structures 25 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the gate connection structures 25 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the gate connection structures 25 may be formed in a curved shape.

[0077] The multiple gate connection structures 25 may each have a depth approximately equal to the depth of the gate structure 20. Of course, the depth of the gate connection structures 25 may be greater than or less than the depth of the gate structure 20.

[0078] The depth of the multiple gate connection structures 25 may be 0.5 μm or more and 10 μm or less. The depth of the gate connection structures 25 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the gate connection structures 25 is preferably 4 μm to 8 μm.

[0079] Each of the multiple gate connection structures 25 includes a gate connection trench 26, a gate connection insulating film 27, and a gate connection buried electrode 28. The gate connection trench 26 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the gate connection structure 25. The gate connection trench 26 communicates with the multiple gate trenches 21.

[0080] The gate connection insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The gate connection insulating film 27 preferably includes the same type of insulator as the gate insulating film 22. In this embodiment, the gate connection insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate connection insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.

[0081] The gate connection insulating film 27 covers in a film form the wall surface of the gate connection trench 26. The gate connection insulating film 27 is connected to the gate insulating film 22 at the communicating portion between the gate trench 21 and the gate connection trench 26.

[0082] The gate connection insulating film 27 may have a thickness approximately equal to that of the gate insulating film 22. Of course, the thickness of the gate connection insulating film 27 may be greater than or less than the thickness of the gate insulating film 22.

[0083] The thickness of the gate connection insulating film 27 may be 10 nm or more and 200 nm or less. The thickness of the gate connection insulating film 27 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the gate connection insulating film 27 is preferably 100 nm or more and 150 nm or less.

[0084] The gate connection buried electrode 28 is buried in the gate connection trench 26 with the gate connection insulating film 27 interposed therebetween. The gate connection buried electrode 28 is connected to the gate buried electrode 23 at the communicating portion between the gate trench 21 and the gate connection trench 26. The gate connection buried electrode 28 faces the drift region 12 and the base region 15 with the gate connection insulating film 27 interposed therebetween.

[0085] The electrode surface of the gate connection buried electrode 28 may be located on the bottom wall side of the gate connection trench 26 with respect to the first main surface 3. The gate connection buried electrode 28 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate connection buried electrode 28 preferably includes the same type of conductor as the gate buried electrode 23.

[0086] The transistor structure T3 includes a plurality of trench electrode type emitter structures 30 formed on the first main surface 3 in the corresponding active regions 6. The emitter structures 30 may be referred to as "second trench structures", "trench emitter structures", etc. A potential different from the gate potential (emitter potential in this embodiment) is applied to the emitter structures 30.

[0087] In this embodiment, at least two emitter structures 30 are disposed in the regions between adjacent pairs of gate structures 20. Specifically, the multiple emitter structures 30 are each formed in a mesa region defined by a pair of gate structures 20 and a pair of gate connection structures 25.

[0088] The multiple emitter structures 30 each extend in a strip shape in the first direction X following the extension direction of the multiple gate structures 20, and are formed at intervals in the second direction Y from the multiple gate connection structures 25. Each of the multiple emitter structures 30 has a length in the longitudinal direction (first direction X) that is shorter than the length of the multiple gate structures 20. Each of the multiple emitter structures 30 has one end on one side (the third side surface 5C side) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X).

[0089] Each of the multiple emitter structures 30 may have a width less than the width of the multiple street regions 9. The width of the emitter structure 30 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the emitter structure 30. The width of the emitter structure 30 may be approximately equal to the width of the gate structure 20. Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the gate structure 20.

[0090] The width of the emitter structure 30 may be 0.5 μm or more and 5 μm or less. The width of the emitter structure 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the emitter structure 30 is preferably 1 μm or more and 2.5 μm or less.

[0091] The multiple emitter structures 30 penetrate the base region 15 to reach the drift region 12. The multiple emitter structures 30 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with a part of the drift region 12 therebetween in the thickness direction.

[0092] The multiple emitter structures 30 may be formed in a tapered shape toward the bottom wall. Of course, the multiple emitter structures 30 may be formed approximately perpendicular to the first main surface 3. The multiple emitter structures 30 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the multiple emitter structures 30 may be formed approximately parallel to the first main surface 3. In this case, corners of the bottom walls of the multiple emitter structures 30 may be formed in a curved shape.

[0093] The emitter structure 30 may have a depth approximately equal to the depth of the gate structure 20. Of course, the depth of the emitter structure 30 may be greater than the depth of the gate structure 20 or less than the depth of the gate structure 20.

[0094] The depth of the plurality of emitter structures 30 may be 0.5 μm to 10 μm. The depth of the emitter structures 30 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the emitter structures 30 is preferably 4 μm to 8 μm.

[0095] The first trench pitch between the center of the gate structure 20 and the center of the emitter structure 30 may be 1 μm to 5 μm. The first trench pitch may have a value belonging to at least one of the following ranges: 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The first trench pitch is preferably 1.5 μm to 3.5 μm.

[0096] Each of the multiple emitter structures 30 includes an emitter trench 31, an emitter insulating film 32, and a buried emitter electrode 33. The emitter trench 31 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the emitter structure 30.

[0097] The emitter insulating film 32 covers the wall surface of the emitter trench 31. The emitter insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The emitter insulating film 32 preferably includes the same type of insulator as the gate insulating film 22. In this embodiment, the emitter insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the emitter insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.

[0098] The emitter insulating film 32 may have a thickness approximately equal to that of the gate insulating film 22. Of course, the thickness of the emitter insulating film 32 may be greater than or less than the thickness of the gate insulating film 22.

[0099] The emitter insulating film 32 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the emitter insulating film 32 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the emitter insulating film 32 is preferably 100 nm or more and 150 nm or less.

[0100] The buried emitter electrode 33 is buried in the emitter trench 31 with the emitter insulating film 32 interposed therebetween. The buried emitter electrode 33 faces the drift region 12 and the base region 15 with the emitter insulating film 32 interposed therebetween.

[0101] An electrode surface of the buried emitter electrode 33 may be located on the bottom wall side of the emitter trench 31 with respect to the first main surface 3. The buried emitter electrode 33 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried emitter electrode 33 preferably includes the same type of conductor as the buried gate electrode 23.

[0102] The transistor structure T3 includes a plurality of emitter connection structures 35 formed on the first main surface 3 to be connected to the plurality of emitter structures 30 in the corresponding active regions 6. An emitter potential is applied to the plurality of emitter connection structures 35. The emitter connection structures 35 may be referred to as a "second trench connection structure", a "trench emitter connection structure", etc.

[0103] The multiple emitter connection structures 35 are disposed on both end sides of the multiple emitter structures 30 in the first direction X so as to be connected to one end and the other end of the multiple emitter structures 30, respectively.

[0104] The multiple emitter connection structures 35 include an emitter connection structure 35 on one end side of the multiple emitter structures 30 and an emitter connection structure 35 on the other end side of the multiple emitter structures 30. The emitter connection structure 35 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple adjacent emitter structures 30. The emitter connection structure 35 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple adjacent emitter structures 30.

[0105] The multiple emitter connection structures 35 penetrate the base region 15 to reach the drift region 12. The multiple emitter connection structures 35 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with a part of the drift region 12 in between in the thickness direction.

[0106] The plurality of emitter connection structures 35 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of emitter connection structures 35 may be formed substantially perpendicular to the first main surface 3. The plurality of emitter connection structures 35 may have a bottom wall formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of emitter connection structures 35 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of emitter connection structures 35 may be formed in a curved shape.

[0107] Each of the multiple emitter connection structures 35 may have a width approximately equal to the width of the emitter structure 30 (gate structure 20). Of course, the width of the emitter connection structure 35 may be greater than or smaller than the width of the emitter structure 30.

[0108] The width of the emitter connection structure 35 may be 0.5 μm or more and 5 μm or less. The width of the emitter connection structure 35 may have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the emitter connection structure 35 is preferably 1 μm or more and 2.5 μm or less.

[0109] The multiple emitter connection structures 35 may each have a depth approximately equal to the depth of the emitter structure 30 (gate structure 20). Of course, the depth of the emitter connection structure 35 may be greater than or less than the depth of the emitter structure 30.

[0110] The depth of the emitter connection structure 35 may be 0.5 μm or more and 10 μm or less. The depth of the emitter connection structure 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the emitter connection structure 35 is preferably 4 μm or more and 8 μm or less.

[0111] Each of the multiple emitter connection structures 35 includes an emitter connection trench 36, an emitter connection insulating film 37, and an emitter connection buried electrode 38. The emitter connection trench 36 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the emitter connection structure 35. The emitter connection trench 36 communicates with the multiple emitter trenches 31.

[0112] The emitter connection insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The emitter connection insulating film 37 preferably includes the same type of insulator as the emitter insulating film 32 (gate insulating film 22). In this embodiment, the emitter connection insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the emitter connection insulating film 37 includes a silicon oxide film made of an oxide of the chip 2.

[0113] The emitter connection insulating film 37 covers the wall surface of the emitter connection trench in a film-like shape. The emitter connection insulating film 37 is connected to the emitter insulating film 32 at the communicating portion between the emitter trench 31 and the emitter connection trench .

[0114] The emitter connection insulating film 37 may have a thickness substantially equal to that of the emitter insulating film 32 (gate insulating film 22). Of course, the thickness of the emitter connection insulating film 37 may be greater than or less than the thickness of the emitter insulating film 32 (gate insulating film 22).

[0115] The emitter connection insulating film 37 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the emitter connection insulating film 37 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the emitter connection insulating film 37 is preferably 100 nm or more and 150 nm or less.

[0116] The emitter connection buried electrode 38 is buried in the emitter connection trench 36 with the emitter connection insulating film 37 in between. The emitter connection buried electrode 38 is connected to the emitter buried electrode 33 at the communicating portion between the emitter trench 31 and the emitter connection trench 36. The emitter connection buried electrode 38 faces the drift region 12 and the base region 15 with the emitter connection insulating film 37 in between.

[0117] The electrode surface of the emitter connection buried electrode 38 may be located on the bottom wall side of the emitter connection trench 36 with respect to the first main surface 3. The emitter connection buried electrode 38 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The emitter connection buried electrode 38 preferably includes the same type of conductor as the emitter buried electrode 33 (gate buried electrode 23).

[0118] The transistor structure T3 includes a plurality of n-type emitter regions 40 (impurity regions) formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The plurality of emitter regions 40 form the emitter of the main transistor structure T1. The emitter regions 40 have a higher n-type impurity concentration than the n-type impurity concentration of the drift region 12. In this embodiment, the emitter regions 40 have a higher n-type impurity concentration than the p-type impurity concentration of the base region 15, and replace the conductivity type of the base region 15 from p-type to n-type.

[0119] The multiple emitter regions 40 are formed in a surface layer portion of the base region 15 on both sides of the multiple gate structures 20, and extend in a strip shape in the first direction X following the extension direction of the multiple gate structures 20. The multiple emitter regions 40 are formed at intervals from the bottom of the base region 15 toward the first main surface 3.

[0120] The multiple emitter regions 40 face the gate buried electrodes 23 of the corresponding gate structures 20 across the gate insulating films 22 of the corresponding gate structures 20. The multiple emitter regions 40 may face the emitter buried electrodes 33 of the corresponding emitter structures 30 across the emitter insulating films 32 of the corresponding emitter structures 30. Of course, the multiple emitter regions 40 may be formed at intervals from the multiple emitter structures 30.

[0121] The transistor structure T3 includes a plurality of p-type contact regions 41 formed in a region different from the plurality of emitter regions 40 in a surface layer portion of the base region 15. The plurality of contact regions 41 have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. The plurality of contact regions 41 are formed on both sides of the plurality of gate structures 20 with a gap between them and the plurality of emitter structures 30.

[0122] The contact regions 41 are formed in regions on the bottom side of the base region 15 relative to the emitter regions 40. The contact regions 41 are formed at intervals from the bottom of the base region 15 toward the first main surface 3. The contact regions 41 each extend in a strip shape in the first direction X following the extension direction of the gate structures 20.

[0123] The transistor structure T3 includes a plurality of n-type storage regions 42 formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The storage regions 42 may be referred to as “carrier storage regions”. The plurality of storage regions 42 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the plurality of storage regions 42 may be lower than the n-type impurity concentration of the emitter region 40.

[0124] The storage regions 42 are formed in regions immediately below the base region 15 on both sides of the gate structures 20, and face the emitter regions 40 corresponding to them in the thickness direction. The storage regions 42 extend in a strip shape in the first direction X following the extension direction of the gate structures 20.

[0125] The multiple storage regions 42 are formed in a thickness range between the bottom of the base region 15 and the bottom wall of the gate structure 20. The multiple storage regions 42 are formed at intervals from the depth position of the bottom wall of the gate structure 20 to the bottom side of the base region 15. The bottoms of the multiple storage regions 42 may be located on the first main surface 3 side with respect to the depth position of the intermediate portion of the gate structure 20. The bottoms of the multiple storage regions 42 may be located on the bottom wall side of the gate structure 20 with respect to the depth position of the intermediate portion of the gate structure 20.

[0126] The transistor structure T3 includes a plurality of p-type well regions 43 formed in a surface layer portion of the first main surface 3 in the corresponding active region 6. The plurality of well regions 43 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 41. The plurality of well regions 43 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the plurality of well regions 43 may be lower than the p-type impurity concentration of the base region 15. In this embodiment, the plurality of well regions 43 are formed in an electrically floating state.

[0127] The multiple well regions 43 are formed in the regions between adjacent pairs of emitter structures 30. Specifically, the multiple well regions 43 are formed in mesa regions defined by the multiple emitter structures 30 and the multiple emitter connection structures 35.

[0128] The multiple well regions 43 each have a bottom located closer to the bottom wall of the multiple emitter structures 30 than the depth position of the bottom of the base region 15. The bottoms of the multiple well regions 43 are each located closer to the bottom wall of the multiple emitter structures 30 than the depth positions of the intermediate portions of the multiple emitter structures 30. In this embodiment, the bottoms of the multiple well regions 43 are located closer to the second main surface 4 than the bottom walls of the multiple emitter structures 30.

[0129] The multiple well regions 43 may have portions (bottoms) covering the bottom walls of the multiple emitter structures 30 and the bottom walls of the multiple emitter connection structures 35. The multiple well regions 43 each extend in a strip shape in the first direction X following the extension direction of the emitter structures 30, and are connected to the multiple emitter structures 30 and the multiple emitter connection structures 35.

[0130] The multiple well regions 43, together with the multiple emitter structures 30, form an IE structure (Injection Enhanced structure). The IE structure limits the movement path of holes flowing into the base region 15, and accumulates the holes in a region directly below the base region 15. In other words, the IE structure promotes low on-resistance and low on-voltage from inside the chip 2.

[0131] 6, semiconductor device 1A includes a p-type peripheral well region 44 formed in a surface layer portion of first main surface 3 in peripheral region 8. Peripheral well region 44 has a p-type impurity concentration lower than the p-type impurity concentration of contact region 41. Peripheral well region 44 may have a p-type impurity concentration higher than the p-type impurity concentration of base region 15. Of course, the p-type impurity concentration of peripheral well region 44 may be lower than the p-type impurity concentration of base region 15.

[0132] The p-type impurity concentration of the peripheral well region 44 may be approximately equal to the p-type impurity concentration of the well region 43. Of course, the p-type impurity concentration of the peripheral well region 44 may be higher than the p-type impurity concentration of the well region 43, or may be lower than the p-type impurity concentration of the well region 43.

[0133] The peripheral well region 44 is formed at a distance inward from the periphery of the first main surface 3, and extends in a band shape along the periphery of the first main surface 3. In this embodiment, the peripheral well region 44 is formed in an annular shape surrounding the multiple active regions 6.

[0134] The peripheral well region 44 is formed deeper than the base region 15, and is in contact with the outermost gate connection structure 25. The peripheral well region 44 is formed deeper than the outermost gate connection structure 25, and has a portion along the bottom wall of the outermost gate connection structure 25. In this embodiment, the peripheral well region 44 is drawn from outside the multiple active regions 6 into the multiple active regions 6, and has a portion covering the bottom walls of the multiple gate structures 20.

[0135] The peripheral well region 44 extends in the vertical direction Z along the sidewalls of the gate structures 20 and the sidewalls of the gate connection structures 25 in the active regions 6, and is connected to the base regions 15 in a surface portion of the first main surface 3. An emitter potential is applied to the peripheral well region 44 via the base regions 15.

[0136] The depth of the peripheral well region 44 may be approximately equal to the depth of the multiple well regions 43. Of course, the depth of the peripheral well region 44 may be greater than the depth of the multiple well regions 43, or may be smaller than the depth of the multiple well regions 43.

[0137] 7, the semiconductor device 1A includes a plurality of p-type street well regions 45 formed in the surface layer portion of the first main surface 3 in the plurality of street regions 9. One street well region 45 has a portion formed in the surface layer portion of the first main surface 3 in the temperature detection region 10. The street well region 45 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the street well region 45 may be lower than the p-type impurity concentration of the base region 15.

[0138] The p-type impurity concentration of the street well region 45 may be approximately equal to the p-type impurity concentration of the well region 43. Of course, the p-type impurity concentration of the street well region 45 may be higher than the p-type impurity concentration of the well region 43, or may be lower than the p-type impurity concentration of the well region 43.

[0139] The p-type impurity concentration of the street well region 45 may be approximately equal to the p-type impurity concentration of the peripheral well region 44. Of course, the p-type impurity concentration of the street well region 45 may be higher than the p-type impurity concentration of the peripheral well region 44, or may be lower than the p-type impurity concentration of the peripheral well region 44.

[0140] The multiple street well regions 45 are formed in a layer shape extending along the first main surface 3 in a region between the gate connection structure 25 on one active region 6 side and the gate connection structure 25 on the other active region 6 side, and are exposed from the first main surface 3. The multiple street well regions 45 each extend in a strip shape in the second direction Y following the extension direction of the multiple street regions 9. The multiple street well regions 45 are connected to the peripheral well region 44 in the peripheral region 8.

[0141] The street well regions 45 are formed deeper than the base regions 15, and are in contact with the gate connection structures 25. Specifically, the street well regions 45 are formed deeper than the gate connection structures 25, and have portions along the bottom walls of the gate connection structures 25.

[0142] In this embodiment, the multiple street well regions 45 have widths greater than the widths of the corresponding street regions 9, extend from the corresponding street regions 9 into the multiple active regions 6, and have portions covering the bottom walls of the multiple gate structures 20.

[0143] The street well regions 45 extend in the vertical direction Z along the sidewalls of the gate structures 20 and the sidewalls of the gate connection structures 25 in the active regions 6, and are connected to the base regions 15 in the surface layer portion of the first main surface 3. An emitter potential is applied to the street well regions 45 via the base regions 15.

[0144] The depth of the plurality of street well regions 45 may be approximately equal to the depth of the plurality of well regions 43. Of course, the depth of the plurality of street well regions 45 may be greater than the depth of the plurality of well regions 43, or may be smaller than the depth of the plurality of street well regions 45. The depth of the plurality of street well regions 45 may be approximately equal to the depth of the periphery well region 44. Of course, the depth of the plurality of street well regions 45 may be greater than the depth of the periphery well region 44, or may be smaller than the depth of the periphery well region 44.

[0145] Fig. 9 is an enlarged plan view showing a main part of the monitor area 7. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 9.

[0146] 9 to 11, the semiconductor device 1A includes a monitor transistor structure T2 in the monitor region 7. The monitor transistor structure T2 (monitor region 7) includes a base region 15, a plurality of gate structures 20, a plurality of gate connection structures 25, a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40, a contact region 41, a plurality of storage regions 42, and a plurality of well regions 43, similar to the transistor structure T3 (active region 6).

[0147] The base region 15, gate structure 20, gate connection structure 25, emitter structure 30, emitter connection structure 35, emitter region 40, contact region 41, storage region 42 and well region 43 of the monitor region 7 may be referred to as the "monitor base region (15)", "monitor gate structure (20)", "monitor gate connection structure (25)", "monitor emitter structure (30)", "monitor emitter connection structure (35)", "monitor emitter region (40)", "monitor contact region (41)", "monitor storage region (42)" and "monitor well region (43)", respectively.

[0148] These components in the monitor region 7 have a layout similar to that of the corresponding components in the active region 6. The description of the corresponding components in the active region 6 applies to the description of these components in the monitor region 7. Since these components in the monitor region 7 are laid out in a planar area smaller than the total planar area of ​​the multiple active regions 6, the monitor current Im of the monitor transistor structure T2 is less than the output current Ice of the main transistor structure T1 (transistor structure T3).

[0149] The semiconductor device 1A includes a main surface insulating film 48 that selectively covers the first main surface 3. The main surface insulating film 48 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 48 preferably includes the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the main surface insulating film 48 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 48 includes a silicon oxide film made of an oxide of the chip 2.

[0150] The main surface insulating film 48 has a portion that selectively covers the multiple active regions 6, a portion that selectively covers the monitor region 7, a portion that selectively covers the peripheral region 8, and a portion that selectively covers the multiple street regions 9.

[0151] The main surface insulating film 48 covers the base regions 15, the emitter regions 40, and the well regions 43 in the active regions 6. The main surface insulating film 48 is connected to the gate insulating films 22, the gate connection insulating films 27, the emitter insulating films 32, and the emitter connection insulating films 37 in the active regions 6, and exposes the gate buried electrodes 23, the gate connection buried electrodes 28, the emitter buried electrodes 33, and the emitter connection buried electrodes 38.

[0152] The main surface insulating film 48 covers the base regions 15, the emitter regions 40, and the well regions 43 in the monitor region 7. The main surface insulating film 48 is connected to the gate insulating films 22, the gate connection insulating films 27, the emitter insulating films 32, and the emitter connection insulating films 37 in the monitor region 7, and exposes the gate buried electrodes 23, the gate connection buried electrodes 28, the emitter buried electrodes 33, and the emitter connection buried electrodes 38.

[0153] The main surface insulating film 48 covers the peripheral well region 44 in the peripheral region 8. The main surface insulating film 48 is connected to the multiple gate connection insulating films 27 in the peripheral region 8, and exposes the multiple gate connection buried electrodes 28. The main surface insulating film 48 may be continuous to the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Of course, the main surface insulating film 48 may be formed at a distance inward from the periphery of the chip 2, and expose the drift region 12 from the periphery of the chip 2.

[0154] The main surface insulating film 48 covers the street well regions 45 in the street regions 9. The main surface insulating film 48 is connected to the gate connection insulating films 27 in the street regions 9, and exposes the gate connection buried electrodes 28.

[0155] The main surface insulating film 48 may have a thickness approximately equal to that of the gate insulating film 22 (gate connection insulating film 27). Of course, the thickness of the main surface insulating film 48 may be greater than the thickness of the gate insulating film 22 (gate connection insulating film 27) or may be smaller than the thickness of the gate insulating film 22 (gate connection insulating film 27).

[0156] The thickness of the main surface insulating film 48 may be approximately equal to the thickness of the emitter insulating film 32 (emitter connection insulating film 37). Of course, the thickness of the main surface insulating film 48 may be greater than the thickness of the emitter insulating film 32 (emitter connection insulating film 37) or may be smaller than the thickness of the emitter insulating film 32 (emitter connection insulating film 37).

[0157] The thickness of the main surface insulating film 48 may be 10 nm or more and 200 nm or less. The thickness of the main surface insulating film 48 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the main surface insulating film 48 is preferably 100 nm or more and 150 nm or less.

[0158] Fig. 12 is an enlarged plan view showing the temperature detection region 10. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 12. With reference to Figs. 12 and 13, the semiconductor device 1A includes a temperature sensing diode structure D arranged on the main surface insulating film 48 in the temperature detection region 10. The configuration of the temperature sensing diode structure D as one component of the semiconductor device 1A will be described below.

[0159] The temperature sensitive diode structure D includes one or more (multiple in this embodiment) polysilicon layers 50 disposed on the main surface insulating film 48. The number of polysilicon layers 50 is arbitrary and is appropriately adjusted depending on the number of first diodes D1 and the number of second diodes D2.

[0160] In this embodiment, the semiconductor device 1A includes four polysilicon layers 50 for the first diode D1 and four polysilicon layers 50 for the second diode D2. In this embodiment, the multiple polysilicon layers 50 are arranged in a matrix of 4 rows by 2 columns with gaps in the first direction X and the second direction Y. In this embodiment, the four polysilicon layers 50 for the first diode D1 are arranged in a row in a first column (one side in the second direction Y), and the four polysilicon layers 50 for the second diode D2 are arranged in a row in a second column (the other side in the second direction Y).

[0161] The multiple polysilicon layers 50 are disposed directly on the main surface insulating film 48, and face the street well region 45 across the main surface insulating film 48. In this embodiment, the multiple polysilicon layers 50 are formed in a polygonal shape having four sides parallel to the periphery of the chip 2 in a planar view. The multiple polysilicon layers 50 may also be formed in a quadrangular, hexagonal, circular, or other shape in a planar view.

[0162] The multiple polysilicon layers 50 have a thickness greater than the thickness of the main surface insulating film 48. The thickness of the multiple polysilicon layers 50 may be less than the depth (thickness) of the street well region 45. The thickness of the multiple polysilicon layers 50 may be less than the depth of the gate structure 20 (emitter structure 30). The thickness of the multiple polysilicon layers 50 may be less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0163] The thickness of the polysilicon layers 50 may be 0.1 μm or more and 2 μm or less. The thickness of the polysilicon layers 50 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the polysilicon layers 50 is preferably 0.25 μm or more and 1.25 μm or less.

[0164] The temperature sensitive diode structure D includes a plurality of p-type anode regions 51 formed in each of a plurality of polysilicon layers 50. The anode regions 51 are formed in the inner portion (preferably the center portion) of the corresponding polysilicon layer 50 at intervals from the periphery of the corresponding polysilicon layer 50.

[0165] The multiple anode regions 51 are formed in a polygonal or circular shape in a plan view. The multiple anode regions 51 may be formed in a quadrangular, hexagonal, or other shape in a plan view. The multiple anode regions 51 are formed throughout the thickness range of the corresponding polysilicon layer 50.

[0166] The temperature sensitive diode structure D includes a plurality of n-type cathode regions 52 formed in a plurality of polysilicon layers 50, respectively. The plurality of cathode regions 52 are formed on the periphery of the corresponding polysilicon layer 50, respectively.

[0167] The multiple cathode regions 52 each extend in a band shape along the periphery of the corresponding anode region 51 in a plan view. In this embodiment, the multiple cathode regions 52 each extend in an annular shape along the periphery of the corresponding polysilicon layer 50 in a plan view, and are each electrically connected to the corresponding anode region 51 over the entire periphery.

[0168] The plurality of cathode regions 52 are formed throughout the thickness range of the corresponding polysilicon layer 50, and are exposed from the sidewalls of the corresponding polysilicon layer 50. The plurality of cathode regions 52 and the corresponding anode regions 51 form pn junctions as the first diode D1 or pn junctions as the second diode D2, respectively.

[0169] Hereinafter, a description will be given of the wiring structure on the first main surface 3. Referring again to Figures 4 to 10, the semiconductor device 1A includes a plurality of emitter wirings 55 electrically connected to corresponding emitter connection structures 35 on the first main surface 3 in the plurality of active regions 6 and the monitor region 7, respectively.

[0170] The plurality of emitter wirings 55 are respectively disposed on the main surface insulating film 48, and respectively connected to the corresponding emitter connection structures 35. In this embodiment, the plurality of emitter wirings 55 are respectively formed integrally with the corresponding emitter connection buried electrodes 38, and each comprises an extension portion that is extended from the corresponding emitter connection buried electrodes 38 onto the main surface insulating film 48.

[0171] That is, the multiple emitter wirings 55 are each made of the same type of conductor (either one or both of p-type conductive polysilicon and n-type conductive polysilicon) as the emitter connection buried electrode 38. The multiple emitter wirings 55 are formed at intervals on the corresponding emitter connection structure 35 side from the multiple gate connection structures 25, and face the base region 15 in the thickness direction with the main surface insulating film 48 sandwiched therebetween.

[0172] The multiple emitter wirings 55 have a thickness greater than the thickness of the main surface insulating film 48. The thickness of the multiple emitter wirings 55 may be less than the depth (thickness) of the well region 43. The thickness of the multiple emitter wirings 55 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the multiple emitter wirings 55 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0173] The thickness of the multiple emitter wirings 55 may be approximately equal to the thickness of the multiple polysilicon layers 50. Of course, the thickness of the multiple emitter wirings 55 may be greater than the thickness of the multiple polysilicon layers 50, or may be smaller than the thickness of the multiple polysilicon layers 50.

[0174] The thickness of the plurality of emitter wirings 55 may be 0.1 μm or more and 2 μm or less. The thickness of the emitter wirings 55 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the emitter wirings 55 is preferably 0.25 μm or more and 1.25 μm or less.

[0175] The semiconductor device 1A includes a plurality of gate wirings 56 electrically connected to corresponding gate connection structures 25 on the first main surface 3 in the periphery region 8 and the plurality of street regions 9, respectively.

[0176] The multiple gate wirings 56 are disposed on the main surface insulating film 48, and are connected to the corresponding gate connection structures 25. In this embodiment, the multiple gate wirings 56 are formed integrally with the corresponding gate connection buried electrodes 28, and each is made of an extension portion that is extended from the corresponding gate connection buried electrodes 28 onto the main surface insulating film 48. That is, the multiple gate wirings 56 are made of the same type of conductor as the gate connection buried electrodes 28 (either one or both of p-type conductive polysilicon and n-type conductive polysilicon).

[0177] The multiple gate wirings 56 include one or more (multiple in this embodiment) first gate wirings 56A arranged in the peripheral region 8, and one or more (multiple in this embodiment) second gate wirings 56B arranged in the multiple street regions 9.

[0178] The multiple first gate wirings 56A are disposed on the main surface insulating film 48 in the peripheral region 8, and are routed in strip-like fashion in the region between the gate pad region 11G and the corresponding gate connection structure 25 (gate connection buried electrode 28). The multiple first gate wirings 56A are formed along the multiple active regions 6, and each have a portion extending in the first direction X and a portion extending in the second direction Y.

[0179] The multiple first gate wirings 56A face the peripheral well region 44 with the main surface insulating film 48 interposed therebetween. The multiple first gate wirings 56A are drawn from above the main surface insulating film 48 onto the gate connection structure 25 (gate connection buried electrode 28) adjacent to the peripheral region 8, and are connected to the gate connection structure 25 (gate connection buried electrode 28). The multiple first gate wirings 56A are electrically connected to the multiple gate structures 20 via the gate connection structure 25 (gate connection buried electrode 28).

[0180] The second gate wirings 56B are respectively disposed on the main surface insulating film 48 in the street regions 9, and are routed in a strip-like manner in the region between the gate pad region 11G and the corresponding gate connection structure 25 (gate connection buried electrode 28). The second gate wirings 56B each extend in a strip-like manner in the second direction Y following the extension direction of the street regions 9. One second gate wiring 56B is routed in the street region 9 so as to bypass the polysilicon layers 50 (temperature sensitive diode structures D).

[0181] The multiple second gate wirings 56B are respectively connected to the gate connection structures 25 (gate connection buried electrodes 28) of one and the other active regions 6 adjacent to each other in the first direction X. In other words, the multiple second gate wirings 56B are electrically connected to the multiple gate structures 20 via the multiple gate connection structures 25 (gate connection buried electrodes 28) that partition the multiple street regions 9.

[0182] At least one of the gate wirings 56 (one second gate wiring 56B in this embodiment) is connected to the gate connection structure 25 (gate connection buried electrode 28) of the monitor region 7. As a result, the gate structure 20 of the monitor region 7 and the gate structure 20 of the active region 6 are controlled to be turned on and off simultaneously.

[0183] The gate wirings 56 have a thickness greater than the thickness of the main surface insulating film 48. The gate wirings 56 may have a thickness less than the depth (thickness) of the well region 43. The gate wirings 56 may have a thickness less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the gate wirings 56 may have a thickness greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0184] The thickness of the multiple gate wirings 56 may be approximately equal to the thickness of the multiple polysilicon layers 50. Of course, the thickness of the multiple gate wirings 56 may be greater than the thickness of the multiple polysilicon layers 50, or may be smaller than the thickness of the multiple polysilicon layers 50. The thickness of the multiple gate wirings 56 may be approximately equal to the thickness of the multiple emitter wirings 55. Of course, the thickness of the multiple gate wirings 56 may be greater than the thickness of the multiple emitter wirings 55, or may be smaller than the thickness of the multiple emitter wirings 55.

[0185] The thickness of the gate wirings 56 may be 0.1 μm or more and 2 μm or less. The thickness of the gate wirings 56 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the gate wirings 56 is preferably 0.25 μm or more and 1.25 μm or less.

[0186] The semiconductor device 1A includes an interlayer film 57 that selectively covers the main surface insulating film 48. The interlayer film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 57 may have a single-layer structure made of a single insulating film, or a layered structure including a plurality of insulating films.

[0187] The interlayer film 57 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films.

[0188] The interlayer film 57 has a portion covering multiple active regions 6, a portion covering the monitor region 7, a portion covering the peripheral region 8, a portion covering multiple street regions 9, and a portion covering the temperature measurement region 10.

[0189] The interlayer film 57 covers the base regions 15, the emitter regions 40, and the well regions 43 in the active regions 6 and the monitor region 7, with the main surface insulating film 48 sandwiched therebetween. The interlayer film 57 covers the gate structures 20, the gate connection structures 25, the emitter structures 30, and the emitter connection structures 35 in the active regions 6 and the monitor region 7.

[0190] Specifically, the interlayer film 57 covers the multiple gate buried electrodes 23, the multiple gate connection buried electrodes 28, the multiple emitter buried electrodes 33, and the multiple emitter connection buried electrodes 38. In this embodiment, the interlayer film 57 extends from above the main surface insulating film 48 into the multiple gate trenches 21, the multiple gate connection trenches 26, the multiple emitter trenches 31, and the multiple emitter connection trenches 36.

[0191] The interlayer film 57 has a portion covering the electrode surfaces of the multiple gate buried electrodes 23 in the multiple gate trenches 21. The interlayer film 57 has a portion covering the electrode surfaces of the multiple gate connection buried electrodes 28 in the multiple gate connection trenches 26. The interlayer film 57 has a portion covering the electrode surfaces of the multiple emitter buried electrodes 33 in the multiple emitter trenches 31. The interlayer film 57 has a portion covering the electrode surfaces of the multiple emitter connection buried electrodes 38 in the multiple emitter connection trenches 36.

[0192] The interlayer film 57 covers the peripheral well region 44 in the peripheral region 8 with the main surface insulating film 48 sandwiched therebetween. The interlayer film 57 may be continuous with the peripheral edge (first to fourth side faces 5A to 5D) of the chip 2. Of course, the interlayer film 57 may be formed at a distance inward from the peripheral edge of the chip 2, exposing the drift region 12 from the peripheral portion of the chip 2.

[0193] The interlayer film 57 covers the street well regions 45 in the street regions 9 with the main surface insulating film 48 therebetween. The interlayer film 57 covers the polysilicon layers 50 in the temperature measurement region 10. The interlayer film 57 fills the gaps between the polysilicon layers 50 to collectively cover the polysilicon layers 50. The interlayer film 57 contacts the main surface insulating film 48 in the gaps. In other words, the interlayer film 57 faces the street well region 45 in the gaps with the main surface insulating film 48 therebetween.

[0194] The interlayer film 57 has a thickness greater than that of the main surface insulating film 48. The thickness of the interlayer film 57 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the interlayer film 57 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0195] The thickness of the interlayer film 57 is preferably greater than the thickness of the multiple polysilicon layers 50. Of course, the thickness of the interlayer film 57 may be less than the thickness of the multiple polysilicon layers 50. The thickness of the interlayer film 57 is preferably greater than the thickness of the multiple emitter wirings 55. Of course, the thickness of the interlayer film 57 may be less than the thickness of the multiple emitter wirings 55. The thickness of the interlayer film 57 is preferably greater than the thickness of the multiple gate wirings 56. Of course, the thickness of the interlayer film 57 may be less than the thickness of the multiple gate wirings 56.

[0196] The interlayer film 57 may have a thickness of 0.1 μm or more and 3 μm or less. The thickness of the interlayer film 57 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The thickness of the interlayer film 57 is preferably 0.5 μm or more and 2 μm or less.

[0197] The semiconductor device 1A includes a plurality of first emitter openings 58 formed in the interlayer film 57 in the plurality of active regions 6 and the monitor region 7. The plurality of first emitter openings 58 are formed on both sides of the plurality of gate structures 20 at intervals from the plurality of gate structures 20, and penetrate the main surface insulating film 48 and the interlayer film 57 to expose the chip 2. Specifically, the plurality of first emitter openings 58 expose the corresponding emitter regions 40 and the corresponding contact regions 41, respectively.

[0198] The multiple first emitter openings 58 are dug down from the height position of the first main surface 3 in the thickness direction of the chip 2, and each has a bottom wall located inside the chip 2. The bottom walls of the multiple first emitter openings 58 are formed at intervals from the bottoms of the corresponding base regions 15 toward the first main surface 3, and each exposes the corresponding contact regions 41. The bottom walls of the multiple first emitter openings 58 are formed at intervals from the bottoms of the corresponding contact regions 41 toward the first main surface 3.

[0199] The multiple first emitter openings 58 may be formed in a tapered shape toward the bottom wall. Of course, the multiple first emitter openings 58 may be formed approximately perpendicular to the first main surface 3. The multiple first emitter openings 58 may have a bottom wall formed in a curved shape toward the second main surface 4. Of course, the multiple first emitter openings 58 may be formed approximately parallel to the first main surface 3. In this case, the corners of the bottom wall of the multiple first emitter openings 58 may be formed in a curved shape.

[0200] The multiple first emitter openings 58 each extend in a strip shape in the first direction X following the extension direction of the multiple gate structures 20. The multiple first emitter openings 58 each have a length in the longitudinal direction (first direction X) that is shorter than the length of the multiple gate structures 20. The length of the multiple first emitter openings 58 may be shorter than the length of the multiple emitter structures 30.

[0201] The semiconductor device 1A includes a plurality of first emitter via electrodes 59 respectively embedded in the plurality of first emitter openings 58. The plurality of first emitter via electrodes 59 are electrically connected to the corresponding emitter regions 40 and the corresponding contact regions 41 in the plurality of first emitter openings 58.

[0202] The multiple first emitter via electrodes 59 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the wall surface side of the multiple first emitter openings 58.

[0203] The first electrode 60 is formed in the form of a film on the wall surface of the first emitter opening 58 as a barrier electrode. The first electrode 60 is electrically connected to the emitter region 40 and the contact region 41 in the first emitter opening 58. The first electrode 60 may have a single-layer structure including a titanium film or a titanium nitride film. The first electrode 60 may have a laminated structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be laminated on the titanium film.

[0204] The second electrode 61 is embedded in the first emitter opening 58 with the first electrode 60 in between, and is electrically connected to the emitter region 40 and the contact region 41 via the first electrode 60. The second electrode 61 may include at least one of a tungsten film, a molybdenum film, a nickel film, a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The second electrode 61 preferably includes a tungsten film.

[0205] The semiconductor device 1A includes a plurality of second emitter openings 62 formed in the interlayer film 57 in the plurality of active regions 6 and the monitor region 7. The plurality of second emitter openings 62 penetrate the interlayer film 57 and expose the corresponding emitter wirings 55. In this embodiment, the plurality of second emitter openings 62 are dug further down from the wiring surface of the corresponding emitter wirings 55 toward the main surface insulating film 48, and each has a bottom wall located within the corresponding emitter wiring 55.

[0206] The second emitter openings 62 may be formed in a tapered shape toward the bottom wall. Of course, the second emitter openings 62 may be formed substantially perpendicular to the first main surface 3. The second emitter openings 62 may be formed in a polygonal shape, a circular shape, or the like in a plan view. The second emitter openings 62 may be formed in a quadrangular shape or a hexagonal shape in a plan view.

[0207] The semiconductor device 1A includes a plurality of second emitter via electrodes 63 respectively embedded in the plurality of second emitter openings 62. The plurality of second emitter via electrodes 63 are mechanically and electrically connected to the corresponding emitter wirings 55 in the plurality of second emitter openings 62. The plurality of second emitter via electrodes 63 may have a laminated structure including a first electrode 60 and a second electrode 61, similar to the first emitter via electrode 59.

[0208] The semiconductor device 1A includes the above-mentioned emitter pad EP collectively covering the multiple active regions 6 on the first main surface 3. The emitter pad EP is a terminal to which an emitter potential is applied from the outside. The emitter pad EP may also be called an "emitter pad electrode," an "emitter terminal electrode," an "emitter external terminal," or the like.

[0209] The emitter pad EP is disposed on a portion of the interlayer film 57 that covers the active regions 6. The emitter pad EP is electrically isolated from the gate structures 20 and the gate connection structures 25 by the interlayer film 57.

[0210] The emitter pad EP is mechanically and electrically connected to a plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63 on the interlayer film 57, and is electrically connected to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40 and the plurality of contact regions 41 via the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63.

[0211] The emitter pad EP has a plurality of street removal portions 64. The plurality of street removal portions 64 expose portions of the interlayer film 57 that cover the plurality of street regions 9, and each extend in a strip shape in the second direction Y following the extension direction of the corresponding street region 9.

[0212] The emitter pad EP may have a thickness larger than that of the interlayer film 57. The thickness of the emitter pad EP may be 0.5 μm or more and 10 μm or less. The thickness of the emitter pad EP may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0213] The emitter pad EP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film shape as a barrier electrode. The first electrode film 65 is electrically connected to a plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63 on the interlayer film 57.

[0214] The first electrode film 65 is connected to the first electrodes 60 of the multiple first emitter via electrodes 59 and the first electrodes 60 of the multiple second emitter via electrodes 63. Of course, the first electrode film 65 may cover the first electrodes 60 of the multiple first emitter via electrodes 59 and the first electrodes 60 of the multiple second emitter via electrodes 63.

[0215] The first electrode film 65 may have a single layer structure including a titanium film or a titanium nitride film. The first electrode film 65 may have a laminated structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be laminated on the titanium film.

[0216] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 covers the first emitter via electrodes 59 and the second emitter via electrodes 63 in a film-like manner. The second electrode film 66 is electrically connected to the first emitter via electrodes 59 and the second emitter via electrodes 63. The second electrode 61 may include at least one of a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0217] The semiconductor device 1A includes a monitor electrode 67 covering the monitor region 7 on the first main surface 3. The monitor electrode 67 is disposed on a portion of the interlayer film 57 covering the monitor region 7. The monitor electrode 67 is electrically isolated from the multiple gate structures 20 and the multiple gate connection structures 25 by the interlayer film 57 in the monitor region 7. The monitor electrode 67 is mechanically and electrically connected to the multiple first emitter via electrodes 59 and the multiple second emitter via electrodes 63 on the interlayer film 57 in the monitor region 7.

[0218] The monitor electrode 67 is electrically connected to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40, and the plurality of contact regions 41 through the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63. The monitor electrode 67 may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side, similar to the emitter pad EP.

[0219] The monitor electrode 67 may have a thickness greater than that of the interlayer film 57. The thickness of the monitor electrode 67 may be approximately equal to that of the emitter pad EP. The thickness range of the monitor electrode 67 is the same as the thickness range of the emitter pad EP (not less than 0.5 μm and not more than 10 μm).

[0220] The semiconductor device 1A includes a plurality of gate openings 68 formed in the interlayer film 57 in the peripheral region 8 and the plurality of street regions 9. The plurality of gate openings 68 penetrate the interlayer film 57 and selectively expose portions of the plurality of gate wirings 56.

[0221] The multiple gate openings 68 may each extend in a strip shape following the extension direction of the multiple gate wirings 56. The multiple gate openings 68 may be formed at intervals following the extension direction of the multiple gate wirings 56. In this case, the multiple gate openings 68 may be formed in a polygonal or circular shape in a plan view. The multiple gate openings 68 may be formed in a quadrangular, hexagonal, or other shape in a plan view.

[0222] In this embodiment, each of the gate openings 68 is dug further down from the wiring surface of the corresponding gate wiring 56 toward the main surface insulating film 48, and has a bottom wall located within the corresponding gate wiring 56. The gate openings 68 may be formed in a tapered shape toward the bottom wall. Of course, the gate openings 68 may be formed approximately perpendicular to the first main surface 3.

[0223] The semiconductor device 1A includes a plurality of gate via electrodes 69 embedded in the plurality of gate openings 68, respectively. The plurality of gate via electrodes 69 are mechanically and electrically connected to the corresponding gate wirings 56 in the plurality of gate openings 68, respectively. The plurality of gate via electrodes 69 may have a laminated structure including a first electrode 60 and a second electrode 61, similar to the first emitter via electrode 59.

[0224] The semiconductor device 1A includes a plurality of gate fingers 70 arranged on an interlayer film 57. The gate fingers 70 may be referred to as “gate finger electrodes”, “finger electrodes”, etc. The plurality of gate fingers 70 are arranged on portions of the interlayer film 57 that cover the plurality of gate wirings 56.

[0225] The multiple gate fingers 70 are mechanically and electrically connected to the multiple gate via electrodes 69 on the interlayer film 57, and are electrically connected to the multiple gate wirings 56 through the multiple gate via electrodes 69. The multiple gate fingers 70 are electrically connected to the multiple gate structures 20 in the multiple active regions 6 and the multiple gate structures 20 in the monitor region 7 through the multiple gate wirings 56.

[0226] The multiple gate fingers 70 include multiple first gate fingers 70A arranged in the outer periphery region 8 and multiple second gate fingers 70B arranged in the multiple street regions 9.

[0227] The multiple first gate fingers 70A are respectively arranged on the multiple first gate wirings 56A in the peripheral region 8. The multiple first gate fingers 70A are routed in strips in the region between the gate pad region 11G and the corresponding gate connection structures 25 (gate connection buried electrodes 28) following the extending direction of the multiple first gate wirings 56A.

[0228] The multiple first gate fingers 70A are formed along the multiple active regions 6, and each have a portion extending in a first direction X and a portion extending in a second direction Y. The multiple first gate fingers 70A are mechanically and electrically connected to the multiple gate via electrodes 69 on the interlayer film 57, and are electrically connected to the multiple first gate wirings 56A through the multiple gate via electrodes 69.

[0229] The second gate fingers 70B are respectively disposed on the second gate wirings 56B in the street regions 9. The second gate fingers 70B are routed in a strip shape in the gate pad region 11G and the region between the corresponding gate connection structures 25 (gate connection buried electrodes 28) following the extending direction of the first gate wirings 56A.

[0230] The second gate fingers 70B each have a portion interposed within the street removal portions 64 of the emitter pad EP, and each extend in a strip shape in the second direction Y following the extension direction of the corresponding street region 9. One second gate finger 70B is routed in the street region 9 so as to bypass the polysilicon layers 50 (temperature sensitive diode structures D).

[0231] The second gate fingers 70B are mechanically and electrically connected to the gate via electrodes 69 on the interlayer film 57, and are electrically connected to the second gate wirings 56B through the gate via electrodes 69. The gate fingers 70 may have a layered structure including a first electrode film 65 and a second electrode film 66 layered in this order from the interlayer film 57 side, similar to the emitter pad EP.

[0232] The gate finger 70 may have a thickness greater than that of the interlayer film 57. The thickness of the gate finger 70 may be approximately equal to the thickness of the emitter pad EP. The thickness range of the gate finger 70 is similar to the thickness range of the emitter pad EP (not less than 0.5 μm and not more than 10 μm).

[0233] 12 and 13 again, the semiconductor device 1A includes, in the temperature detection region 10, a plurality of anode openings 71 formed in portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of anode openings 71 penetrate the interlayer film 57 and expose the corresponding anode regions 51. The plurality of anode openings 71 each extend in a strip shape along the corresponding anode region 51 in a plan view.

[0234] In this embodiment, the multiple anode openings 71 are formed in an annular shape extending along the corresponding anode regions 51 in a plan view, and surround the corresponding cathode regions 52. The multiple anode openings 71 may be formed in a square, hexagonal, polygonal, circular, or other annular shape in a plan view. Of course, the multiple anode openings 71 may be formed in an annular shape with ends extending along the corresponding anode openings 71.

[0235] The semiconductor device 1A includes a plurality of cathode openings 72 formed in portions of the interlayer film 57 covering the plurality of polysilicon layers 50 in the temperature detection region 10. The plurality of cathode openings 72 penetrate the interlayer film 57 at intervals corresponding to the plurality of anode openings 71, and expose the corresponding cathode regions 52. The plurality of cathode openings 72 each extend in a strip shape along the corresponding cathode region 52.

[0236] In this embodiment, the multiple cathode openings 72 are formed in an annular shape with ends extending along the corresponding cathode regions 52 in a plan view, and surround the corresponding anode regions 51. The multiple cathode openings 72 may be formed in an annular shape with ends, such as a square annular shape, a hexagonal annular shape with ends, a polygonal annular shape with ends, or a circular annular shape with ends in a plan view. Of course, the multiple cathode openings 72 may be formed in a square, hexagonal, polygonal, or circular shape in a plan view.

[0237] The semiconductor device 1A includes a plurality of anode via electrodes 73 respectively embedded in the plurality of anode openings 71. The plurality of anode via electrodes 73 are mechanically and electrically connected to the corresponding anode regions 51 in the corresponding anode openings 71. The plurality of anode via electrodes 73 may have a laminated structure including a first electrode 60 and a second electrode 61, similar to the plurality of first emitter via electrodes 59.

[0238] The semiconductor device 1A includes a plurality of cathode via electrodes 74 respectively embedded in the plurality of cathode openings 72. The plurality of cathode via electrodes 74 are mechanically and electrically connected to the corresponding cathode regions 52 in the corresponding cathode openings 72. The plurality of cathode via electrodes 74 may have a laminated structure including a first electrode 60 and a second electrode 61, similar to the plurality of first emitter via electrodes 59.

[0239] The semiconductor device 1A includes an anode wiring 75 disposed on the interlayer film 57. The anode wiring 75 is routed from the temperature detection region 10 through the street region 9 to the anode pad region 11A. The anode wiring 75 has a portion that extends in a strip-like shape in the second direction Y following the extension direction of the street region 9 within the street region 9, and a portion that extends in a strip-like shape in an arbitrary direction (first direction X) outside the street region 9 toward the anode pad region 11A.

[0240] The anode wiring 75 has a portion that extends parallel to the gate finger 70 in the street region 9. Like the emitter pad EP, the anode wiring 75 may have a laminated structure including a first electrode film 65 and a second electrode film 66 that are laminated in this order from the interlayer film 57 side.

[0241] The anode wiring 75 may have a thickness larger than that of the interlayer film 57. The thickness of the anode wiring 75 may be approximately equal to that of the emitter pad EP. The thickness range of the anode wiring 75 is the same as the thickness range of the emitter pad EP (not less than 0.5 μm and not more than 10 μm).

[0242] The semiconductor device 1A includes a cathode wiring 76 disposed on the interlayer film 57. The cathode wiring 76 is routed from the temperature detection region 10 through the street region 9 to the cathode pad region 11C. The cathode wiring 76 has a portion that extends in a strip-like shape in the second direction Y following the extension direction of the street region 9 within the street region 9, and a portion that extends in a strip-like shape in an arbitrary direction (first direction X) outside the street region 9 toward the cathode pad region 11C.

[0243] The cathode wiring 76 has a portion that extends parallel to both the gate finger 70 and the anode wiring 75 in the street region 9. Like the emitter pad EP, the cathode wiring 76 may have a laminated structure including a first electrode film 65 and a second electrode film 66 that are laminated in this order from the interlayer film 57 side.

[0244] The cathode wiring 76 may have a thickness larger than that of the interlayer film 57. The thickness of the cathode wiring 76 may be approximately equal to that of the emitter pad EP. The thickness range of the cathode wiring 76 is the same as that of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0245] The semiconductor device 1A includes a plurality of anode connection wirings 77 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The anode connection wirings 77 have portions that extend along the corresponding anode via electrodes 73 on the interlayer film 57, and are mechanically and electrically connected to the corresponding anode via electrodes 73, respectively.

[0246] The multiple anode connection wirings 77 may be formed in a polygonal shape, a circular shape, etc. in a planar view. The multiple anode connection wirings 77 may be formed in a quadrangular shape, a hexagonal shape, etc. in a planar view. The multiple anode connection wirings 77 may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side, similar to the emitter pad EP.

[0247] The anode connection wiring 77 may have a thickness greater than that of the interlayer film 57. The thickness of the anode connection wiring 77 may be approximately equal to that of the emitter pad EP. The thickness range of the anode connection wiring 77 is the same as the thickness range of the emitter pad EP (not less than 0.5 μm and not more than 10 μm).

[0248] The semiconductor device 1A includes a plurality of cathode connection wirings 78 formed on a portion of the interlayer film 57 covering the plurality of polysilicon layers 50. The plurality of cathode connection wirings 78 have portions extending in stripes along the corresponding cathode via electrodes 74 on the interlayer film 57, and are mechanically and electrically connected to the corresponding cathode via electrodes 74. Similar to the emitter pad EP, the plurality of cathode connection wirings 78 may each have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the interlayer film 57 side.

[0249] The cathode connecting wiring 78 may have a thickness larger than that of the interlayer film 57. The thickness of the cathode connecting wiring 78 may be approximately equal to that of the emitter pad EP. The thickness range of the cathode connecting wiring 78 is the same as the thickness range of the emitter pad EP (not less than 0.5 μm and not more than 10 μm).

[0250] The semiconductor device 1A includes a plurality of connection wirings 79 formed on a portion of the interlayer film 57 that covers the plurality of polysilicon layers 50. The plurality of connection wirings 79 are respectively interposed in regions between the plurality of polysilicon layers 50 adjacent to each other in the second direction Y on the interlayer film 57, and electrically connect the corresponding anode wirings 75 to the corresponding cathode wirings 76. The plurality of connection wirings 79 each extend in a strip shape in the second direction Y in a plan view.

[0251] One connection wiring 79 positioned at the outermost position on one side in the second direction Y electrically connects the outermost anode connection wiring 77 to the anode wiring 75. The other connection wiring 79 positioned at the outermost position on one side in the second direction Y electrically connects the outermost cathode connection wiring 78 to the anode wiring 75. This forms a first series circuit SC1 including a plurality of first diodes D1.

[0252] One connection wiring 79 positioned at the outermost position on the other side in the second direction Y electrically connects the outermost cathode connection wiring 78 to the cathode wiring 76. The other connection wiring 79 positioned at the outermost position on the other side in the second direction Y electrically connects the outermost anode connection wiring 77 to the cathode wiring 76. This forms a second series circuit SC2 including a plurality of second diodes D2.

[0253] The connection wiring 79 may have a thickness greater than that of the interlayer film 57. The thickness of the connection wiring 79 may be approximately equal to that of the emitter pad EP. The thickness range of the connection wiring 79 is the same as the thickness range of the emitter pad EP (not less than 0.5 μm and not more than 10 μm).

[0254] The configuration within the multiple pad regions 11 will be described below. Fig. 14 is an enlarged plan view showing the configuration within the pad region 11 together with a pad capacitor structure 84 according to a first layout example. Fig. 15 is an enlarged plan view showing a main part of the pad region 11. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 15. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 15.

[0255] The semiconductor device 1A includes a plurality of p-type pad well regions 80 formed in the surface layer portion of the first main surface 3 in the plurality of pad regions 11. The pad well regions 80 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the pad well regions 80 may be lower than the p-type impurity concentration of the base region 15. The p-type impurity concentration of the pad well regions 80 is lower than the p-type impurity concentration of the contact region 41.

[0256] The p-type impurity concentration of the pad well region 80 may be approximately equal to the p-type impurity concentration of the peripheral well region 44. Of course, the p-type impurity concentration of the pad well region 80 may be higher than the p-type impurity concentration of the peripheral well region 44, or may be lower than the p-type impurity concentration of the peripheral well region 44.

[0257] The p-type impurity concentration of the pad well region 80 may be approximately equal to the p-type impurity concentration of the street well region 45. Of course, the p-type impurity concentration of the pad well region 80 may be higher than the p-type impurity concentration of the street well region 45, or may be lower than the p-type impurity concentration of the street well region 45.

[0258] The multiple pad well regions 80 are formed throughout the corresponding pad regions 11. In this embodiment, the multiple pad well regions 80 are connected to the peripheral well region 44 and the multiple street well regions 45, and are formed integrally with the multiple street well regions 45 and the peripheral well region 44. In this embodiment, the multiple pad well regions 80 have a width in the first direction X that is greater than the width of the multiple street well regions 45.

[0259] The pad well regions 80 are formed deeper than the base regions 15. Specifically, the pad well regions 80 are formed deeper than the gate structures 20, the gate connection structures 25, the emitter structures 30, and the emitter connection structures 35.

[0260] The multiple pad well regions 80 may have a depth approximately equal to the depth of the multiple well regions 43. Of course, the depth of the multiple pad well regions 80 may be greater than the depth of the multiple well regions 43, or may be less than the depth of the multiple well regions 43.

[0261] The depth of the multiple pad well regions 80 may be approximately equal to the depth of the periphery well region 44. Of course, the depth of the multiple pad well regions 80 may be greater than the depth of the periphery well region 44, or may be less than the depth of the periphery well region 44.

[0262] The depth of the pad well regions 80 may be approximately equal to the depth of the street well regions 45. Of course, the depth of the pad well regions 80 may be greater than the depth of the street well regions 45, or may be less than the depth of the street well regions 45.

[0263] The semiconductor device 1A includes a plurality of pad capacitor structures 84 formed in the plurality of pad regions 11, respectively (see also FIG. 3). In this embodiment, the plurality of pad capacitor structures 84 include a monitor capacitor structure CM formed in the monitor pad region 11M, an anode capacitor structure CA formed in the anode pad region 11A, and a cathode capacitor structure CC formed in the cathode pad region 11C. In the following, the configuration of the anode capacitor structure CA will be mainly described as an example of the pad capacitor structure 84.

[0264] The configuration of the monitor capacitor structure CM can be obtained by replacing "anode capacitor structure CA" with "monitor capacitor structure CM" and "anode pad area 11A" with "monitor pad area 11M" in the following description. The configuration of the cathode capacitor structure CC can be obtained by replacing "anode capacitor structure CA" with "cathode capacitor structure CC" and "anode pad area 11A" with "cathode pad area 11C" in the following description.

[0265] The anode capacitor structure CA includes a plurality of trench electrode type capacitor structures 85 formed on the first main surface 3. The emitter potential of the transistor structure T3 is applied to the plurality of capacitor structures 85. In other words, the same potential as that applied to the pad well region 80 is applied to the plurality of capacitor structures 85.

[0266] The multiple capacitor structures 85 do not form a voltage drop caused by an externally applied potential with the pad well region 80, except for a voltage drop caused by an electric field distribution formed in the chip 2. The multiple capacitor structures 85 are electrically isolated from the monitor potential of the monitor transistor structure T2.

[0267] The number of capacitor structures 85 is less than the number of gate structures 20. The total area (total extension) of the multiple capacitor structures 85 is less than the total area (total extension) of the multiple gate structures 20. The number of capacitor structures 85 is less than the number of emitter structures 30. The total area (total extension) of the multiple capacitor structures 85 is less than the total area (total extension) of the multiple emitter structures 30.

[0268] The multiple capacitor structures 85 extend in a strip shape in the first direction X in the anode pad region 11A, and are arranged at intervals in the second direction Y. That is, the multiple capacitor structures 85 are arranged in stripes extending in the first direction X. The extension direction of the multiple capacitor structures 85 coincides with the extension direction of the multiple gate structures 20. The extension direction of the multiple capacitor structures 85 coincides with the extension direction of the multiple emitter structures 30.

[0269] Each of the multiple capacitor structures 85 may have a width less than the width of the multiple street regions 9. The width of the capacitor structure 85 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the capacitor structure 85.

[0270] The width of the capacitor structure 85 may be approximately equal to the width of the gate structure 20. Of course, the width of the capacitor structure 85 may be greater than or smaller than the width of the gate structure 20. The width of the capacitor structure 85 may be approximately equal to the width of the gate connection structure 25. Of course, the width of the capacitor structure 85 may be greater than or smaller than the width of the gate connection structure 25.

[0271] The width of the capacitor structure 85 may be approximately equal to the width of the emitter structure 30. Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the emitter structure 30. The width of the capacitor structure 85 may be approximately equal to the width of the emitter connection structure 35. Of course, the width of the capacitor structure 85 may be greater than or smaller than the width of the emitter connection structure 35.

[0272] The width of the capacitor structure 85 may be 0.5 μm to 5 μm. The width of the capacitor structure 85 may have a value belonging to at least one of the following ranges: 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The width of the capacitor structure 85 is preferably 1 μm to 2.5 μm.

[0273] The second trench pitch between the centers of the capacitor structures 85 may be approximately equal to the first trench pitch between the centers of the gate structures 20 and the emitter structures 30. Of course, the second trench pitch may be larger than the first trench pitch or smaller than the first trench pitch.

[0274] The second trench pitch may be 1 μm or more and 5 μm or less. The second trench pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0275] The plurality of capacitor structures 85 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3. Specifically, the plurality of capacitor structures 85 are formed on the first main surface 3 so as to be located within the pad well region 80.

[0276] More specifically, the capacitor structures 85 are formed at intervals from the bottom of the pad well region 80 toward the first main surface 3, and face the drift region 12 across a part of the pad well region 80 in the thickness direction. In other words, the capacitor structures 85 are connected to the pad well region 80 over the entire depth direction. Each of the capacitor structures 85 may have a bottom wall located on the bottom side of the pad well region 80 with respect to the depth position of the intermediate portion of the pad well region 80. Of course, the bottom wall of the capacitor structures 85 may be located on the first main surface 3 side with respect to the depth position of the intermediate portion of the pad well region 80. Of course, the capacitor structures 85 may penetrate the pad well region 80 to reach the drift region 12.

[0277] The plurality of capacitor structures 85 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of capacitor structures 85 may be formed substantially perpendicular to the first main surface 3. The bottom walls of the plurality of capacitor structures 85 may be formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of capacitor structures 85 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of capacitor structures 85 may be formed in a curved shape.

[0278] The plurality of capacitor structures 85 may have a depth approximately equal to the depth of the plurality of gate structures 20. Of course, the depth of the capacitor structures 85 may be greater than or less than the depth of the gate structures 20. The depth of the capacitor structures 85 may be approximately equal to the depth of the gate connection structure 25. Of course, the depth of the capacitor structures 85 may be greater than or less than the depth of the gate connection structure 25.

[0279] The depth of the capacitor structure 85 may be approximately equal to the depth of the emitter structure 30. Of course, the depth of the emitter structure 30 may be greater than the depth of the emitter structure 30 or may be smaller than the depth of the emitter structure 30. The depth of the capacitor structure 85 may be approximately equal to the depth of the emitter connection structure 35. Of course, the depth of the capacitor structure 85 may be greater than the depth of the emitter connection structure 35 or may be smaller than the depth of the emitter connection structure 35.

[0280] The depth of the capacitor structure 85 may be 0.5 μm to 10 μm. The depth of the capacitor structure 85 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the capacitor structure 85 is preferably 4 μm to 8 μm.

[0281] The multiple capacitor structures 85 each have an extension portion 85a that is extended from the anode pad region 11A to the active region 6 (in this embodiment, the first active region 6A), and are each electrically connected to the multiple emitter structures 30 within the active region 6.

[0282] For example, the multiple lead-out portions 85a may be led out to the active region 6 via open portions of the gate connection structure 25 where no gate connection structure 25 is present, and may be connected to the multiple emitter structures 30 in the active region 6, respectively. In this way, the emitter potential is applied to the multiple capacitor structures 85 via the multiple emitter structures 30.

[0283] The multiple lead-out portions 85a (capacitor structures 85) may be mechanically connected to the multiple emitter structures 30 in the active region 6. The multiple lead-out portions 85a (capacitor structures 85) may be connected to the multiple emitter connection structures 35 in the active region 6. In this case, the multiple capacitor structures 85 are mechanically and electrically connected to the multiple emitter structures 30 via the multiple emitter connection structures 35.

[0284] The multiple capacitor structures 85 (lead portions 85a) may be drawn out to the anode pad region 11A in a one-to-one correspondence from the multiple emitter structures 30. In this case, the multiple capacitor structures 85 may be drawn out at the same trench pitch (third trench pitch) as the trench pitch of the multiple emitter structures 30.

[0285] The multiple capacitor structures 85 (drawing portion 85a) do not necessarily have to be drawn out to the anode pad region 11A in a one-to-one correspondence from the multiple emitter structures 30. Therefore, one or more capacitor structures 85 (drawing portion 85a) may be drawn out to the anode pad region 11A from one corresponding emitter structure 30. Of course, one capacitor structure 85 (drawing portion 85a) may be drawn out from multiple emitter structures 30 to the anode pad region 11A.

[0286] One or more of the lead-out portions 85a (capacitor structures 85) may have both a portion extending in a first direction X and a portion extending in a second direction Y within the active region 6 and / or the anode pad region 11A, and may be configured to adjust the trench pitch (third trench pitch) in the anode pad region 11A.

[0287] Of course, one or more capacitor structures 85 may have one or more pull-out portions 85a extending in the second direction Y and be connected to one or more emitter structures 30 of an active region 6 (e.g., the first active region 6A or the second active region 6B) adjacent in the second direction Y.

[0288] Each of the plurality of capacitor structures 85 includes a capacitor trench 86, a capacitor insulating film 87, and a capacitor buried electrode 88. The capacitor trench 86 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the capacitor structure 85.

[0289] The capacitor trench 86 communicates with the emitter trench 31 of the corresponding one or more emitter structures 30. When the capacitor structure 85 is connected to the emitter connection structure 35, the capacitor trench 86 may communicate with the emitter connection trench 36. That is, the capacitor trench 86 may communicate with the emitter trench 31 via the emitter connection trench 36.

[0290] The capacitor insulating film 87 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The capacitor insulating film 87 preferably includes the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the capacitor insulating film 87 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the capacitor insulating film 87 includes a silicon oxide film made of an oxide of the chip 2.

[0291] The capacitor insulating film 87 covers the wall surface of the capacitor trench 86. The capacitor insulating film 87 is connected to the emitter insulating film 32 at the communication portion between the emitter trench 31 and the capacitor trench 86. When the capacitor structure 85 is connected to the emitter connecting structure 35, the capacitor insulating film 87 may be connected to the emitter connection insulating film 37 at the communication portion between the emitter trench 31 and the capacitor trench 86. In other words, the capacitor insulating film 87 may be connected to the emitter insulating film 32 via the emitter connection insulating film 37.

[0292] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the gate insulating film 22. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the gate insulating film 22 or may be smaller than the thickness of the gate insulating film 22. The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the gate connection insulating film 27. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the gate connection insulating film 27 or may be smaller than the thickness of the gate connection insulating film 27.

[0293] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the emitter insulating film 32. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the emitter insulating film 32, or may be smaller than the thickness of the emitter insulating film 32. The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the emitter connection insulating film 37. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the emitter connection insulating film 37, or may be smaller than the thickness of the emitter connection insulating film 37.

[0294] The thickness of the capacitor insulating film 87 may be 10 nm or more and 200 nm or less. The thickness of the capacitor insulating film 87 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the capacitor insulating film 87 is preferably 100 nm or more and 150 nm or less.

[0295] The capacitor buried electrode 88 is buried in the capacitor trench 86 with a capacitor insulating film 87 interposed therebetween. The capacitor buried electrode 88 faces the pad well region 80 with the capacitor insulating film 87 interposed therebetween. Specifically, the capacitor buried electrode 88 faces the pad well region 80 at the sidewall and bottom wall of the capacitor trench 86. When the capacitor trench 86 penetrates the pad well region 80, the capacitor buried electrode 88 may have a portion facing the pad well region 80 with the capacitor insulating film 87 interposed therebetween and a portion facing the drift region 12 with the capacitor insulating film 87 interposed therebetween.

[0296] The capacitor buried electrode 88 is connected to the emitter buried electrode 33 at the communicating portion between the emitter trench 31 and the capacitor trench 86. When the capacitor structure 85 is connected to the emitter connecting structure 35, the capacitor buried electrode 88 may be connected to the emitter connecting buried electrode 38 at the communicating portion between the emitter trench 31 and the capacitor trench 86. In other words, the capacitor insulating film 87 may be connected to the emitter buried electrode 33 via the emitter connecting buried electrode 38.

[0297] The capacitor buried electrode 88 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The capacitor buried electrode 88 preferably includes the same type of conductor as the gate buried electrode 23 (emitter buried electrode 33).

[0298] The anode capacitor structure CA includes the aforementioned main surface insulating film 48 covering the first main surface 3 of the anode pad region 11A. The main surface insulating film 48 covers the pad well region 80 on the first main surface 3. The main surface insulating film 48 is connected to the capacitor insulating film 87 in the anode pad region 11A. The thickness of the main surface insulating film 48 may be approximately equal to the thickness of the capacitor insulating film 87. Of course, the thickness of the main surface insulating film 48 may be greater than the thickness of the capacitor insulating film 87, or may be smaller than the thickness of the capacitor insulating film 87.

[0299] The anode capacitor structure CA includes one or more (one in this embodiment) capacitor electrode films 90 covering the multiple capacitor structures 85 on the main surface insulating film 48 in the anode pad region 11A. The capacitor electrode film 90 is electrically connected to the multiple capacitor structures 85. As a result, an emitter potential is applied to the capacitor electrode film 90 via the multiple capacitor structures 85.

[0300] That is, the capacitor electrode film 90 is applied with the same potential as that applied to the pad well region 80. The capacitor electrode film 90 does not form a voltage drop with the pad well region 80 due to an externally applied potential, except for a voltage drop due to an electric field distribution formed in the chip 2.

[0301] In this embodiment, the capacitor electrode film 90 collectively covers the plurality of capacitor structures 85 in the anode pad region 11 A. In this embodiment, the capacitor electrode film 90 is formed integrally with the plurality of capacitor embedded electrodes 88 and comprises lead-out portions led out from the plurality of capacitor embedded electrodes 88 onto the main surface insulating film 48.

[0302] The capacitor electrode film 90 has a portion located in a region outside the plurality of capacitor structures 85. The capacitor electrode film 90 faces the first main surface 3 in the region outside the plurality of capacitor structures 85, with the main surface insulating film 48 interposed therebetween. Specifically, the capacitor electrode film 90 faces the pad well region 80, with the main surface insulating film 48 interposed therebetween.

[0303] In this embodiment, the capacitor electrode film 90 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The capacitor electrode film 90 may be formed in a hexagonal or circular shape in a plan view. The capacitor electrode film 90 may have an electrode sidewall that extends substantially perpendicular to the first main surface 3. Of course, the electrode sidewall of the capacitor electrode film 90 may be inclined obliquely downward from the electrode main surface toward the chip 2 (first main surface 3) side.

[0304] The capacitor electrode film 90 may be made of a conductive film other than metal. In this embodiment, the capacitor electrode film 90 is made of the same type of conductor as the capacitor buried electrodes 88 (either one or both of p-type conductive polysilicon and n-type conductive polysilicon). Of course, the capacitor electrode film 90 may be made of a metal film. In this case, the capacitor electrode film 90 may be mechanically and electrically connected to a plurality of capacitor structures 85 (capacitor buried electrodes 88) on the main surface insulating film 48.

[0305] The capacitor electrode film 90 has a thickness greater than the thickness of the main surface insulating film 48. The thickness of the capacitor electrode film 90 is preferably less than the depth (thickness) of the pad well region 80. The thickness of the capacitor electrode film 90 is preferably less than the depth of the capacitor structure 85. The thickness of the capacitor electrode film 90 is preferably less than the depth of the gate structure 20 (emitter structure 30). The thickness of the capacitor electrode film 90 is preferably less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0306] The thickness of the capacitor electrode film 90 may be approximately equal to the thickness of the polysilicon layer 50. Of course, the thickness of the capacitor electrode film 90 may be greater than the thickness of the polysilicon layer 50, or may be smaller than the thickness of the polysilicon layer 50.

[0307] The thickness of the capacitor electrode film 90 may be approximately equal to the thickness of the emitter wiring 55. Of course, the thickness of the capacitor electrode film 90 may be greater than the thickness of the emitter wiring 55, or may be smaller than the thickness of the emitter wiring 55. The thickness of the capacitor electrode film 90 may be approximately equal to the thickness of the gate wiring 56. Of course, the thickness of the capacitor electrode film 90 may be greater than the thickness of the gate wiring 56, or may be smaller than the thickness of the gate wiring 56.

[0308] The thickness of the capacitor electrode film 90 may be 0.1 μm or more and 2 μm or less. The thickness of the capacitor electrode film 90 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the capacitor electrode film 90 is preferably 0.25 μm or more and 1.25 μm or less.

[0309] The anode capacitor structure CA includes a dielectric film 46 that covers the capacitor electrode film 90 in the anode pad region 11A. The dielectric film 46 covers the pad well region 80 with the main surface insulating film 48 and the capacitor electrode film 90 in between, and covers the plurality of capacitor structures 85 with the capacitor electrode film 90 in between. The dielectric film 46 covers the entire area of ​​the capacitor electrode film 90 in a film-like manner.

[0310] The thickness of the dielectric film 46 is preferably smaller than the thickness of the capacitor electrode film 90. Of course, the thickness of the dielectric film 46 may be larger than the thickness of the capacitor electrode film 90.

[0311] The dielectric film 46 includes a laminated structure of a first film 53 and a second film 54 on the first film 53 .

[0312] The first film 53 covers the main surface insulating film 48 and the capacitor electrode film 90. In this embodiment, the first film 53 directly covers the capacitor electrode film 90 and forms a contact interface with the capacitor electrode film 90. The first film 53 has a first relative dielectric constant ε r1 The first film 53 has a first relative dielectric constant ε r1 For example, is greater than or equal to 3.5 and less than or equal to 4.5.

[0313] The first film 53 is a film containing an oxide. The first film 53 preferably contains an oxide of silicon. The first film 53 is more preferably a silicon oxide film in which the surface of the capacitor electrode film 90 is oxidized. Of course, the first film 53 does not have to be a silicon oxide film.

[0314] The thickness of the first film 53 is, for example, 1500 Å or less. The thickness of the first film 53 may have a value belonging to at least one of the ranges of 100 Å to 1500 Å, 300 Å to 1200 Å, and 500 Å to 1000 Å. The thickness of the first film 53 may also have a value belonging to at least one of the ranges of 100 Å to 300 Å, 300 Å to 500 Å, 500 Å to 700 Å, 700 Å to 900 Å, 900 Å to 1100 Å, 1100 Å to 1300 Å, and 1300 Å to 1500 Å.

[0315] The second film 54 covers the capacitor electrode film 90 with the first film 53 sandwiched therebetween. In this embodiment, the second film 54 directly covers the first film 53 and forms a contact interface with the first film 53. Therefore, in this embodiment, a dielectric film 46 having a two-layer structure of the first film 53 and the second film 54 is laminated on the surface of the capacitor electrode film 90.

[0316] The second film 54 has a first relative dielectric constant ε r1 The second relative dielectric constant ε r2 The second film 54 has a second relative dielectric constant ε r2 is the first relative dielectric constant ε of the first film 53 r1 Of course, the second relative dielectric constant ε of the second film 54 is preferably higher than r2 is the first relative dielectric constant ε of the first film 53 r1 The second relative dielectric constant ε of the second film 54 may be lower than r2 For example, is greater than or equal to 7.5 and less than or equal to 8.5.

[0317] The second film 54 is a film containing a nitride. The second film 54 preferably contains a nitride of silicon. The second film 54 is more preferably a silicon nitride film. Of course, the second film 54 does not have to be a silicon nitride film, and may be, for example, a silicon oxynitride film.

[0318] The thickness of the second film 54 is, for example, 3000 Å or less. The thickness of the second film 54 may have a value belonging to at least one of the ranges of 1600 Å to 3000 Å, 1800 Å to 2800 Å, 2000 Å to 2600 Å, and 2200 Å to 2400 Å. The thickness of the second film 54 may also have a value belonging to at least one of the ranges of 1600 Å to 1800 Å, 1800 Å to 2000 Å, 2000 Å to 2200 Å, 2200 Å to 2400 Å, 2400 Å to 2600 Å, 2600 Å to 2800 Å, and 2800 Å to 3000 Å.

[0319] The anode capacitor structure CA includes a pad electrode 91 arranged on the dielectric film 46 in the anode pad region 11A. The pad electrode 91 may be referred to as a "pad," a "terminal electrode," an "external terminal," or the like. The pad electrode 91 in the anode pad region 11A constitutes the above-mentioned anode pad AP. The anode pad AP is a terminal to which an anode potential is applied from the outside. The anode pad AP may be referred to as an "anode pad electrode," an "anode terminal electrode," an "anode external terminal," or the like.

[0320] The anode pad AP is disposed on a portion of the dielectric film 46 that covers the plurality of capacitor structures 85, and forms a capacitive connection with the plurality of capacitor structures 85 via the dielectric film 46. In this embodiment, the anode pad AP is disposed on a portion of the dielectric film 46 that covers the capacitor electrode film 90, and forms a capacitive connection with the plurality of capacitor structures 85 and the capacitor electrode film 90 via the dielectric film 46.

[0321] The anode pad AP has a portion overlapping the multiple capacitor structures 85 and a portion overlapping the pad well region 80 (main surface insulating film 48) outside the multiple capacitor structures 85. The anode pad AP forms a capacitive connection with the capacitor electrode film 90 in both the portion overlapping the multiple capacitor structures 85 and the portion overlapping the pad well region 80 (main surface insulating film 48). As a result, the anode pad AP forms a capacitor C that functions as an anode capacitor structure CA together with the multiple capacitor structures 85 and the capacitor electrode film 90.

[0322] In this embodiment, the anode pad AP has a planar area smaller than that of the capacitor electrode film 90, and is disposed on an inner portion of the capacitor electrode film 90 with a space therebetween from the periphery (electrode side wall) of the capacitor electrode film 90. In other words, the anode pad AP has a periphery (electrode side wall) located inward from the periphery of the capacitor electrode film 90, and is surrounded by the periphery of the capacitor electrode film 90 in a plan view.

[0323] Of course, the anode pad AP may have a planar area larger than the planar area of ​​the capacitor electrode film 90. In this case, the periphery (electrode side wall) of the anode pad AP may be positioned outward from the periphery (electrode side wall) of the capacitor electrode film 90 and surround the capacitor electrode film 90.

[0324] In this embodiment, the anode pad AP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The anode pad AP may be formed in a hexagonal or circular shape in plan view.

[0325] The anode pad AP is mechanically and electrically connected to the anode wiring 75 on the dielectric film 46. As a result, the anode potential applied to the anode pad AP is applied to the temperature sensitive diode structure D via the anode wiring 75.

[0326] The anode pad AP may have a thickness greater than that of the interlayer film 57. The thickness of the anode pad AP is preferably greater than that of the capacitor electrode film 90. The thickness of the anode pad AP may be not less than 0.5 μm and not more than 10 μm.

[0327] The thickness of the anode pad AP may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0328] The anode pad AP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the dielectric film 46 side, similar to the emitter pad EP. The first electrode film 65 covers the dielectric film 46 in a film form as a barrier electrode. The first electrode film 65 is connected to the first electrode film 65 of the anode wiring 75 on the dielectric film 46.

[0329] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like shape. The second electrode film 66 is connected to the second electrode film 66 of the anode wiring 75 on the first electrode film 65.

[0330] 1, 3, etc., the monitor capacitor structure CM, like the anode capacitor structure CA, includes a plurality of capacitor structures 85, a main surface insulating film 48, a capacitor electrode film 90, a dielectric film 46, and a pad electrode 91. Like the plurality of capacitor structures 85 associated with the anode capacitor structure CA, the plurality of capacitor structures 85 associated with the monitor capacitor structure CM are drawn out from active regions 6 adjacent to each other in the first direction X (third active region 6C in this embodiment) to the monitor pad region 11M.

[0331] Of course, one or more capacitor structures 85 associated with the monitor capacitor structure CM may have one or more lead-out portions 85a extending in the second direction Y and be connected to one or more emitter structures 30 of active regions 6 (e.g., the third active region 6C) adjacent in the second direction Y. The configurations of the main surface insulating film 48, the capacitor electrode film 90, and the dielectric film 46 in the monitor region 7 are similar to the layout of the anode pad region 11A.

[0332] The pad electrode 91 in the monitor region 7 constitutes the above-mentioned monitor pad MP. The monitor pad MP is a terminal to which a monitor potential is applied from the outside. The monitor pad MP may be called a "monitor pad electrode," a "monitor terminal electrode," a "monitor external terminal," etc.

[0333] The monitor pad MP is disposed on a portion of the dielectric film 46 that covers the plurality of capacitor structures 85, and forms a capacitive connection with the plurality of capacitor structures 85 via the interlayer film 57 serving as a dielectric film. In this embodiment, the monitor pad MP is disposed on a portion of the interlayer film 57 that covers the capacitor electrode film 90, and forms a capacitive connection with the plurality of capacitor structures 85 and the capacitor electrode film 90 via the interlayer film 57 serving as a dielectric film.

[0334] The monitor pad MP has a portion overlapping the multiple capacitor structures 85 and a portion overlapping the pad well region 80 (main surface insulating film 48) outside the multiple capacitor structures 85. The monitor pad MP forms a capacitive connection with the capacitor electrode film 90 in both the portion overlapping the multiple capacitor structures 85 and the portion overlapping the pad well region 80 (main surface insulating film 48). As a result, the monitor pad MP forms a capacitor C that functions as a monitor capacitor structure CM together with the multiple capacitor structures 85 and the capacitor electrode film 90.

[0335] In this embodiment, the monitor pad MP has a planar area smaller than that of the capacitor electrode film 90, and is disposed on an inner portion of the capacitor electrode film 90 at a distance from the periphery (electrode sidewall) of the capacitor electrode film 90. In other words, the monitor pad MP has a periphery (electrode sidewall) located inward from the periphery of the capacitor electrode film 90, and is surrounded by the periphery of the capacitor electrode film 90 in a plan view.

[0336] Of course, the monitor pad MP may have a planar area larger than the planar area of ​​the capacitor electrode film 90. In this case, the periphery (electrode sidewall) of the monitor pad MP may be positioned outward from the periphery (electrode sidewall) of the capacitor electrode film 90 and surround the capacitor electrode film 90.

[0337] In this embodiment, the monitor pad MP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The monitor pad MP may be formed in a hexagonal or circular shape in plan view.

[0338] The monitor pad MP is disposed on the first side surface 5A side of the monitor electrode 67, and has an extraction portion that is extracted toward the monitor electrode 67. The extraction portion extends in a strip shape in the second direction Y, and is mechanically and electrically connected to the monitor electrode 67. As a result, a monitor potential applied to the monitor pad MP is applied to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40, and the plurality of contact regions 41 via the monitor electrode 67, the plurality of first emitter via electrodes 59, and the plurality of second emitter via electrodes 63.

[0339] The monitor pad MP may have a thickness greater than that of the dielectric film 46. The thickness of the monitor pad MP is preferably greater than that of the capacitor electrode film 90. The thickness range of the monitor pad MP is similar to that of the anode pad AP (not less than 0.5 μm and not more than 10 μm).

[0340] The monitor pad MP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the dielectric film 46 side, similar to the emitter pad EP. The first electrode film 65 covers the dielectric film 46 in a film shape as a barrier electrode. The first electrode film 65 is connected to the first electrode film 65 of the monitor electrode 67 on the interlayer film 57.

[0341] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 is connected to the second electrode film 66 of the monitor electrode 67 on the first electrode film 65.

[0342] Similar to the anode capacitor structure CA, the cathode capacitor structure CC includes a plurality of capacitor structures 85, a main surface insulating film 48, a capacitor electrode film 90, a dielectric film 46, and a pad electrode 91. Similar to the plurality of capacitor structures 85 related to the anode capacitor structure CA, the plurality of capacitor structures 85 related to the cathode capacitor structure CC are drawn out from active regions 6 adjacent to each other in the first direction X (first active regions 6A in this embodiment) to the cathode pad region 11C.

[0343] In this embodiment, the plurality of capacitor structures 85 associated with the cathode capacitor structure CC are connected to the plurality of capacitor structures 85 associated with the anode capacitor structure CA via the plurality of lead-out portions 85a. That is, the plurality of capacitor structures 85 associated with the cathode capacitor structure CC are connected to the plurality of emitter structures 30 of the active region 6 (the first active region 6A in this embodiment) via the plurality of capacitor structures 85 associated with the anode capacitor structure CA.

[0344] Of course, one or more capacitor structures 85 associated with the cathode capacitor structure CC may have one or more pull-out portions 85a extending in the second direction Y and be connected to one or more emitter structures 30 of an active region 6 (e.g., the second active region 6B) adjacent in the second direction Y.

[0345] The pad electrode 91 in the cathode pad region 11C constitutes the above-mentioned cathode pad CaP. The cathode pad CaP is a terminal to which a cathode potential is applied from the outside. The cathode pad CaP may be called a "cathode pad electrode," a "cathode terminal electrode," a "cathode external terminal," or the like.

[0346] The cathode pad CaP is disposed on a portion of the dielectric film 46 that covers the plurality of capacitor structures 85, and forms a capacitive connection with the plurality of capacitor structures 85 via the dielectric film 46. In this embodiment, the cathode pad CaP is disposed on a portion of the dielectric film 46 that covers the capacitor electrode film 90, and forms a capacitive connection with the plurality of capacitor structures 85 and the capacitor electrode film 90 via the dielectric film 46.

[0347] The cathode pad CaP has a portion overlapping the multiple capacitor structures 85 and a portion overlapping the pad well region 80 (main surface insulating film 48) outside the multiple capacitor structures 85. The cathode pad CaP forms a capacitive connection with the capacitor electrode film 90 in both the portion overlapping the multiple capacitor structures 85 and the portion overlapping the pad well region 80 (main surface insulating film 48). As a result, the cathode pad CaP forms a capacitor C that functions as a cathode capacitor structure CC together with the multiple capacitor structures 85 and the capacitor electrode film 90.

[0348] In this embodiment, the cathode pad CaP has a planar area smaller than that of the capacitor electrode film 90, and is disposed on an inner portion of the capacitor electrode film 90 with a space therebetween from the periphery (electrode sidewall) of the capacitor electrode film 90. In other words, the cathode pad CaP has a periphery (electrode sidewall) located inward from the periphery of the capacitor electrode film 90, and is surrounded by the periphery of the capacitor electrode film 90 in a plan view.

[0349] Of course, the cathode pad CaP may have a planar area larger than the planar area of ​​the capacitor electrode film 90. In this case, the periphery (electrode sidewall) of the cathode pad CaP may be positioned outward from the periphery (electrode sidewall) of the capacitor electrode film 90 and may surround the capacitor electrode film 90.

[0350] In this embodiment, the cathode pad CaP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The cathode pad CaP may be formed in a hexagonal or circular shape in plan view.

[0351] The cathode pad CaP is connected to the cathode wiring 76 on the dielectric film 46. As a result, the cathode potential applied to the cathode pad CaP is applied to the temperature sensitive diode structure D via the cathode wiring 76.

[0352] The cathode pad CaP may have a thickness greater than that of the dielectric film 46. The thickness of the cathode pad CaP is preferably greater than that of the capacitor electrode film 90. The thickness range of the cathode pad CaP is similar to the thickness range of the anode pad AP (not less than 0.5 μm and not more than 10 μm).

[0353] The cathode pad CaP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the dielectric film 46 side, similar to the emitter pad EP. The first electrode film 65 covers the dielectric film 46 in a film form as a barrier electrode. The first electrode film 65 is connected to the first electrode film 65 of the cathode wiring 76 on the dielectric film 46.

[0354] The second electrode film 66 has a thickness larger than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 is connected to the second electrode film 66 of the cathode wiring 76 on the first electrode film 65.

[0355] The semiconductor device 1A does not have a capacitor structure 85 and a capacitor electrode film 90 in the gate pad region 11G. In other words, the gate pad region 11G does not have a pad capacitor structure 84. This is because the capacitance value is guaranteed by the multiple gate structures 20 arranged in the multiple active regions 6.

[0356] The semiconductor device 1A includes a pad electrode 91 arranged on the dielectric film 46 in the gate pad region 11G. The pad electrode 91 in the gate pad region 11G constitutes the above-mentioned gate pad GP. The gate pad GP is a terminal to which a gate potential is applied from the outside. The gate pad GP may also be referred to as a "gate pad electrode," a "gate terminal electrode," a "gate external terminal," etc.

[0357] The gate pad GP faces the pad well region 80 with the main surface insulating film 48 and the dielectric film 46 sandwiched therebetween. The entire area of ​​the gate pad GP preferably faces the pad well region 80. The gate pad GP is connected to the multiple gate fingers 70 on the interlayer film 57. As a result, the gate potential applied to the gate pad GP is applied to the multiple gate structures 20 via the multiple gate wirings 56 and the multiple gate fingers 70.

[0358] In this embodiment, the gate pad GP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The gate pad GP may be formed in a hexagonal or circular shape in plan view.

[0359] The gate pad GP may have a thickness greater than that of the dielectric film 46. The thickness of the gate pad GP is preferably greater than that of the capacitor electrode film 90. The thickness range of the gate pad GP is similar to that of the anode pad AP (not less than 0.5 μm and not more than 10 μm).

[0360] The gate pad GP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the dielectric film 46 side, similar to the emitter pad EP. The first electrode film 65 covers the dielectric film 46 in a film form as a barrier electrode. The first electrode film 65 is connected to the first electrode films 65 of the multiple gate fingers 70 on the dielectric film 46.

[0361] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 is connected to the second electrode films 66 of the multiple gate fingers 70 on the first electrode film 65.

[0362] The semiconductor device 1A includes a collector pad CoP covering the second main surface 4. The collector pad CoP is a terminal to which a collector potential is applied from the outside. The collector pad CoP may be called a "collector pad electrode," a "collector terminal electrode," a "collector external terminal," or the like. The collector pad CoP is formed in the form of a film along the second main surface 4, and is electrically connected to the collector region 14.

[0363] The collector pad CoP covers, from the second main surface 4 side, the multiple active regions 6, the monitor region 7, the outer periphery region 8, the multiple street regions 9, the multiple temperature detection regions 10, and the multiple pad regions 11. The collector pad CoP may cover the entire second main surface 4. Of course, the collector pad CoP may be formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4, exposing the periphery (collector region 14) of the second main surface 4.

[0364] A breakdown voltage that can be applied between the emitter pad EP and the collector pad CoP (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or less and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0365] 18A to 18D are cross-sectional views showing a part of the manufacturing process of the semiconductor device 1A according to the first embodiment. Hereinafter, the manufacturing process of the anode capacitor structure CA in the manufacturing process of the semiconductor device 1A according to the first embodiment will be described with reference to FIGS.

[0366] To form the anode capacitor structure CA of the semiconductor device 1A, for example, referring to Fig. 18A, the pad well region 80 is selectively removed from the first main surface 3 of the chip 2. This forms a plurality of capacitor trenches 86 having bottoms in the middle of the pad well region 80 in the thickness direction of the chip 2. Next, the chip 2 is subjected to a thermal oxidation treatment, whereby a capacitor insulating film 87 covering the wall surfaces of the capacitor trenches 86 and a main surface insulating film 48 covering the first main surface 3 are integrally formed.

[0367] 18B , a conductive material film 89 that will become the capacitor buried electrode 88 and the capacitor electrode film 90 is deposited on the first main surface 3 by, for example, a CVD method. The deposition of the conductive material film 89 is continued until the capacitor trench 86 is backfilled and the first main surface 3 is covered and hidden by the conductive material film 89.

[0368] 18C, the chip 2 is subjected to a thermal oxidation process, whereby oxidation of the conductive material film 89 (polysilicon) progresses in a direction from the upper surface of the conductive material film 89 toward the first main surface 3 and the conductive material film 89 is transformed into silicon oxide, forming the first film 53 of the dielectric film 46. In other words, the first film 53 is a film obtained by the thermal oxidation process of the conductive material film 89. After the thermal oxidation process, the portion of the conductive material film 89 remaining on the first main surface 3 becomes the capacitor electrode film 90, and the portion of the conductive material film 89 remaining in the capacitor trench 86 becomes the capacitor buried electrode 88.

[0369] 18D, a nitride material is deposited in a film shape on the first film 53 by, for example, a CVD method. This forms a second film 54, and a dielectric film 46 having a two-layer structure of the first film 53 and the second film 54 is formed. Through the above steps, it is possible to form up to the dielectric film 46 of the anode capacitor structure CA described above.

[0370] Other layout examples of the capacitor structure 85 are shown below. Figures 19A to 19M are plan views showing capacitor structures 85 according to second to fourteenth layout examples. Each of the multiple pad capacitor structures 84 may include at least one of the capacitor structures 85 according to the second to fourteenth layout examples instead of or in addition to the capacitor structure 85 according to the first layout example.

[0371] That is, the monitor capacitor structure CM may include at least one of the capacitor structures 85 according to the first to fourteenth layout examples in the monitor pad region 11M. The anode capacitor structure CA may include at least one of the capacitor structures 85 according to the first to fourteenth layout examples in the anode pad region 11A.

[0372] The cathode capacitor structure CC may include at least one of the capacitor structures 85 according to the first to fourteenth layout examples in the cathode pad region 11C. The monitor capacitor structure CM, the anode capacitor structure CA, and the cathode capacitor structure CC do not necessarily have to have the capacitor structure 85 according to the same layout example, and may have the capacitor structures 85 according to different layout examples.

[0373] 19A (second layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the first direction X, and one second capacitor structure 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0374] Each of the first capacitor structures 85A has a base end on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0375] The second capacitor structure 85B extends in a band shape in the second direction Y and is connected to the tip ends of the multiple first capacitor structures 85A. That is, the multiple capacitor structures 85 form one comb-shaped capacitor structure 85 in a plan view. Of course, the second capacitor structure 85B may be connected to regions on the base end side of the multiple first capacitor structures 85A.

[0376] 19B (third layout example), pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in a first direction X, and a plurality of second capacitor structures 85B extending in a second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0377] Each of the first capacitor structures 85A has a base end on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0378] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the first direction X. One second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the tip ends of the first capacitor structures 85A. The other second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the region on the base end side of the first capacitor structures 85A. That is, the capacitor structures 85 form one ladder-shaped capacitor structure 85 in a plan view.

[0379] 19C (fourth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the first direction X, and a plurality of second capacitor structures 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0380] Each of the first capacitor structures 85A has a base end on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0381] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the first direction X. One of the second capacitor structures 85B is formed at intervals in the second direction Y and is respectively connected to the tip ends of the first capacitor structures 85A (two in this embodiment) adjacent to each other in the second direction Y.

[0382] The other plurality of second capacitor structures 85B are formed at intervals in the second direction Y so as to face the one of the plurality of second capacitor structures 85B in the first direction X in a one-to-one correspondence, and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent in the second direction Y. In other words, the plurality of capacitor structures 85 form a plurality of annular (quadratic annular) capacitor structures 85 extending in the first direction X in a plan view.

[0383] 19D (fifth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in a first direction X, and a plurality of second capacitor structures 85B extending in a second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0384] Each of the first capacitor structures 85A has a base end on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0385] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the first direction X. One of the second capacitor structures 85B is formed at intervals in the second direction Y and is respectively connected to the tip ends of the first capacitor structures 85A (two in this embodiment) adjacent to each other in the second direction Y.

[0386] The other plurality of second capacitor structures 85B are arranged shifted in the second direction Y with respect to one of the plurality of second capacitor structures 85B so as to face the one of the two second capacitor structures 85B in the first direction X. The other plurality of second capacitor structures 85B are formed spaced apart in the second direction Y and are respectively connected to regions on the base end side of the multiple (two in this embodiment) first capacitor structures 85A adjacent to each other in the second direction Y.

[0387] That is, the multiple capacitor structures 85 constitute one zigzag-shaped capacitor structure 85 having a portion extending in the first direction X and a portion extending in the second direction Y in a plan view. One end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a. The other end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a.

[0388] 18E (sixth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. The plurality of capacitor structures 85 has a layout in which the extension direction of the capacitor structures 85 in the first layout example is changed from the first direction X to the second direction Y. That is, the plurality of capacitor structures 85 extend in a stripe shape in the second direction Y. In this embodiment, the extension direction of the plurality of capacitor structures 85 intersects (specifically, is perpendicular to) the extension direction of the plurality of gate structures 20 (the plurality of emitter structures 30).

[0389] In this embodiment, the lead-out portions 85a of the multiple capacitor structures 85 extend in the second direction Y and are led out from the anode pad region 11A to one or more active regions 6. The multiple lead-out portions 85a are connected to the multiple emitter structures 30 in the one or more active regions 6, respectively. The multiple lead-out portions 85a may be connected to the multiple emitter connection structures 35 in the one or more active regions 6. The multiple lead-out portions 85a may have a portion extending in the first direction X in a region outside the anode pad region 11A.

[0390] 19F (seventh layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the second direction Y, and one second capacitor structure 85B extending in the first direction X, similar to the sixth layout example. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0391] Each of the first capacitor structures 85A has a tip portion on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base portion on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0392] The second capacitor structure 85B extends in a band shape in the first direction X, and is connected to the tip ends of the multiple first capacitor structures 85A. That is, the multiple capacitor structures 85 form one comb-shaped capacitor structure 85 in a plan view. Of course, the second capacitor structure 85B may be connected to regions on the base end side of the multiple second capacitor structures 85B.

[0393] 19G (eighth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X, similar to the sixth layout example. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0394] Each of the first capacitor structures 85A has a tip portion on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base portion on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0395] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the second direction Y. One second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the tip ends of the first capacitor structures 85A. The other second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the region on the base end side of the first capacitor structures 85A. That is, the capacitor structures 85 form one ladder-shaped capacitor structure 85 in a plan view.

[0396] 19H (ninth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X, similar to the sixth layout example. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0397] Each of the first capacitor structures 85A has a tip portion on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base portion on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0398] The multiple second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the multiple first capacitor structures 85A in the second direction Y. One of the multiple second capacitor structures 85B is formed at intervals in the first direction X and is respectively connected to the tip ends of the multiple (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X.

[0399] The other plurality of second capacitor structures 85B are formed at intervals in the first direction X so as to face the one of the plurality of first capacitor structures 85A in a one-to-one correspondence in the second direction Y, and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent in the first direction X. In other words, the plurality of capacitor structures 85 form a plurality of annular (quadratic annular) capacitor structures 85 extending in the second direction Y in a plan view.

[0400] 19I (tenth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X, similar to the sixth layout example. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0401] Each of the first capacitor structures 85A has a tip portion on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base portion on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrode 91 (anode pad AP).

[0402] The multiple second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the multiple first capacitor structures 85A in the second direction Y. One of the multiple second capacitor structures 85B is formed at intervals in the first direction X and is respectively connected to the tip ends of the multiple (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X.

[0403] The other plurality of second capacitor structures 85B are arranged shifted in the first direction X with respect to the plurality of second capacitor structures 85B so as to face the two second capacitor structures 85B on one side in the second direction Y. The other plurality of second capacitor structures 85B are formed spaced apart in the first direction X and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X.

[0404] That is, the multiple capacitor structures 85 constitute one zigzag-shaped capacitor structure 85 having a portion extending in the first direction X and a portion extending in the second direction Y in a plan view. One end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a. The other end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a.

[0405] 19J (an eleventh layout example), a pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. The plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in a first direction X, and a plurality of second capacitor structures 85B extending in a second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead-out portions 85a. Of course, the plurality of second capacitor structures 85B may also have a plurality of lead-out portions 85a.

[0406] The multiple second capacitor structures 85B are each disposed in a region between multiple first capacitor structures 85A adjacent to each other in the second direction Y, and are arranged at intervals in the first direction X. The multiple second capacitor structures 85B disposed on one side in the second direction Y of one first capacitor structure 85A respectively face the multiple second capacitor structures 85B disposed on the other side in the second direction Y of one first capacitor structure 85A in a one-to-one correspondence.

[0407] The second capacitor structures 85B form a plurality of crosses with the first capacitor structures 85A, and define a plurality of mesa portions arranged in a matrix in the first direction X and the second direction Y. In other words, the capacitor structures 85 constitute one capacitor structure 85 extending in a lattice (mesh) shape along the first direction X and the second direction Y in a plan view.

[0408] 19K (twelfth layout example), the pad capacitor structure 84 includes a plurality of capacitor structures 85, similar to the first layout example. The plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the first direction X, and a plurality of second capacitor structures 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead-out portions 85a. Of course, the plurality of second capacitor structures 85B may also have a plurality of lead-out portions 85a.

[0409] The multiple second capacitor structures 85B are each disposed in a region between multiple first capacitor structures 85A adjacent to each other in the second direction Y, and are arranged at intervals in the first direction X. The multiple second capacitor structures 85B disposed on one side in the second direction Y of one first capacitor structure 85A each face, in a one-to-one correspondence, a region between multiple second capacitor structures 85B disposed on the other side in the second direction Y of one first capacitor structure 85A.

[0410] The second capacitor structures 85B form a plurality of T-junctions with the first capacitor structures 85A, and define a plurality of mesa portions arranged in a staggered pattern in the first direction X and the second direction Y. In other words, the capacitor structures 85 constitute one capacitor structure 85 extending in a staggered pattern (mesh pattern) along the first direction X and the second direction Y in a plan view.

[0411] 19L (a thirteenth layout example), a pad capacitor structure 84 includes a single capacitor structure 85 formed in a spiral shape in a plan view. In this embodiment, the capacitor structure 85 is formed in a polygonal spiral shape (a square spiral shape in this embodiment) and has a plurality of portions extending in a first direction X and a plurality of portions extending in a second direction Y. The capacitor structure 85 may also be formed in a hexagonal spiral shape, a circular spiral shape, or the like.

[0412] An outer end of the spiral capacitor structure 85 is electrically connected to one or more emitter structures 30 via an extension portion 85a. The extension portion 85a may be extended in a first direction X or may be extended in a second direction Y.

[0413] 19M (a fourteenth layout example), the pad capacitor structure 84 may include two or more layout regions 92. For example, the number of layout regions 92 may be ten or less. In this embodiment, the pad capacitor structure 84 includes, as an example, four layout regions 92.

[0414] The multiple layout regions 92 may be arranged in a line in the first direction X. The multiple layout regions 92 may be arranged in a line in the second direction Y. The multiple layout regions 92 may be arranged in a matrix along the first direction X and the second direction Y. The multiple layout regions 92 may have substantially the same planar area as each other, or may have different planar areas as each other.

[0415] The pad capacitor structure 84 includes a plurality of capacitor structures 85 formed in a plurality of layout regions 92 at intervals from each other. The plurality of capacitor structures 85 may have the same layout or different layouts. Each of the plurality of capacitor structures 85 may have any one of the first to fourteenth layout examples. The plurality of capacitor structures 85 formed in adjacent layout regions 92 may be mechanically and electrically connected to each other.

[0416] An example of an electrical test performed on the semiconductor device 1A is shown below. Fig. 20 is a plan view explaining an electrical test on the gate pad GP side. Fig. 21 is a plan view explaining an electrical test on the monitor pad MP side. Fig. 22 is a plan view explaining an electrical test on the anode pad AP side. Fig. 23 is a plan view explaining an electrical test on the cathode pad CaP side.

[0417] The electrical test is a human body model (HBM) ESD (Electro Static Discharge) tolerance measurement test for the semiconductor device 1A (plurality of pad electrodes 91). The HBM is a model that assumes that ESD occurs between the human body and the plurality of pad electrodes 91.

[0418] 20, in the test on the gate pad GP side, a predetermined first test voltage V1 is applied between the emitter pad EP and the gate pad GP. Various values ​​are adopted for the first test voltage V1 according to the specifications of the semiconductor device 1A. The first test voltage V1 is typically 500V or more and 8000V or less.

[0419] When the first test voltage V1 is applied, a predetermined test current is generated in the emitter pad EP and the gate pad GP, and the ESD resistance between the emitter pad EP and the gate pad GP is measured. A relatively high capacitance value is guaranteed between the emitter pad EP and the gate pad GP by the multiple gate structures 20, so that a relatively high ESD resistance is achieved.

[0420] 21, in a test on the monitor pad MP side, a predetermined second test voltage V2 is applied between the emitter pad EP and the monitor pad MP. The second test voltage V2 may be applied between the gate pad GP and the monitor pad MP. Various values ​​are adopted for the second test voltage V2 depending on the specifications of the semiconductor device 1A. The second test voltage V2 is typically 500V or more and 8000V or less.

[0421] When the second test voltage V2 is applied, a predetermined test current is generated in the emitter pad EP and the monitor pad MP, and the ESD resistance between the emitter pad EP and the monitor pad MP is measured.

[0422] In the monitor region 7, the number of gate structures 20 formed is less than the number of gate structures 20 associated with the active regions 6. That is, the capacitance value associated with the gate structures 20 in the monitor region 7 is lower than the capacitance value associated with the gate structures 20 in the active regions 6. Therefore, the ESD resistance between the emitter pad EP and the monitor pad MP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0423] In this regard, in the semiconductor device 1A, the monitor capacitor structure CM (capacitor C) is formed in the monitor pad region 11M, and the capacitance value between the emitter pad EP and the monitor pad MP is complemented by the monitor capacitor structure CM. This improves the ESD resistance compared to the case where the monitor capacitor structure CM does not exist in the monitor pad region 11M.

[0424] 22, in the test on the anode pad AP side, a predetermined third test voltage V3 is applied between the emitter pad EP and the anode pad AP. The third test voltage V3 may be applied between the gate pad GP and the anode pad AP. Various values ​​are adopted for the third test voltage V3 depending on the specifications of the semiconductor device 1A. The third test voltage V3 is typically 500V or more and 8000V or less.

[0425] When the third test voltage V3 is applied, a predetermined test current is generated in the emitter pad EP and the anode pad AP, and the ESD resistance between the emitter pad EP and the anode pad AP is measured. The gate structure 20 is not electrically interposed in the region between the emitter pad EP and the anode pad AP. Therefore, the ESD resistance between the emitter pad EP and the anode pad AP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0426] In this regard, in the semiconductor device 1A, the anode capacitor structure CA (capacitor C) is formed in the anode pad region 11A, and the capacitance between the emitter pad EP and the anode pad AP is complemented by the anode capacitor structure CA. This increases the ESD resistance compared to a case where the anode capacitor structure CA does not exist in the anode pad region 11A.

[0427] 23, in the test on the cathode pad CaP side, a predetermined fourth test voltage V4 is applied between the emitter pad EP and the cathode pad CaP. The fourth test voltage V4 may be applied between the gate pad GP and the cathode pad CaP. Various values ​​are adopted for the fourth test voltage V4 depending on the specifications of the semiconductor device 1A. The fourth test voltage V4 is typically 500V or more and 8000V or less.

[0428] When the fourth test voltage V4 is applied, a predetermined test current is generated in the emitter pad EP and the cathode pad CaP, and the ESD resistance between the emitter pad EP and the cathode pad CaP is measured. The gate structure 20 is not electrically interposed in the region between the emitter pad EP and the cathode pad CaP. Therefore, the ESD resistance between the emitter pad EP and the cathode pad CaP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0429] In this regard, in the semiconductor device 1A, a cathode capacitor structure CC (capacitor C) is formed in the cathode pad CaP, and the capacitance between the emitter pad EP and the cathode pad CaP is complemented by the cathode capacitor structure CC. This increases the ESD resistance compared to a case where the cathode capacitor structure CC does not exist in the cathode pad CaP.

[0430] As described above, the semiconductor device 1A may include the chip 2, the trench electrode type capacitor structure 85, the dielectric film 46, and the pad electrode 91. The chip 2 may have a first main surface 3. The capacitor structure 85 may be formed on the first main surface 3. A first potential may be applied to the capacitor structure 85.

[0431] The dielectric film 46 may cover the capacitor structure 85 on the first main surface 3. The pad electrode 91 may be disposed on the dielectric film 46 and form a capacitive connection with the capacitor structure 85 via the interlayer film 57. A second potential different from the first potential may be applied to the pad electrode 91.

[0432] This configuration provides the semiconductor device 1A with improved electrical characteristics. Specifically, in the semiconductor device 1A, the capacitance associated with the pad electrode 91 is increased by the capacitor structure 85, and as a result, the ESD resistance is improved.

[0433] The first potential may be a potential other than the gate potential. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor structure 85 to which a potential other than the gate potential is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor structure 85 to which a potential other than the gate potential is applied.

[0434] The first potential may be a reference potential that is a reference for circuit operation. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor structure 85 to which a potential other than the reference potential is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor structure 85 to which a potential other than the reference potential is applied.

[0435] The first potential may be an emitter potential. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor structure 85 to which the emitter potential is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor structure 85 to which the emitter potential is applied.

[0436] The second potential may be a potential other than the gate potential. According to this configuration, the pad electrode 91 to which a potential other than the gate potential is applied forms a capacitive connection with the capacitor structure 85. As a result, the capacitance value associated with the pad electrode 91 to which a potential other than the gate potential is applied can be improved by the capacitor structure 85.

[0437] The second potential may be a potential other than the reference potential that is the reference for circuit operation. According to this configuration, the pad electrode 91 to which a potential other than the reference potential is applied forms a capacitive connection with the capacitor structure 85. As a result, the capacitance value associated with the pad electrode 91 to which a potential other than the reference potential is applied can be improved by the capacitor structure 85.

[0438] The second potential may be a potential other than the emitter potential. According to this configuration, the pad electrode 91 to which a potential other than the emitter potential is applied forms a capacitive connection with the capacitor structure 85. As a result, the capacitance value associated with the pad electrode 91 to which a potential other than the emitter potential is applied can be improved by the capacitor structure 85.

[0439] The semiconductor device 1A may include an active region 6, a pad region 11, and a transistor structure T3. The active region 6 may be provided on the first main surface 3. The pad region 11 may be provided in a region outside the active region 6 on the first main surface 3. The transistor structure T3 may be formed in the active region 6.

[0440] In this case, the capacitor structure 85 may be formed on the first main surface 3 in the pad region 11. The dielectric film 46 may cover the capacitor structure 85 in the pad region 11. The pad electrode 91 may be disposed on the dielectric film 46 in the pad region 11. According to this configuration, the capacitance value associated with the pad electrode 91 can be improved by the capacitor structure 85 in the pad region 11 outside the active region 6 (transistor structure T3).

[0441] The first potential may be a potential for the transistor structure T3. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor structure 85 to which the potential for the transistor structure T3 is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor structure 85 to which a potential other than the gate potential is applied.

[0442] The second potential may be a potential other than the potential for the transistor structure T3. According to this configuration, the pad electrode 91 to which a potential other than the potential for the transistor structure T3 is applied forms a capacitive connection with the capacitor structure 85. As a result, the capacitance value associated with the pad electrode 91 to which a potential other than the potential for the transistor structure T3 is applied can be improved by the capacitor structure 85.

[0443] The transistor structure T3 may include a trench electrode type gate structure 20 to which a gate potential is applied. The capacitor structure 85 may be electrically isolated from the gate structure 20. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor structure 85 electrically isolated from the gate structure 20. As a result, the capacitance value associated with the pad electrode 91 can be improved by the capacitor structure 85 electrically isolated from the gate structure 20.

[0444] The transistor structure T3 may include a trench electrode type emitter structure 30 to which an emitter potential is applied. The capacitor structure 85 may be electrically connected to the emitter structure 30. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor structure 85 electrically connected to the emitter structure 30. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor structure 85 electrically connected to the emitter structure 30. In this case, the capacitor structure 85 may be connected to the emitter structure 30.

[0445] The semiconductor device 1A may include a temperature detection region 10 as a diode region, and a temperature sensing diode structure D as a diode structure. The temperature detection region 10 may be provided in a region outside the active region 6 on the first main surface 3. The temperature sensing diode structure D may be formed in the temperature detection region 10.

[0446] In such a configuration, the pad region 11 may be provided in a region outside the active region 6 and the temperature detection region 10. A potential for the temperature sensitive diode structure D may be applied to the pad electrode 91. According to this configuration, the pad electrode 91 to which the potential for the temperature sensitive diode structure D is applied forms a capacitive connection with the capacitor structure 85. As a result, the capacitance value associated with the pad electrode 91 to which the potential for the temperature sensitive diode structure D is applied can be improved by the capacitor structure 85.

[0447] The semiconductor device 1A may include an anode wiring 75. The anode wiring 75 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the pad electrode 91 may be electrically connected to the anode wiring 75 and apply an anode potential to the temperature sensitive diode structure D via the anode wiring 75. According to this configuration, the capacitance value associated with the pad electrode 91 to which the anode potential is applied can be improved by the capacitor structure 85.

[0448] The semiconductor device 1A may include a cathode wiring 76. The cathode wiring 76 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the pad electrode 91 may be electrically connected to the cathode wiring 76 and apply a cathode potential to the temperature sensitive diode structure D via the cathode wiring 76. According to this configuration, the capacitance value associated with the pad electrode 91 to which the cathode potential is applied can be improved by the capacitor structure 85.

[0449] The semiconductor device 1A may include a monitor region 7 and a monitor transistor structure T2 for monitoring a current. The monitor region 7 may be provided in a region outside the active region 6 on the first main surface 3. The monitor transistor structure T2 may be formed in the monitor region 7.

[0450] In such a configuration, the pad region 11 may be provided in a region outside the active region 6 and the monitor region 7. A potential for the monitor transistor structure T2 may be applied to the pad electrode 91. According to this configuration, the pad electrode 91 to which the potential for the monitor transistor structure T2 is applied forms a capacitive connection with the capacitor structure 85. As a result, the capacitance value associated with the pad electrode 91 to which the potential for the monitor transistor structure T2 is applied can be improved by the capacitor structure 85.

[0451] The semiconductor device 1A may include a monitor electrode 67. The monitor electrode 67 may be electrically connected to the monitor transistor structure T2 on the first main surface 3 of the monitor region 7. In this case, the pad electrode 91 may be electrically connected to the monitor electrode 67 and apply a potential to the monitor transistor structure T2 via the monitor electrode 67.

[0452] The semiconductor device 1A may include a capacitor electrode film 90. The capacitor electrode film 90 may be disposed on the first main surface 3 and electrically connected to the capacitor structure 85. In this configuration, the dielectric film 46 may cover the capacitor electrode film 90. The pad electrode 91 may form a capacitive connection with the capacitor electrode film 90 via the dielectric film 46. According to this semiconductor device 1A, the capacitance value associated with the pad electrode 91 can be improved by the capacitor structure 85 and the capacitor electrode film 90.

[0453] The capacitor electrode film 90 may be made of a conductor other than a metal. With this configuration, the capacitance associated with the pad electrode 91 can be improved by the capacitor electrode film 90 made of a conductor other than a metal.

[0454] The capacitor structure 85 may include a capacitor trench 86, a capacitor insulating film 87, and a capacitor buried electrode 88. The capacitor trench 86 may be formed on the first main surface 3. The capacitor insulating film 87 may cover a wall surface of the capacitor trench 86. The capacitor buried electrode 88 may be buried in the capacitor trench 86 with the capacitor insulating film 87 sandwiched therebetween.

[0455] In this configuration, the capacitor electrode film 90 may include the same type of conductor as the capacitor buried electrode 88, and may be formed integrally with the capacitor buried electrode 88. According to this configuration, the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90 that is integral with the capacitor buried electrode 88.

[0456] The semiconductor device 1A may include an n-type drift region 12 (semiconductor region) and a p-type pad well region 80. The drift region 12 may be formed in the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 and electrically connected to the drift region 12. In this case, the capacitor structure 85 may be disposed in the pad well region 80.

[0457] According to this configuration, a depletion layer spreads from the pn junction between the drift region 12 and the pad well region 80. This improves the breakdown voltage in the pad region 11. In addition, the capacitance associated with the pad electrode 91 can be improved by the capacitor structure 85 disposed in the pad well region 80.

[0458] The capacitor structure 85 may be located in the pad well region 80 at a distance from the bottom of the pad well region 80 toward the first main surface 3. With this configuration, the breakdown voltage in the pad region 11 can be appropriately improved.

[0459] From another perspective, the semiconductor device 1A may include a chip 2, a pad region 11, a capacitor electrode film 90, a dielectric film 46, and a pad electrode 91. The chip 2 may have a first main surface 3. The pad region 11 may be provided on the first main surface 3. The capacitor electrode film 90 may be formed on the first main surface 3 in the pad region 11. A first potential may be applied to the capacitor electrode film 90.

[0460] The dielectric film 46 may cover the capacitor electrode film 90 on the first main surface 3 in the pad region 11. The pad electrode 91 may be disposed on the dielectric film 46 in the pad region 11 and form a capacitive connection with the capacitor electrode film 90 via the dielectric film 46. A second potential different from the first potential may be applied to the pad electrode 91.

[0461] This configuration provides the semiconductor device 1A with improved electrical characteristics. Specifically, in the semiconductor device 1A, the capacitance associated with the pad electrode 91 is increased by the capacitor electrode film 90, and as a result, the ESD resistance is improved.

[0462] The capacitor electrode film 90 may be made of a conductor other than a metal. With this configuration, the capacitance associated with the pad electrode 91 can be improved by the capacitor electrode film 90 made of a conductor other than a metal.

[0463] The first potential may be a reference potential that serves as a reference for circuit operation. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor electrode film 90 to which a potential other than the reference potential is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor electrode film 90 to which a potential other than the reference potential is applied.

[0464] The second potential may be a potential other than the reference potential that is the reference for circuit operation. According to this configuration, the pad electrode 91 to which a potential other than the reference potential is applied forms a capacitive connection with the capacitor electrode film 90. As a result, the capacitance value associated with the capacitor electrode film 90 to which a potential other than the reference potential is applied can be improved by the capacitor electrode film 90.

[0465] The semiconductor device 1A may include a temperature detection region 10 as a diode region, and a temperature sensing diode structure D as a diode. The temperature detection region 10 may be provided on the first main surface 3. The temperature sensing diode structure D may be formed in the temperature detection region 10. In this case, the pad region 11 may be provided in a region outside the temperature detection region 10 on the first main surface 3.

[0466] In this case, the first potential may be a potential other than the potential for the temperature sensitive diode structure D. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor electrode film 90 to which a potential other than the potential for the temperature sensitive diode structure D is applied. As a result, the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90 to which a potential other than the potential for the temperature sensitive diode structure D is applied.

[0467] The second potential may be a potential for the temperature sensitive diode structure D. According to this configuration, the pad electrode 91 to which the potential for the temperature sensitive diode structure D is applied forms a capacitive connection with the capacitor electrode film 90. As a result, the capacitance value associated with the capacitor electrode film 90 to which the potential for the temperature sensitive diode structure D is applied can be improved by the capacitor electrode film 90.

[0468] The semiconductor device 1A may include a monitor region 7 and a monitor transistor structure T2 as a current monitor. The monitor region 7 may be provided on the first main surface 3. The monitor transistor structure T2 may be formed in the monitor region 7. In this case, the pad region 11 may be provided in a region outside the monitor region 7 on the first main surface 3.

[0469] In this case, the first potential may be a potential other than the potential for the monitor transistor structure T2. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor electrode film 90 to which a potential other than the potential for the monitor transistor structure T2 is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor electrode film 90 to which a potential other than the potential for the monitor transistor structure T2 is applied.

[0470] The second potential may be a potential for the monitor transistor structure T2. According to this configuration, the pad electrode 91 to which the potential for the monitor transistor structure T2 is applied forms a capacitive connection with the capacitor electrode film 90. As a result, the capacitance value associated with the capacitor electrode film 90 to which the potential for the monitor transistor structure T2 is applied can be improved by the capacitor electrode film 90.

[0471] The semiconductor device 1A may include an n-type drift region 12 (semiconductor region), a p-type pad well region 80, and a main surface insulating film 48. The drift region 12 may be formed in the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11, and may be electrically connected to the drift region 12. The main surface insulating film 48 may cover the pad well region 80 on the first main surface 3 in the pad region 11.

[0472] In this case, the capacitor electrode film 90 may face the pad well region 80 with the main surface insulating film 48 interposed therebetween. With this configuration, a depletion layer spreads from the pn junction between the drift region 12 and the pad well region 80. This improves the breakdown voltage in the pad region 11. In addition, the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90 facing the pad well region 80.

[0473] The semiconductor device 1A may include a trench electrode type capacitor structure 85. The capacitor structure 85 may be formed on the first main surface 3 in the pad region 11. In this case, the capacitor electrode film 90 may cover the capacitor structure 85 on the first main surface 3 and be electrically connected to the capacitor structure 85.

[0474] The pad electrode 91 may form a capacitive connection with the capacitor structure 85 and the capacitor electrode film 90 via the dielectric film 46 in the pad region 11. According to this configuration, the capacitance associated with the pad electrode 91 can be improved by the capacitor structure 85 and the capacitor electrode film 90.

[0475] In such a configuration, the semiconductor device 1A may include an n-type drift region 12 (semiconductor region) and a p-type pad well region 80. The drift region 12 may be formed in the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11, and may be electrically connected to the drift region 12. In this case, the capacitor structure 85 may be disposed in the pad well region 80.

[0476] According to this configuration, a depletion layer spreads from the pn junction between the drift region 12 and the pad well region 80. This improves the breakdown voltage in the pad region 11. In addition, the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90 disposed in the pad well region 80.

[0477] The capacitor structure 85 may be located in the pad well region 80 at a distance from the bottom of the pad well region 80 toward the first main surface 3. With this configuration, the breakdown voltage in the pad region 11 can be appropriately improved.

[0478] The semiconductor device 1A may include an active region 6 and a transistor structure T3 (transistor). The active region 6 may be provided on the first main surface 3. The transistor structure T3 may be formed on the first main surface 3 of the active region 6. In this case, the pad region 11 may be provided in a region outside the active region 6 on the first main surface 3. According to this configuration, in a configuration having the active region 6 (transistor structure T3), the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90.

[0479] The first potential may be a potential for the transistor structure T3. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor electrode film 90 to which the potential for the transistor structure T3 is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor electrode film 90 to which the potential for the transistor structure T3 is applied.

[0480] The second potential may be a potential for the transistor structure T3. According to this configuration, the pad electrode 91 to which the potential for the transistor structure T3 is applied forms a capacitive connection with the capacitor electrode film 90. As a result, the capacitance value associated with the capacitor electrode film 90 to which the potential for the transistor structure T3 is applied can be improved by the capacitor electrode film 90.

[0481] The first potential may be a potential other than the gate potential. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor electrode film 90 to which a potential other than the gate potential is applied. This allows the capacitance value associated with the pad electrode 91 to be improved by the capacitor electrode film 90 to which a potential other than the gate potential is applied.

[0482] The second potential may be a potential other than the gate potential. According to this configuration, the pad electrode 91 to which a potential other than the gate potential is applied forms a capacitive connection with the capacitor electrode film 90. As a result, the capacitance value associated with the capacitor electrode film 90 to which a potential other than the gate potential is applied can be improved by the capacitor electrode film 90.

[0483] The transistor structure T3 may include a trench electrode type emitter structure 30 (trench structure). A first potential may be applied to the emitter structure 30. According to this configuration, the pad electrode 91 forms a capacitive connection with the capacitor electrode film 90 to which the potential for the emitter structure 30 is applied. As a result, the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90 to which the potential for the emitter structure 30 is applied.

[0484] In such a configuration, the semiconductor device 1A may include a trench electrode type capacitor structure 85. The capacitor structure 85 may be formed on the first main surface 3 in the pad region 11. In this case, the capacitor electrode film 90 may be electrically connected to the capacitor structure 85 on the first main surface 3 in the pad region 11.

[0485] The pad electrode 91 may form a capacitive connection with the capacitor structure 85 and the capacitor electrode film 90 via the dielectric film 46 in the pad region 11. According to this configuration, the capacitance associated with the pad electrode 91 can be improved by the capacitor structure 85 and the capacitor electrode film 90.

[0486] In such a configuration, the capacitor structure 85 may be extended from the pad region 11 to the active region 6, and connected to the emitter structure 30 in the active region 6. According to this configuration, a potential applied to the emitter structure 30 can be transmitted to the capacitor electrode film 90 via the capacitor structure 85.

[0487] As a result, the capacitance value associated with the pad electrode 91 can be appropriately improved by the capacitor structure 85 and the capacitor electrode film 90. In addition, the potential applied to the emitter structure 30 can be transmitted to the capacitor electrode film 90 via the capacitor structure 85, which serves as a wiring structure located below the height position of the first main surface 3.

[0488] In such a configuration, the semiconductor device 1A may include an n-type drift region 12 (semiconductor region) and a p-type pad well region 80. The drift region 12 may be formed in the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11, and may be electrically connected to the drift region 12. In this case, the capacitor structure 85 may be disposed in the pad well region 80.

[0489] According to this configuration, a depletion layer spreads from the pn junction between the drift region 12 and the pad well region 80. This improves the breakdown voltage in the pad region 11. In addition, the capacitance value associated with the pad electrode 91 can be improved by the capacitor electrode film 90 disposed in the pad well region 80.

[0490] In such a configuration, the transistor structure T3 may include a p-type base region 15. The base region 15 may be formed in a surface layer portion of the first main surface 3 of the active region 6 and electrically connected to the drift region 12. In this case, the emitter structure 30 may penetrate the base region 15.

[0491] The pad well region 80 may be formed deeper than the base region 15. The capacitor structure 85 may be located in the pad well region 80 at a distance from the bottom of the pad well region 80 toward the first main surface 3. With this configuration, the breakdown voltage in the pad region 11 can be appropriately improved.

[0492] Fig. 24 and Fig. 25 are cross-sectional views of a semiconductor device 1B according to the second embodiment. More specifically, Fig. 24 is a cross-section of the same portion of the configuration in the pad region 11 of the semiconductor device 1B as Fig. 16, and shows the cross-sectional structure of an anode capacitor structure CA of the semiconductor device 1B. Fig. 25 is a cross-section of the same portion of the configuration in the pad region 11 of the semiconductor device 1B as Fig. 17, and shows the cross-sectional structure of an anode capacitor structure CA of the semiconductor device 1B.

[0493] Similar to the semiconductor device 1A, the semiconductor device 1B includes a plurality of pad capacitor structures 84 formed in a plurality of pad regions 11. In Figures 24 and 25, an anode capacitor structure CA is shown as an example of the plurality of pad capacitor structures 84.

[0494] In the anode capacitor structure CA of the semiconductor device 1B, the electrode portion of the capacitor structure 85 does not include a capacitor electrode film 90, but is formed by a plurality of capacitor buried electrodes 88. Unlike the configuration in Fig. 16, the plurality of capacitor buried electrodes 88 are not integrally conductive in the upper region of the capacitor trench 86, but are buried in each of the plurality of capacitor trenches 86 while being physically separated from one another.

[0495] The first film 53 of the dielectric film 46 is also formed as the main surface insulating film 48 , and covers the upper surfaces of the multiple buried capacitor electrodes 88 collectively.

[0496] The other configuration is the same as the anode capacitor structure CA of the semiconductor device 1A, so the description will be omitted.

[0497] Although not shown, the capacitor structure 85 of the semiconductor device 1B may be arranged in any of the layouts of the first layout shown in FIG. 14 and the second to fourteenth layouts shown in FIG. 19A to FIG. 19M. The structures of FIG. 24 and FIG. 25 may be applied to the monitor capacitor structure CM and the cathode capacitor structure CC in addition to the anode capacitor structure CA. Of course, the anode capacitor structure CA, the monitor capacitor structure CM, and the cathode capacitor structure CC may have the same cross-sectional structure as that shown in FIG. 16 and FIG. 24, or may have different cross-sectional structures. Furthermore, the anode capacitor structure CA, the monitor capacitor structure CM, and the cathode capacitor structure CC may be arranged in the same layout as that shown in FIG. 14 and FIG. 19A to FIG. 19M, or may have different layouts.

[0498] 26A to 26D are cross-sectional views showing a manufacturing process of the semiconductor device 1B according to the second embodiment. Hereinafter, the manufacturing process of the anode capacitor structure CA in the manufacturing process of the semiconductor device 1B according to the second embodiment will be described with reference to FIGS.

[0499] To form the anode capacitor structure CA of the semiconductor device 1B, for example, referring to Fig. 26A, the pad well region 80 is selectively removed from the first main surface 3 of the chip 2. This forms a plurality of capacitor trenches 86 having bottoms in the middle of the pad well region 80 in the thickness direction of the chip 2. Next, the chip 2 is subjected to a thermal oxidation treatment, whereby a capacitor insulating film 87 covering the wall surfaces of the capacitor trenches 86 and a main surface insulating film 48 covering the first main surface 3 are integrally formed.

[0500] 26B, a conductive material film (not shown) that will become the capacitor buried electrode 88 is deposited on the first main surface 3, for example, by a CVD method. The deposition of the conductive material film is continued until the capacitor trench 86 is backfilled and the first main surface 3 is covered and hidden by the conductive material film. Next, the portion of the conductive material that is outside the capacitor trench 86 is removed, for example, by etch-back. This forms the capacitor buried electrode 88 made of the conductive material film remaining in the capacitor trench 86.

[0501] 26C, the chip 2 is thermally oxidized. As a result, silicon of the chip 2 is oxidized from the interface between the first main surface 3 and the main surface insulating film 48 toward the second main surface 4 and is transformed into silicon oxide, and the main surface insulating film 48 is thickened. At the same time, oxidation of the capacitor buried electrode 88 (polysilicon) progresses in a direction from the upper surface of the capacitor buried electrode 88 toward the first main surface 3 and the capacitor buried electrode 88 is transformed. As a result, the insulating film formed by the thermal oxidation of the capacitor buried electrode 88 and the thickened main surface insulating film 48 are integrated to form the first film 53 of the dielectric film 46.

[0502] 26D, a nitride material is deposited in a film shape on the first film 53 by, for example, a CVD method. This forms a second film 54, and a dielectric film 46 having a two-layer structure of the first film 53 and the second film 54 is formed. Through the above steps, it is possible to form up to the dielectric film 46 of the anode capacitor structure CA described above.

[0503] Fig. 27 is a plan view showing a main part of the pad region 11 of the semiconductor device 1C according to the third embodiment. More specifically, Fig. 27 is a plan view of the same portion of the configuration in the pad region 11 of the semiconductor device 1C as Fig. 14, and shows the planar structure of the anode capacitor structure CA of the semiconductor device 1C. Fig. 28 is an enlarged plan view showing a main part of the pad region 11 of the semiconductor device 1C according to the third embodiment, which is a further enlargement of Fig. 27. Fig. 29 is a cross-sectional view taken along the line XXIX-XXIX shown in Fig. 28. Fig. 30 is a cross-sectional view taken along the line XXX-XXX shown in Fig. 28.

[0504] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of pad capacitor structures 84 formed in a plurality of pad regions 11. In Figures 27 to 30, an anode capacitor structure CA is shown as an example of the plurality of pad capacitor structures 84.

[0505] In the anode capacitor structure CA of the semiconductor device 1C, an interlayer film 57 (second dielectric film) is further formed in the anode capacitor structure CA of the semiconductor device 1B. That is, in this embodiment, the interlayer film 57 has a portion covering the pad region 11 in addition to a portion covering the multiple active regions 6, a portion covering the monitor region 7, a portion covering the outer periphery region 8, a portion covering the multiple street regions 9, and a portion covering the temperature measurement region 10.

[0506] The anode capacitor structure CA of the semiconductor device 1C includes one or more (seven in this embodiment) pad openings 95 (recesses) formed in the interlayer film 57 in the corresponding pad region 11. The pad openings 95 are selectively formed in the interlayer film 57 so as to reach from the upper surface to the lower surface of the interlayer film 57, and partially expose the second film 54 of the dielectric film 46. In this embodiment, the pad openings 95 extend in a strip shape along the longitudinal direction of the capacitor structure 85 in a plan view.

[0507] 28, in this embodiment, the pad opening 95 is formed in an upper region of the capacitor trench 86 with a width narrower than that of the capacitor trench 86 in a plan view. More specifically, the pad opening 95 is formed at a position facing the capacitor trench 86 with the dielectric film 46 interposed therebetween. In this embodiment, the multiple pad openings 95 are arranged in a one-to-one relationship with the multiple capacitor trenches 86. It is preferable that the pad opening 95 has a wall surface at a position spaced inward from the wall surface of the capacitor trench 86 in a plan view, and is formed in a region surrounded by the wall surfaces of the capacitor trench 86. Of course, the pad opening 95 may be formed at a position shifted from the capacitor trench 86 in the horizontal direction.

[0508] The anode capacitor structure CA of the semiconductor device 1C includes a pad via electrode 96 embedded in a pad opening 95 in the corresponding pad region 11. The pad via electrode 96 has a portion in contact with the interlayer film 57 and the dielectric film 46 (second film 54). The pad via electrode 96 is mechanically connected to the dielectric film 46 (second film 54) in the pad opening 95. The pad via electrode 96 may include at least one of a tungsten film, a molybdenum film, a nickel film, a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The pad via electrode 96 preferably includes a tungsten film.

[0509] The first electrode film 65 of the anode pad AP is interposed within the pad opening 95 between the wall surface of the pad opening 95 and the pad via electrode 96. As a result, the pad via electrode 96 is mechanically connected to the dielectric film 46 (second film 54) via the first electrode film 65.

[0510] The other configuration is the same as the anode capacitor structure CA of the semiconductor device 1A and the semiconductor device 1B, and therefore a description thereof will be omitted.

[0511] Although not shown, the capacitor structure 85 of the semiconductor device 1C may be arranged in any of the layouts of the first layout shown in FIG. 14 and the second to fourteenth layouts shown in FIG. 19A to FIG. 19M. The structures of FIG. 27 to FIG. 30 may be applied to the monitor capacitor structure CM and the cathode capacitor structure CC in addition to the anode capacitor structure CA. Of course, the anode capacitor structure CA, the monitor capacitor structure CM, and the cathode capacitor structure CC may have the same cross-sectional structure as those shown in FIG. 16, FIG. 24, and FIG. 29, or may have different cross-sectional structures. Furthermore, the anode capacitor structure CA, the monitor capacitor structure CM, and the cathode capacitor structure CC may be arranged in the same layout as those shown in FIG. 14 and FIG. 19A to FIG. 19M, or may have different layouts.

[0512] 31A to 31C are cross-sectional views showing a manufacturing process of a semiconductor device 1C according to the third embodiment. Hereinafter, a manufacturing process of an anode capacitor structure CA out of the manufacturing process of the semiconductor device 1C according to the third embodiment will be described with reference to FIGS.

[0513] To form the anode capacitor structure CA of the semiconductor device 1C, for example, with reference to FIG. 31A, the dielectric film 46 is formed on the first main surface 3 by performing the steps of FIGS. 26A to 26D described above.

[0514] Next, referring to FIG. 31B, an interlayer film 57 is laminated on the dielectric film 46 by, for example, a CVD method.

[0515] 31C, the interlayer film 57 is selectively etched in a predetermined pattern. As a result, a plurality of pad openings 95 are formed in the interlayer film 57. Through the above steps, the interlayer film 57 of the anode capacitor structure CA described above can be formed.

[0516] 32 is a cross-sectional view showing a main part of a semiconductor device 1D according to a fourth mode. The semiconductor device 1D has a modified form of the semiconductor device 1A according to the first mode.

[0517] In the anode capacitor structure CA of the semiconductor device 1D, an interlayer film 57 (second dielectric film) is further formed in the anode capacitor structure CA of the semiconductor device 1A. The structure of this interlayer film 57 is the same as that of the interlayer film 57 of the semiconductor device 1C. That is, the anode capacitor structure CA of the semiconductor device 1D includes one or more (seven in this embodiment) pad openings 95 (recesses) formed in the interlayer film 57 in the corresponding pad region 11. A pad via electrode 96 is embedded in each of the multiple pad openings 95.

[0518] 33 is a cross-sectional view showing a main part of a semiconductor device 1E according to a fifth embodiment. The semiconductor device 1E has a modified form of the semiconductor device 1A according to the first embodiment.

[0519] Similar to the semiconductor device 1A, the anode capacitor structure CA of the semiconductor device 1E includes a main surface insulating film 48, a dielectric film 46, a capacitor electrode film 90, and a pad electrode 91. Unlike the semiconductor device 1A, the anode capacitor structure CA of the semiconductor device 1E does not have a capacitor structure 85.

[0520] In this embodiment, the capacitor electrode film 90 covers the main surface insulating film 48 in the corresponding pad region 11 in a film form, and is electrically insulated from the chip 2 by the main surface insulating film 48. A potential different from the potential applied to the chip 2 is applied to the capacitor electrode film 90. Specifically, a potential different from the potential applied to the pad well region 80 is applied to the capacitor electrode film 90.

[0521] The anode pad AP forms a capacitive connection with a plurality of capacitor electrode films 90 via the dielectric film 46. As a result, the anode pad AP forms a capacitor C that functions as an anode capacitor structure CA together with the capacitor electrode films 90.

[0522] 34 is a cross-sectional view showing a main part of a semiconductor device 1F according to a sixth embodiment. The semiconductor device 1F has a configuration obtained by modifying the semiconductor device 1E according to the fifth embodiment.

[0523] In the anode capacitor structure CA of the semiconductor device 1F, an interlayer film 57 (second dielectric film) is further formed in the anode capacitor structure CA of the semiconductor device 1E. The structure of this interlayer film 57 is the same as that of the interlayer film 57 of the semiconductor device 1C. That is, the anode capacitor structure CA of the semiconductor device 1F includes one or more (seven in this embodiment) pad openings 95 (recesses) formed in the interlayer film 57 in the corresponding pad region 11. A pad via electrode 96 is embedded in each of the multiple pad openings 95.

[0524] Fig. 35 is a plan view showing a layout example of a first main surface 3 of a semiconductor device 1G according to the seventh embodiment. Fig. 36 is an enlarged plan view showing a main part of an active region 6 of the semiconductor device 1G shown in Fig. 35. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Fig. 36. The semiconductor device 1G is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT (Reverse Conducting - IGBT) structure having a transistor structure T3 and a freewheeling diode structure WD.

[0525] The semiconductor device 1G includes one or more (multiple in this embodiment) transistor regions 100 provided in each of the active regions 6, and one or more (multiple in this embodiment) free wheel diode regions 101 provided in each of the active regions 6. The multiple transistor regions 100 are regions including the above-mentioned transistor structure T3. The multiple transistor regions 100 are provided at intervals in the second direction Y in the corresponding active regions 6.

[0526] With respect to the multiple active regions 6 adjacent to each other, the multiple transistor regions 100 arranged in one active region 6 face the multiple transistor regions 100 arranged in the other active region 6 in a one-to-one correspondence in the first direction X. In other words, the multiple transistor regions 100 are arranged in a matrix on the first main surface 3 at intervals in the first direction X and the second direction Y.

[0527] The plurality of freewheeling diode regions 101 are regions including a freewheeling diode structure WD. The plurality of freewheeling diode regions 101 are provided in regions adjacent to one or more transistor regions 100 in the second direction Y in the corresponding active region 6. Specifically, the plurality of freewheeling diode regions 101 are arranged alternately with the plurality of transistor regions 100 in the second direction Y.

[0528] With respect to the active regions 6 adjacent to each other, the free wheel diode regions 101 arranged in one active region 6 face the free wheel diode regions 101 arranged in the other active region 6 in a one-to-one correspondence in the first direction X. In other words, the free wheel diode regions 101 are arranged in a matrix on the first main surface 3 at intervals in the first direction X and the second direction Y. Of course, the free wheel diode regions 101 may face the transistor regions 100 in the first direction X.

[0529] The semiconductor device 1G includes, in each transistor region 100, a base region 15, a plurality of gate structures 20, a plurality of gate connection structures 25, a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40, a contact region 41, a plurality of storage regions 42 and a plurality of well regions 43.

[0530] The layout of these components in the transistor region 100 is similar to the layout of the corresponding components in the active region 6 according to the first embodiment. For the description of the layout of these components in the transistor region 100, the description of the layout of the corresponding components in the active region 6 according to the first embodiment applies.

[0531] The semiconductor device 1G includes an n-type return cathode region 103 formed in a surface layer portion of the second main surface 4 in the return diode region 101. The return cathode region 103 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the return cathode region 103 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the return cathode region 103 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and the conductivity type of the collector region 14 is replaced from p-type to n-type.

[0532] The return cathode region 103 passes through the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the return cathode region 103 has an upper end located within the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The return cathode region 103 may pass through the buffer region 13 and have an upper end located within the drift region 12.

[0533] The semiconductor device 1G includes a freewheeling diode structure WD formed on the first main surface 3 in the freewheeling diode region 101. In the following, the configuration of one freewheeling diode structure WD as one component of the semiconductor device 1G will be described.

[0534] The freewheeling diode structure WD includes a p-type freewheeling anode region 104 formed in a surface layer portion of the first main surface 3 in the freewheeling diode region 101. The freewheeling anode region 104 is formed in a surface layer portion of the drift region 12. In this embodiment, the freewheeling anode region 104 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and replaces the conductivity type of the drift region 12 from n-type to p-type.

[0535] The p-type impurity concentration of the return anode region 104 may be approximately equal to the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the return anode region 104 may be higher than the p-type impurity concentration of the base region 15, or may be lower than the p-type impurity concentration of the base region 15.

[0536] The return anode regions 104 are formed in the return diode region 101 in a layer shape extending along the first main surface 3, and face the return cathode region 103 across the drift region 12 in the thickness direction. The return anode regions 104 are formed at an interval from the depth position of the middle part of the drift region 12 toward the first main surface 3.

[0537] The return anode region 104 may have a depth approximately equal to that of the base region 15. Of course, the depth of the return anode region 104 may be greater than or less than the depth of the base region 15. The depth of the return anode region 104 is preferably less than the depth of the well region 43. Of course, the depth of the return anode region 104 may be approximately equal to or greater than the depth of the well region 43. The freewheeling diode structure WD includes a plurality of trench electrode type anode structures 105 formed on the first main surface 3 in the freewheeling diode region 101. An emitter potential is applied to the plurality of anode structures 105. The plurality of anode structures 105 each extend in a strip shape in the first direction X in the anode pad region 11A and are arranged at intervals in the second direction Y.

[0538] That is, the multiple anode structures 105 are arranged in a stripe pattern extending in the first direction X. The extension direction of the multiple anode structures 105 coincides with the extension direction of the multiple gate structures 20. The extension direction of the multiple anode structures 105 coincides with the extension direction of the multiple emitter structures 30.

[0539] Each of the multiple anode structures 105 may have a width less than the width of the multiple street regions 9. The width of the anode structure 105 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the anode structure 105. The width of the anode structure 105 may be approximately equal to the width of the gate structure 20 (gate connection structure 25). Of course, the width of the anode structure 105 may be greater than the width of the gate structure 20 (gate connection structure 25) or less than the width of the gate structure 20 (gate connection structure 25).

[0540] The width of the anode structure 105 may be approximately equal to the width of the emitter structure 30 (emitter connecting structure 35). Of course, the width of the emitter structure 30 may be greater than the width of the emitter structure 30 (emitter connecting structure 35) or may be smaller than the width of the emitter structure 30 (emitter connecting structure 35).

[0541] The width of the anode structure 105 may be 0.5 μm to 5 μm. The width of the anode structure 105 may have a value belonging to at least one of the following ranges: 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The width of the anode structure 105 is preferably 1 μm to 2.5 μm.

[0542] The multiple anode structures 105 penetrate the return anode region 104 to reach the drift region 12. The multiple anode structures 105 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3. The multiple anode structures 105 face the return cathode region 103 with a part of the drift region 12 interposed therebetween in the thickness direction.

[0543] The plurality of anode structures 105 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of anode structures 105 may be formed substantially perpendicular to the first main surface 3. The bottom walls of the plurality of anode structures 105 may be formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of anode structures 105 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of anode structures 105 may be formed in a curved shape.

[0544] The plurality of anode structures 105 may have a depth approximately equal to the depth of the plurality of gate structures 20 (gate connection structures 25). Of course, the depth of the anode structures 105 may be greater than or less than the depth of the gate structures 20 (gate connection structures 25).

[0545] The depth of the anode structure 105 may be approximately equal to the depth of the emitter structure 30 (emitter connecting structure 35). Of course, the depth of the anode structure 105 may be greater than the depth of the emitter structure 30 (emitter connecting structure 35) or less than the depth of the emitter structure 30 (emitter connecting structure 35).

[0546] The depth of the anode structure 105 may be 0.5 μm to 10 μm. The depth of the anode structure 105 may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the anode structure 105 is preferably 4 μm to 8 μm.

[0547] A third trench pitch between the centers of the multiple anode structures 105 may be approximately equal to the first trench pitch between the centers of the gate structures 20 and the centers of the emitter structures 30. Of course, the third trench pitch may be larger or smaller than the first trench pitch.

[0548] The third trench pitch may be 1 μm or more and 5 μm or less. The third trench pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The third trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0549] Each of the multiple anode structures 105 includes an anode trench 106, an anode insulating film 107, and a buried anode electrode 108. The anode trench 106 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the anode structure 105.

[0550] The anode insulating film 107 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The anode insulating film 107 preferably includes the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the anode insulating film 107 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the anode insulating film 107 includes a silicon oxide film made of an oxide of the chip 2.

[0551] The anode insulating film 107 covers the wall surface of the anode trench 106. The thickness of the anode insulating film 107 may be approximately equal to the thickness of the gate insulating film 22 (gate connection insulating film 27). Of course, the thickness of the anode insulating film 107 may be greater than the thickness of the gate insulating film 22 (gate connection insulating film 27) or may be smaller than the thickness of the gate insulating film 22 (gate connection insulating film 27).

[0552] The thickness of the anode insulating film 107 may be approximately equal to the thickness of the emitter insulating film 32 (emitter connection insulating film 37). Of course, the thickness of the anode insulating film 107 may be greater than the thickness of the emitter insulating film 32 (emitter connection insulating film 37) or may be smaller than the thickness of the emitter insulating film 32 (emitter connection insulating film 37).

[0553] The thickness of the anode insulating film 107 may be 10 nm or more and 200 nm or less. The thickness of the anode insulating film 107 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the anode insulating film 107 is preferably 100 nm or more and 150 nm or less.

[0554] The buried anode electrode 108 is buried in the anode trench 106 with the anode insulating film 107 therebetween. The buried anode electrode 108 faces the drift region 12 and the return anode region 104 with the anode insulating film 107 therebetween.

[0555] The electrode surface of the buried anode electrode 108 may be located on the bottom wall side of the anode trench 106 with respect to the first main surface 3. The buried anode electrode 108 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried anode electrode 108 preferably includes the same type of conductor as the buried gate electrode 23.

[0556] The freewheeling diode structure WD includes a plurality of trench electrode type anode connection structures 110 formed on the first main surface 3 to be connected to the plurality of anode structures 105. An emitter potential is applied to the plurality of anode connection structures 110. The anode connection structures 110 may be referred to as "trench anode connection structures."

[0557] The multiple anode connection structures 110 are arranged on both end sides of the multiple anode structures 105 so as to be connected to one end and the other end of the multiple anode structures 105 in the first direction X, and together with the outermost multiple anode structures 105, define corresponding freewheeling diode regions 101.

[0558] The multiple anode connection structures 110 include an anode connection structure 110 on one end side of the multiple anode structures 105 in the first direction X, and an anode connection structure 110 on the other end side of the multiple anode structures 105. The anode connection structure 110 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple anode structures 105. The anode connection structure 110 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple anode structures 105.

[0559] Each of the multiple anode connection structures 110 may have a width approximately equal to the width of the anode structure 105 (gate structure 20). Of course, the width of the anode connection structure 110 may be larger than the width of the anode structure 105 or may be smaller than the width of the anode structure 105.

[0560] The width of the anode connection structure 110 may be 0.5 μm or more and 5 μm or less. The width of the anode connection structure 110 may have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the anode connection structure 110 is preferably 1 μm or more and 2.5 μm or less.

[0561] The multiple anode connection structures 110 penetrate the return anode region 104 to reach the drift region 12. The multiple anode connection structures 110 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the return cathode region 103 with a part of the drift region 12 in between in the thickness direction.

[0562] The multiple anode connection structures 110 may be formed in a tapered shape toward the bottom wall. Of course, the multiple anode connection structures 110 may be formed approximately perpendicular to the first main surface 3. The multiple anode connection structures 110 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the multiple anode connection structures 110 may be formed approximately parallel to the first main surface 3. In this case, corners of the bottom walls of the multiple anode connection structures 110 may be formed in a curved shape.

[0563] The multiple anode connection structures 110 may each have a depth approximately equal to the depth of the anode structure 105 (gate structure 20). Of course, the depth of the anode connection structure 110 may be greater than or less than the depth of the anode structure 105.

[0564] The depth of the anode connection structure 110 may be 0.5 μm or more and 10 μm or less. The depth of the anode connection structure 110 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the anode connection structure 110 is preferably 4 μm or more and 8 μm or less.

[0565] Each of the multiple anode connection structures 110 includes an anode connection trench 111, an anode connection insulating film 112, and an anode connection buried electrode 113. The anode connection trench 111 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the anode connection structure 110. The anode connection trench 111 communicates with the multiple anode trenches 106.

[0566] The anode connection insulating film 112 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The anode connection insulating film 112 preferably includes the same type of insulator as the anode insulating film 107 (gate insulating film 22). In this embodiment, the anode connection insulating film 112 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the anode connection insulating film 112 includes a silicon oxide film made of an oxide of the chip 2.

[0567] The anode connection insulating film 112 covers the wall surface of the anode connection trench 111 in a film-like shape. The anode connection insulating film 112 is connected to the anode insulating film 107 at the communicating portion between the anode trench 106 and the anode connection trench 111.

[0568] The anode connection insulating film 112 may have a thickness approximately equal to that of the anode insulating film 107. Of course, the thickness of the anode connection insulating film 112 may be greater than or less than the thickness of the anode insulating film 107.

[0569] The anode connection insulating film 112 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the anode connection insulating film 112 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the anode connection insulating film 112 is preferably 100 nm or more and 150 nm or less.

[0570] The anode connection buried electrode 113 is buried in the anode connection trench 111 with the anode connection insulating film 112 sandwiched therebetween. The anode connection buried electrode 113 is connected to the anode buried electrode 108 at the communicating portion between the anode trench 106 and the anode connection trench 111. The anode connection buried electrode 113 faces the drift region 12 and the return anode region 104 with the anode connection insulating film 112 sandwiched therebetween. The anode connection buried electrode 113 is partially covered with the interlayer film 57.

[0571] The electrode surface of the anode connection buried electrode 113 may be located on the bottom wall side of the anode connection trench 111 with respect to the first main surface 3. The anode connection buried electrode 113 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The anode connection buried electrode 113 preferably contains the same type of conductor as the anode buried electrode 108.

[0572] The freewheel diode structure WD includes a p-type boundary well region 115 formed in a surface layer portion of the first main surface 3 in the freewheel diode region 101. The boundary well region 115 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the boundary well region 115 may be lower than the p-type impurity concentration of the base region 15. The p-type impurity concentration of the boundary well region 115 may be approximately equal to the p-type impurity concentration of the well region 43. In this embodiment, the boundary well region 115 is formed in an electrically floating state.

[0573] The boundary well region 115 is formed in a region between a pair of anode structures 105 among the multiple anode structures 105 that are adjacent to the transistor region 100. Specifically, the boundary well region 115 is formed in a mesa region defined by the pair of anode structures 105 and the pair of anode connection structures 110.

[0574] The boundary well region 115 has a bottom located on the bottom wall side of the anode structures 105 relative to the depth position of the bottom of the base region 15. The bottoms of the anode regions 51 are located on the bottom wall side of the anode structures 105 relative to the depth positions of the intermediate parts of the anode structures 105. In this embodiment, the bottoms of the boundary well region 115 are located on the second main surface 4 side of the bottom walls of the anode structures 105.

[0575] The boundary well region 115 extends in a strip shape in the first direction X following the extension direction of the multiple anode structures 105, and is connected to the multiple anode structures 105 and the multiple anode connection structures 110. The boundary well region 115 may have a portion (bottom) covering the bottom walls of the multiple anode structures 105 and the bottom walls of the multiple anode connection structures 110.

[0576] The semiconductor device 1G includes the aforementioned main surface insulating film 48 that selectively covers the first main surface 3 in the freewheeling diode region 101. The main surface insulating film 48 covers the freewheeling anode region 104 and the boundary well region 115 in the freewheeling diode region 101. The main surface insulating film 48 is connected to the anode insulating film 107 and the anode connection insulating film 112 in the freewheeling diode region 101, and exposes the anode buried electrode 108 and the anode connection buried electrode 113.

[0577] The main surface insulating film 48 may have a thickness substantially equal to that of the anode insulating film 107 (anode connection buried electrode 113). Of course, the thickness of the main surface insulating film 48 may be greater than or less than the thickness of the anode insulating film 107 (anode connection buried electrode 113).

[0578] The semiconductor device 1G includes the above-mentioned interlayer film 57 that selectively covers the main surface insulating film 48 in the freewheeling diode region 101. The interlayer film 57 covers the freewheeling anode region 104 and the boundary well region 115 in the freewheeling diode region 101, with the main surface insulating film 48 in between. The interlayer film 57 selectively covers the multiple anode structures 105 and the multiple anode connection structures 110.

[0579] In this embodiment, the interlayer film 57 extends from above the main surface insulating film 48 into the multiple anode trenches 106 and the multiple anode connection trenches 111. The interlayer film 57 has portions that cover the electrode surfaces of the multiple anode buried electrodes 108 in the multiple anode trenches 106. The interlayer film 57 has portions that cover the electrode surfaces of the multiple anode connection buried electrodes 113 in the multiple anode connection trenches 111.

[0580] The semiconductor device 1G includes a diode opening 116 formed in the interlayer film 57 in the freewheeling diode region 101. In this embodiment, the diode opening 116 exposes the inner portion of the anode region 51 and the inner portions of the multiple anode structures 105. The diode opening 116 exposes all of the anode structures 105. The emitter pad EP described above enters the diode opening 116 from above the interlayer film 57, and is mechanically and electrically connected to the anode region 51 and the multiple anode structures 105 within the diode opening 116.

[0581] In this embodiment, an example in which a plurality of anode structures 105 and a plurality of anode connecting structures 110 are formed has been shown, but the plurality of anode structures 105 and the plurality of anode connecting structures 110 are not necessarily required and may be removed.

[0582] 38 is a cross-sectional view showing a main part of a semiconductor device 1H according to the eighth embodiment. The semiconductor device 1H is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT structure having a transistor structure T3 and a free wheel diode structure WD. The configuration of the semiconductor device 1H may be combined with the semiconductor device 1G.

[0583] The semiconductor device 1H includes an n-type peripheral cathode region 120 formed in a surface layer portion of the second main surface 4 around the multiple active regions 6. The peripheral cathode region 120 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the peripheral cathode region 120 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the peripheral cathode region 120 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and replaces the conductivity type of the collector region 14 from p-type to n-type.

[0584] The peripheral cathode region 120 is formed in a region facing the peripheral well region 44 in the thickness direction of the chip 2 in the surface layer portion of the second main surface 4. The peripheral cathode region 120 is preferably formed narrower than the peripheral well region 44 and faces the peripheral well region 44 with a gap inward from both ends of the peripheral well region 44. In other words, the entire peripheral cathode region 120 preferably faces the peripheral well region 44 in the thickness direction in a cross-sectional view.

[0585] The peripheral cathode region 120 penetrates the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the peripheral cathode region 120 has an upper end located in the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The peripheral cathode region 120 may also penetrate the buffer region 13 and have an upper end located in the drift region 12.

[0586] The peripheral cathode region 120 extends in a band shape along the periphery of the first main surface 3 with a gap inward from the periphery of the first main surface 3. In this embodiment, the peripheral cathode region 120 extends in a band shape along the extension direction of the peripheral well region 44 in a plan view. The peripheral cathode region 120 may be formed in an annular shape surrounding a plurality of active regions 6.

[0587] As described above, semiconductor device 1H may include a freewheeling diode structure WD including peripheral well region 44 as an anode and peripheral cathode region 120 as a cathode.

[0588] 39 is a cross-sectional view showing a main part of a semiconductor device 1I according to a ninth embodiment. The semiconductor device 1I is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT structure having a transistor structure T3 and a free wheel diode structure WD. The configuration of the semiconductor device 1I may be combined with the semiconductor device 1G and the semiconductor device 1H.

[0589] The semiconductor device 1I includes an n-type street cathode region 121 formed in a surface layer portion of the second main surface 4 in the street region 9. The street cathode region 121 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the street cathode region 121 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the street cathode region 121 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and replaces the conductivity type of the collector region 14 from p-type to n-type.

[0590] The street cathode region 121 is formed in a region facing the street well region 45 in the thickness direction of the chip 2 in the surface layer portion of the second main surface 4. It is preferable that the street cathode region 121 is formed narrower than the street well region 45 and faces the street well region 45 with a space inward from both ends of the street well region 45.

[0591] The street cathode region 121 is preferably formed at a distance from the multiple active regions 6. In other words, the street cathode region 121 is preferably formed at a distance from the multiple gate structures 20 and the multiple gate connection structures 25 on the inward side of the street region 9. The entire area of ​​the street cathode region 121 is preferably opposed to the street well region 45 in the thickness direction in a cross-sectional view.

[0592] Of course, the street cathode region 121 may have a width larger than that of the street region 9 and may have a portion drawn out from the street region 9 into the multiple active regions 6. In this case, the street cathode region 121 may face the multiple gate structures 20 and the multiple gate connection structures 25 in the thickness direction. The street cathode region 121 is formed in a strip shape extending in the second direction Y following the extension direction of the street region 9.

[0593] The street cathode region 121 penetrates the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the street cathode region 121 has an upper end located in the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The street cathode region 121 may penetrate the buffer region 13 and have an upper end located in the drift region 12.

[0594] As described above, the semiconductor device 1I may include a freewheeling diode structure WD including the street well region 45 as an anode and the street cathode region 121 as a cathode.

[0595] 40 is a cross-sectional view showing a main part of a semiconductor device 1J according to a tenth embodiment. The semiconductor device 1J is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT structure having a transistor structure T3 and a free wheel diode structure WD. The configuration of the semiconductor device 1J may be combined with the semiconductor device 1G, the semiconductor device 1H, and the semiconductor device 1I.

[0596] The semiconductor device 1J includes an n-type pad cathode region 122 formed in a surface layer portion of the second main surface 4 in one or more pad regions 11. Fig. 40 shows an example in which the pad cathode region 122 is formed in the anode pad region 11A. Of course, the pad cathode region 122 may be formed in at least one of the gate pad region 11G, the monitor pad region 11M, and the cathode pad region 11C.

[0597] The pad cathode region 122 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the pad cathode region 122 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the pad cathode region 122 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and replaces the conductivity type of the collector region 14 from p-type to n-type.

[0598] The pad cathode region 122 is formed in a region facing the pad well region 80 in the thickness direction of the chip 2 in the surface layer portion of the second main surface 4. In this embodiment, the pad cathode region 122 faces the pad well region 80 and the multiple capacitor structures 85 in the thickness direction.

[0599] The pad cathode region 122 may be formed over the entire area of ​​the corresponding pad region 11, or may be formed partially in a part of the corresponding pad region 11. The pad cathode region 122 may face all of the capacitor structures 85, or may face some of the capacitor structures 85. The pad cathode region 122 may face the entire areas of the plurality of capacitor structures 85, or may face some of the plurality of capacitor structures 85.

[0600] The pad cathode region 122 passes through the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the pad cathode region 122 has an upper end located in the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The pad cathode region 122 may pass through the buffer region 13 and have an upper end located in the drift region 12.

[0601] As described above, the semiconductor device 1J may include a freewheeling diode structure WD including the pad well region 80 as an anode and the pad cathode region 122 as a cathode.

[0602] 41 is a cross-sectional view showing a main part of a semiconductor device 1K according to the 11th embodiment. The semiconductor device 1K has a modified form of the semiconductor device 1J according to the 10th embodiment.

[0603] In the anode capacitor structure CA of the semiconductor device 1K, unlike the semiconductor device 1J, the electrode portion of the capacitor structure 85 does not include a capacitor electrode film 90, but is formed by a plurality of capacitor buried electrodes 88. Unlike the configuration in Fig. 40, the plurality of capacitor buried electrodes 88 are not integrally conductive in the upper region of the capacitor trench 86, but are buried in each of the plurality of capacitor trenches 86 while being physically separated from one another.

[0604] The first film 53 of the dielectric film 46 is also formed as the main surface insulating film 48 , and covers the upper surfaces of the multiple buried capacitor electrodes 88 collectively.

[0605] The other configuration is the same as that of the anode capacitor structure CA of the semiconductor device 1J, and therefore a description thereof will be omitted.

[0606] 42 is a cross-sectional view showing a main part of a semiconductor device 1L according to the twelfth mode. The semiconductor device 1L has a modified form of the semiconductor device 1K according to the eleventh mode.

[0607] In the anode capacitor structure CA of the semiconductor device 1L, an interlayer film 57 (second dielectric film) is further formed in the anode capacitor structure CA of the semiconductor device 1K. The structure of this interlayer film 57 is the same as that of the interlayer film 57 of the semiconductor device 1C. That is, the anode capacitor structure CA of the semiconductor device 1L includes one or more (seven in this embodiment) pad openings 95 (recesses) formed in the interlayer film 57 in the corresponding pad region 11. A pad via electrode 96 is embedded in each of the multiple pad openings 95.

[0608] Modifications applied to the semiconductor devices 1A to 1L according to the first to twelfth embodiments are shown below. Figs. 43 to 46 are plan views showing first to fourth modifications of the semiconductor devices 1A to 1L according to the first to twelfth embodiments. In Figs. 43 to 46, the semiconductor device 1A is illustrated. The semiconductor devices 1A to 1L according to the first to twelfth embodiments may have at least one of the configurations according to the first to fourth modifications. Of course, the semiconductor devices 1A to 1L according to the first to twelfth embodiments may have a configuration in which at least two of the configurations according to the first to fourth modifications are combined.

[0609] With reference to Fig. 43 (first modification), the semiconductor devices 1A-1L not having a monitor capacitor structure CM may be employed. With reference to Fig. 44 (second modification), the semiconductor devices 1A-1L not having an anode capacitor structure CA may be employed. With reference to Fig. 45 (third modification), the semiconductor devices 1A-1L not having a cathode capacitor structure CC may be employed.

[0610] 46 (fourth modification), the semiconductor devices 1A to 1L may include a gate capacitor structure CG as a pad capacitor structure 84 formed in the gate pad region 11G. The gate capacitor structure CG may have a configuration similar to any one of the pad capacitor structures 84 (anode capacitor structures CA) shown in the first to sixth embodiments.

[0611] The configuration of the gate capacitor structure CG is obtained by replacing the "pad capacitor structure 84 (anode capacitor structure CA)" in the above description with the "gate capacitor structure CG", the "pad region 11 (anode pad region 11A)" with the "gate pad region 11G", and the "pad electrode 91 (anode pad AP)" with the "gate pad GP".

[0612] Of course, the gate capacitor structure CG may have at least one feature of the capacitor structures 85 according to the first to fourteenth layout examples (see FIG. 14 and FIGS. 19A to 19M).

[0613] Each of the above-described embodiments (including modified examples) can be embodied in other forms. For example, in each of the above-described embodiments, the monitor capacitor structure CM, the anode capacitor structure CA, the cathode capacitor structure CC, and the gate capacitor structure CG do not necessarily have to have the same configuration, and may have different configurations.

[0614] That is, the monitor capacitor structure CM in the first to twelfth embodiments may have any one of the configurations of the pad capacitor structures 84 according to the first to sixth embodiments. Also, the anode capacitor structure CA in the first to twelfth embodiments may have any one of the configurations of the pad capacitor structures 84 according to the first to sixth embodiments.

[0615] In addition, the cathode capacitor structure CC in the first to twelfth embodiments may have any one of the configurations of the pad capacitor structures 84 according to the first to sixth embodiments. In addition, the gate capacitor structure CG in the first to twelfth embodiments may have any one of the configurations of the pad capacitor structures 84 according to the first to sixth embodiments.

[0616] In each of the above-described embodiments (including the modified examples), it is sufficient that the plurality of capacitor structures 85 have a configuration in which an emitter potential is applied. Therefore, the lead-out portion 85a of the capacitor structure 85 does not necessarily need to be mechanically connected to either one or both of the emitter structure 30 and the emitter connecting structure 35.

[0617] For example, the semiconductor devices 1A-IL may have an emitter wiring 55 for the capacitor structure 85 (drawing portion 85a), a second emitter opening 62, and a second emitter via electrode 63 in the active region 6. In this case, the emitter wiring 55 is connected to the capacitor buried electrode 88 on the first main surface 3 (main surface insulating film 48). The second emitter opening 62 exposes the emitter wiring 55 for the capacitor structure 85 (drawing portion 85a).

[0618] The second emitter via electrode 63 is mechanically and electrically connected to the emitter wiring 55 in the second emitter opening 62, and is electrically connected to the capacitor buried electrode 88 via the emitter wiring 55. The emitter pad EP is electrically connected to the capacitor structure 85 (drawing portion 85a) in the active region 6 via the emitter wiring 55 and the second emitter via electrode 63. As a result, the emitter potential is transmitted to the capacitor structure 85 via the emitter wiring 55 and the second emitter via electrode 63.

[0619] In each of the above-described embodiments (including the modified examples), a configuration may be adopted in which the monitor region 7 (monitor transistor structure T2) is not provided, but the active region 6 (transistor structure T3) and the temperature measuring region 10 (temperature sensitive diode structure D) are provided.

[0620] In each of the above-described embodiments, a configuration may be adopted in which the temperature detection region 10 (temperature sensitive diode structure D) is not included, but the active region 6 (transistor structure T3) and the monitor region 7 (monitor transistor structure T2) are included.

[0621] In each of the above-mentioned forms (including modified examples), a configuration may be adopted that does not have an active region 6 (transistor structure T3) but has either or both of a monitor region 7 (monitor transistor structure T2) and a temperature measurement region 10 (temperature sensing diode structure D).

[0622] In each of the above-mentioned embodiments (including the modified examples), a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type" and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and at the same time replacing "p-type" with "n-type" in the above description and the accompanying drawings.

[0623] In each of the above-described embodiments (including modified examples), the collector region 14 may be removed. In this case, the main transistor structure T1 (transistor structure T3) includes a MISFET structure instead of an IGBT structure. A specific configuration in this case is obtained by replacing the "emitter" of the IGBT structure with the "source" of the MISFET structure and the "collector" of the IGBT structure with the "drain" of the MISFET structure in the above description. In this case, the chip 2 may have a laminated structure including an n-type semiconductor substrate on the second main surface 4 side and an n-type epitaxial layer on the first main surface 3 side.

[0624] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned forms, but are not intended to limit the scope of each clause to the above-mentioned forms. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide band gap semiconductor device," "semiconductor switching device," "IGBT device," "RC-IGBT device," "MISFET device," "semiconductor rectifier device," etc., as necessary.

[0625] [Appendix 1-1] A chip (2) having a main surface (3); a trench electrode type capacitor structure (85, 85A, 85B) formed on the main surface (3) and to which a first potential is applied; a dielectric film (46) covering the capacitor structure (85, 85A, 85B) on the main surface (3); a pad electrode (91, GP, MP, AP, CaP) disposed on the dielectric film (46) so as to form a capacitive connection with the capacitor structure (85, 85A, 85B) via the dielectric film (46), and to which a second potential different from the first potential is applied; The dielectric film (46) is a first film (53) covering the capacitor structure (85, 85A, 85B); a second film (54) made of a different dielectric material from the first film (53), the second film (54) being disposed on the first film (53) so as to sandwich the first film (53) and cover the capacitor structure (85, 85A, 85B), the second film (54) being made of a different dielectric material from the first film (53), the semiconductor device (1A to 1L).

[0626] [Appendix 1-2] The first film (53) has a first relative dielectric constant (ε r1 ) The second film (54) has the first relative dielectric constant (ε r1 ) higher than the second relative dielectric constant (ε r2 The semiconductor device (1A to 1L) according to Appendix 1-1,

[0627] [Appendix 1-3] The first relative dielectric constant (ε r1 ) is greater than or equal to 3.5 and less than or equal to 4.5, The second relative dielectric constant (ε r2 ) is 7.5 or more and 8.5 or less.

[0628] [Appendix 1-4] The semiconductor device (1A to 1L) according to any one of Appendix 1-1 to Appendix 1-3, wherein the first film (53) is an oxide film.

[0629] [Appendix 1-5] The semiconductor device (1A to 1L) according to any one of Appendix 1-1 to Appendix 1-4, wherein the second film (54) is a film containing nitrogen.

[0630] [Appendix 1-6] the first film (53) is a silicon oxide film, The semiconductor device (1A to 1L) according to any one of Appendix 1-1 to Appendix 1-5, wherein the second film (54) is a silicon nitride film.

[0631] [Appendix 1-7] The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-6, wherein the first potential is a potential other than a gate potential.

[0632] [Appendix 1-8] The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-7, wherein the first potential is a reference potential that serves as a reference for circuit operation.

[0633] [Appendix 1-9] The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-7, wherein the first potential is an emitter potential.

[0634] [Appendix 1-10] The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-9, wherein the second potential is a potential other than a gate potential.

[0635] [Appendix 1-11] The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-10, wherein the second potential is a potential other than a reference potential that is a reference for circuit operation.

[0636] [Appendix 1-12] The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-11, wherein the second potential is a potential other than an emitter potential.

[0637] [Appendix 1-13] an active region (6, 6A to 6D) provided on the main surface (3); a pad region (11, 11A, 11C, 11G, 11M) provided in an area outside the active region (6, 6A to 6D) on the main surface (3); A transistor structure formed in the active region (6, 6A to 6D), the capacitor structure (85, 85A, 85B) is formed on the main surface (3) in the pad region (11, 11A, 11C, 11G, 11M); the dielectric film (46) covers the capacitor structures (85, 85A, 85B) in the pad regions (11, 11A, 11C, 11G, 11M); The semiconductor device (1A to 1L) according to any one of Appendices 1-1 to 1-12, wherein the pad electrode (91, GP, MP, AP, CaP) is arranged on the dielectric film (46) in the pad region (11, 11A, 11C, 11G, 11M).

[0638] [Appendix 1-14] a monitor region (7) provided in a region outside the active regions (6, 6A to 6D) on the main surface (3); a monitor transistor structure (T2) for monitoring a current formed in the monitor region (7); the pad region (11, 11A, 11C, 11G, 11M) is provided in a region outside the active region (6, 6A to 6D) and the monitor region (7); The semiconductor device (1A to 1L) according to appendix 1-13, wherein a potential for the monitor transistor structure (T2) is applied to the pad electrode (91, GP, MP, AP, CaP).

[0639] [Appendix 1-15] a diode region (10) provided in a region outside the active region (6, 6A to 6D) on the main surface (3); a diode structure (D) formed in the diode region (10), the pad region (11, 11A, 11C, 11G, 11M) is provided in a region outside the active region (6, 6A to 6D) and the diode region (10); The semiconductor device (1A to 1L) according to Appendix 1-13 or Appendix 1-14, wherein a potential with respect to the diode structure (D) is applied to the pad electrode (91, GP, MP, AP, CaP).

[0640] [Appendix 1-16] The capacitor structure (85, 85A, 85B) includes a capacitor trench (86) formed in the chip (2), a capacitor insulating film (87) formed on the inner surface of the capacitor trench (86), and a capacitor buried electrode (88) buried in the capacitor trench (86) with the capacitor insulating film (87) interposed therebetween; The capacitor buried electrode (88) includes an integral electrode (90) spanning a plurality of the capacitor trenches (86); The semiconductor device (1A to 1L) according to any one of Appendix 1-1 to Appendix 1-15, wherein the dielectric film (46) covers an upper surface of the integrated electrode (90).

[0641] [Appendix 1-17] The capacitor structure (85, 85A, 85B) includes a capacitor trench (86) formed in the chip (2), a capacitor insulating film (87) formed on the inner surface of the capacitor trench (86), and a capacitor buried electrode (88) buried in the capacitor trench (86) with the capacitor insulating film (87) interposed therebetween; A plurality of the capacitor buried electrodes (88) are buried in the respective capacitor trenches (86) while being physically separated from each other; The semiconductor device (1A to 1L) according to any one of Supplementary Notes 1-1 to 1-15, wherein the dielectric film (46) collectively covers upper surfaces of the plurality of capacitor buried electrodes (88).

[0642] [Appendix 1-18] Further comprising a second dielectric film (57) disposed on the dielectric film (46), A recess (95) is formed in the second dielectric film (57)...

Claims

1. a chip having a major surface; a trench electrode type capacitor structure formed on the main surface and having a first potential applied thereto; a dielectric film covering the capacitor structure on the major surface; a pad electrode disposed on the dielectric film so as to form a capacitive connection with the capacitor structure via the dielectric film, the pad electrode being applied with a second potential different from the first potential; The dielectric film is a first film covering the capacitor structure; a second film disposed on the first film so as to sandwich the first film and cover the capacitor structure, the second film being made of a different dielectric material from the first film.

2. the first film has a first dielectric constant; The semiconductor device according to claim 1 , wherein said second film has a second relative dielectric constant higher than said first relative dielectric constant.

3. the first relative dielectric constant is equal to or greater than 3.5 and equal to or less than 4.5; The semiconductor device according to claim 2 , wherein the second relative dielectric constant is equal to or greater than 7.5 and equal to or less than 8.

5.

4. The semiconductor device according to claim 1 , wherein the first film is an oxide film.

5. The semiconductor device according to claim 1 , wherein the second film is a film containing nitrogen.

6. the first film is a silicon oxide film, The semiconductor device according to claim 3 , wherein the second film is a silicon nitride film.

7. The semiconductor device according to claim 1 , wherein the first potential is a potential other than a gate potential.

8. 2. The semiconductor device according to claim 1, wherein the first potential is a reference potential that serves as a reference for circuit operation.

9. 2. The semiconductor device according to claim 1, wherein the first potential is an emitter potential.

10. The semiconductor device according to claim 1 , wherein the second potential is a potential other than a gate potential.

11. 2. The semiconductor device according to claim 1, wherein the second potential is a potential other than a reference potential that serves as a reference for circuit operation.

12. 2. The semiconductor device according to claim 1, wherein the second potential is a potential other than an emitter potential.

13. an active region provided on the primary surface; a pad region provided on the main surface in a region outside the active region; a transistor structure formed in the active region, the capacitor structure is formed on the major surface in the pad region; the dielectric film covers the capacitor structure in the pad region; 13. The semiconductor device according to claim 1, wherein the pad electrode is disposed on the dielectric film in the pad region.

14. a monitor region provided in a region outside the active region on the main surface; a monitor transistor structure for monitoring a current formed in the monitor region; the pad region is provided in an area outside the active area and the monitor area, 14. The semiconductor device according to claim 13, wherein a potential for said monitor transistor structure is applied to said pad electrode.

15. a diode region provided in a region outside the active region on the main surface; a diode structure formed in the diode region, the pad region is provided in a region outside the active region and the diode region, The semiconductor device according to claim 13 , wherein a potential for said diode structure is applied to said pad electrode.

16. the capacitor structure includes a capacitor trench formed in the chip, a capacitor insulating film formed on an inner surface of the capacitor trench, and a capacitor buried electrode buried in the capacitor trench with the capacitor insulating film interposed therebetween; the capacitor buried electrode includes an integral electrode spanning a plurality of the capacitor trenches; 13. The semiconductor device according to claim 1, wherein the dielectric film covers an upper surface of the integrated electrode.

17. the capacitor structure includes a capacitor trench formed in the chip, a capacitor insulating film formed on an inner surface of the capacitor trench, and a capacitor buried electrode buried in the capacitor trench with the capacitor insulating film interposed therebetween; a plurality of the capacitor buried electrodes are buried in the respective plurality of the capacitor trenches while being physically separated from each other; 13. The semiconductor device according to claim 1, wherein said dielectric film collectively covers upper surfaces of said buried capacitor electrodes.

18. further comprising a second dielectric film disposed on the dielectric film; a recessed portion is formed in the second dielectric film in a region above the capacitor structure, the recessed portion extending from an upper surface to a lower surface of the second dielectric film; 13. The semiconductor device according to claim 1, wherein the pad electrode is formed on the second dielectric film so as to cover the recess.

19. the capacitor structure includes a capacitor trench formed in the chip, a capacitor insulating film formed on an inner surface of the capacitor trench, and a capacitor buried electrode buried in the capacitor trench with the capacitor insulating film interposed therebetween; the capacitor buried electrode includes an integral electrode spanning a plurality of the capacitor trenches; The semiconductor device according to claim 18 , wherein the dielectric film covers an upper surface of the integrated electrode.

20. the capacitor structure includes a capacitor trench formed in the chip, a capacitor insulating film formed on an inner surface of the capacitor trench, and a capacitor buried electrode buried in the capacitor trench with the capacitor insulating film interposed therebetween; a plurality of the capacitor buried electrodes are buried in the respective plurality of the capacitor trenches while being physically separated from each other; 20. The semiconductor device according to claim 18, wherein said dielectric film collectively covers upper surfaces of said buried capacitor electrodes.

21. 21. The semiconductor device according to claim 20, wherein the recess is formed at a position facing the capacitor trench with the dielectric film interposed therebetween.

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