Template substrate, semiconductor substrate and method of manufacturing semiconductor device

Abstract

To provide a template substrate, a semiconductor substrate and a method of manufacturing a semiconductor device.SOLUTION: There is provided a template substrate (7) that comprises a main substrate having an edge (E), a peripheral edge part (1S) including the edge, and a non-peripheral edge part (1P) located inside the peripheral edge part, and a mask pattern located above the main substrate, wherein the mask pattern has a mask part (5), a plurality of first opening parts (KF) which have widths in a first direction and lengths in a second direction, and overlap with the non-peripheral edge part (1P) in plan view, and one or more second opening parts (KB) arranged along the edge in plan view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a template substrate and the like. [Background technology]

[0002] Patent Document 1 discloses a technique for forming a plurality of semiconductor portions corresponding to a plurality of openings in a mask, respectively, by using an ELO (Epitaxial Lateral Overgrowth) method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication "JP Patent Publication No. 2011-66390" Summary of the Invention

[0004] The template substrate according to the present disclosure comprises a main substrate having an edge, a peripheral portion including the edge, and a non-peripheral portion located more inward than the peripheral portion, and a mask pattern located above the main substrate, the mask pattern having a mask portion, a first direction being the width direction and a second direction being the length direction, a plurality of first openings overlapping the non-peripheral portion in a planar view, and one or more second openings arranged along the edge in a planar view. [Brief description of the drawings]

[0005] [Figure 1] FIG. 2 is a plan view showing a configuration of a template substrate according to the present embodiment. [Diagram 2] FIG. 2 is a cross-sectional view (non-peripheral part) taken along the line aa in FIG. [Diagram 3] FIG. 2 is a cross-sectional view (peripheral portion) taken along the line bb in FIG. [Figure 4] 1 is a plan view showing a configuration of a semiconductor substrate according to an embodiment of the present invention. [Figure 5A] 5 is a cross-sectional view taken along the line AA in FIG. 4. [Figure 5B] FIG. 5 is a cross-sectional view taken along the line cc in FIG. 4 . [Figure 6] 10 is a cross-sectional view showing another configuration of the semiconductor substrate according to the embodiment. [Figure 7] 10 is a cross-sectional view showing another configuration of the semiconductor substrate according to the embodiment. [Figure 8] 4 is a flowchart showing an example of a method for manufacturing a template substrate according to the present embodiment. [Figure 9] FIG. 1 is a block diagram showing an example of a template substrate manufacturing apparatus according to an embodiment of the present invention. [Figure 10] 2 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to the present embodiment. [Figure 11] 1 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to an embodiment of the present invention; [Figure 12] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the present embodiment. [Figure 13] FIG. 2 is a plan view showing an example of separation of an element portion. [Figure 14] 11 is a cross-sectional view showing an example of separation and isolation of element portions. FIG. [Figure 15] FIG. 1 is a schematic diagram illustrating a configuration of an electronic device according to an embodiment of the present invention. [Figure 16] 10 is a schematic diagram showing another configuration of the electronic device according to the embodiment. FIG. [Figure 17] FIG. 2 is a plan view showing the configuration of a template substrate according to the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view taken along the arrow dd in FIG. [Figure 19] 1 is a plan view showing a configuration of a semiconductor substrate according to a first embodiment. [Figure 20] 1 is a cross-sectional view showing an example of lateral growth of an ELO semiconductor portion. [Figure 21] 4 is a plan view showing another configuration of the template substrate according to the first embodiment. FIG. [Figure 22] 22 is a plan view showing a configuration of a semiconductor substrate including the template substrate of FIG. 21. [Diagram 23]4 is a plan view showing another configuration of the template substrate according to the first embodiment. FIG. [Figure 24] 4 is a plan view showing another configuration of the template substrate according to the first embodiment. FIG. [Diagram 25] FIG. 11 is a plan view showing a configuration of a template substrate according to a second embodiment. [Figure 26] FIG. 11 is a plan view showing a configuration of a semiconductor substrate according to a second embodiment. [Figure 27] FIG. 11 is a plan view showing another configuration of the template substrate according to the second embodiment. [Figure 28] FIG. 11 is a plan view showing another configuration of the template substrate according to the second embodiment. [Figure 29] 10 is a schematic cross-sectional view showing the configuration of Example 4. [Diagram 30] FIG. 11 is a cross-sectional view showing an example of application of the fourth embodiment to an electronic device. [Diagram 31] FIG. 11 is a schematic cross-sectional view showing the configuration of Example 5. [Diagram 32] FIG. 13 is a cross-sectional view showing the configuration of Example 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Template substrate] Fig. 1 is a plan view showing the configuration of a template substrate according to this embodiment, Fig. 2 is a cross-sectional view (non-peripheral portion) taken along line aa in Fig. 1, and Fig. 3 is a cross-sectional view (peripheral portion) taken along line bb in Fig. 1.

[0007] 1, the template substrate 7 according to the present embodiment includes a main substrate 1 having an edge E (end face, side face), a peripheral portion 1S including the edge E, and a non-peripheral portion 1P located inside the peripheral portion 1S, and a mask pattern 6 (mask layer) located above the main substrate 1. The mask pattern 6 has a mask portion 5, a first direction (X direction) as a width direction and a second direction (Y direction) as a length direction, a plurality of first openings KF overlapping with the non-peripheral portion 1P in a plan view, and a plurality of second openings KB arranged along the edge E in a plan view. The template substrate 7 can be used for forming a semiconductor portion (semiconductor layer), for example, for forming a GaN-based semiconductor portion (GaN-based semiconductor crystal) by the ELO (Epitaxial Lateral Overgrowth) method.

[0008] In FIG. 1, the edge E (side surface, end surface) of the main substrate 1 includes a curved surface Er and a flat surface Ef, but is not limited to this, and the edge E may be composed of only a curved surface or a flat surface.

[0009] Each first opening KF only needs to overlap with the non-peripheral portion 1P in a planar view, and may be located entirely in the non-peripheral portion 1P, or may have a portion located in the peripheral portion 1S and the remaining portion located in the non-peripheral portion 1P.

[0010] The second openings KB may be located along the edge E in a plan view. Each second opening KB may be located entirely in the non-peripheral portion 1P, entirely in the peripheral portion 1S, or partly in the non-peripheral portion 1P with the remaining part in the peripheral portion 1S.

[0011] In FIG. 1, the mask pattern 6 includes a plurality of second openings KB, but is not limited thereto and may include only one. The shape of the second opening KB may be a rectangle with the Y direction or the X direction as the longitudinal direction, a square or a circle, or a ring or curved longitudinal shape. One of the plurality of second openings KB may have a different shape from the other. For example, the mask pattern 6 may include a plurality of second openings KB with different lengths in at least one of the X direction and the Y direction, or may include a ring-shaped second opening KB and a rectangular second opening.

[0012] The template substrate 7 may have an underlayer 4 including a seed layer 3 above the main substrate 1, and may be configured such that the seed portion 3S of the seed layer 3 is exposed at least in the first and second openings KF and KB. The first and second openings KF and KB may have a tapered shape (a shape in which the width narrows toward the underlayer 4 side).

[0013] 1, multiple layers are stacked on the main substrate 1, and the stacking direction can be referred to as the "upward direction." Also, viewing a substrate-like object such as the template substrate 7 from a line of sight parallel to the substrate normal can be referred to as a "planar view."

[0014] [Semiconductor Substrate] FIG. 4 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 5A is a cross-sectional view taken along line AA in FIG. 4. FIG. 5B is a cross-sectional view taken along line cc in FIG. 4. As shown in FIGS. 4, 5A and 5B, the semiconductor substrate 10 includes a template substrate 7 and first and second semiconductor portions 8F-8B located above the mask pattern 6. The term "semiconductor substrate" refers to a substrate including a semiconductor portion, and the main substrate 1 may be a semiconductor or a non-semiconductor. At least one of the first and second semiconductor portions 8F-8B may be a layered semiconductor layer.

[0015] The first and second semiconductor portions 8F and 8B include, for example, a nitride semiconductor. The nitride semiconductor can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductor, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor that includes gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The first and second semiconductor portions 8F and 8B may be doped (for example, n-type including donors) or non-doped.

[0016] The first and second semiconductor portions 8F and 8B including nitride semiconductors can be formed by the ELO method. In the ELO method, for example, a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor is used as the main substrate 1, a GaN-based semiconductor is used for the seed portion 3S, an inorganic compound film is used for the mask pattern 6, and the GaN-based first and second semiconductor portions 8F and 8B are grown laterally on the mask portion 5. In this case, the thickness direction (Z direction) of the first semiconductor portion 8F can be made to be a GaN-based crystal. <0001> The direction (c-axis direction) of the first and second openings KF·KB, which are elongated, can be the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the first and second openings KF·KB can be the <1-100> direction (m-axis direction) of the GaN-based crystal. The first semiconductor portion 8F or the first and second semiconductor portions 8F·8B formed by the ELO method may be collectively referred to as ELO semiconductor portion (ELO semiconductor layer) 8.

[0017] The first semiconductor portion 8F formed by the ELO method includes a plurality of ridge portions 8U corresponding to the respective first openings KF, and each ridge portion 8U has a longitudinal direction in the Y direction. The ridge portion 8U includes a low defect portion (dislocation non-inheritance portion) EK having relatively few threading dislocations, and a dislocation inheritance portion NS having relatively many threading dislocations, which overlaps with the first opening KF in a planar view. When an active layer (e.g., a layer in which electrons and holes combine) is formed above the first semiconductor portion 8F, the active layer can be provided so as to overlap with the low defect portion EK in a planar view. In the low defect portion EK, <0001> The non-threading dislocation density in a cross section parallel to the direction may be greater than the threading dislocation density.

[0018] Threading dislocations are dislocations (defects) that extend from the lower surface or inside of the first semiconductor portion 8F to its surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Threading dislocations can be observed by performing CL (cathode luminescence) measurement on the surface (parallel to the c-plane) of the first semiconductor portion 8F. Non-threading dislocations are dislocations that are measured by CL in a cross section parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations. The cross section parallel to the thickness direction is, for example, the (1-100) plane (m-plane) or the (11-20) plane (a-plane).

[0019] In FIG. 4 and FIG. 5, each ridge portion 8U of the first semiconductor portion 8F is separated from the second semiconductor portion 8B. Since the first opening portion KF is separated from the second opening portion KB arranged along the edge E (closer to the edge than the first opening portion KF), even if the second semiconductor portion 8B overlapping with the second opening portion KB in a planar view becomes an unintended deformed shape, the first semiconductor portion 8F overlapping with the first opening portion FK in a planar view is unlikely to meet with the second semiconductor portion 8B and is unlikely to be affected by it. That is, in this embodiment, the shape of the first semiconductor portion 8F can be guaranteed by using the second semiconductor portion 8B as a sacrificial layer. As shown in FIG. 4 and FIG. 5, when the second semiconductor portion 8B becomes an unintended deformed shape, the average thickness of the second semiconductor portion 8B may become smaller than the average thickness of the first semiconductor portion 8F due to an increase in raw material consumption.

[0020] For example, when an opening extending in the Y direction is formed in a mask pattern so as to extend from edge to edge of the main substrate in a planar view, and a semiconductor portion is formed by the ELO method, there is a risk that shape disturbance in the semiconductor portion in the peripheral portion will propagate to the semiconductor portion on the inside (non-peripheral portion); however, this risk can be reduced by providing a second opening KB separated from the first opening KF.

[0021] 6 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 6, it is also possible to configure a semiconductor substrate 10 from which the second semiconductor portion 8B, which is a sacrificial layer, has been removed.

[0022] Fig. 7 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. The semiconductor substrate 10 in Fig. 7 has a functional layer 9 above the first and second semiconductor portions 8F and 8B. The functional layer 9 may be a compound semiconductor portion including, for example, a nitride semiconductor, and may be a single layer or a laminate.

[0023] In the semiconductor substrate 10 of FIG. 7, the portion including the second semiconductor portion 8B, which is the sacrificial layer, is the unusable portion NP, and the portion including the first semiconductor portion 8F is the usable portion DP.

[0024] [Manufacturing of template substrate] Fig. 8 is a flowchart showing an example of a method for manufacturing a template substrate according to this embodiment. In the method for manufacturing a template substrate in Fig. 8, after the step of preparing a main substrate 1, a step of forming a mask pattern 6 above the main substrate 1 is performed.

[0025] Fig. 9 is a block diagram showing an example of a template substrate manufacturing apparatus according to the present embodiment. The template substrate manufacturing apparatus 60 in Fig. 9 includes a mask pattern forming unit 62 that forms a mask pattern 6 above the main substrate 1, and a control unit 64 that controls the mask pattern forming unit 62. The mask pattern forming unit 62 forms a mask portion 5, a plurality of first openings KF that overlap with the non-peripheral portion 1P in planar view, with the X direction as the width direction and the Y direction as the length direction, and one or more second openings KB that are arranged along the edge E in planar view.

[0026] The mask pattern forming unit 62 may include a CVD device or a PECVD device, and the control unit 64 may include a processor and a memory. The control unit 64 may be configured to control the mask pattern forming unit 62 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network, and this program and a recording medium on which this program is stored are also included in this embodiment.

[0027] [Manufacturing of Semiconductor Substrates] Fig. 10 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to this embodiment. In the method for manufacturing a semiconductor substrate in Fig. 10, after the step of preparing a template substrate 7, a step of forming first and second semiconductor portions 8F and 8B on the template substrate 7 by using an ELO method is performed. After the step of forming the first and second semiconductor portions 8F and 8B, a step of forming a functional layer 9 can be performed as necessary.

[0028] Fig. 11 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to the present embodiment. The semiconductor substrate manufacturing apparatus 70 in Fig. 11 includes a semiconductor portion forming section 72 that forms first and second semiconductor portions 8F and 8B on a template substrate 7 by the ELO method, and a control section 74 that controls the semiconductor portion forming section 72. The semiconductor substrate manufacturing apparatus 70 may be configured to form a functional layer 9.

[0029] [Semiconductor device manufacturing] FIG. 12 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the present embodiment. FIG. 13 is a plan view showing an example of separation of an element portion. FIG. 14 is a cross-sectional view (cross-sectional view taken along the arrow in FIG. 13) showing an example of separation and isolation of an element portion. In the method for manufacturing a semiconductor device shown in FIG. 12, after the step of preparing a semiconductor substrate 10, a step of forming a functional layer 9 on the first and second semiconductor portions 8F and 8B is performed as necessary. Thereafter, as shown in FIG. 13 and FIG. 14, a step of forming a plurality of trenches TR (separation grooves) in the semiconductor substrate 10 to separate the element portion DS (including the low defect portion EK of the ridge portion 8U and the functional layer 9) is performed. The trenches TR penetrate the functional layer 9 and the first semiconductor portion 8F. The underlayer 4 and the mask portion 5 may be exposed in the trenches TR. At this stage, the element portion DS is van der Waals bonded to the mask portion 5 and is a part of the semiconductor substrate 10. 14, a process is performed in which the element portion DS (including at least a part of the ridge portion 8U) of the usable portion DP is separated from the template substrate 7 to form a semiconductor device 20. The process of preparing the semiconductor substrate 10 in FIG. 12 may include each of the steps of the method for manufacturing a semiconductor substrate shown in FIG.

[0030] The element portion DS may be isolated by removing the portions of the first semiconductor portion 8F and the functional layer 9 that overlap with the first opening portion KF in a plan view by vapor-phase etching, and peeling the element portion DS from the template substrate 7. During peeling, the first semiconductor portion 8F and the functional layer 9 can be easily peeled off from the mask portion 5 by using, for example, a stamp. The stamp may be a viscoelastic elastomer stamp, a PDMS (Polydimethylsiloxane) stamp, an electrostatic adhesive stamp, or the like.

[0031] [Semiconductor Devices] 14, a semiconductor device 20 (including, for example, a GaN-based crystal) can be formed by separating the element portion DS from the template substrate 7. Specific examples of the semiconductor device 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, transistors (including power transistors and high electron mobility transistors), and the like.

[0032] [Electronic equipment] Fig. 15 is a schematic diagram showing the configuration of an electronic device according to this embodiment. Electronic device 30 in Fig. 15 includes a semiconductor substrate 10 (a configuration that functions as a semiconductor device when including a template substrate 7, for example, when the template substrate 7 is light-transmitting), a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0033] Fig. 16 is a schematic diagram showing another configuration of the electronic device according to the present embodiment. The electronic device 30 in Fig. 16 includes a semiconductor device 20 including a first semiconductor portion 8F, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0034] Examples of the electronic device 30 include a display device, a laser emission device (including a Fabry-Perot type and a surface emission type), a lighting device, a communication device, an information processing device, a sensing device, and a power control device.

[0035] Example 1 Fig. 17 is a plan view showing the configuration of a template substrate according to Example 1. Fig. 18 is a cross-sectional view taken along the line dd in Fig. 17. Fig. 19 is a plan view showing the configuration of a semiconductor substrate according to Example 1.

[0036] 17 and 18, the mask pattern 6 of the template substrate 7 according to Example 1 has a mask portion 5, a plurality of first openings KF1-KF2 whose width direction is the X direction and whose length direction is the Y direction, overlapping with the non-peripheral portion 1P in a planar view, and a plurality of second openings KB1-KB4 arranged along the edge E in a planar view. The peripheral portion 1S can be, for example, a region within 2 mm from the edge E.

[0037] (Main board) The main substrate 1 may be a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor. Examples of heterogeneous substrates include a single crystal silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation may be used as long as the first and second semiconductor portions 8F and 8B can be grown by the ELO method.

[0038] (base layer) As the underlayer 4, a buffer layer 2 and a seed layer 3 can be provided in this order from the main substrate side. The buffer layer 2 has a function of reducing the melting of the main substrate 1 and the seed layer 3 due to direct contact between them. When a silicon substrate or the like is used for the main substrate 1, the silicon substrate melts with the GaN-based semiconductor which is the seed layer 3, so that melting can be reduced by providing a buffer layer 2 such as an AlN layer. For example, when a main substrate 1 which does not melt with the seed layer 3 which is a GaN-based semiconductor is used, it is also possible to configure without providing the buffer layer 2. An AlN layer which is an example of the buffer layer 2 can be formed to a thickness of about 10 nm to about 5 μm using, for example, an MOCVD apparatus. The buffer layer 2 may have at least one of the effects of increasing the crystallinity of the seed layer 3 and the effect of relaxing the internal stress of the ELO semiconductor portion 8. The buffer layer 2 can also be made of silicon carbide (SiC) of a hexagonal or cubic crystal system.

[0039] For example, a GaN-based semiconductor such as GaN, a nitride such as AlN, or hexagonal silicon carbide (SiC) can be used for the seed layer 3. The seed layer 3 includes a seed portion 3S (a growth starting point of the ELO semiconductor portion 8) overlapping with the first and second openings (KF1 to KF2 and KB1 to KB4) of the mask pattern 6.

[0040] A graded layer in which the Al composition approaches GaN in a graded manner may be used as the seed layer 3. The graded layer may be, for example, a first layer of Al 0.7 Ga 0.3 N layer and the second layer, Al 0.3 Ga 0.7 The graded layer is a laminate having an N layer. In this case, the Ga composition ratio (0.7 / 2=0.35) in the second layer (Al:Ga:N=0.3:0.7:1) is greater than the Ga composition ratio (0.3 / 2=0.15) in the first layer (Al:Ga:N=0.7:0.3:1). The graded layer can be easily formed by MOCVD and may be composed of three or more layers. By using a graded layer for the seed layer 3, it is possible to relieve stress from the main substrate 1, which is a heterogeneous substrate. The seed layer 3 may be composed of a GaN layer. In this case, the seed layer 3 may be a single layer of GaN, or the top layer of the graded layer, which is the seed layer 3, may be a GaN layer.

[0041] Note that the seed layer 3 does not necessarily have to be disposed on the main substrate 1. Depending on the type of the main substrate 1, even without the seed layer, the ELO semiconductor portion 8 can be directly deposited on the main substrate 1 having the mask pattern 6 disposed thereon. For example, it is also possible to form the mask pattern 6 including the mask portion 5 and the first opening portion KF on the SiC substrate 1, and to deposit (directly) the ELO semiconductor portion 8 made of GaN on the mask pattern.

[0042] (Mask pattern) The first opening KF of the mask pattern 6 (mask layer) functions as a growth initiation hole that exposes the seed portion 3S and initiates the growth of the ELO semiconductor portion 8, and the mask portion 5 may function as a selective growth mask for growing the semiconductor portion 8 laterally. The opening of the mask pattern is a portion where there is no mask portion (non-formation portion), and may or may not be surrounded by the mask portion. The mask pattern 6 may be, for example, a single layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher) (e.g., a film of platinum, rhodium, iridium, ruthenium, osmium, tungsten, molybdenum, etc.), or a laminate film including at least two of these.

[0043] For example, a silicon oxide film with a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the underlayer 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned by photolithography to form a resist with a plurality of stripe-shaped openings. Parts of the silicon oxide film are then removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including KF1 to KF2, KB1 to KB4), and the resist is removed by organic cleaning to form the mask pattern 6.

[0044] The width of the first openings KF1 and KF2 is approximately 0.1 μm to 20 μm. The smaller the width of the first openings KF1 and KF2, the fewer the number of threading dislocations propagating from the first openings KF1 and KF2 to the ELO semiconductor portion 8. Also, it becomes easier to peel (separate) the ELO semiconductor portion 8 from the template substrate 7 in a later process. Furthermore, the area of ​​the low-defect portion EK with few surface defects in the ELO semiconductor portion 8 (ridge portion 8U) can be increased.

[0045] A small amount of silicon oxide film may decompose and evaporate during the formation of ELO semiconductor portion 8 and may be taken into ELO semiconductor portion 8, but a silicon nitride film and a silicon oxynitride film have the advantage of being less likely to decompose and evaporate at high temperatures. Therefore, mask portion 5 may be a single layer film of silicon nitride film or silicon oxynitride film, or a laminate film in which a silicon oxide film and a silicon nitride film are formed in this order on underlayer 4, or a laminate film in which a silicon nitride film and a silicon oxide film are formed in this order on underlayer 4, or a laminate film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on underlayer.

[0046] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, and then re-introducing the mask portion 5 into the film formation apparatus to form a film of the same type. A good quality mask portion 5 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method again.

[0047] In the first embodiment, in a plan view, the minimum distance between the first openings KF1 and KF2 and the edge E is greater than the distance between the second openings KB1 to KB4 and the edge E. The first openings (including KF1 and KF2) are arranged in the X direction, and the length of each opening in the Y direction decreases with increasing distance from the main substrate center MC in the X direction. For example, the first opening KF2 is greater in distance from the main substrate center MC in the X direction and has a smaller length in the Y direction than the first opening KF1. The minimum length Yf of the first openings (including KF1 and KF2) in the Y direction is greater than the length Yb of the second openings (including KB1 to KB4) in the Y direction. The number of the second openings (including KB1 to KB4) is equal to twice the number of the first openings (including KF1 and KF2).

[0048] Moreover, the first opening KF1 and the second opening KB1 are adjacent to each other and overlap when viewed in the Y direction, and the first opening KF1 is located between two second openings KB1 and KB3 arranged in the Y direction. That is, the second opening KB1, the first opening KF1, and the second opening KB3 are arranged in the Y direction, and one end of the first opening KF1 is adjacent to the second opening KB1, and the other end is adjacent to the second opening KB3. The interval between the first opening KF1 and the second opening KB1 and the interval between the first opening KF1 and the second opening KB3 are larger than the interval between the second openings KB1 and KB3 and the edge E. The width (length in the X direction) of the second openings KB1 and KB3 may be the same as, larger than, or smaller than the width of the first opening KF1. The widths of the multiple second openings KB1 to KB4 may be different from each other.

[0049] In plan view, the aperture pattern including the plurality of first apertures KF1 and KF2 and the plurality of second apertures KB1 to KB4 may be symmetrical with respect to a line that passes through the main substrate center MC and is parallel to the X direction.

[0050] In the first embodiment, the edge E of the main substrate 1 has a curved portion Er and a flat portion Ef that is connected to the curved portion Er and has a normal line parallel to the X direction, but is not limited to this. The main substrate 1 may be disk-shaped. The flat portion Ef may function as a surface orientation mark (orientation flat). The surface orientation mark may be a notch (cutout).

[0051] (Specific example of template substrate) The main substrate 1 is a silicon substrate having a (111) surface, and the buffer layer 2 of the underlayer 4 is an AlN layer (for example, 30 nm). 0.6 Ga 0.4 A graded layer is formed in this order of an N layer (e.g., 300 nm) and a second layer, a GaN layer (e.g., 1 to 2 μm). That is, the Ga composition ratio (1 / 2=0.5) in the second layer (Ga:N=1:1) is greater than the Ga composition ratio (0.6 / 2=0.3) in the first layer (Al:Ga:N=0.6:0.4:1).

[0052] A laminated body in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) are formed in this order is used for the mask portion 5. The silicon oxide film has a thickness of, for example, 0.3 μm, and the silicon nitride film has a thickness of, for example, 70 nm. The silicon oxide film and the silicon nitride film are each formed by a plasma chemical vapor deposition (CVD) method.

[0053] (ELO Semiconductor Division) 19, the semiconductor substrate 10 of the first embodiment includes a first semiconductor portion 8F overlapping with the first openings KF1 and KF2 in a plan view, and a second semiconductor portion 8B overlapping with the second openings KB1 and KB2 in a plan view. The first and second semiconductor portions 8F and 8B may be ELO semiconductor portions including a nitride semiconductor (e.g., a GaN-based ELO semiconductor portion).

[0054] The first semiconductor portion 8F has a longitudinal direction in the Y direction and includes a plurality of ridge portions 8U aligned in the X direction. The end of each ridge portion 8U is tapered, and in the first embodiment, a plurality of second openings KB1 and KB2 are provided along the edge E. This separates each ridge portion 8U of the first semiconductor portion 8F from the irregularly shaped second semiconductor portion 8B (sacrificial layer), and ensures the shape (e.g., thickness and width) of each ridge portion 8U.

[0055] In Example 1, the first and second semiconductor portions 8F and 8B were GaN layers, and ELO film formation was performed on the above-mentioned template substrate 7 using an MOCVD apparatus included in the semiconductor formation portion 72 of Fig. 11. As an example of the ELO film formation conditions, the following can be adopted: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, V / III = 6000 (ratio of the supply amount of group V raw material to the supply amount of group III raw material).

[0056] In this case, the first and second semiconductor portions 8F and 8B are selectively grown on the seed portion 3S (the GaN layer that is the uppermost layer of the seed layer 3) exposed in the first and second openings KF1, KF2, KB1, and KB2, and then grow laterally on the mask portion 5. Then, this lateral growth is stopped before the films (ridge portions 8U) that have grown laterally from both sides of the mask portion 5 meet each other.

[0057] The width Wm of the mask portion 5 was 50 μm, the width of the first openings KF1 and KF2 was 5 μm, the horizontal width of each ridge portion 8U of the first semiconductor portion 8F was 53 μm, the width (size in the X direction) of the low defect portion EK was 24 μm, and the layer thickness of the ridge portion 8U was 5 μm. The aspect ratio was 53 μm / 5 μm = 10.6, which is an extremely high aspect ratio.

[0058] In forming the first semiconductor portion 8F, it is preferable to reduce mutual reaction between the first semiconductor portion 8F and the mask portion 5 and to place the first semiconductor portion 8F and the mask portion 5 in contact with each other by van der Waals forces.

[0059] The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer that grows in the Z direction (c-axis direction) is formed on the seed portion 3S, and then a horizontally grown layer that grows in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertically grown layer to 10 μm or less, 5 μm or less, 3 μm or less, or 1 μm or less, the thickness of the horizontally grown layer can be kept low and the lateral film formation rate can be increased.

[0060] 20 is a cross-sectional view showing an example of lateral growth of the first semiconductor portion. As shown in FIG. 20, it is preferable to form an initial growth layer (vertical growth layer) SL on a seed portion 3S, and then grow the first semiconductor portion 8F (multiple ridge portions 8U) laterally from the initial growth layer SL. The initial growth layer SL serves as a starting point for the lateral growth of the first semiconductor portion 8F. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the first semiconductor portion 8F to the Z direction (c-axis direction) or the X direction (a-axis direction).

[0061] Here, a method can be used in which the deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where the edge is in contact with the upper end of the side surface of the mask portion 5) or just after the edge rises onto the upper surface of the mask portion 5 (i.e., the ELO deposition conditions are switched from the c-axis deposition conditions to the a-axis deposition conditions at this timing). In this way, the lateral deposition progresses from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that the material consumed for the growth in the thickness direction is reduced, and the first semiconductor portion 8F (the plurality of ridge portions 8U) can be grown in the lateral direction at a high speed. The initial growth layer SL can be formed to a thickness of, for example, 50 nm to 5.0 μm (for example, 80 nm to 2 μm). The thickness of the mask portion 5 and the thickness of the initial growth layer SL may be 500 nm or less.

[0062] As shown in FIG. 20, the ridge portion 8U of the first semiconductor portion 8F can be grown laterally after the initial growth layer SL (part of the dislocation inheritance portion NS) is formed, thereby increasing the number of non-threading dislocations in the low defect portion EK (reducing the threading dislocation density on the surface of the low defect portion EK). In addition, the distribution of the impurity concentration (e.g., silicon, oxygen) in the low defect portion EK can be controlled. By using the method of FIG. 20, the aspect ratio (ratio of the size in the X direction to the thickness=WL / d1) of the ridge portion 8U can be dramatically increased to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more. 20, the ratio of the width (WL) of the ridge portion 8U to the opening width can be set to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the ratio of low defect portions EK. The first semiconductor portion 8F shown in FIG. 20 can be a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0063] The deposition temperature of the ELO semiconductor portion 8 (first and second semiconductor portions 8F and 8B) is preferably 1150°C or lower, rather than a high temperature exceeding 1200°C. It is also possible to form the ELO semiconductor portion 8 at a low temperature below 1000°C, which is more preferable from the viewpoint of reducing mutual reactions. In such low-temperature deposition, if trimethylgallium (TMG) is used as the gallium source, the source is not sufficiently decomposed, and gallium atoms and carbon atoms are simultaneously incorporated into the ELO semiconductor portion 8 in greater amounts than usual. This is thought to be because, with the ELO method, deposition in the a-axis direction is fast and deposition in the c-axis direction is slow, so that more is incorporated during deposition on the c-plane.

[0064] The carbon incorporated into ELO semiconductor portion 8 reduces reaction with mask portion 5 and reduces adhesion between mask portion 5 and ELO semiconductor portion 8. Therefore, in low-temperature deposition of ELO semiconductor portion 8, the amount of ammonia supplied is reduced and deposition is performed at a low V / III ratio (<1000), so that carbon elements in the raw material or chamber atmosphere can be incorporated into ELO semiconductor portion 8 and reaction with mask portion 5 can be reduced. In this case, ELO semiconductor portion 8 contains carbon.

[0065] It is preferable to use triethylgallium (TEG) as the gallium source gas for low-temperature film formation below 1000° C. TEG decomposes organic sources more efficiently at low temperatures than TMG, and can therefore increase the lateral film formation rate.

[0066] FIG. 21 is a plan view showing another configuration example of the template substrate according to the first embodiment. FIG. 22 is a plan view showing a configuration of a semiconductor substrate including the template substrate of FIG. 21. In FIG. 17, the first opening KF1 and the second opening KB1 are adjacent to each other and overlap when viewed in the Y direction, but this is not limited thereto. As shown in FIG. 21, the mask pattern 6 may include a plurality of first openings KF1 and KF2 and second openings KB1 to KB6 arranged along the edge E, and the first opening KF1 and the second opening KB1 may be adjacent to each other and overlap when viewed in the X direction. In FIG. 21, one end of the first opening KF2 is located between the second openings KB1 and KB2 arranged in the X direction, and the other end is located between the second openings KB3 and KB4 arranged in the X direction. In addition, the number of the multiple second openings (including KB1 to KB6) is more than twice the number of the multiple first openings (including KF1 and KF2), and in terms of the X direction, the second openings KB5 and KB6 are located outside the two first openings that are the outermost of all the first openings.

[0067] The semiconductor substrate 10 in FIG. 22 includes a first semiconductor portion 8F that overlaps the mask portion 5 and the first openings KF1 and KF2 in a plan view, and a second semiconductor portion 8B that overlaps the mask portion 5 and the second openings KB1 and KB2 in a plan view, and the first semiconductor portion 8F includes a plurality of ridge portions 8U that overlap the first openings KF1 and KF2 in a plan view. In FIG. 11 and FIG. 22, the plurality of second openings KB1 and KB2 are also arranged along the edge E of the main substrate 1 in a plan view, so that each ridge portion 8U of the first semiconductor portion 8F is separated from the irregularly shaped second semiconductor portion 8B (sacrificial layer), and the shape of each ridge portion 8U is guaranteed. In addition, for example, the tip of the first opening KF2 is sandwiched between two second openings KB1 and KB2 arranged in the X direction, so that edge growth (convex portion) occurring at the tip of the ridge portion 8U that overlaps the first opening KF2 can be reduced.

[0068] Fig. 23 is a plan view showing another configuration example of the template substrate according to the first embodiment. In Fig. 23, the mask pattern is provided with a plurality of first openings KF1 and KF2 and second openings KB1 to KB6 arranged along the edge E of the main substrate 1 in a plan view, the second opening KB2, the first opening KF1, and the second opening KB5 are aligned in the Y direction, one end of the first opening KF1 is adjacent to the second opening KB2, and the other end is adjacent to the second opening KB5. Furthermore, one end of the first opening KF1 is located between the second openings KB1 and KB3 aligned in the X direction, and the other end is located between the second openings KB4 and KB6 aligned in the X direction.

[0069] Fig. 24 is a plan view showing another configuration example of the template substrate according to Example 1. As shown in Fig. 24, a main substrate 1 including a curved surface portion Er can be used, and a plurality of second openings KB having a curved elongated shape can be arranged in a mask pattern 6 so as to follow an edge E of the main substrate 1 in a plan view.

[0070] Example 2 Fig. 25 is a plan view showing another configuration example of the template substrate according to the second embodiment. Fig. 26 is a plan view showing the configuration of a semiconductor substrate including the template substrate of Fig. 25. In the first embodiment, a plurality of second openings are provided in the mask pattern, but this is not limited thereto. As shown in Fig. 26, a main substrate 1 including a curved portion Er may be used, and an annular second opening KBL may be arranged in the mask pattern 6 so as to follow the edge E of the main substrate 1 in a plan view.

[0071] In the second embodiment, in a plan view, the minimum distance between the multiple first openings KF1-KF2 and the edge E is greater than the distance between the annular second opening KBL and the edge E. Also, the multiple first openings (including KF1-KF2) with the Y direction as their longitudinal direction are aligned in the X direction, and their Y direction lengths decrease with increasing distance from the main substrate center MC in the X direction.

[0072] Furthermore, the first opening KF1 and the second opening KBL are adjacent to each other and overlap when viewed in the Y direction. In a plan view, an opening pattern including the multiple first openings KF1-KF2 and the annular second opening KBL may have an axisymmetric shape with respect to a line that passes through the main substrate center MC and is parallel to the X direction.

[0073] The semiconductor substrate 10 in Figure 26 includes a first semiconductor portion 8F that overlaps with the first openings KF1 and KF2 in a planar view, and a second semiconductor portion 8B that overlaps with the second openings KBL in a planar view, and the first semiconductor portion 8F includes a plurality of ridge portions 8U that overlap with the first openings KF1 and KF2 in a planar view.

[0074] Also in Example 2, a ring-shaped second opening KBL is arranged so as to follow the edge E of the main substrate 1 in a planar view, so that each ridge portion 8U of the first semiconductor portion 8F is separated from the irregularly shaped second semiconductor portion 8B (sacrificial layer), and the shape of each ridge portion 8U is preserved.

[0075] FIG. 27 is a plan view showing another configuration example of the template substrate according to the second embodiment. In FIG. 27, the mask pattern 6 includes a plurality of first openings KF1 and KF2, an annular second opening KBL arranged along the edge E, and second openings KB1 to KB4 arranged along the edge E, and the first opening KF1 and the second opening KB1 may be adjacent to each other and overlap when viewed in the X direction. In FIG. 27, one end of the first opening KF2 is located between the second openings KB1 and KB2 arranged in the X direction, and the other end is located between the second openings KB3 and KB4 arranged in the X direction. In addition, the number of the plurality of second openings (including KB1 to KB4) is less than twice the number of the plurality of first openings (including KF1 and KF2), and no island-shaped second openings are present outside the two first openings that are the outermost positions of all the first openings in the X direction, and only the annular second opening KBL is present.

[0076] FIG. 28 is a plan view showing another configuration example of the template substrate according to the second embodiment. In FIG. 27, the mask portion 5 is present at the edge of the template substrate 7, but the present invention is not limited to this. As shown in FIG. 28, the template substrate 7 may have a configuration in which the mask portion is not present at the edge. That is, when the mask pattern 6 is patterned, the mask pattern 6 penetrates a ring-shaped region having the edge E of the main substrate 1 as the outer periphery in a plan view (provides a ring-shaped edge opening KE), thereby exposing the ring-shaped seed portion 3S at the edge of the template substrate 7. In the template substrate 7 of FIG. 28, a ring-shaped sacrificial layer is formed on the edge, so that the shape of the first semiconductor portion 8F overlapping with the first openings KF1 and KF2 is guaranteed.

[0077] Example 3 In the first and second embodiments, the ELO semiconductor portion 8 is a GaN layer, but is not limited thereto. The first and second semiconductor portions 8F and 8B (ELO semiconductor portion 8) in the first and second embodiments may be formed as InGaN layers, which are GaN-based semiconductor portions. The lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000° C. This is because at high temperatures, the vapor pressure of indium increases and indium is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable to incorporate indium into the InGaN layer at an In composition level of 1% or more, since this further reduces the reactivity with the mask portion 5. As the gallium source gas, triethylgallium (TEG) is preferably used.

[0078] Example 4 FIG. 29 is a schematic cross-sectional view showing the configuration of Example 4. In Example 4, a functional layer 9 constituting an LED is formed on a base semiconductor portion 8S obtained as all or a part of the ridge portion 8U of the first semiconductor portion 8F. The base semiconductor portion 8S is, for example, an n-type doped with silicon or the like. The functional layer 9 includes, in order from the lower layer side, an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor portion 36. The active layer 34 is an MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer. The electron blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor portion 36 is, for example, a GaN layer. The anode 38 is disposed so as to contact the GaN-based p-type semiconductor portion 36, and the cathode 39 is disposed so as to contact the base semiconductor portion 8S. A semiconductor device 20 (including a GaN-based crystal) can be obtained by separating the base semiconductor portion 8S and the functional layer 10 from the template substrate 7.

[0079] 30 is a cross-sectional view showing an application example of Example 6 to an electronic device. According to Example 4, a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B can be obtained, and by mounting these on a driving substrate (TFT substrate) 23, a micro LED display 30D (electronic device) can be configured. As an example, the red micro LED 20R, the green micro LED 20G, and the blue micro LED 20B are mounted on a plurality of pixel circuits 27 of the driving substrate 23 via a conductive resin 24 (e.g., anisotropic conductive resin), and then a control circuit 25, a driver circuit 29, and the like are mounted on the driving substrate 23. A part of the driver circuit 29 may be included in the driving substrate 23.

[0080] Example 5 FIG. 31 is a schematic cross-sectional view showing the configuration of Example 5. In Example 5, a functional layer 9 constituting a semiconductor laser is formed on a base semiconductor portion 8S. The functional layer 9 includes, in order from the bottom, an n-type optical cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type optical cladding layer 46, and a GaN-based p-type semiconductor portion 47. An InGaN layer can be used for each of the guide layers 42 and 45. A GaN layer or an AlGaN layer can be used for each of the cladding layers 41 and 46. An anode 48 is disposed so as to contact the GaN-based p-type semiconductor portion 47, and a cathode 49 is disposed so as to contact the base semiconductor portion 8S. A semiconductor device 20 can be obtained by separating the base semiconductor portion 8S and the functional layer 10 from the template substrate 7.

[0081] Example 6 FIG. 32 is a cross-sectional view showing the configuration of Example 6. In Example 6, a sapphire substrate with a surface textured surface is used as the main substrate 1. The underlayer 4 has a buffer layer 2 and a seed layer 3. In FIG. 32, a GaN layer having a (20-21) plane is formed as the underlayer 4 on the main substrate 1. In this case, the first semiconductor portion 8F has a (20-21) plane, which is the crystal main surface, in the underlayer 4, and the first semiconductor portion 8F having a semipolar plane can be obtained. By providing a functional layer for a laser or LED on the semipolar plane, there is an advantage that the probability of recombination of electrons and holes is increased in the active layer. In addition, by using a sapphire substrate with a surface textured surface, a GaN layer having a (11-22) plane can also be formed as the underlayer 4 on the main substrate 1. [Explanation of symbols]

[0082] 1 Main Board 2. Buffer layer 3 Seed layer 3S Seed Department 4 Base layer 5 Mask section 6 Mask Pattern 8F 1st Semiconductor Department 8B Second Semiconductor Section 8U ridge 9. Functional Layer 10. Semiconductor Substrate 20 Semiconductor Devices 30 Electronic equipment KF KF1 / KF2 1st opening KB KB1~KB6 2nd opening

Claims

1. a main substrate having an edge, a peripheral portion including the edge, and a non-peripheral portion located inside the peripheral portion; and a mask pattern located above the main substrate and having a mask portion; the mask pattern includes a plurality of first openings overlapping the non-peripheral portion in a plan view and a plurality of second openings overlapping the peripheral portion in a plan view; The plurality of first openings are aligned in a first direction and form a stripe shape.

2. The template substrate according to claim 1 , wherein a sum of areas of the second openings is smaller than a sum of areas of the first openings.

3. The template substrate according to claim 1 , wherein the first openings and the second openings are separated from each other.

4. The template substrate according to claim 1 , wherein the second openings are elongated in the first direction.

5. The template substrate of claim 4 , wherein a width of the second openings is greater than a width of the first openings.

6. The template substrate according to claim 1 , wherein the mask pattern is symmetrical with respect to a line that passes through a center of the main substrate and is parallel to a longitudinal direction of the plurality of first openings.

7. The template substrate according to any one of claims 1 to 6, wherein the plurality of second openings includes two adjacent openings, and the distance between the two openings is smaller than the distance between adjacent ones of the plurality of first openings.

8. 8. The template substrate according to claim 1, wherein at least one of the plurality of first openings is adjacent to the plurality of second openings, and when viewed in the longitudinal direction of the plurality of first openings, at least one of the plurality of first openings overlaps with at least one of the plurality of second openings.

9. The template substrate according to claim 1 , wherein the peripheral portion has an annular shape along the edge, and the non-peripheral portion is a region surrounded by the peripheral portion.

10. The template substrate according to claim 1 , further comprising a seed layer overlapping the first openings in a plan view.

11. The template substrate of claim 10 , wherein each of the first openings is a seed region for growing a semiconductor layer to be utilized, and each of the second openings is a seed region for growing a semiconductor layer to be unused.

12. The main substrate is a sapphire substrate or a silicon substrate; The template substrate according to any one of claims 1 to 11, which is used for ELO formation of a nitride semiconductor portion.

13. 13. A semiconductor substrate comprising: the template substrate according to claim 1; and a first semiconductor portion overlapping the mask portion.

14. the first semiconductor portion includes a nitride semiconductor, The longitudinal direction of the plurality of first openings is defined as a second direction, the first direction is an a-axis direction of the nitride semiconductor, The semiconductor wafer according to claim 13 , wherein the second direction is an m-axis direction of the nitride semiconductor.

15. Providing a semiconductor substrate according to claim 13; and forming a functional layer above the first semiconductor portion.

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