Communication system and communication method

Abstract

To enable appropriate I2C communication to be executed by communication devices connected by a transmission line other than an I2C bus.SOLUTION: According to an aspect of this disclosure, a system is a communication system including a first communication device and a second communication device connected by a transmission line other than an I2C bus. The first communication device includes a first processor having a master function of I2C, and a first relay part connected to a first bus, which is an I2C bus in the first communication device. The second communication device includes a second processor having a slave function of I2C, and a second relay part connected to a second bus, which is an I2C bus in the second communication device. The first relay part and the second relay part enable communication through the transmission line. The first relay part executes an operation of notifying the first relay part of a signal of the first bus, and an operation of outputting to the first bus a signal of the second bus notified from the second relay part. The second relay part executes an operation of outputting to the second bus a signal of the first bus notified from the first relay part, and an operation of notifying the second relay part of a signal of the second bus.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a communication system and a communication method. [Background technology]

[0002] Patent document 1 discloses a slave device for I2C (Inter-Integrated Circuit) communication that is assigned a unique address and can be set to a disabled mode in which it does not respond to access requests, regardless of whether the slave address accompanying the access request matches or does not match the unique address. According to the slave device of Patent Document 1, by executing the above-mentioned disable mode, it is possible to prevent a slave device that is busy performing other processing from monopolizing the I2C bus. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-232414 A Summary of the Invention [Problem to be solved by the invention]

[0004] I2C communication is generally used for serial communication between electronic components mounted on a single board. Therefore, Patent Document 1 does not consider an appropriate communication method when a transmission path other than the I2C bus, such as an optical fiber, is present between a master device and a slave device. In view of the above-mentioned problems in the related art, the present disclosure aims to enable appropriate I2C communication to be performed between communication devices connected via a transmission path other than an I2C bus. [Means for solving the problem]

[0005] A system according to one embodiment of the present disclosure is a communication system including a first communication device and a second communication device connected by a transmission path other than an I2C bus, wherein the first communication device includes a first processor having an I2C master function and a first relay unit connected to a first bus, which is an I2C bus in the first communication device, and the second communication device includes a second processor having an I2C slave function and a second relay unit connected to a second bus, which is an I2C bus in the second communication device, and the first relay unit and the second relay unit are capable of communication via the transmission path.

[0006] In the above system, the first relay unit performs an operation of notifying the first relay unit of a signal of the first bus and an operation of outputting the signal of the second bus notified from the second relay unit to the first bus, and the second relay unit performs an operation of outputting the signal of the first bus notified from the first relay unit to the second bus and an operation of notifying the second relay unit of the signal of the second bus.

[0007] The present disclosure can be realized not only as a system and device having the above-mentioned characteristic configuration, but also as a program for causing a computer to execute such characteristic configuration. Furthermore, the present disclosure can be realized as a semiconductor integrated circuit that realizes part or all of the system and device. Effect of the Invention

[0008] According to the present disclosure, it is possible to execute appropriate I2C communication between communication devices connected via a transmission path other than an I2C bus. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a network connection diagram showing an example of the configuration of an optical communication system. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a master device and a slave device. [Diagram 3] FIG. 3 is a sequence diagram illustrating an example of a write operation of I2C communication. [Figure 4] FIG. 4 is a sequence diagram showing an example of a write operation of I2C communication (continuation of FIG. 3). [Diagram 5] FIG. 5 is a sequence diagram showing an example of a read operation of I2C communication. [Figure 6] FIG. 6 is a sequence diagram showing an example of a read operation of I2C communication (continuation of FIG. 5). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Overview of the embodiment of the present disclosure> Below, an overview of the embodiments of the present disclosure will be listed and described. (1) A system according to one aspect of this embodiment is a communication system including a first communication device and a second communication device connected by a transmission path other than an I2C bus, wherein the first communication device includes a first processor having an I2C master function and a first relay unit connected to the I2C bus in the first communication device, and the second communication device includes a second processor having an I2C slave function and a second relay unit connected to the I2C bus in the second communication device, and the first relay unit and the second relay unit are capable of communication via the transmission path.

[0011] In the communication system of this embodiment, the first relay unit performs an operation of notifying the first relay unit of a signal of the first bus and an operation of outputting the signal of the second bus notified from the second relay unit to the first bus, and the second relay unit performs an operation of outputting the signal of the first bus notified from the first relay unit to the second bus and an operation of notifying the second relay unit of the signal of the second bus.

[0012] According to the communication system of this embodiment, the first relay unit of the first communication device performs each of the above operations (first emulation), and the second relay unit of the second communication device performs each of the above operations (second emulation), so that appropriate I2C communication can be performed between the first communication device and the second communication device that are connected by a transmission path other than an I2C bus.

[0013] (2) In the communication system of (1) described above, the first relay unit may store at least one address set in the second processor, and the operation of notifying the first relay unit by the first relay unit may be executed on the condition that the address obtained from the signal of the first bus matches the stored address. In this case, appropriate I2C communication can be performed by responding to requests that include the stored address and not responding to requests that do not include the address.

[0014] (3) In the communication system of (1) or (2) described above, the first relay unit may perform clock stretching on the first bus when a write command is received from the first processor, and release the clock stretching on the condition that a response to the write command is received from the second relay unit. In this way, the first processor can be made to wait by clock stretching, so that the write operation can be executed appropriately even if, for example, a communication delay is large due to a long transmission path.

[0015] (4) In the communication system of (1) to (3) described above, the first relay unit may perform clock stretching on the first bus when a read command is received from the first processor, and release the clock stretching on the condition that read data is received from the second relay unit. In this way, the first processor can be made to wait by clock stretching, so that the read operation can be executed properly even if there is a large communication delay due to a long transmission path, for example.

[0016] (5) In the communication systems described above in (1) to (4), the transmission line may be a transmission line including an optical fiber. In this case, appropriate I2C communication can be performed between the first communication device and the second communication device that perform optical communication.

[0017] (6) In the communication systems described above in (1) to (5), a communication band for communication between the first relay unit and the second relay unit in the transmission path may be set to a low band that does not interfere with a communication band for a main signal in the transmission path. In this way, the I2C signal does not interfere with the main signal, so that the I2C signal can be transmitted reliably.

[0018] (7) A method according to one aspect of the present embodiment is a communication method executed in the communication system described above in (1) to (6). Therefore, the communication method of the present embodiment has the same effects as those of the communication systems described above in (1) to (6).

[0019] <Details of the embodiment of the present disclosure> Hereinafter, the details of the embodiments of the present disclosure will be described with reference to the drawings. Note that at least some of the embodiments described below may be combined in any combination.

[0020] [Example of optical communication system configuration] FIG. 1 is a network connection diagram showing an example of the configuration of an optical communication system 100. As shown in FIG. As shown in FIG. 1, communication nodes of an optical communication system 100 include a communication device 1, an optical communication device 2, an optical communication device 3, a communication device 4, and a controller 5. The communication device 1 and the optical communication device 2 are connected one-to-one by a metal cable 6. The optical communication device 2 and the optical communication device 3 are connected one-to-one by an optical fiber 7. The optical fiber 7 may be either a single-core bidirectional transmission or a dual-core transmission optical fiber.

[0021] The optical communication device 3 and the communication device 4 are connected one-to-one by a metal cable 8. The controller 5 is connected to the optical communication device 2 via a metal cable 9. However, the connections between the communication device 1 and the optical communication device 2, between the optical communication device 3 and the communication device 4, and between the optical communication device 2 and the controller 5 may be connections via a network such as a LAN (Local Area Network) rather than direct connections via metal cables 6, 8, and 9.

[0022] In this embodiment, the direction from communication device 1 to communication device 4 (to the right in FIG. 1) is referred to as the "downstream direction", and the opposite direction (to the left in FIG. 1) is referred to as the "upstream direction". Moreover, the upper optical communication device 2 to which the controller 5 is connected is referred to as the "master device 2," and the lower optical communication device 3 opposite the master device 2 is referred to as the "slave device 3."

[0023] The optical communication system 100 is a system in which optical communication devices 2 and 3 relay communications between user communication devices 1 and 4, and the optical communication devices 2 and 3 are under the management of a communication manager. The controller 5 is a management computer operated by, for example, a communications manager. The controller 5 is capable of transmitting setting information input by the operations manager to the master device 2.

[0024] In this embodiment, the physical transmission that realizes the logical "data communication" derived from the communication frames exchanged between the communication device 1 and the communication device 4 is called "main signal transmission." In addition, the communication for setting the setting information related to the quality of the optical communication and the like (for example, the operating wavelength and transmission speed of the optical signal) in the optical communication devices 2 and 3 is called "management communication," and the signal exchanged during the management communication is called "management signal."

[0025] As shown in FIG. 1, in the section from communication device 1 to master device 2 and in the section from slave device 3 to communication device 4, only main signal transmission is carried out. As shown in FIG. 1, in the section from the master device 2 to the slave device 3, a main signal and a management signal are superimposed and transmitted.

[0026] When the received setting information is setting information for the master device 2, the master device 2 performs management communication using an internal bus (for example, I2C communication) to apply the setting information to the device of the master device 2. If the received setting information is setting information for the slave device 3, the master device 2 performs management communication with the slave device 3 to notify the slave device 3 of the setting information.

[0027] For management communication between the master device 2 and the slave device 3, for example, Auxiliary Management and Control Channel (AMCC), which is a type of in-channel control technology, is used. AMCC is a transmission method in which a weak and low-speed (low-bandwidth in terms of frequency) intensity modulation is superimposed on the main signal so as not to affect reception of the main signal. In this case, the low-speed intensity-modulated signal serves as the supervisory signal.

[0028] [Example of master device configuration] FIG. 2 is a block diagram showing an example of the configuration of the master device 2 and the slave device 3. As shown in FIG. 2, the master device 2 of this embodiment includes a main signal processing unit 21, an AMCC processing unit 22, a combining circuit 23A, a distribution circuit 23B, an optical transceiver 24, an upper-side relay unit 25, and a management control unit 26. As described later, the management control unit 26 may be abbreviated as "MA", and the upper-side relay unit 25 may be abbreviated as "MR".

[0029] The optical transceiver 24 is an optical module that converts optical signals into electrical signals and vice versa, and may be, for example, an on-off keying optical transceiver of the CFP (Centum Form-factor Pluggable) type conforming to the MSA (Multi-Source Agreement) standard. The optical transceiver 24 may be a small form factor pluggable (SFP) type optical transceiver. The SFP type is a general term for SFP, SFP+, SFP28, QSFP, QSFP28, and their upwardly compatible pluggable optical modules.

[0030] The optical transceiver 24 may be a digital coherent optical transceiver. In this case, the main signal processing unit 21 and the optical transceiver 24 are connected by a plurality of analog signals according to the modulation method, and one analog signal is modulated by AMCC.

[0031] The optical transceiver 24 has a function of switching the wavelength of the optical signal used in optical communication. The optical signal may be a subcarrier. When the optical signal is divided into subcarriers, the optical transceiver 24 may have a switching function that uses the subcarrier as the wavelength. As the optical transceiver 24 having a wavelength switching function, an optical transceiver using a subcarrier multiplexing (SCM) system, or a multi-channel WDM (Wavelength Division Multiplexing) optical transceiver using a wavelength multiplexing system can be used.

[0032] In this case, when using AMCC, at least one subcarrier or wavelength may be further modulated by AMCC. Note that at least one subcarrier or wavelength may be assigned to a management signal without using AMCC.

[0033] The main signal processing unit 21, the AMCC processing unit 22, the combining circuit 23A, the distribution circuit 23B, and the upper side relay unit 25 may be configured using one or more integrated circuits. The integrated circuit may be at least one of a central processing unit (CPU), a field-programmable gate array (FPGA), and an application specific integrated circuit (ASIC).

[0034] The management control unit 26 is a processor having a communication function with the controller 5 and an I2C communication function. The management control unit 26 can be configured with one or more integrated circuits having a CPU and a volatile memory. The management control unit 26 may include at least one of an FPGA and an ASIC in addition to the CPU.

[0035] The optical transceiver 24 includes a processor 24A for adjusting the operating wavelength, etc. The processor 24A is, for example, a micro processing unit (MPU). The management control unit 26, the processor 24A, and the upper side relay unit 25 are each connected to an I2C bus 27. The management control unit 26 functions as an I2C master, and the processor 24A functions as an I2C slave. The upper side relay unit 25 of the master device 2 functions as an I2C slave with respect to the management control unit 26.

[0036] The management control unit 26 takes the lead in management communication using I2C communication. Specifically, when the management control unit 26 acquires setting information of the optical transceiver 24 from the controller 5, the management control unit 26 transmits the setting information to the processor 24A by I2C communication. When the management control unit 26 acquires the setting information of the optical transceiver 34 of the slave device 3, the management control unit 26 transmits the setting information to the upper relay unit 25 by I2C communication.

[0037] The upper relay unit 25 has a memory 25A that holds the address of at least one slave in the slave device 3 (the processor 34A in FIG. 2). When a plurality of slaves are mounted in the slave device 3, the addresses of the slaves are stored as a list in the memory 25A. The upper side relay unit 25 executes a determination process as to whether to respond to or not respond to a write request or a read request received from the management control unit 26, based on the addresses stored in the memory 25A.

[0038] Specifically, in the case of a request that includes the address of a slave stored in memory 25A, the upper side relay unit 25 returns a response (ACK) to the management control unit 26 on behalf of the slave, and in the case of a request that does not include the address, the upper side relay unit 25 returns a non-response (NACK) to the management control unit 26. In addition, in the case where the slave device 3 is implemented with only one slave, the upper side relay unit 25 may not hold the slave address and always return an ACK to the management control unit 26 without performing the above-mentioned determination process.

[0039] The address of the slave in the memory 25A is set by a user in the controller 5, for example. Alternatively, the upper relay unit 25 may search for subordinate slaves by sequentially polling the addresses of the slaves, and store the addresses that respond in the memory 25A. Note that "subordinate" here refers to the slave device 3 side, and "searching" means, for example, performing a read operation (described later) on the polling target address, regardless of the operation of the master device 2 on the I2C bus 27.

[0040] When responding to the management control unit 26, the upper relay unit 25 functions as an emulator of I2C communication inside the master device 2. That is, the upper relay unit 25 executes a "first emulation" including the following alternative operations. Alternative operation 0: Timing arbitration regarding data exchange with the management control unit 26 (such as ACK and clock stretch operations)

[0041] Alternative operation 1: An operation of notifying a signal on the I2C bus 27 of the master device 2 to the lower-level relay unit 35 of the slave device 3 Alternative operation 2: An operation of outputting a signal on the I2C bus 36 of the slave device 3, which is notified from the lower-level relay unit 35 of the slave device 3, to the I2C bus 27 of the master device 2

[0042] Specifically, the upper side relay unit 25 is configured with a conversion circuit capable of performing two-way data conversion, for example, a process of converting I2C serial data into a communication frame and a process of converting the communication frame back into serial data. In this case, alternative behavior 1 is realized by the following framing process, and alternative behavior 2 is realized by the following serialization process.

[0043] Framing process (alternative operation 1): A process of generating a communication frame (hereinafter referred to as a “management frame”) including data corresponding to the serial data (SDA) from the management control unit 26 and outputting it to the AMCC processing unit 22. Serialization process (alternative operation 2): A process of returning the management frame (communication frame framed by the lower-level relay unit 35) input from the AMCC processing unit 22 to I2C serial data for the management control unit 26

[0044] The AMCC processing unit 22 performs a predetermined coding method (for example, Manchester coding) on ​​the management frame input from the upper-level relay unit 25 to generate a management signal, and outputs the generated management signal to the multiplexing circuit 23A. The AMCC processing unit 22 decodes the management signal input from the demultiplexing circuit 23B to generate a management frame, and outputs the generated management frame to the upper-level relay unit 25.

[0045] In the master device 2, the clock cycle of the encoding process performed by the AMCC processor 22 may be synchronous with or asynchronous to the serial clock (SCL) of I2C. When the clocks are asynchronous, a buffer memory for absorbing the difference in clock speeds may be provided in the master device 2 .

[0046] [Example of the configuration of a slave device] 2, the slave device 3 of this embodiment includes a main signal processing unit 31, an AMCC processing unit 32, a combining circuit 33A, a distribution circuit 33B, an optical transceiver 34, and a lower-side relay unit 35. As described below, the lower-side relay unit 35 may be abbreviated as "SR," and the processor 34A of the optical transceiver 34 may be abbreviated as "SL."

[0047] The circuit configurations of the optical transceiver 34, main signal processing unit 31, AMCC processing unit 32, combining circuit 33A, and distribution circuit 33B of the slave device 3 are generally similar to the optical transceiver 24, main signal processing unit 21, AMCC processing unit 22, combining circuit 23A, and distribution circuit 23B of the master device 2. Therefore, the contents of the master side are used for these circuit configurations. The main signal processing unit 31, the AMCC processing unit 32, the synthesis circuit 33A, the distribution circuit 33B, and the lower-side relay unit 35 may also be configured with one or more integrated circuits. As the integrated circuit, at least one of a CPU, an FPGA, an ASIC, and the like may be adopted.

[0048] The optical transceiver 34 includes a processor 34A for adjusting the operating wavelength, etc. The processor 34A is, for example, an MPU. The processor 34A and the lower-side relay unit 35 are each connected to an I2C bus 36. The processor 34A functions as an I2C slave. The lower-side relay unit 35 of the slave device 3 functions as an I2C master with respect to the processor 34A.

[0049] The lower-side relay unit 35 functions as an emulator of I2C communication inside the slave device 3. That is, the lower-side relay unit 35 executes a "second emulation" that includes the following alternative operation. Alternative operation 3: Timing arbitration regarding data transmission and reception with processor 34L (such as ACK and clock stretch operations)

[0050] Alternative operation 4: An operation of outputting a signal of the I2C bus 27 of the master device 2, which is notified from the upper side relay unit 25 of the master device 2, to the I2C bus 36 of the slave device 3 Alternative operation 5: An operation of notifying the upper relay unit 25 of the master device 2 of a signal on the I2C bus 36 of the slave device 3

[0051] Specifically, the lower-level relay unit 35 is configured with a conversion circuit capable of performing two-way data conversion, that is, a process of converting I2C serial data into a communication frame and a process of converting the communication frame back into serial data. In this case, alternative behavior 4 is realized by the following serialization process, and alternative behavior 5 is realized by the following framing process.

[0052] Serialization process (alternative operation 4): A process of returning the management frame (the communication frame framed by the upper relay unit 25) input from the AMCC processing unit 32 to I2C serial data for the processor 34A. Framing process (alternative operation 5): A process of generating a management frame including data corresponding to the serial data (SDA) from the processor 34A and outputting the management frame to the AMCC processing unit 32.

[0053] The AMCC processing unit 32 performs, for example, Manchester encoding on the management frame input from the lower-level relay unit 35 to generate a management signal, and outputs the generated management signal to the multiplexing circuit 33A. The AMCC processing unit 32 decodes the management signal input from the demultiplexing circuit 33B to generate a management frame, and outputs the generated management frame to the lower-level relay unit .

[0054] In the slave device 3 as well, the clock cycle of the encoding process performed by the AMCC processor 32 may be synchronous with or asynchronous to the serial clock (SCL) of I2C. When the clocks are asynchronous, the slave device 3 may be provided with a buffer memory for absorbing the difference in clock speed. Hereinafter, with reference to FIG. 2, the process contents performed by the master device 2 and the slave device 3 in each of the downstream communication and the upstream communication will be described.

[0055] [Downstream communication in optical communication systems] (Processing of master device 2 in downstream communication) The main signal processing unit 21 performs signal processing such as modulation and error correction coding on the downstream frame (electrical signal) received from the communication device 1 to generate downstream data. The main signal processing unit 21 converts the generated downstream data into an analog signal and outputs it as a main signal to the combining circuit 23 A. The transmission speed of the main signal is, for example, 25 Gbps (on-off keying).

[0056] The AMCC processing unit 22 performs modulation and analog conversion on the management frame input from the upper-level relay unit 25 to generate a management signal. As described above, the supervisory signal is, for example, a weak electric signal that has been Manchester-encoded. The transmission speed of Manchester encoding is, for example, 500 kHz. The AMCC processing unit 22 outputs the generated supervisory signal to the combining circuit 23A as an electric signal whose speed is lower than that of the main signal.

[0057] The combining circuit 23A combines the input main signal and management signal and outputs the combined signal to the optical transceiver 24. The optical transceiver 24 converts the electrical signal input from the combining circuit 23A into a downstream optical signal, and transmits the converted downstream optical signal to the optical fiber 7.

[0058] (Processing Contents of Slave Device 3 in Downstream Communication) The optical transceiver 34 converts the downstream optical signal received from the optical fiber 7 into an electrical signal and outputs it to the distribution circuit 33 B. The distribution circuit 33 B outputs the input electrical signal to the main signal processing unit 31 and the AMCC processing unit 32.

[0059] The main signal processing unit 31 filters the electrical signal input from the distribution circuit 33B to extract the main signal component. The main signal processing unit 31 performs signal processing such as demodulation and error correction on the extracted main signal components to regenerate downstream frames, and transmits the regenerated downstream frames to the communication device 4.

[0060] The AMCC processing unit 32 filters the electrical signal input from the distribution circuit 33B to extract the AMCC signal components. The AMCC processing unit 32 performs signal processing such as demodulation on the extracted AMCC signal components to reproduce the management signal, performs decoding processing on the reproduced management signal to decode the management frame, and outputs the decoded management frame to the lower-side relay unit 35.

[0061] The downstream relay unit 35 converts the input management frame into I2C serial data (SDA) and transmits the converted serial data to the processor 34A of the optical transceiver 34 by outputting it to the I2C bus 36 of its own device together with a clock (SCL).

[0062] [Upstream communication in optical communication system] (Processing Contents of Slave Device 3 in Upstream Communication) After outputting SDA and SCL, the lower-level relay unit 35 waits to receive I2C serial data transmitted by the processor 34A. The lower-level relay unit 35 converts the I2C serial data received from the processor 34A into a management frame, and outputs the converted management frame to the AMCC processing unit 32.

[0063] The AMCC processing unit 32 performs modulation and analog conversion on the management frame input from the lower-level relay unit 35 to generate a management signal. As mentioned above, the supervisory signal is, for example, a weak electrical signal that is Manchester encoded. The transmission speed of Manchester encoding is, for example, 500 kHz. The AMCC processor 32 outputs the generated supervisory signal to the combiner circuit 33A as an electrical signal whose speed is lower than that of the main signal.

[0064] The main signal processing unit 31 performs signal processing such as modulation and error correction coding on the upstream frame (electrical signal) received from the communication device 4 to generate downstream data. The main signal processor 31 converts the generated upstream data into an analog signal and outputs it as a main signal to the combiner circuit 33 A. The transmission speed of the main signal is, for example, 25 Gbps (on-off keying).

[0065] The combining circuit 33A combines the input main signal and management signal and outputs the combined signal to the optical transceiver 34. The optical transceiver 34 converts the electrical signal input from the combining circuit 33A into an upstream optical signal, and transmits the converted upstream optical signal to the optical fiber 7.

[0066] (Processing of master device 2 in upstream communication) The optical transceiver 24 converts the upstream optical signal received from the optical fiber 7 into an electrical signal and outputs it to the distribution circuit 23B. The distribution circuit 23B outputs the input electrical signal to the main signal processing unit 21 and the AMCC processing unit 22.

[0067] The main signal processing unit 31 filters the electrical signal input from the distribution circuit 23B to extract the main signal component. The main signal processing unit 31 performs signal processing such as demodulation and error correction on the extracted main signal components to regenerate upstream frames, and transmits the regenerated upstream frames to the communication device 1.

[0068] The AMCC processing unit 22 filters the electrical signal input from the distribution circuit 23B to extract the AMCC signal components. The AMCC processing unit 22 performs signal processing such as demodulation on the extracted AMCC signal components to reproduce the management signal, performs decoding processing on the reproduced management signal to decode the management frame, and outputs the decoded management frame to the upper side relay unit 25.

[0069] The upper side relay unit 25 converts the input management frame into I2C serial data (SDA) and transmits the converted serial data to the management control unit 26 by outputting it to the I2C bus 27 of its own device together with a clock (SCL).

[0070] [I2C communication including optical communication section] Figures 3 to 6 are sequence diagrams showing the contents of I2C communication including the optical communication section in a time series. The meanings of the parameters used in Figures 3 to 6 are as follows:

[0071] MA: I2C master (management control unit 26 in Figure 2) MR: I2C master side relay unit (upper side relay unit 25 in Figure 2) SR: I2C slave side relay unit (lower side relay unit 35 in FIG. 2) SL: I2C slave (processor 34A in Figure 2)

[0072] S: Start condition W: Write request R: Lead request ACK: Response to a request

[0073] A0~A6: A bit string representing the I2C slave address (7 bits in the example) D0~D7: A bit string representing the data transmitted via I2C (8 bits in the example) L: SCL or SDA is in low state H: SCL or SDA in high state SCL and SDA are in a Hi-Z pull-up state except when they are L or H. Hereinafter, the contents of the I2C communication including the optical communication section will be described with reference to FIG. 3 to FIG.

[0074] [Light Operation] 3 and 4 are sequence diagrams showing an example of a “write operation” of I2C communication executed between the master device 2 and the slave device 3. In FIG. The downward arrows in Figures 3 and 4 indicate the time axis. Figure 4 is a sequence diagram following Figure 3.

[0075] 3, the MA first executes a write command for the SL (step ST11). The write command is executed by outputting the addresses A0 to A6 of the SL and a write request W to the I2C bus 27 following a start condition S.

[0076] Upon detecting the write command, the MR returns an ACK on behalf of the SL (step ST12) on the condition that the addresses A0 to A6 of the write request W match the address value stored in the memory 25A, and transfers the write command to the SR (step ST13). The transfer of the write command by the MR is performed by converting a bit string representing the addresses A0 to A6 of the SL and the write request W into a management frame and outputting the converted management frame to the AMCC processing unit 22.

[0077] Note that MR may transfer the write command to SR regardless of whether the address values ​​match or not. In this case, the I2C slave of the slave device 3 determines whether to respond to the write command or ignore the write command.

[0078] After returning the ACK, the MR executes clock stretching and waits for an ACK notification from the slave side (step ST14). The clock stretching is performed by setting the SCL of the I2C bus 27 to Low. As described later, clock stretching is released on the condition that an ACK management frame is received from the slave side (step ST19).

[0079] When the SR receives the management frame including the write command, it transfers the write command to the SL (step ST15). The above management frame is input from the AMCC processing unit 32. The transfer of the write command by SR is performed by decoding the bit string representing the addresses A0 to A6 and the write request W from the input management frame and outputting the decoded bit string to the I2C bus 36.

[0080] Next, the SL performs address confirmation (step ST16), and returns an ACK on condition that the address A0 to A6 of the received I2C matches its own address (step ST17). If the SL cannot receive the write data immediately, the SL may perform clock stretching after returning an ACK.

[0081] The SR that detected the ACK transfers the ACK to the MR (step ST18). The SR transfers the ACK by outputting a management frame in which the I2C ACK is encoded to the AMCC processing unit 32. Next, the MR that has received the ACK management frame releases the clock stretch (step ST19). The clock stretch is released by returning the SCL of the I2C bus 27 to High.

[0082] 4, when the MA detects the release of the clock stretch, the MA starts transmitting the write data D0 to D7 (step ST20). This transmission is performed by outputting the bit string of the write data D0 to D7 to the I2C bus 27. Next, the MR transfers the write data D0 to D7 to the SR (step ST21). This transfer is performed by outputting to the AMCC processor 22 a management frame in which a bit string representing the write data D0 to D7 is encoded.

[0083] The MR may transfer the write data D0 to D7 (step ST21) after returning an ACK (step ST24) which will be described later. In particular, when the speed of management communication is faster than the speed of I2C communication, it is convenient to implement the data transfer after receiving it from I2C.

[0084] When the SR receives the management frame including the write data D0 to D7, it transfers the write data D0 to D7 to the SL (step ST22), and the SL executes writing of the transferred write data D0 to D7 (step ST23). The above management frame is input from the AMCC processing unit 32. The transfer of the write data D0 to D7 by SR is performed by decoding the bit string of the write data D0 to D7 from the input management frame and outputting the decoded bit string to the I2C bus 36.

[0085] In the master device 2, the MR that has received the write data D0 to D7 returns an ACK on behalf of the SL (step ST24). When the MA confirms the return of the ACK (step ST25), it issues a command to end the communication (stop condition) (step ST26). The command to end the communication is issued by setting both SCL and SDA of the I2C bus 27 to High. This allows the MR to confirm the end of the write operation (slave ST27).

[0086] Meanwhile, in the slave device 3, the SL that has received the write data D0 to D7 returns an ACK (step ST28). When the SR confirms the ACK (step ST29), it issues a command to end the communication (stop condition) to the SL on behalf of the MA (step ST30). The command to end the communication is issued by setting both the SCL and SDA of the I2C bus 36 to High. This allows the SL to confirm the end of the write operation (slave ST31).

[0087] [Lead Operation] 5 and 6 are sequence diagrams showing an example of a “read operation” of I2C communication executed between the master device 2 and the slave device 3. FIG. The downward arrows in Figures 5 and 6 indicate the time axis. Figure 6 is a sequence diagram following Figure 5.

[0088] 5, MA first executes a read command for SL (step ST51). The read command is executed by outputting the addresses A0 to A6 of SL and a read request R to the I2C bus 27 following a start condition S.

[0089] Upon detecting the read command, the MR returns an ACK on behalf of the SL (step ST52), provided that the addresses A0 to A6 of the read request R match the address values ​​stored in the memory 25A, and transfers the read command to the SR (step ST53). The transfer of the read command by the MR is performed by converting the addresses A0 to A6 of the SL and a bit string representing the read request R into a management frame, and outputting the converted management frame to the AMCC processing unit 22.

[0090] After returning the ACK, the MR executes clock stretching and waits for reception of read data from the slave side (step ST54). The clock stretching is performed by setting the SCL of the I2C bus 27 to Low. As described later, the clock stretching is released immediately before the read data is transferred from the slave side and starts to be transmitted to the I2C 27 (step ST59 in FIG. 6).

[0091] When the SR receives the management frame including the read command, it transfers the read command to the SL (step ST55). The above management frame is input from the AMCC processing unit 32. The transfer of the read command by SR is performed by decoding the bit string representing the addresses A0 to A6 and the read request R from the input management frame and outputting the decoded bit string to the I2C bus 36.

[0092] Next, the SL executes address confirmation (step ST56), and returns an ACK on condition that the address A0 to A6 of the received I2C matches its own address (step ST57). If the SL cannot immediately send the read data, the SL may perform clock stretching after returning an ACK (step ST58).

[0093] 6, the SL that returned the ACK starts transmitting the read data D0 to D7 (step ST60) immediately after returning the ACK if clock stretching is not performed, or after canceling cross stretch if clock stretching is performed. This transmission is performed by outputting the bit string of the read data D0 to D7 to the I2C bus 36.

[0094] Next, the SR transfers the read data D0 to D7 to the MR (step ST61). This transfer is performed by converting a bit string representing the read data D0 to D7 into a management frame and outputting the converted management frame to the AMCC processing unit 32.

[0095] The SR may transfer the above read data D0 to D7 (step ST61) after returning an ACK (step ST68) which will be described later. In particular, when the speed of management communication is faster than the speed of I2C communication, it is convenient to implement the data transfer after receiving it from I2C.

[0096] When the MR receives the management frame including the read data D0 to D7, the MR transfers the read data D0 to D7 to the MA (step ST62). The above management frame is input from the AMCC processing unit 22. The transfer of the read data D0 to D7 by the MR is performed by decoding the bit string of the read data D0 to D7 from the input management frame and outputting the decoded bit string of the read data D0 to D7 to the I2C bus 27.

[0097] Next, MA executes reading of the read data D0 to D7 (step ST63), and returns an ACK after the end of reading (step ST64). The MR that detects the ACK confirms the ACK on behalf of the SL (step ST69).

[0098] In the master device 2, after returning the ACK, the MA issues a command to end the communication (stop condition) (step ST66). The command to end the communication is issued by setting both the SCL and SDA of the I2C bus 27 to High. This causes the MR to confirm the end of the write operation (step ST67).

[0099] Meanwhile, in the slave device 3, the SR that transferred the read data D0 to D7 returns an ACK on behalf of the MA (step ST68). The SR's return of the proxy ACK allows the SL to confirm the ACK of the completion of reading the read data by the MA (step ST69).

[0100] When the SR returns an ACK (step ST68), it issues a command to end communication (stop condition) to the SL on behalf of the MR (step ST70). The command to end communication is issued by setting both SCL and SDA of the I2C bus 36 to High. This allows the SL to confirm the end of the read operation (step ST71).

[0101] [Modification of Light Operation] In the above-described write sequence (FIGS. 3 and 4), the clock stretching by the MR for waiting for the ACK notification from the SL of the slave device 3 may be omitted. Specifically, in the above-mentioned write sequence (FIGS. 3 and 4), steps ST14, ST18, and ST19 may be skipped, and the MR may transfer the write data D0 to D7 to the slave side without performing clock stretching.

[0102] [Other Modifications] The embodiments disclosed herein are illustrative and not restrictive in all respects. The scope of the present invention is not limited to the above-described embodiments, but includes all modifications within the scope of the equivalents of the configurations described in the claims.

[0103] For example, I2C has the option to specify a 10-bit address, or to send more than 8 bits of data continuously. Even when these options are adopted, the above-mentioned write operation and read operation can be performed by converting the address and data together into a management frame and transferring it (ie, outputting it to the AMCC processing units 22, 32).

[0104] In the above embodiment, the case where the transmission path connecting the master device 3 and the slave device 3 is the optical fiber 7 has been exemplified, but an optical passive component such as an optical coupler or an optical connector may be interposed in the middle of the optical fiber 7. Furthermore, the transmission path connecting the master device 3 and the slave device 3 may be any other than an I2C bus, and may be, for example, a metal cable or a wireless line. [Explanation of symbols]

[0105] 1. Communications equipment 2 Optical communication device (master device, first communication device) 3 Optical communication device (slave device, second communication device) 4. Communications equipment 5. Controller 6 Metal Cable 7 Optical fiber (transmission line) 8 Metal Cable 9 Metal Cable 21 Main signal processing section 22 AMCC Processing Section 23 Combining and distribution circuits 24 Optical Transceiver 24A Processor 25 Upper relay section (first relay section) 26 Management control unit (first processor) 27 I2C bus (first bus) 31 Main signal processing section 32 AMCC Processing Section 33 Combining and distribution circuits 34 Optical Transceiver 34A Processor (Second Processor) 35 Lower relay unit (second relay unit) 36 I2C bus (second bus) 100 Optical communication system

Claims

1. A communication system including a first communication device and a second communication device connected by a transmission path other than an I2C bus, The first communication device is a first processor having an I2C master function; a first relay unit connected to a first bus, which is an I2C bus in the first communication device; The second communication device is a second processor having an I2C slave function; a second relay unit connected to a second bus, which is an I2C bus in the second communication device; The first relay portion and the second relay portion are Communication via the transmission path is possible, The first relay portion is executes an operation of notifying the first relay unit of a signal of the first bus, and an operation of outputting the signal of the second bus notified from the second relay unit to the first bus; The second relay portion is an operation of outputting a signal of the first bus notified from the first relay unit to the second bus; and notifying the second relay unit of a signal on the second bus.

2. The first relay portion is storing at least one address set in the second processor; The operation of notifying the first relay unit by the first relay unit includes:

2. The communication system according to claim 1, wherein the communication is executed on the condition that an address obtained from the signal on the first bus matches the stored address.

3. The first relay portion is 2. The communication system according to claim 1, wherein clock stretching is performed on the first bus when a write command is received from the first processor, and the clock stretching is released on the condition that a response to the write command is received from the second relay unit.

4. The first relay portion is 2. The communication system according to claim 1, wherein clock stretching is performed on the first bus when a read command is received from the first processor, and the clock stretching is released on the condition that read data is received from the second relay unit.

5. The transmission path is 5. The communication system according to claim 1, wherein the transmission line includes an optical fiber.

6. A communication band for communication between the first relay unit and the second relay unit in the transmission path is The communication system according to claim 1 , wherein the communication band is set to a low band that does not interfere with a communication band for a main signal in the transmission path.

7. A communication method executed by a first communication device and a second communication device that are connected by a transmission path other than an I2C bus, The first communication device is a first processor having an I2C master function; a first relay unit connected to a first bus, which is an I2C bus in the first communication device; The second communication device is a second processor having an I2C slave function; a second relay unit connected to a second bus, which is an I2C bus in the second communication device; The communication method includes: a step of the first relay unit and the second relay unit performing communication via the transmission path; a step of executing, by the first relay unit, an operation of notifying the first relay unit of a signal of the first bus, and an operation of outputting, to the first bus, the signal of the second bus notified from the second relay unit; A communication method comprising the steps of: the second relay unit performing an operation of outputting a signal of the first bus notified from the first relay unit to the second bus; and an operation of notifying the second relay unit of the signal of the second bus.

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