Display device and mother board for display device

Abstract

To provide a display device that can improve the yield in a manufacturing process.SOLUTION: In an embodiment, a display device includes a substrate, an organic insulating layer disposed over the substrate in a display region where a plurality of display elements are disposed and a peripheral region around the display region, a first partition wall disposed over the organic insulating layer between the adjacent display elements, and a second partition wall disposed in the peripheral region. Each of the first partition wall and the second partition wall includes a lower part with conductivity, and an upper part protruding from a side surface of the lower part. The organic insulating layer has an opening in the peripheral region. The second partition wall is disposed outside the opening along an edge of the opening.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device and a mother substrate for the display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. The display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] In manufacturing the above-mentioned display devices, a technique for improving the yield in the manufacturing process is required. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device and a mother substrate for the display device that can improve the yield in the manufacturing process. [Means for solving the problem]

[0006] Generally, according to an embodiment, a display device includes a substrate, an organic insulating layer disposed above the substrate across a display region in which a plurality of display elements are disposed and a peripheral region around the display region, a first partition disposed above the organic insulating layer between adjacent display elements, and a second partition disposed in the peripheral region. The first partition and the second partition each have a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The organic insulating layer has an opening in the peripheral region. The second partition is disposed outside the opening and along an edge of the opening.

[0007] According to an embodiment, a mother substrate for a display device includes a panel section having a display area for displaying an image and a peripheral area around the display area, a margin on the outside of the panel section, an organic insulating layer disposed across the panel section and the margin, a first partition disposed in the display area above the organic insulating layer, and a second partition disposed in the margin. The first partition and the second partition each have a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The organic insulating layer has an opening in the margin. The second partition is disposed outside the opening and along the edge of the opening.

[0008] According to an embodiment, the display device includes a substrate, an organic insulating layer disposed above the substrate across a display region in which a plurality of display elements are disposed and a peripheral region around the display region, and a partition disposed above the organic insulating layer between adjacent display elements. The partition has a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The organic insulating layer has an opening in the peripheral region. The opening has a rounded portion in a plan view, and the radius of curvature of the rounded portion is 25 μm or more.

[0009] According to an embodiment, a mother substrate for a display device includes a panel section having a display area for displaying an image and a peripheral area around the display area, a margin on the outside of the panel section, an organic insulating layer disposed across the panel section and the margin, and a partition wall disposed in the display area above the organic insulating layer. The partition wall has a conductive lower portion and an upper portion protruding from a side surface of the lower portion. The organic insulating layer has an opening in the margin. The opening has a rounded portion. The rounded portion has a radius of curvature of 25 μm or more. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a layer structure that can be applied to the organic layer. [Diagram 5] FIG. 5 is a plan view showing an example of a mother substrate for a display device according to the first embodiment. [Figure 6] FIG. 6 is a plan view showing an example of a configuration of the pad. [Figure 7] FIG. 7 is a plan view showing an example of the configuration of an area including pads in the peripheral area or the marginal portion. [Figure 8] FIG. 8 is a plan view showing an example of the configuration of a region including a window portion in the peripheral region or marginal portion. [Figure 9] FIG. 9 is a schematic enlarged partial view showing portion IX in FIGS. [Figure 10] FIG. 10 is a schematic cross-sectional view of the mother substrate for a display device taken along the line XX in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing another example of the configuration of a mother substrate for a display device. [Figure 12]FIG. 12 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 13] FIG. 13 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 14] FIG. 14 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 15] FIG. 15 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 16] FIG. 16 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 17] FIG. 17 is a schematic cross-sectional view of the mother substrate for a display device taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing another configuration example of a mother substrate for a display device. [Figure 19] FIG. 19 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 20] FIG. 20 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 21] FIG. 21 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 22] FIG. 22 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Diagram 23] FIG. 23 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 24] FIG. 24 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Diagram 25] FIG. 25 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 26] FIG. 26 is a schematic cross-sectional view showing still another configuration example of a mother substrate for a display device. [Figure 27]FIG. 27 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the second embodiment. [Figure 28] FIG. 28 is a partial enlarged view of a portion XXVIII in FIG. [Figure 29] FIG. 29 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the third embodiment. [Diagram 30] FIG. 30 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the fourth embodiment. [Diagram 31] FIG. 31 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the fifth embodiment. [Diagram 32] FIG. 32 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the sixth embodiment. [Diagram 33] FIG. 33 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the seventh embodiment. [Diagram 34] FIG. 34 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the eighth embodiment. [Diagram 35] FIG. 35 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the ninth embodiment. [Diagram 36] FIG. 36 is a schematic plan view showing an area including pads in the peripheral area or marginal portion in the tenth embodiment. [Figure 37] FIG. 37 is a diagram for explaining other shapes of the opening that can be applied to the window portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those skilled in the art can easily think of appropriate modifications that maintain the gist of the invention and are naturally included in the scope of the present invention.

[0012] In addition, in order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, components that have the same or similar functions as those described above with respect to the previous drawings are given the same reference numerals, and duplicated detailed descriptions may be omitted as appropriate.

[0013] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are shown as necessary for ease of understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is a normal direction of a plane including the X-direction and the Y-direction. In each embodiment, the X-direction corresponds to the first direction, and the Y-direction corresponds to the second direction. Also, viewing various elements parallel to the Z-direction is called planar view.

[0014] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0015] [First embodiment] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA around the display area DA, on an insulating substrate 10. A plurality of display elements, which will be described later, are arranged in the display area DA. The substrate 10 may be glass or a flexible resin film.

[0016] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0017] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0018] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0019] In the display area DA, there are arranged a plurality of scanning lines GL which supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL which supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example shown in Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0020] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4.

[0021] In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE. Note that the configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0022] In the peripheral area SA, pads PD and window portions WP used for testing and the like are arranged. In the example shown in Fig. 1, a plurality of pads PD and a plurality of window portions WP are arranged, but the number of pads PD and the number of window portions WP may be changed as appropriate. In addition, at least one of the pads PD and the window portions WP may be omitted in the display panel PNL.

[0023] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0024] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example shown in FIG.

[0025] In the display area DA, an inorganic insulating layer 5 is disposed. The inorganic insulating layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these pixel openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] 2, pixel aperture AP1 is larger than pixel aperture AP2, which is larger than pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, subpixel SP1 has the largest aperture ratio and subpixel SP3 has the smallest aperture ratio.

[0027] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0028] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later.

[0029] In the display area DA, conductive partition walls 6 (first partition walls) are arranged. The partition walls 6 are arranged on the inorganic insulating layer 5. The partition walls 6 entirely overlap the inorganic insulating layer 5, and have the same planar shape as the inorganic insulating layer 5. The partition walls 6 are arranged between adjacent display elements DE1, DE2, and DE3.

[0030] That is, the partition 6 has an opening in each of the subpixels SP1, SP2, and SP3. The inorganic insulating layer 5 and the partition 6 have a lattice shape in a plan view and surround each of the subpixels SP1, SP2, and SP3. The partition 6 serves as a wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0031] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that serves as a planarizing film for planarizing unevenness caused by the circuit layer 11.

[0032] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5.

[0033] Although not shown in the cross section shown in FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the insulating layer 12.

[0034] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0035] 3, the lower portion 61 has a bottom layer 63 disposed on the inorganic insulating layer 5 and an axis layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the axis layer 64. In addition, in the example shown in FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the axis layer 64.

[0036] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR1 is disposed between the lower electrode LE1 and the upper electrode UE1.

[0037] The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0038] The display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0039] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0040] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located below the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located below the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located below the partition wall 6 (a part that constitutes the display element DE3).

[0041] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE2 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE3 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0042] 3, the stacked film FL1 and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE2 on the partition 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE3 on the partition 6.

[0043] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15. The resin layers 13, 15, and the sealing layer 14 are provided continuously at least throughout the display area DA, and a portion of them extends into the peripheral area SA.

[0044] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer 15. Such a cover member may be adhered to the resin layer 15 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0045] The insulating layer 12 is made of an organic insulating material such as polyimide. The inorganic insulating layer 5 and the sealing layers 14, SE1, SE2, and SE3 are made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0046] In one example, the inorganic insulating layer 5 is made of silicon oxynitride, and the sealing layers 14, SE1, SE2, and SE3 are made of silicon nitride. The resin layers 13 and 15 are made of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin.

[0047] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0048] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0049] 4 is a diagram showing an example of a layer structure that can be applied to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emitting layer EML.

[0050] In this embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emitting layers EML.

[0051] The cap layers CP1, CP2, and CP3 (shown in FIG. 3) have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers made of inorganic materials and layers made of organic materials. In addition, these transparent layers have different refractive indices.

[0052] For example, the refractive index of these transparent layers is different from the refractive index of the upper electrodes UE1, UE2, UE3 and the refractive index of the sealing layers SE1, SE2, SE3. At least one of the cap layers CP1, CP2, CP3 may be omitted.

[0053] The bottom layer 63 and the shaft layer 64 (shown in FIG. 3) of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb).

[0054] Examples of the metal material that can be used for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be made of an insulating material.

[0055] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0056] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0057] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength region.

[0058] As another example, the emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the emitting layers EML into light of a color corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the emitting layers EML to generate light of a color corresponding to the subpixels SP1, SP2, and SP3.

[0059] The circuit layer 11, the insulating layer 12, and the inorganic insulating layer 5 shown in FIG. 3 are disposed across the display area DA and the peripheral area SA.

[0060] Next, a display device mother substrate 100 for manufacturing a plurality of display devices DSPs at once will be described.

[0061] 5 is a plan view showing an example of a display device mother substrate 100 according to this embodiment. The display device mother substrate 100 includes, on a large substrate 10, a plurality of panel portions PP and blank portions MP on the outer sides of the plurality of panel portions PP.

[0062] In this embodiment, the shape of the large substrate 10 in a plan view is rectangular. However, the shape of the large substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0063] The panel sections PP are arranged in a matrix in the X and Y directions. Each of the panel sections PP is taken out by cutting the display device mother substrate 100 along a cut line (not shown).

[0064] Each of the extracted panel portions PP corresponds to the display panel PNL of the display device DSP shown in Fig. 1. In the blank portion MP, for example, a plurality of pads PD electrically connected to a test element group or the like and a window portion WP are arranged.

[0065] Fig. 6 is a plan view showing an example of the configuration of the pad PD. The pad PD shown in Fig. 6 corresponds to the pad PD in the peripheral area SA shown in Fig. 1 or the pad PD in the marginal portion MP shown in Fig. 5.

[0066] An organic insulating layer IL is disposed on the inorganic insulating layer 5 (shown in FIG. 3). The organic insulating layer IL includes at least the insulating layer 12 shown in FIG. 3. The organic insulating layer IL and the inorganic insulating layer 5 are disposed in each panel portion PP and also disposed across the margin portion MP. Focusing on the panel portion PP, the organic insulating layer IL and the inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0067] In the peripheral region SA and the marginal portion MP, the organic insulating layer IL has an opening OP1, and the inorganic insulating layer 5 has an opening OP2. The opening OP1 is indicated by a dotted line, and the opening OP2 is indicated by a solid line.

[0068] The circuit layer 11 (shown in FIG. 3) includes a metal layer MT. The metal layer MT indicated by the dashed line corresponds to the electrode of the pad PD. The metal layer MT overlaps an opening OP1 in the organic insulating layer IL and an opening OP2 in the inorganic insulating layer 5. The portion of the organic insulating layer IL that does not overlap the opening OP1 is marked with a dot.

[0069] The area of ​​the opening OP2 is smaller than the area of ​​the opening OP1 in a plan view. The portions of the metal layer MT exposed through the openings OP1 and OP2 are indicated by diagonal lines. The peripheral portion of the metal layer MT is covered with the organic insulating layer IL and the inorganic insulating layer 5.

[0070] The openings OP1 and OP2 have, for example, a quadrangular shape in plan view. The quadrangular shape includes a rectangular shape, a square shape, a rhombus shape, a trapezoid shape, a parallelogram shape, and the like. As an example, the openings OP1 and OP2 have a square shape in plan view. The distance in the X direction and the Y direction of the opening OP1 is, for example, about 400 μm, but is not limited to this example.

[0071] As shown in Fig. 6, the opening OP1 has an edge 30. The edge 30 of the opening OP1 is a step portion. The edge 30 includes a pair of edges 31 (first edges) extending in the X direction, a pair of edges 33 (second edges) extending in the Y direction, and a rounded portion 35. The rounded portion 35 is an example of a corner portion connecting the edge 31 and the edge 33. The edge 30 includes four rounded portions 35.

[0072] Fig. 7 is a plan view showing a configuration example of a region including pads PD in the peripheral region SA or the marginal portion MP. In the example shown in Fig. 7, four pads PD are arranged. Each of the metal layers MT of the pads PD is exposed from an opening OP1 and an opening OP2.

[0073] The display device mother substrate 100 (display device DSP) further includes a conductive partition wall 7 (second partition wall) and a conductive partition wall 8. These partition walls 7, 8 are disposed above the organic insulating layer IL in the peripheral region SA or the marginal portion MP. The partition wall 7 is disposed outside the opening OP1 and along the edge 30 of the opening OP1. The partition wall 7 surrounds, for example, the opening OP1.

[0074] The partition walls 8 are arranged in the cross-shaped regions between the four pads PD. The partition walls 8 are also arranged in the peripheral regions of the four pads PD. In the example shown in Fig. 7, the partition walls 8 are formed in a lattice pattern. The partition walls 8 are formed in the same pattern as the lattice-shaped partition walls 6 shown in Fig. 2, for example. The partition walls 7 and 8 are not formed in the regions overlapping the opening OP1.

[0075] Fig. 8 is a plan view showing an example of the configuration of a region including a window portion WP in the peripheral region SA or the marginal portion MP. In the example shown in Fig. 8, a region including one window portion WP is shown.

[0076] The organic insulating layer IL has an opening OP3. The window portion WP is formed by the organic insulating layer IL having the opening OP3. In Fig. 8, the opening OP3 is indicated by a dotted line. The portion of the organic insulating layer IL that does not overlap with the opening OP3 is indicated by a dot.

[0077] The opening OP3 has, for example, a quadrangular shape in plan view. As one example, the opening OP3 has a rectangular shape that is elongated in the Y direction in plan view.

[0078] 8, the opening OP3 has an edge 40. The edge 40 includes a pair of edges 41 (first edges) extending in the X direction, a pair of edges 43 (second edges) extending in the Y direction, and a rounded portion 45 connecting the edges 41 and 43. The rounded portion 45 is an example of a corner portion connecting the edges 41 and 43. The edge 40 includes four rounded portions 45.

[0079] In the window portion WP, a plurality of (for example, three) marks MA are arranged in a region overlapping with the opening OP3. The marks MA are marks used for the purpose of improving precision in the manufacturing process, for example.

[0080] The mark MA is formed, for example, by a metal layer included in the circuit layer 11 (shown in FIG. 3). The mark MA is formed by combining figures, characters, symbols, etc. The mark MA includes, for example, a mark M1 formed by a figure and a mark M2 formed by a character. Note that the mark MA is not limited to these examples.

[0081] The partition wall 7 is also disposed outside the opening OP3, similarly to the opening OP1. That is, the partition wall 7 is disposed outside the opening OP3 along the edge 40 of the opening OP3. The partition wall 7, for example, surrounds the opening OP3. Moreover, the partition wall 7 is not formed in the region overlapping with the opening OP3.

[0082] Fig. 9 is a schematic partial enlarged view showing portion IX in Fig. 7 and Fig. 8. Fig. 9 shows a region including one of the multiple round portions 35, 45, but the structure of the regions including the other round portions 35, 45 is also similar to that shown in Fig. 9.

[0083] As shown in Fig. 9, the rounded portions 35, 45 have an arc shape in a plan view. In other words, the rounded portions 35, 45 have a radius of curvature R1. The radius of curvature R1 of the rounded portions 35, 45 is greater than the thickness of the organic insulating layer IL, for example. The radius of curvature R1 of the rounded portions 35, 45 is preferably, for example, 25 µm or more.

[0084] As described above, the partition 7 is disposed along the edges 30, 40 of the openings OP1, OP3. Focusing on the rounded portions 35, 45, at least a part of the partition 7 is disposed outside the rounded portions 35, 45 (corner portions).

[0085] Focusing on the opening OP1, the partition 7 is disposed outside the rounded portion 35 and also outside the edges 31 and 33. Focusing on the opening OP3, the partition 7 is disposed outside the rounded portion 45 and also outside the edges 41 and 43.

[0086] Next, a configuration example of the display device mother substrate 100 including the opening OP1 will be described.

[0087] Fig. 10 is a schematic cross-sectional view of the display device mother substrate 100 taken along line XX in Fig. 7. The circuit layer 11 (shown in Fig. 3) includes an insulating layer 111, a wiring layer 112, an insulating layer 113, an insulating layer 114, and a metal layer MT.

[0088] The insulating layer 111 is an inorganic insulating layer, and is disposed on the substrate 10. The wiring layer 112 is disposed on the insulating layer 111. The insulating layer 113 is an inorganic insulating layer, and is disposed on the wiring layer 112.

[0089] The wiring layer 112 is exposed from the insulating layer 113 at the pad PD. The insulating layer 114 is an organic insulating layer, and is disposed on the insulating layer 113. The metal layer MT is disposed on the insulating layer 113 and the insulating layer 114, and is in contact with the wiring layer 112 at the pad PD.

[0090] As a result, metal layer MT is electrically connected to wiring layer 112. Insulating layer 111, wiring layer 112, insulating layer 113, insulating layer 114 and metal layer MT are included in circuit layer 11 shown in Fig. 3. Note that circuit layer 11 may include an insulating layer and a conductive layer in addition to the layers shown in the figure.

[0091] The insulating layer 12 is an organic insulating layer, and is disposed on the insulating layer 114 and the metal layer MT. The above-mentioned organic insulating layer IL has the insulating layer 114 and the insulating layer 12. That is, the organic insulating layer IL is disposed above the substrate 10. The insulating layer 12 has an opening OP1 that exposes the metal layer MT. The opening OP1 corresponds to an opening in the organic insulating layer IL.

[0092] The inorganic insulating layer 5 covers the insulating layer 12 and is in contact with the metal layer MT. The inorganic insulating layer 5 has an opening OP2 overlapping the opening OP1. The metal layer MT is exposed from the inorganic insulating layer 5 at the opening OP2.

[0093] The partition walls 7 and 8 are disposed above the organic insulating layer IL. The partition walls 7 and 8 have conductive lower portions 71 and 81 disposed on the inorganic insulating layer 5, and upper portions 72 and 82 disposed on the lower portions 71 and 81, respectively. The upper portions 72 and 82 have a width greater than that of the lower portions 71 and 81.

[0094] Both end portions of the upper portions 72, 82 protrude beyond the side surfaces of the lower portions 71, 81. In this manner, the partition walls 7, 8 have an overhanging shape similar to the partition wall 6 shown in Fig. 3. The lower portions 71, 81 may each have a bottom layer disposed on the inorganic insulating layer 5 and an axis layer disposed on the bottom layer, similar to the partition wall 6 shown in Fig. 3.

[0095] The partition walls 7 and 8 can be formed in the same process as the partition wall 6. In this case, the lower parts 71 and 81 are formed of the same material as the lower part 61, and the upper parts 72 and 82 are formed of the same material as the upper part 62.

[0096] Next, another example of the cross-sectional structure of the display device mother substrate 100 including the opening OP1 will be described.

[0097] Fig. 11 is a schematic cross-sectional view showing another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 11 is different from the configuration example shown in Fig. 10 in that the organic insulating layer IL has a stepped cross section.

[0098] The organic insulating layer IL has an insulating layer 114 and an insulating layer 12. The insulating layer 12 has an opening OP1. Focusing on the cross-sectional shape of the organic insulating layer IL, the organic insulating layer IL has a stepped cross section in which the thickness decreases toward the opening OP1.

[0099] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 114 and the thickness of the insulating layer 12, and corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the approximately flat upper surface 121A of the insulating layer 12.

[0100] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 12 between the insulating layer 114 and the opening OP1, and corresponds to the distance along the Z direction from the upper surface of the metal layer MT to the substantially flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the opening OP1. The upper surface 122A is located lower than the upper surface 121A.

[0101] The partition walls 7 and 8 are disposed above the organic insulating layer IL and on the inorganic insulating layer 5. In the example shown in Fig. 11, the partition wall 7 is disposed above the upper surface 121A, but is not disposed above the upper surface 122A. However, the partition wall 7 may be disposed above the upper surface 122A.

[0102] The organic insulating layer IL having a stepped cross section can be formed, for example, by the following method. First, an insulating layer 114 is formed on an insulating layer 113. Then, a metal layer MT is formed. Then, an insulating layer 12 having an opening OP1, an upper surface 121A, and an upper surface 122A is formed.

[0103] Such an insulating layer 12 can be formed, for example, by the following method. An insulating layer is formed, for example, from a positive organic material, on the entire surface of the mother substrate 100 for a display device on which the metal layer MT is formed. Then, the insulating layer is exposed to light. In this exposure process, the exposure amount at the opening OP1 is set to a maximum, and the exposure amount is set to decrease stepwise from the opening OP1 toward the outside. Then, the exposed insulating layer is developed. Then, the insulating layer is baked. As a result, an organic insulating layer IL having the above-mentioned cross-sectional shape is formed.

[0104] Fig. 12 is a schematic cross-sectional view showing yet another configuration example of the mother substrate 100 for a display device. The configuration example shown in Fig. 12 differs from the configuration example shown in Fig. 11 in that the inorganic insulating layer 5 does not have an opening. The inorganic insulating layer 5 covers the insulating layer 12 and also covers the metal layer MT exposed from the opening OP1. In other words, the metal layer MT is not exposed.

[0105] Fig. 13 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 13 differs from the configuration example shown in Fig. 11 in that the insulating layer 114 extends further toward the pad PD than the insulating layer 12. The insulating layer 114 has an opening OP1. Focusing on the cross-sectional shape of the organic insulating layer IL, the organic insulating layer IL has a stepped cross section whose thickness decreases toward the opening OP1.

[0106] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 114 and the thickness of the insulating layer 12, and corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 12A of the insulating layer 12. The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 114 between the insulating layer 12 and the opening OP1, and corresponds to the distance along the Z direction from the upper surface of the wiring layer 112 to the substantially flat upper surface 114A of the insulating layer 114. The thickness T2 is smaller than the thickness T1. The upper surface 114A is located between the upper surface 12A and the opening OP1. The upper surface 114A is located below the upper surface 12A.

[0107] 13, the partition wall 7 is disposed above the upper surface 12A, but is not disposed above the upper surface 114A. However, the partition wall 7 may be disposed above the upper surface 114A.

[0108] The organic insulating layer IL having a stepped cross section can be formed, for example, by the following method. First, an insulating layer 114 having an opening OP1 and an upper surface 114A is formed on an insulating layer 113. Then, a metal layer MT is formed. Then, an insulating layer 12 having an upper surface 12A is formed. In this way, an organic insulating layer IL having the above-mentioned cross-sectional shape is formed.

[0109] Fig. 14 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 14 is different from the configuration example shown in Fig. 13 in that the inorganic insulating layer 5 does not have an opening.

[0110] Fig. 15 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 15 differs from the configuration example shown in Fig. 11 in that the organic insulating layer IL having a stepped cross section is a single layer body of the insulating layer 12. In other words, the organic insulating layer IL does not have the insulating layer 114. The insulating layer 12 has an opening OP1.

[0111] The thickness T1 of the organic insulating layer IL corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 121A of the insulating layer 12. The thickness T2 of the organic insulating layer IL corresponds to the distance along the Z direction from the upper surface of the metal layer MT to the substantially flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the opening OP1. The upper surface 122A is located below the upper surface 121A.

[0112] The partition walls 7 and 8 are disposed above the organic insulating layer IL and on the inorganic insulating layer 5. In the example shown in Fig. 15, the partition wall 7 is disposed above the upper surface 121A, but is not disposed above the upper surface 122A. However, the partition wall 7 may be disposed above the upper surface 122A.

[0113] The insulating layer 12 can be formed, for example, by the following method. An insulating layer is formed from, for example, a positive organic material on the entire surface of the mother substrate 100 for a display device on which the metal layer MT is formed. The insulating layer is then exposed to light. In this exposure process, the exposure amount at the opening OP1 is set to a maximum, and is set to decrease stepwise from the opening OP1 toward the outside. The exposed insulating layer is then developed. The insulating layer is then baked. As a result, the insulating layer 12 (organic insulating layer IL) having the above-mentioned cross-sectional shape is formed.

[0114] Fig. 16 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 16 is different from the configuration example shown in Fig. 15 in that the inorganic insulating layer 5 does not have an opening.

[0115] Next, a configuration example of the display device mother substrate 100 including the opening OP3 will be described.

[0116] Fig. 17 is a schematic cross-sectional view of the display device mother substrate 100 taken along line XVII-XVII in Fig. 8. The insulating layer 114 is disposed on the substrate 10. The insulating layer 12 is disposed on the insulating layer 114. The insulating layer 12 has an opening OP3 that exposes the insulating layer 114. In other words, the insulating layer 114 does not have an opening at a position overlapping with the opening OP3.

[0117] The organic insulating layer IL described above has an insulating layer 114 and an insulating layer 12. The opening OP3 corresponds to an opening in the organic insulating layer IL. The inorganic insulating layer 5 covers the insulating layer 12 and contacts the insulating layer 114 at the opening OP3.

[0118] The partition wall 7 is disposed above the organic insulating layer IL. The partition wall 7 has a lower portion 71 disposed on the inorganic insulating layer 5 and an upper portion 72 disposed on the lower portion 71. The upper portion 72 has a width greater than that of the lower portion 71.

[0119] Next, another example of the cross-sectional structure of the display device mother substrate 100 including the window portion WP will be described.

[0120] Fig. 18 is a schematic cross-sectional view showing another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 18 differs from the configuration example shown in Fig. 17 in that insulating layers 111 and 113 are arranged and insulating layer 114 has an opening.

[0121] The insulating layer 111 is disposed on the substrate 10. The insulating layer 113 is disposed on the insulating layer 111. The insulating layer 114 is disposed on the insulating layer 113. The insulating layer 12 covers the insulating layer 114 and has an opening OP3 in a region in contact with the insulating layer 113. In other words, the insulating layer 114 has an opening at a position overlapping with the opening OP3.

[0122] In the example shown in Fig. 18, the organic insulating layer IL has a cross-sectional shape similar to that of the organic insulating layer IL shown in Fig. 11. The thickness T1 of the organic insulating layer IL is the sum of the thicknesses of the insulating layers 114 and 12, and corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 121A of the insulating layer 12.

[0123] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 12, and corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the opening OP3. The upper surface 122A is located below the upper surface 121A.

[0124] The inorganic insulating layer 5 covers the insulating layer 12, and covers the insulating layer 113 at the opening OP3. The partition wall 7 is disposed above the organic insulating layer IL. In the example shown in Fig. 18, the partition wall 7 is disposed above the upper surface 121A, but is not disposed above the upper surface 122A. However, the partition wall 7 may be disposed above the upper surface 122A.

[0125] Fig. 19 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 19 is different from the configuration example shown in Fig. 18 in that the insulating layers 111 and 113 are omitted.

[0126] The insulating layer 114 is disposed on the substrate 10. The insulating layer 12 covers the insulating layer 114, and has an opening OP3 in a region in contact with the substrate 10. The inorganic insulating layer 5 covers the substrate 10 at the opening OP3.

[0127] Fig. 20 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 20 differs from the configuration example shown in Fig. 19 in that the inorganic insulating layer 5 is omitted. The partition walls 7 are disposed on the insulating layer 12.

[0128] Fig. 21 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 20 differs from the configuration example shown in Fig. 18 in that the insulating layer 114 extends further toward the center of the opening OP3 than the insulating layer 12. The insulating layer 114 has an opening OP3.

[0129] In the example shown in Fig. 21, the organic insulating layer IL has a cross-sectional shape similar to that of the organic insulating layer IL shown in Fig. 13. The thickness T1 of the organic insulating layer IL is the sum of the thicknesses of the insulating layers 114 and 12, and corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 12A of the insulating layer 12.

[0130] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 114 exposed from the insulating layer 12, and corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 114A of the insulating layer 114. The thickness T2 is smaller than the thickness T1. The upper surface 114A is located between the upper surface 12A and the opening OP3. The upper surface 114A is located below the upper surface 12A.

[0131] The inorganic insulating layer 5 covers the insulating layer 12, covers the insulating layer 114 exposed from the insulating layer 12, and covers the insulating layer 113 at the opening OP3. The partition wall 7 is disposed above the organic insulating layer IL. In the example shown in Fig. 20, the partition wall 7 is disposed above the upper surface 12A, but is not disposed above the upper surface 114A. However, the partition wall 7 may be disposed above the upper surface 114A.

[0132] Fig. 22 is a schematic cross-sectional view showing yet another configuration example of the mother substrate 100 for a display device. The configuration example shown in Fig. 22 differs from the configuration example shown in Fig. 21 in that the insulating layers 111 and 113 are omitted. The insulating layer 114 is disposed on the substrate 10 and has an opening OP3. The inorganic insulating layer 5 covers the substrate 10 at the opening OP3.

[0133] Fig. 23 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 23 differs from the configuration example shown in Fig. 22 in that the inorganic insulating layer 5 is omitted. The partition walls 7 are disposed on the insulating layer 12.

[0134] Fig. 24 is a schematic cross-sectional view showing yet another configuration example of the display device mother substrate 100. The configuration example shown in Fig. 24 differs from the configuration example shown in Fig. 18 in that the organic insulating layer IL having a stepped cross section is a single layer body of the insulating layer 12. In other words, the organic insulating layer IL does not have the insulating layer 114. The insulating layer 12 has an opening OP3.

[0135] In the example shown in Fig. 24, the organic insulating layer IL has a cross-sectional shape similar to that of the organic insulating layer IL shown in Fig. 15. The thickness T1 of the organic insulating layer IL corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 121A of the insulating layer 12.

[0136] The thickness T2 of the organic insulating layer IL corresponds to the distance along the Z direction from the upper surface of the insulating layer 113 to the substantially flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the opening OP3. The upper surface 122A is located lower than the upper surface 121A.

[0137] The inorganic insulating layer 5 covers the insulating layer 12, and covers the insulating layer 113 at the opening OP3. The partition wall 7 is disposed above the organic insulating layer IL. In the example shown in Fig. 24, the partition wall 7 is disposed above the upper surface 121A, but is not disposed above the upper surface 122A. However, the partition wall 7 may be disposed above the upper surface 122A.

[0138] Fig. 25 is a schematic cross-sectional view showing yet another configuration example of the mother substrate 100 for a display device. The configuration example shown in Fig. 25 differs from the configuration example shown in Fig. 24 in that the insulating layers 111 and 113 are omitted. An insulating layer 12 corresponding to the organic insulating layer IL is disposed on the substrate 10 and has an opening OP3. An inorganic insulating layer 5 covers the substrate 10 at the opening OP3.

[0139] Fig. 26 is a schematic cross-sectional view showing yet another configuration example of the mother substrate 100 for a display device. The configuration example shown in Fig. 26 differs from the configuration example shown in Fig. 25 in that the inorganic insulating layer 5 is omitted. An insulating layer 12 corresponding to the organic insulating layer IL is disposed on the substrate 10 and has an opening OP3. A partition wall 7 is disposed on the insulating layer 12.

[0140] The display device DSP configured as above can improve the yield in the manufacturing process. Specifically, the display device mother substrate 100 (display device DSP) includes partition walls 7 arranged along the edges 30 and 40 of the openings OP1 and OP3 on the outer side of the openings OP1 and OP3 in the peripheral area SA and the marginal portion MP.

[0141] The laminated films FL1, FL2, and FL3 (shown in FIG. 3) formed by vapor deposition have a weak adhesion to the base, and therefore may peel off from the base during the manufacturing process of the display device DSP. If such peeling spreads, the laminated films FL1, FL2, and FL3 and the sealing layers SE1, SE2, and SE3 thereon may peel off and become a cause of contamination of the chambers of the manufacturing line.

[0142] In this embodiment, the stacked films FL1, FL2, and FL3 are divided by the overhanging partition wall 7. Therefore, even if peeling occurs in the stacked films FL1, FL2, and FL3, the peeling does not spread easily. In addition, the stacked films FL1, FL2, and FL3 divided by the partition wall 7 are held down by the sealing layers SE1, SE2, and SE3 formed to bite into the lower part of the upper part 72 of the partition wall 7, so that they are unlikely to peel off.

[0143] The laminated films FL1, FL2, FL3 tend to peel off at the edges 30, 40 of the openings OP1, OP3. Specifically, the laminated films FL1, FL2, FL3 tend to peel off starting from the corners of the edges 30, 40 of the openings OP1, OP3.

[0144] In this embodiment, the partition 7 surrounds at least a part of the corner portion in the peripheral region SA and the margin portion MP, thereby making it possible to suppress peeling of the stacked films FL1, FL2, and FL3 in the portions that tend to become the starting points of peeling.

[0145] In this embodiment, the radius of curvature R1 of the rounded portions 35, 45 is 25 μm or more. When the corner portions have a right-angled shape, the side surfaces of the organic insulating layer IL that form the corner portions are steeper than the edges 31, 32.

[0146] Such a shape of the organic insulating layer IL may cause residues of the materials constituting the partition wall 7 to be generated inside the opening OP1 during the manufacturing process. Such residues become the starting point for peeling of the laminated films FL1, FL2, and FL3. The larger the radius of curvature R1 of the rounded portions 35 and 45, the less likely the residues are to be generated. Residues were observed when the radius of curvature R1 of the rounded portions 35 and 45 was up to about 20 μm.

[0147] By making the radius of curvature R1 25 μm or more as in the rounded portions 35 and 45, the shape of the side surface of the organic insulating layer IL in the rounded portions 35 and 45 can be made gentle. This makes it difficult for the above-mentioned residues to be generated in the manufacturing process. As a result, the rounded portions 35 and 45 are less likely to become the starting point for peeling off the laminated films FL1, FL2, and FL3.

[0148] As described above, according to the configuration of this embodiment, it is possible to suppress peeling of the stacked films FL1, FL2, and FL3 and improve the yield in the manufacturing process. In addition, various other advantageous effects can be obtained from this embodiment.

[0149] Next, other examples of the openings OP1, OP3 and the partition wall 7 in the peripheral area SA and the marginal portion MP will be described. In the following, the area including the pad PD will be mainly described, but the configuration examples of the embodiments described below can also be applied to the area including the window portion WP. Of the configurations in the following embodiments, the same ones as in the first embodiment can be applied to the parts not specifically mentioned.

[0150] [Second embodiment] Fig. 27 is a schematic plan view showing a region including pads PD in the peripheral region SA or marginal portion MP in this embodiment. Fig. 28 is a partial enlarged view of part XXVIII in Fig. 27. The example shown in Fig. 27 is different from the configuration example shown in Fig. 7 in the shape of the partition wall 7.

[0151] 27, the partition wall 7 surrounds the opening OP1 on the outside thereof. The partition wall 7 includes a pair of partition wall portions 7X extending in the X direction, a pair of partition wall portions 7Y extending in the Y direction, and a partition wall portion 7Z connecting the partition wall portions 7X and 7Y.

[0152] 28, the partition wall 7Z has an arc shape in a plan view. The partition wall 7Z has a predetermined radius of curvature. Focusing on the rounded portion 35, the partition wall 7Z is disposed along the rounded portion 35.

[0153] The partition 7 is disposed at a certain distance from the edge 30 of the opening OP1. Specifically, the partition portion 7X is disposed at a certain distance from the edge 31, the partition portion 7Y is disposed at a certain distance from the edge 33, and the partition portion 7Z is disposed at a certain distance from the round portion 35. The distances here are the distances along the normal direction of the edge 30.

[0154] In other words, the partition 7 is disposed parallel to the edge 30 of the opening OP1. In such a case, the distance W1 (shown in FIG. 28) from the edge 30 of the opening OP1 to the partition 7 is approximately constant along the edge 30 of the opening OP1.

[0155] The configuration of this embodiment can also provide the same effects as those of the first embodiment. In this embodiment, the partition 7 is disposed at a constant distance from the edge 30 of the opening OP1. More specifically, the distance between the partition portion 7Z of the partition 7 and the rounded portion 35 of the edge 30 is constant.

[0156] Peeling of the laminated films FL1, FL2, FL3 is more likely to occur as the distance between the partition wall 7 and the edge 30 increases. By forming the partition wall portion 7Z in an arc shape and keeping the distance between the partition wall portion 7Z and the round portion 35 constant, the distance between the partition wall 7 and the edge 30 can be made smaller than in the first embodiment.

[0157] This makes it possible to further suppress peeling of the stacked films FL1, FL2, and FL3 at the corners, which are likely to be the starting points of peeling. Even if peeling occurs between the partition wall portion 7Z and the rounded portion 35, the partition wall 7 can suppress the peeling from expanding, thereby making it possible to reduce the range of peeling. As a result, the yield in the manufacturing process can be improved.

[0158] [Third embodiment] Fig. 29 is a schematic plan view showing an area including pads PD in the peripheral area SA or marginal portion MP in this embodiment. The example shown in Fig. 29 is different from the configuration example shown in Fig. 7 in that the partition wall 7 has a plurality of segments arranged at intervals. The partition wall 7 has segments 7A, 7B, 7C, and 7D. Each of the segments 7A, 7B, 7C, and 7D has an L-shape.

[0159] The segments 7A, 7B, 7C, and 7D are each disposed outside the round portion 35. Gaps G1 are formed between adjacent segments 7A and 7B in the X direction, between adjacent segments 7C and 7D in the X direction, between adjacent segments 7A and 7D in the Y direction, and between adjacent segments 7B and 7C in the Y direction.

[0160] Focusing on segment 7A, segment 7A has end 7Ax facing segment 7B and end 7Ay facing segment 7D. Here, as shown in Fig. 29, the distance between edge 33 and end 7Ax in the X direction is defined as distance DX, and the distance between edge 31 and end 7Ay in the Y direction is defined as distance DY.

[0161] The segment 7A is formed so that the distance DX and the distance DY are at least 50 μm or more. In this case, the segment 7A is disposed outside the rounded portion 35 and at least a part of the edges 31 and 33 connected to the rounded portion 35.

[0162] When the radius of curvature R1 (shown in FIG. 9) of the rounded portion 35 is 25 μm or more, it is preferable that the segment 7A is formed so that the distance DX and the distance DY are each 50 μm or more. Here, the relationship with the opening OP1 has been described with focus on the segment 7A, but the segments 7B, 7C, and 7D are also formed to have a similar structure.

[0163] The configuration of this embodiment can also provide the same effects as those of Embodiment 1. In this embodiment, the partition wall 7 has segments 7A, 7B, 7C, and 7D that are spaced apart from each other.

[0164] If the partition wall 7 is not divided into a plurality of segments, there is a possibility that a resist (for example, a resist for patterning the inorganic insulating layer 5) disposed behind the partition wall 7 in the manufacturing process may be poorly formed.

[0165] That is, the partition 7 suppresses the spread of the resist, and there may be some places where the resist is not sufficiently filled under the upper part 72 of the partition 7. In this case, when the resist is dried in a reduced pressure environment, the space where the resist is not placed may expand and burst.

[0166] By forming the partition wall 7 with a plurality of segments as in this embodiment, the resist spreads easily through the gap G1, which makes it possible to suppress defects in the shape of the resist, thereby improving the yield in the manufacturing process.

[0167] [Fourth embodiment] Fig. 30 is a schematic plan view showing a region including pads PD in the peripheral region SA or marginal portion MP in this embodiment. The example shown in Fig. 30 is different from the configuration example shown in Fig. 27 in that the partition wall 7 is composed of a plurality of segments arranged at intervals.

[0168] The partition wall 7 has segments 7A, 7B, 7C, and 7D. Each of the segments 7A, 7B, 7C, and 7D has an L-shape. Each of the segments 7A, 7B, 7C, and 7D is disposed outside the round portion 35.

[0169] Gaps G1 are formed between adjacent segments 7A, 7B in the X direction, between adjacent segments 7C, 7D in the X direction, between adjacent segments 7A, 7D in the Y direction, and between adjacent segments 7B, 7C in the Y direction.

[0170] Focusing on the segment 7A, the segment 7A includes a partition portion 7X extending in the X direction, a partition portion 7Y extending in the Y direction, and a partition portion 7Z connecting the partition portion 7X and the partition portion 7Y. The partition portion 7Z has an arc shape in a plan view. The partition portion 7Z has a predetermined radius of curvature.

[0171] Segment 7A is disposed at a fixed distance from edge 30 of opening OP1. Distance W1 from edge 30 of opening OP1 to segment 7A is fixed along edge 30 of opening OP1. Here, the relationship with opening OP1 has been described with focus on segment 7A, but segments 7B, 7C, and 7D are also formed to have a similar structure.

[0172] The configuration of this embodiment is a combination of the configuration of the second embodiment described with reference to Fig. 27 and the configuration of the third embodiment described with reference to Fig. 29. The configuration of this embodiment can also provide the same effects as those of the above-mentioned embodiments.

[0173] [Fifth embodiment] Fig. 31 is a schematic plan view showing a region including the pad PD in the peripheral region SA or the marginal portion MP in this embodiment. The example shown in Fig. 31 is different from the configuration example shown in Fig. 7 in that the edge 30 of the opening OP1 does not have a rounded portion.

[0174] Corner portion 37 of edge 30 is formed by connecting edge 31 and edge 33. Corner portion 37 has a right-angled shape as shown in Fig. 13. Here, the right-angled shape does not only mean that the angle formed by edges 31 and 33 is 90 degrees, but also includes variations in the angle caused by the manufacturing process.

[0175] The configuration of this embodiment can also provide the same effects as the first embodiment.

[0176] [Sixth embodiment] Fig. 32 is a schematic plan view showing a region including pads PD in the peripheral region SA or marginal portion MP in this embodiment. The example shown in Fig. 32 is different from the configuration example shown in Fig. 31 in that the partition wall 7 is composed of a plurality of segments arranged at intervals.

[0177] The partition wall 7 has segments 7A, 7B, 7C, and 7D. Each of the segments 7A, 7B, 7C, and 7D has an L-shape. Each of the segments 7A, 7B, 7C, and 7D is disposed outside the round portion 35.

[0178] Gaps G1 are formed between adjacent segments 7A, 7B in the X direction, between adjacent segments 7C, 7D in the X direction, between adjacent segments 7A, 7D in the Y direction, and between adjacent segments 7B, 7C in the Y direction. Focusing on segment 7A, segment 7A has an end 7Ax facing segment 7B and an end 7Ay facing segment 7D.

[0179] When the corner portion 37 has a right angle shape, the segment 7A is preferably formed so that the distance DX and the distance DY are each 100 μm or more. Not only when the corner portion 37 has a right angle shape, but also when the radius of curvature R1 (shown in FIG. 9) of the round portion 35 is smaller than 25 μm, the segment 7A is preferably formed so that the distance DX and the distance DY are each 100 μm or more.

[0180] Here, the relationship with the opening OP1 has been described with focus on the segment 7A, but the segments 7B, 7C, and 7D are also formed to have a similar structure.

[0181] The configuration of this embodiment is a combination of the configuration of the third embodiment described with reference to Fig. 29 and the configuration of the fifth embodiment described with reference to Fig. 31. The configuration of this embodiment can also provide the same effects as those of the above-mentioned embodiments.

[0182] [Seventh embodiment] Fig. 33 is a schematic plan view showing a region including pads PD in the peripheral region SA or marginal portion MP in this embodiment. The example shown in Fig. 33 is different from the configuration example shown in Fig. 29 in that the openings OP1 and OP2 have a circular shape.

[0183] The openings OP1 and OP2 each have a circular shape in a plan view. In this embodiment, a part of the edge 30 of the opening OP1 in the circumferential direction corresponds to the rounded portion of the opening OP1. The radius (curvature radius) of the edge 30 of the opening OP1 is, for example, 25 μm or more, and in one example, the radius is 200 μm, but is not limited to this example. The area of ​​the opening OP2 is smaller than the area of ​​the opening OP1. In other words, the radius of the edge of the opening OP2 is smaller than the radius of the edge 30 of the opening OP1.

[0184] The partition 7 is disposed along the edge 30 of the opening OP1. The partition 7 has segments 7A, 7B, 7C, and 7D. Each of the segments 7A, 7B, 7C, and 7D has an L-shape. A gap G1 is formed between the segments 7A and 7B adjacent to each other in the X direction, between the segments 7C and 7D adjacent to each other in the X direction, between the segments 7A and 7D adjacent to each other in the Y direction, and between the segments 7B and 7C adjacent to each other in the Y direction.

[0185] The configuration of this embodiment can also provide the same effects as those of the first embodiment. In this embodiment, by making the opening OP1 circular, no part that is likely to become a starting point for peeling is formed, so that peeling of the stacked films FL1, FL2, and FL3 can be further suppressed. As a result, the yield in the manufacturing process can be improved.

[0186] [Eighth embodiment] Fig. 34 is a schematic plan view showing a region including pads PD in the peripheral region SA or the marginal portion MP in this embodiment. The example shown in Fig. 34 is different from the configuration example shown in Fig. 33 in the shape of the partition wall 7.

[0187] The partition 7 has a substantially circular shape in a plan view. The partition 7 is disposed at a constant distance from the edge 30 of the opening OP1. In other words, the partition 7 is disposed parallel to the edge 30 of the opening OP1. That is, the distance W2 from the edge 30 of the opening OP1 to the partition 7 is constant along the edge 30 of the opening OP1.

[0188] The partition wall 7 has segments 7A, 7B, 7C, and 7D. Each of the segments 7A, 7B, 7C, and 7D has an arc shape. The segments 7A, 7B, 7C, and 7D are arranged at intervals in the circumferential direction. A gap G1 is formed between the segments 7A, 7B, 7C, and 7D adjacent to each other in the circumferential direction.

[0189] The configuration of this embodiment can also provide the same effects as those of the first embodiment. In this embodiment, the segments 7A, 7B, 7C, and 7D are formed in an arc shape, so that the distance to the edge 30 is constant, and the distance between the partition wall 7 and the edge 30 can be made smaller than that of the seventh embodiment.

[0190] 33 and 34, the partition wall 7 has segments 7A, 7B, 7C, and 7D, but the partition wall 7 may surround the opening OP1. In other words, the partition wall 7 may be integrally formed so as to not provide the gap G1.

[0191] [Ninth embodiment] Fig. 35 is a schematic plan view showing a region including pads PD in the peripheral region SA or marginal portion MP in this embodiment. Fig. 35 shows an enlarged view of the vicinity of rounded portion 35 of opening OP1. Edge 30 of opening OP1 has edges 31 and 33 and rounded portion 35. Partition wall 7 is disposed along edge 30 of opening OP1.

[0192] The partition wall 7 has segments 7A and 7D. Focusing on the segment 7A, the segment 7A has an arc shape that follows the round portion 35. The segment 7A is separated from the segment 7D in the Y direction.

[0193] Focusing on the vicinity of the edge 33, the partition 7 further has a segment 7E. The segment 7E is disposed between the adjacent segments 7A and 7D. The segment 7E has a linear shape along the Y direction.

[0194] The segment 7E is disposed at a distance from the segments 7A and 7D in the Y direction. A gap G2 is formed between the segment 7A and the segment 7E, and between the segment 7D and the segment 7E.

[0195] The display device mother substrate 100 (display device DSP) may further include a partition wall 9 (third partition wall). The partition wall 9 is disposed outside the partition wall 7 so as to overlap the gap G2. Specifically, the partition wall 9 overlaps the gap G2 when viewed in the X direction. The distance of the partition wall 9 in the Y direction is greater than, for example, the distance of the gap G2 in the Y direction.

[0196] Although not shown, the partition wall 9 has a conductive lower portion disposed on the inorganic insulating layer 5 and an upper portion disposed on the lower portion. The upper portion has a width greater than that of the lower portion. The mother substrate 100 for a display device (display device DSP) may further include a partition wall 90. The partition wall 90 is disposed outside the partition wall 9.

[0197] The configuration of this embodiment can also provide the same effects as those of Embodiment 1. In this embodiment, the partition 9 is disposed outside the partition 7 so as to overlap the gap G2.

[0198] As a result, even if peeling of the stacked films FL1, FL2, FL3 occurs through the gap G2, the expansion of the peeling can be suppressed by the partition wall 9. As a result, the yield in the manufacturing process can be improved.

[0199] The segment 7E described with reference to Fig. 35 can also be applied to each of the embodiments described with reference to Fig. 29, Fig. 30, Fig. 32, and Fig. 33. A plurality of segments 7E may be arranged so as to be spaced apart from each other in the X and Y directions.

[0200] [Tenth embodiment] Fig. 36 is a schematic plan view showing an area including pads PD in the peripheral area SA or marginal portion MP in this embodiment. In the example shown in Fig. 36, the partition wall 7 is not disposed outside the opening OP1. In this case, the edge 30 of the opening OP1 has a rounded portion 35. The radius of curvature R1 (shown in Fig. 9) of the rounded portion 35 is 25 μm or more, as described above.

[0201] The configuration of this embodiment also makes it possible to improve the yield in the manufacturing process. Specifically, the edge 30 of the opening OP1 has a rounded portion 35. By rounding the corner portion, the corner portion becomes less likely to become a starting point for peeling, and peeling of the stacked films FL1, FL2, and FL3 can be suppressed.

[0202] Next, the shapes of the openings OP1, OP3 applicable to each of the above-mentioned embodiments will be described.

[0203] 37 is a diagram for explaining another shape of the opening OP3 applicable to the window portion WP. The opening OP3 has an oval shape that is long in the Y direction. The edge 40 of the opening OP3 includes a pair of edges 47 extending in the Y direction and a pair of rounded portions 49 connecting the ends of the pair of edges 47. The radius of curvature of the rounded portions 49 is 25 μm or more.

[0204] The partition wall 7 surrounds the opening OP3 from the outside of the opening OP3. The partition wall 7 may be disposed at a certain distance from the edge 40 of the opening OP3. The partition wall 7 may have a plurality of segments spaced apart from each other.

[0205] Here, the opening OP3 is used for the description, but the same shape can be applied to the opening OP1. Also, shapes that can be applied to the openings OP1 and OP3 include not only a circular shape (shown in FIGS. 33 and 34) and an oval shape, but also an elliptical shape.

[0206] All display devices and motherboards for display devices that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices and motherboards for display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0207] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of each of the above-mentioned embodiments, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0208] Furthermore, with regard to other effects and advantages brought about by the aspects described in each of the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately conceived by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0209] 5...inorganic insulating layer, 6,7...partition wall, 7A,7B,7C,7D,7E...segments, 8,9...partition wall, 10...substrate, 30,31,33...edge, 35...rounded portion, 37...corner portion, 40,41,43...edge, 45...rounded portion, 61...lower portion, 62...upper portion, 63...bottom layer, 64...axis layer, 71...lower portion, 72...upper portion, 100...mother substrate for display device, AP1,AP2,AP3...pixel opening, DA...display area, DE1,DE2,DE3...display element, DSP...display device, G1,G2...gap, IL...organic insulating layer, MP...margin portion, OP1,OP2,OP3...opening, PNL...display panel, PP...panel portion, SA...peripheral area.

Claims

1. A substrate; an organic insulating layer disposed above the substrate across a display area in which a plurality of display elements are disposed and a peripheral area around the display area; a first partition disposed between adjacent display elements above the organic insulating layer; a second partition disposed in the peripheral region, each of the first partition and the second partition has a conductive lower portion and an upper portion protruding from a side surface of the lower portion; the organic insulating layer has an opening in the peripheral region, The second partition is disposed outside the opening and along an edge of the opening. Display device.

2. the opening has a first edge extending in a first direction, a second edge extending in a second direction intersecting the first direction, and a corner portion connected to the first edge and the second edge, At least a portion of the second partition wall is disposed outside the corner portion. The display device according to claim 1 .

3. the second partition wall is formed in the first direction at a distance of 50 μm or more from the second edge, and is formed in the second direction at a distance of 50 μm or more from the first edge, The display device according to claim 2 .

4. The corner portion has an arc shape. The display device according to claim 3 .

5. The radius of curvature of the corner portion is 25 μm or more. The display device according to claim 4.

6. The opening has a circular shape. The display device according to claim 1 .

7. The second partition surrounds the opening. The display device according to claim 1 .

8. The second partition is disposed outside the opening at a certain distance from the edge of the opening. The display device according to claim 1 .

9. The second partition has a plurality of spaced apart segments. The display device according to claim 1 .

10. a third partition wall disposed outside the second partition wall so as to overlap with the gaps between the adjacent segments; The display device according to claim 9.

11. A panel unit having a display area for displaying an image and a peripheral area surrounding the display area; a margin on the outer side of the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a first partition disposed in the display region above the organic insulating layer; A second partition wall is disposed in the marginal portion, each of the first partition and the second partition has a conductive lower portion and an upper portion protruding from a side surface of the lower portion; the organic insulating layer has an opening in the marginal portion, The second partition is disposed outside the opening and along an edge of the opening. Mother board for display devices.

12. the opening has a first edge extending in a first direction, a second edge extending in a second direction intersecting the first direction, and a corner portion connected to the first edge and the second edge, At least a portion of the second partition wall is disposed outside the corner portion. The mother substrate for a display device according to claim 11.

13. the second partition wall is formed in the first direction at a distance of 50 μm or more from the second edge, and is formed in the second direction at a distance of 50 μm or more from the first edge, The mother substrate for a display device according to claim 12.

14. The corner portion has an arc shape. The mother substrate for a display device according to claim 13.

15. The radius of curvature of the corner portion is 25 μm or more. The mother substrate for a display device according to claim 14.

16. The opening has a circular shape. The mother substrate for a display device according to claim 11.

17. The second partition surrounds the opening. The mother substrate for a display device according to claim 11.

18. The second partition is disposed outside the opening at a certain distance from the edge of the opening. The mother substrate for a display device according to claim 11.

19. The second partition has a plurality of spaced apart segments. The mother substrate for a display device according to claim 11.

20. a third partition wall disposed outside the second partition wall so as to overlap with the gaps between the adjacent segments; 20. The mother substrate for a display device according to claim 19.

21. A substrate; an organic insulating layer disposed above the substrate across a display area in which a plurality of display elements are disposed and a peripheral area around the display area; a partition wall disposed between adjacent display elements above the organic insulating layer, the partition wall has a conductive lower portion and an upper portion protruding from a side surface of the lower portion, the organic insulating layer has an opening in the peripheral region, The opening has a rounded portion in a plan view, The radius of curvature of the round portion is 25 μm or more. Display device.

22. The opening has a first edge extending in a first direction and a second edge extending in a second direction intersecting the first direction, The round portion connects the first edge and the second edge. The display device according to claim 21.

23. The opening has a circular shape. The display device according to claim 21.

24. A panel unit having a display area for displaying an image and a peripheral area surrounding the display area; a margin on the outer side of the panel portion; an organic insulating layer disposed across the panel portion and the marginal portion; a partition wall disposed in the display region above the organic insulating layer; the partition wall has a conductive lower portion and an upper portion protruding from a side surface of the lower portion, the organic insulating layer has an opening in the marginal portion, The opening has a rounded portion, The radius of curvature of the round portion is 25 μm or more. Mother board for display devices.

25. The opening has a first edge extending in a first direction and a second edge extending in a second direction intersecting the first direction, The round portion connects the first edge and the second edge.

25. The mother substrate for a display device according to claim 24.

26. The opening has a circular shape.

25. The mother substrate for a display device according to claim 24.

Images