Product-sum arithmetic circuit and information processing device provided with product-sum arithmetic circuit

Abstract

To provide a product-sum arithmetic circuit capable of remarkably reducing power consumption and of suppressing heat generation, in particular, a product-sum arithmetic circuit suitable for executing a process of product-sum operation at an output layer upon receiving data on an intermediate layer in the processes by a neural network.SOLUTION: A product-sum arithmetic circuit includes: N voltage followers 11 which output, relative to N input signals including n negative voltage signals and p positive voltage signals, output signals electrically separated from the input signals; an n-side summing circuit 12 that executes a weighting summing process on the output signals with respect to the n negative voltage signals among the output signals by the N voltage followers so as to be output as first signals; a p-side summing circuit 13 that executes a weighting summing process on the output signals with respect to the p positive voltage signals so as to be output as second signals; and an inversion amplifier circuit 14 which adds the first signal polarity and the second signal polarity by polarity, and which outputs an output signal amplified by a predetermined amplification rate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a product-sum operation circuit and an information processing device equipped with the product-sum operation circuit, and more particularly to a product-sum operation circuit suitable for receiving data from an intermediate layer and performing product-sum operation processing in an output layer in neural network processing used in machine learning. [Background technology]

[0002] In recent years, the social implementation of artificial intelligence (AI) has been progressing in earnest. The processing of neural networks used in machine learning, which is the core technology of artificial intelligence (AI), is usually carried out on general-purpose computers such as personal computers (hereinafter referred to as PCs). When neural network processing is performed by a general-purpose computer, the load is heavy, and as the size of the neural network increases, the power consumption tends to become very large, and the amount of heat generated also increases accordingly.

[0003] As a measure to reduce power consumption, a case has been disclosed in which the processing performed in the intermediate layer (learning section) nodes in the processing of a neural network is performed using dedicated hardware (Patent Document 1).

[0004] Fig. 7 is an explanatory diagram of a conventional information processing device that processes neural networks. In Fig. 7, an AC sine wave or the like is input to the middle layer, where an output signal that has undergone learning processing or the like using dedicated hardware is output to the output layer, which is a PC. The PC converts the analog signal into a digital signal using A / D conversion, then executes processing such as product-sum calculation processing using software to output the signal to the outside, converts the digital signal into an analog signal using D / A conversion, and finally outputs the analog signal.

[0005] In order to further reduce power consumption, it would be effective to execute the output layer processing performed on the PC, particularly the product-sum calculation processing, using appropriate hardware. However, the reality is that there are few publicly available appropriate and specific circuits for performing the product-sum calculation processing in the output layer using hardware.

[0006] It is expected that in the future, the use of electronics will increase in robots and other machines that work in collaboration with humans, but if they were to overheat and go out of control, it would be a major problem. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2020-204888 A Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention is made to solve these problems, and its object is to provide hardware for a product-sum operation circuit, and an information processing device equipped with a product-sum operation circuit, which can significantly reduce power consumption and generate little heat, and in particular to provide specific product-sum operation circuit hardware that is most suitable for receiving data from an intermediate layer and performing processes such as product-sum operation in an output layer in neural network processing. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, the present invention provides a product-sum operation circuit that performs a product-sum operation on N input signals consisting of n negative voltage signals and p positive voltage signals, and outputs the result of the product-sum operation as an output signal, the product-sum operation circuit including: N voltage followers that receive the N input signals respectively and output output signals that are electrically isolated from the input side; an n-side adder circuit that performs weighted addition processing on output signals corresponding to the n negative voltage signals among the output signals output by the N voltage followers, and outputs the result as a first signal; a p-side adder circuit that performs weighted addition processing on output signals corresponding to the p positive voltage signals among the output signals output by the N voltage followers, and outputs the result as a second signal; and an inverting amplifier circuit that aligns the polarities of the first signal and the second signal, adds them together, and outputs an output signal amplified by a predetermined amplification factor (N is an integer of 2 or more, and n and p are integers that satisfy N=n+p).

[0010] The present invention also provides a product-sum operation circuit which performs a product-sum operation on N input signals consisting of n negative voltage signals and p positive voltage signals and outputs the result of the product-sum operation as an output signal, comprising: a multiplexer which sequentially and periodically switches and outputs one signal selected from the N input signals in response to a first control signal; a control circuit which holds the voltage values ​​of the N signals which are sequentially and periodically switched and output from the multiplexer for one cycle and outputs them as N digital signals; a parallel D / A converter which receives the N digital signals output from the control circuit and outputs N analog signals which have been D / A converted; and a first control signal which selects n negative voltage signals from the N output signals output from the D / A converter. a p-side adder circuit which performs weighted addition processing on output signals corresponding to p positive voltage signals among the N output signals output by the D / A converter and outputs the result as a second signal; and an inverting amplifier circuit which aligns the polarities of the first and second signals, adds them together, and outputs an output signal amplified by a predetermined amplification factor, wherein the control circuit outputs the first control signal for controlling the multiplexer, and is a product-sum operation circuit which is capable of controlling the weighting for the weighted addition of the n-side adder circuit and the p-side adder circuit (N is an integer of 2 or more, and n and p are integers which satisfy N=n+p). Effect of the Invention

[0011] According to the present invention, it is possible to provide a product-sum calculation circuit with significantly reduced power consumption. In particular, by using this product-sum calculation circuit for processing the output layer of a neural network, it is possible to provide an information processing device that realizes neural network processing with significantly reduced power consumption. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram for explaining a product-sum calculation circuit according to a first embodiment and an information processing device including the product-sum calculation circuit; [Diagram 2]FIG. 1 is a diagram for explaining a circuit block used in a product-sum calculation circuit according to the first embodiment; [Diagram 3] A photograph of the actual circuit prototyped in the first embodiment. [Figure 4] FIG. 1 is a diagram showing an output waveform when a waveform is generated by the actual circuit prototyped in the first embodiment. [Diagram 5] FIG. 11 is a diagram for explaining a product-sum calculation circuit according to a second embodiment; [Figure 6] FIG. 11 is a diagram for explaining a product-sum calculation circuit according to a third embodiment; [Figure 7] FIG. 1 is a diagram for explaining conventional neural network processing; [Figure 8] Diagram of reservoir device and multiply-and-accumulate circuit mounted on board [Figure 9] A diagram showing a plurality of modules shown in FIG. 8 mounted on one substrate 20. [Figure 10] Block diagram of a robot according to embodiment 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described. Note that the present invention is not limited to the following embodiment, and various improvements and modifications are possible within the scope of the present invention.

[0014] (Embodiment 1) In this embodiment 1, the configuration and operation of a product-sum calculation circuit used in the output layer of a neural network will be described. A neural network usually includes an input layer, an intermediate layer (learning unit) that learns the input from the input layer and outputs the results, and an output layer that processes the output from the intermediate layer by weighted product-sum calculation or the like before outputting it to the outside.

[0015] Fig. 1 is a diagram for explaining a product-sum calculation circuit and an information processing device according to a first embodiment of the present invention. In comparison with Fig. 7 explained in the background art, this is a configuration in which the product-sum calculation processed by the PC in Fig. 7 is realized by hardware. The configuration and operation of Fig. 1 will be explained below.

[0016] Fig. 1 illustrates an example of a product-sum operation circuit and information processing device for the output layer in reservoir computing, a type of neural network. In Fig. 1, the middle layer 2 (Ag2Se nanowire device) uses Ag2Se (silver selenide) nanowires as a reservoir computing device (hereinafter abbreviated as reservoir device).

[0017] In addition to the above, the reservoir device is configured in a block shape including a conductor such as a carbon nanotube and a nonlinear section. The conductor may be any conductive material that connects each nonlinear section. For example, organic nanowires such as carbon nanotubes, metallic nanowires composed of one or more elements selected from the group consisting of Ag, Au, Ni, Cu, Pd, Pt, Rh, Ir, Ru, Os, Fe, Co, and Sn, and oxide nanowires composed of one or more oxides selected from the group consisting of IrO2, In2O3, SnO2, and ITO, polymerizable polymer wires, and composite wires in which the surface of insulating nanowires such as DNA is covered with a conductive material can be used as the conductor. The nonlinear section is a particle-like or a gap that enables a tunnel junction, and can be formed by conductive molecules, ions, complexes, polymers, metals, organic materials, inorganic materials, organic-inorganic hybrid materials, and mixtures thereof. For example, polyoxometalate particles can be used as the nonlinear section.

[0018] In this embodiment, a product-sum calculation circuit suitable for use in the above-mentioned reservoir device will be described below.

[0019] First, an overview of the overall signal processing operation will be described. p-pA sine wave 3 of 1000 MHz is input to the intermediate layer 2. The intermediate layer 2 is a learning LSI that performs arithmetic processing for learning, and the arithmetic processing is performed using an Ag2Se nanowire device. From the intermediate layer 2, a plurality of signals (in this embodiment, a total of N signals consisting of n negative voltage signals and p positive voltage signals, n=9, p=6, N=15) that output the results of the arithmetic processing are output to the output layer 1. Each of the plurality of signals input to the output layer 1 is first electrically separated by a voltage follower 11 into pre-input and pre-output. After that, each signal is weighted by adjusting the resistance value of each variable resistor, the weighted signals are added, and an inversion circuit and a summing amplifier circuit are used to obtain an output signal in which the above-mentioned 15 signals are appropriately summed.

[0020] The configuration and operation of the output layer 1 (the product-sum calculation circuit according to the present invention) will be described in detail below.

[0021] A total of N signals consisting of n negative voltage signals and p positive voltage signals are output from the intermediate layer 2. Each output signal is input to the non-inverting input terminal of the operational amplifier of the voltage follower 11 corresponding to the respective output signal. The operation of the voltage follower 11 shown in FIG. 2(a) will be explained. The voltage follower 11 shorts the inverting input terminal of the operational amplifier to the output terminal. With this circuit configuration, as shown in equation 1, the output voltage (Vout) of the output terminal of the operational amplifier is the same as the voltage (Vin) of the positive input terminal (the current flowing between the non-inverting input terminal and the inverting input terminal of an ideal operational amplifier is ignored).

[0022]

number

[0023] Among the output signals of the operational amplifier of voltage follower 11, the output signal for n negative voltage signals is connected to an n-side adder circuit 12 for weighted addition (corresponding to the circuit combined with reference numbers 12-1 and 12-2 in Figure 1), and the output signal for p positive voltage signals is connected to a p-side adder circuit 13 for weighted addition (corresponding to the circuit combined with reference numbers 13-1 and 13-2 in Figure 1).

[0024] 1, the n-side adder circuit 12 is composed of n n-side weighting resistors (variable resistors) 12-11, an n-side operational amplifier 12-21, and an n-side amplification factor adjustment resistor 12-22, and the p-side adder circuit 13 is composed of p p-side weighting resistors (variable resistors) 13-11, a p-side operational amplifier 13-21, and a p-side amplification factor adjustment resistor 13-22. One end of each of the n-side weighting resistor 12-11 and the p-side weighting resistor 13-11 is connected to the output end of the operational amplifier of the voltage follower 11.

[0025] FIG. 2(b) is a diagram for explaining the operation of the weighted summation circuit. The three output signals (V in,1 , V in,2 , V in,3 ) is input, and a product-sum operation is performed to output an output voltage Vout.

[0026] In Figure 2(b), the weights of the signals from the three signal lines can be adjusted. By adjusting the resistance of each variable resistor R1, R2, and R3, the weights of each input voltage (V in,1 , V in,2 , V in,3 ) can be adjusted. In other words, the output voltage Vout from the operational amplifier is the output voltage shown in Equation 2. It is also possible to adjust the amplification factor to an appropriate level by adjusting the ratio of the amplification factor adjustment resistor Rf to R1, R2, and R3. As shown in FIG. 2(b), the other ends of the weighting resistors R1, R2, R3, and Rf are connected to the non-inverting input terminal of the operational amplifier, and the inverting input terminal is connected to ground. In the n-side adder circuit 12 and p-side adder circuit 13 in FIG. 1, the value of Rf is set to 10 kΩ.

[0027]

number

[0028] Similarly, the six positive voltage signal lines (R6, R7, R8, R9, R 11 , R 12 That is, the weights of the six signal lines are adjusted by p-side weighting resistors (variable resistors) 13-11 in p-side adder circuit 13, and the adjusted voltages are added.

[0029] Next, the output voltage of the output signal of the n-side adder circuit 12 is inverted using an inverter circuit 14-1 to make the polarity the same as the output signal of the p-side adder circuit 13. Figure 2(c) shows the inverter circuit 14-1, and as shown in equation 3, the output voltage is inverted due to the characteristics of the inverter circuit 14-1 and amplified by the ratio of R2 to R1. In the inverter circuit 14-1 of Figure 1, the values ​​of R2 and R1 are set to the same 10 kΩ, and only inversion is performed without amplification.

[0030]

number

[0031] Next, a product-sum calculation circuit according to the first embodiment was actually fabricated as a prototype, and the results of an experiment will be described.

[0032] FIG. 3 is a photograph of an actual circuit produced as a prototype of the product-sum calculation circuit according to the first embodiment. As shown in FIG. 3, one "Ag2Se nanowire device" LSI, five "TL047" ICs (ICs capable of using four operational amplifiers), and 15 variable resistors were placed on the board, and wiring was performed in the same manner as in FIG. 1. An 11 Hz sine wave (2V p-p ) and adjusted the variable resistor so that the output signal became the desired signal.

[0033] Figure 4 shows the output waveforms generated by the actual circuit prototyped in the first embodiment. Figure 4(a) shows a cosine wave, Figure 4(b) shows a triangle wave, Figure 4(c) shows a square wave, and Figure 4(d) shows a sawtooth wave. While observing the output waveform, the variable resistor was adjusted to approach the ideal waveform.

[0034] The accuracy compared to the ideal waveform was 91.1% for the Cosine wave in Figure 4(a), 86.1% for the Triangle wave in Figure 4(b), 52.9% for the Square wave in Figure 4(c), and 50.3% for the Sawtooth wave in Figure 4(d). There is still room for improvement in the accuracy of the Square wave and Sawtooth wave, but overall it was demonstrated that they are suitable for practical use.

[0035] In this prototype and experiment, we attempted to apply the technology to Cosine waves, Triangle waves, Square waves, and Sawtooth waves, but it can also be applied to other tasks.

[0036] In the first embodiment, the number of output signals from the intermediate layer 2 to the output layer 1 is described as 15, but the number of output signals is not particularly limited. In addition, the number of input signals to the intermediate layer 2 is described as one, but there may be multiple input signals.

[0037] The output layer including the product-sum operation circuit shown in the first embodiment can be configured with an integrated circuit, and it is more preferable to configure it with an integrated circuit with low power consumption such as CMOS. When configuring it as an integrated circuit, it is sufficient to adjust the variable resistor in advance for the desired output waveform, and configure the circuit with a resistor having an adjusted fixed resistance value.

[0038] As explained in detail above, conventionally, analog output signals from the intermediate layer 2 are A / D converted to digital signals, and processing for output to the outside, such as product-sum calculation processing, is executed on a general-purpose computer using software, and the digital signals are finally output as analog signals by D / A conversion. However, according to the product-sum calculation circuit of the present embodiment 1, an output layer equipped with an appropriate product-sum calculation circuit can be created with a simple circuit configuration, and it has become possible to provide a product-sum calculation circuit that consumes significantly less power and generates less heat.

[0039] By using the product-sum calculation circuit according to the first embodiment in an information processing device, particularly in processing the output layer of a neural network, it is possible to realize a neural network with significantly reduced power consumption.

[0040] (Embodiment 2) In the second embodiment, a product-sum operation circuit in which the circuit scale is further reduced by partially modifying the configuration of the product-sum operation circuit in the first embodiment will be described.

[0041] Fig. 5 is a diagram for explaining a product-sum calculation circuit according to embodiment 2. In Fig. 5, embodiment 2 is different from embodiment 1 in the locations of inverting circuit 14-1 and summing amplifier circuit 14-2 in Fig. 1, but other locations are the same.

[0042] In the second embodiment, a subtraction amplifier circuit 14-3 is used instead of the inversion circuit 14-1 and the summing amplifier circuit 14-2 in Fig. 1. The subtraction amplifier circuit 14-3 will be described below.

[0043] In the first embodiment, in order to align the polarities of the output signal of n-side adder circuit 12 and the output signal of p-side adder circuit 13, the output signal of n-side adder circuit 12 is inverted by inversion circuit 14-1, and then the output signal of n-side adder circuit 12 and the output signal of p-side adder circuit 13 are added, amplified, and output by summing amplifier circuit 14-2. In the present embodiment, the processing performed by inversion circuit 14-1 and summing amplifier circuit 14-2 is replaced by using subtraction amplifier circuit 14-3.

[0044] The output voltage Vout is given by the subtraction amplifier circuit 14-3 in accordance with the formula 4, and the process performed by the inversion circuit 14-1 and the summing amplifier circuit 14-2 can be substituted.

[0045]

number

[0046] Compared with the product-sum calculation circuit of the first embodiment, the calculation circuit of the second embodiment does not require one operational amplifier used in the inversion circuit 14-1, and it is expected that the power consumption will be further reduced.

[0047] (Embodiment 3) In the third embodiment, a product-sum calculation circuit in which digital control is introduced will be described. In particular, the configuration different from the first and second embodiments will be mainly described.

[0048] 6 is a diagram for explaining a product-sum calculation circuit according to the present embodiment 3. A control circuit 16-1 built into a controller 16 such as a microcomputer or an FPGA controls the multiplexer 15 and the parallel D / A converter 17, and can change the resistance values ​​of n n-side variable resistors 18 and p p-side variable resistors 19 at any time.

[0049] N output signals (I0, I1, ... I14) are input from the intermediate layer 2 (Ag2Se nanowire device) to the multiplexer 15. The N output signals consist of n negative voltage signals and p positive voltage signals (N = 15, n = 9, p = 6) as in the first and second embodiments.

[0050] The multiplexer 15 receives digital control signals (S1, S2, S3, S4) and a clock signal (not shown) which is a synchronous signal from a control circuit 16-1.

[0051] The multiplexer 15 selects one of 15 signals (I0, I1, . . . I14) according to a combination of the digital control signals (S1, S2, S3, S4), and inputs the selected signal to the controller 16. For example, when the digital control signals (S1, S2, S3, S4)=(0, 0, 0, 0), I0 is selected, when (S1, S2, S3, S4)=(0, 0, 0, 1), I14 is selected, and when (S1, S2, S3, S4)=(1, 1, 1, 0), I14 is selected. In the third embodiment, the control circuit 16-1 switches the digital control signals (S1, S2, S3, S4) while synchronizing with a synchronous signal so that the 15 signals I0, I1, . . . I14 are one cycle, and the signals are selected and output in the order of I0, I1, . . . I14 in a time-division manner.

[0052] The controller 16 holds one cycle (15 lines) of the input voltage signal as a digitized voltage value, and outputs the 15 voltage values ​​as digital signals to the parallel D / A converter 17. The period of one cycle is measured in synchronization with a synchronization signal. The parallel D / A converter 17 converts each of the 15 digitized voltage values ​​into analog, and outputs n negative voltage signals in parallel to an n-side variable resistor 18 and p positive voltage signals in parallel to a p-side variable resistor 19. The subsequent operations can be processed in the same way as in the embodiment 1 or embodiment 2, and therefore a description thereof will be omitted.

[0053] The digital control signals are preferably switched cyclically in a time-division manner so that the 15 lines I0, I1, ...I14 are output in one cycle in the order I0, I1, ...I14, but the output order is not particularly limited. The speed of the clock signal, which is a synchronization signal, is not particularly limited, but must be set to an appropriate speed according to the processing speed in the intermediate layer 2.

[0054] As described above, in the third embodiment, by introducing digital control, it becomes possible to flexibly and quickly change the signals used in the product-sum calculation and the resistance values ​​for weighting. This makes it possible to take advantage of the low power consumption that is an advantage of processing by hardware circuits, while improving functionality to the same extent as when the product-sum calculation processing was performed on a PC, and enabling large amounts of weighting and online learning to be performed efficiently.

[0055] (Embodiment 4) In the fourth embodiment, a robot using the product-sum calculation circuit according to the first to third embodiments will be described.

[0056] First, as a preliminary step before mounting on a robot, as shown in FIG. 8, a reservoir device 21 and a product-sum operation circuit 22 are mounted on an insulating substrate 20. In this case, the substrate 20 is made of glass epoxy resin, ceramic, etc. (a representative configuration is shown in FIG. 3). An input signal is input to the reservoir device 21 from an input terminal, a signal output from the reservoir device 21 is processed by the product-sum operation circuit 22, and an output signal is output from an output terminal. The module is configured in this manner and mounted in a robot, which will be described later. Also, as shown in FIG. 9, a plurality of modules shown in FIG. 8 may be mounted on one substrate 20 (four modules in FIG. 9), and in this case, the input signals may be different signals or the same signals. Basically, input signals 1 to 4 are processed and output as output signals 1 to 4, respectively.

[0057] FIG. 10 shows a block diagram of the robot of the present invention, and the robot body 23 is equipped with the following: an external data communication unit 25 that connects to an external network 24 or the like to send and receive data, and a main control unit 26 that controls each unit. The robot body 23 is also equipped with a plurality of driving members such as motors and solenoids that move the robot body 23, grasp objects, and rotate each unit. Electricity is supplied to these driving members according to commands from the main control unit 26. A driving unit 27 controls the rotation speed, etc. of these driving members.

[0058] The robot body 23 is also equipped with various sensors 28, such as an imaging sensor capable of acquiring moving images and still images, a temperature sensor, an illuminance sensor for measuring brightness, etc., a sensor capable of measuring the distance traveled by the robot body 23, a sensor for measuring the rotation angle of an arm mounted on the robot body 23, and a sensor for measuring the distance to an object, etc. In this fourth embodiment, the modules shown in Fig. 8 and Fig. 9 are mounted inside or on the surface of the robot body as a reservoir unit 29. In this fourth embodiment, output signals of the various sensors 28 serve as input signals to the reservoir unit 29 (the input signals in Fig. 8).

[0059] The signal processed by the reservoir unit 29 is input to the recognition unit 30 provided in the robot body 23, which recognizes the shape of the object, the sound, etc., and inputs the recognition result to the main control unit 26. The robot body 23 is also provided with an input / display unit 31 composed of a video device such as a liquid crystal display, and the robot's status and the contents recognized by the recognition unit are displayed by the main control unit 26. By providing an input device such as a touch panel in addition to the input / display unit 31, desired data and information can be input to the robot body 23. The robot body 23 is also provided with a power supply unit 32, which supplies power to each unit of the robot body 23. The power supply unit 32 may be a storage battery such as a lithium ion battery, or a power source supplied from an external source.

[0060] As an example of the operation, when a voice is input from a sound sensor in the various sensors 28, a signal corresponding to the voice is input in the reservoir unit 29, and the processed result is sent to the recognition unit 30. The recognition unit 30 analyzes the meaning of the voice, and if the voice is, for example, "move forward," it outputs a signal to that effect to the main control unit 26. In response to the signal from the recognition unit 30, the main control unit 26 issues a command to the drive unit 27 to rotate the motor that controls the movement of the robot body 23. As the motor rotates, the robot body 23 moves forward.

[0061] As the performance of robots improves, the robot itself is required to move more precisely and to observe the surrounding environment with greater precision, which places a greater burden on the main control unit 26. In this fourth embodiment, in order to improve the convenience of the robot, the robot itself is being equipped with a reservoir device. However, as described above, having the main control unit 26 also process the reservoir device places a great burden on the main control unit 26, which results in high power consumption and heat generation problems. In this fourth embodiment, a product-sum operation circuit is intentionally created to prevent or reduce the processing of the reservoir device in the main control unit 26, thereby reducing power consumption and enabling the robot to operate for a long period of time.

[0062] Using the above embodiments, the product-sum arithmetic circuit according to the present invention, the information processing device equipped with this product-sum arithmetic circuit, and the robot equipped with this product-sum arithmetic circuit have been described in detail, but the present invention is not limited to these embodiments, and various improvements and modifications are possible within the scope of the present invention. [Explanation of symbols]

[0063] 1 Output layer 2. Middle tier 3 Input current (AC voltage) 4. Power supply voltage 11 Voltage Follower 12 n-side adder circuit 12-11 N-side weighted resistor 12-21 N-side op amp 12-22 n-side gain adjustment resistor 13 p-side adding circuit 13-11 P-side weighted resistor 13-21 P-side op amp 13-22 p-side gain adjustment resistor 14 Inverting amplifier circuit 14-1 Inverting circuit 14-2 Adding amplifier circuit 14-3 Subtraction amplifier circuit 15 Multiplexer 16 Controller 16-1 Control circuit 17 Parallel D / A Converter 18 ···N-side weighted variable resistor 19 p-side weighted variable resistor 20... Substrate 21 Reservoir Device 22 Multiply-and-accumulate circuit section 23 Robot body 24 Networks, etc. 25 External data communication section 26 Main control unit 27 Drive unit 28 Various sensors 29 Reservoir section 30 Identification unit 31 Input and display section 32...Power supply section

Claims

1. A product-sum operation circuit that performs a product-sum operation on N input signals consisting of n negative voltage signals and p positive voltage signals, and outputs the product-sum operation result as an output signal, N voltage followers each receiving the N input signals and outputting an output signal electrically isolated from the input side; an n-side adder circuit that performs weighted addition processing on output signals corresponding to n negative voltage signals among the output signals output from the N voltage followers, and outputs the result as a first signal; a p-side adder circuit that performs weighted addition processing on output signals corresponding to p positive voltage signals among the output signals output from the N voltage followers, and outputs the result as a second signal; a product-sum operation circuit (N is an integer of 2 or more, and n and p are integers satisfying N=n+p) including an inverting amplifier circuit that adds the first signal and the second signal with the same polarity, and outputs an output signal amplified by a predetermined amplification factor.

2. A product-sum operation circuit that performs a product-sum operation on N input signals consisting of n negative voltage signals and p positive voltage signals, and outputs the product-sum operation result as an output signal, a multiplexer that sequentially and periodically switches and outputs one signal selected from the N input signals in response to a first control signal; a control circuit that holds the voltage values ​​of the N signals output from the multiplexer in a sequential and cyclic manner for one cycle and outputs the N signals as digital signals; a parallel D / A converter which receives the N digital signals output from the control circuit and outputs N analog signals that have been D / A converted; an n-side addition circuit that performs weighted addition processing on output signals corresponding to n negative voltage signals among the N output signals output by the D / A converter, and outputs the result as a first signal; a p-side adder circuit which performs weighted addition processing on output signals corresponding to p positive voltage signals among N output signals outputted from the D / A converter, and outputs the weighted addition processing as a second signal; an inverting amplifier circuit that adds the first signal and the second signal with the same polarity, and outputs an output signal amplified by a predetermined amplification factor; The control circuit outputs the first control signal for controlling the multiplexer, A product-sum calculation circuit (N is an integer of 2 or more, and n and p are integers that satisfy N=n+p) that makes it possible to control weighting for weighted addition of the n-side adder circuit and the p-side adder circuit.

3. The inverting amplifier circuit includes: an inversion circuit that outputs a third signal obtained by inverting a voltage of the first signal; 3. The product-sum calculation circuit according to claim 1, further comprising: a summing amplifier circuit which receives the first signal and the third signal, adds the first signal and the second signal, and outputs an output signal amplified by a predetermined amplification factor.

4. The inverting amplifier circuit includes:

3. The product-sum calculation circuit according to claim 1, further comprising a subtraction amplifier circuit which receives the first signal and the second signal, subtracts the second signal from the first signal, and outputs an output signal amplified by a predetermined amplification factor.

5. The voltage follower comprises an operational amplifier; A non-inverting input terminal of the operational amplifier receives one of the N input signals, an output terminal and an inverting input terminal of the operational amplifier are short-circuited, and an output signal of the output terminal of the operational amplifier is an output signal of the voltage follower; the n-side adder circuit includes n n-side weighting resistors each having a specific resistance value corresponding to each signal, one n-side operational amplifier, and one n-side amplification factor adjustment resistor; The n-side weighting resistor has one end connected to the output terminal of the operational amplifier and the other end connected to the inverting input terminal of the n-side operational amplifier, The n-side operational amplifier has an inverting input terminal connected to the other ends of all of the n n-side weighting resistors and one end of the n-side amplification factor adjustment resistor, an output terminal connected to the other end of the n-side amplification factor adjustment resistor, and a non-inverting input terminal connected to ground, the p-side adder circuit includes p p-side weighting resistors each having a specific resistance value corresponding to each signal, one p-side operational amplifier, and one p-side amplification factor adjustment resistor; one end of the p-side weighting resistor is connected to the output terminal of the operational amplifier, and the other end is connected to the inverting input terminal of the p-side operational amplifier; 3. The product-sum calculation circuit according to claim 1, wherein the p-side operational amplifier has an inverting input terminal connected to the other ends of all of the p p-side weighting resistors and one end of the p-side gain adjustment resistor, an output terminal connected to the other ends of the p-side gain adjustment resistors, and a non-inverting input terminal connected to ground.

6. The inverting circuit is An inverting op-amp whose non-inverting input terminal is connected to ground; a first resistor provided between a first signal output from the n-side adder circuit and an inverting input terminal of an operational amplifier for the inversion circuit; a second resistor provided between an inverting input terminal of the operational amplifier for the inverting circuit and an output terminal of the operational amplifier for the inverting circuit, the first resistor and the second resistor having the same resistance value; The summing amplifier circuit includes: An op-amp for summing amplification output, with the non-inverting input terminal connected to ground; a third resistor provided between the second signal output from the p-side adder circuit and the inverting input terminal of the operational amplifier for the summing amplifier output; a fourth resistor provided between the output terminal of the operational amplifier for the inverting circuit and the inverting input terminal of the operational amplifier for the summing amplifier output; a fifth resistor provided between the inverting input terminal and the output terminal of the operational amplifier for the summing amplification output; 4. The product-sum operation circuit according to claim 3, wherein an output signal from an output terminal of said operational amplifier for summing amplification output is an output signal of said inverting amplifier circuit.

7. The subtraction amplifier circuit includes: An operational amplifier for the subtraction amplification output; a fifth resistor provided between the second signal output from the p-side adder circuit and the inverting input terminal of the operational amplifier for the subtraction amplification output; a sixth resistor provided between a first signal output from the n-side adder circuit and a non-inverting input terminal of the operational amplifier for the subtraction amplification output; a seventh resistor provided between the non-inverting input terminal of the operational amplifier for the subtraction amplification output and ground; an eighth resistor provided between the inverting input terminal and the output terminal of the operational amplifier for the subtraction amplification output; the fifth resistor and the sixth resistor have the same resistance value, the seventh resistor and the eighth resistor have the same resistance value, 5. The multiply-accumulate circuit according to claim 4, wherein an output signal from an output terminal of said operational amplifier for subtraction amplification output is an output signal from said inverting amplifier circuit.

8. 3. An integrated circuit comprising the product-sum calculation circuit according to claim 1.

9. 3. An information processing device comprising the product-sum calculation circuit according to claim 1.

10. The device includes a main body, various sensors provided in the main body, a reservoir unit to which output signals from the various sensors are input, an identification unit that identifies information based on the output signal from the reservoir unit, a drive unit that drives each part of the main body, and a main control unit that controls each part, 3. A robot comprising: a reservoir device for receiving signals from the various sensors; and a product-sum calculation circuit according to claim 1, for processing signals output from the reservoir device.

11. The robot of claim 10 , wherein the reservoir portion comprises a substrate and a reservoir device mounted on the substrate and having a conductor and a nonlinear portion.

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