Semiconductor device

Abstract

To provide a semiconductor device that can be downsized.SOLUTION: A semiconductor device A1 has a first power supply terminal 2A, a second power supply terminal 2B, a first semiconductor element 1A, a capacitor element 3, and a resistor substrate 4 including a resistor layer 40. The first semiconductor element 1A is supported by the resistor substrate 4. The capacitor element 3 and the resistor layer 40 are electrically connected in series between the first power supply terminal 2A and the second power supply terminal 2B.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an example of a conventional power module. The power module disclosed in the document includes a bridge circuit configured with a plurality of SiC-MOSFETs and a snubber circuit. The snubber circuit includes a snubber capacitor and a snubber resistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO2016 / 067835 publication

[0004] [overview]

[0005] If space is provided for the snubber capacitor and the snubber resistor, the power module will become larger.

[0006] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device that can be miniaturized.

[0007] A semiconductor device provided by one embodiment of the present disclosure comprises a first power supply terminal, a second power supply terminal, a capacitor element, a resistance substrate including a resistive layer, and a first semiconductor element located on the resistance substrate, wherein the capacitor element and the resistive layer are electrically connected in series between the first power supply terminal and the second power supply terminal.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a partial cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a partially enlarged cross-sectional view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a partial cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a partially enlarged cross-sectional view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a circuit diagram showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a partial perspective view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 11] FIG. 11 is a partial cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 14] FIG. 14 is a partial perspective view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 15] FIG. 15 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 16] FIG. 16 is a partial cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a partial enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 18]FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a partial enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 20] FIG. 20 is a partial perspective view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 21] FIG. 21 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Figure 23] FIG. 23 is a partially enlarged cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. [Diagram 25] FIG. 25 is a partially enlarged cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure.

[0010] [Detailed Description] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used merely for identification purposes and are not intended to impose any ordering on their objects.

[0012] In this disclosure, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B in contact with a certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B". Unless otherwise specified, "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entirety of an object B" and "an object A overlaps a part of an object B." In this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] [First embodiment] 1 to 8 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes one or more first semiconductor elements 1A, a first power supply terminal 2A, a second power supply terminal 2B, one or more capacitor elements 3, and a resistor substrate 4. The semiconductor device A1 may include one or more second semiconductor elements 1B, control terminals 2D to 2G, a connecting portion 21B, an output terminal 2C, an insulating substrate 5A, an insulating substrate 5B, a support substrate 6, a sub-substrate 7A, a sub-substrate 7B, conductive members 81 to 85, and a plurality of wires 88.

[0014] FIG. 1 is a partial perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a partial plan view showing the semiconductor device A1. FIG. 4 is a partial cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 6 is a partial cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 8 is a circuit diagram showing the semiconductor device A1.

[0015] In these figures, the thickness direction of the present disclosure is defined as the z direction. The first side in the z direction is referred to as the z1 side, and the second side opposite the first side in the z direction is referred to as the z2 side. A direction perpendicular to the thickness direction z is defined as the x direction. The first side in the x direction is referred to as the x1 side, and the second side opposite the x1 side is referred to as the x2 side. A direction perpendicular to the z direction and the x direction is defined as the y direction. The first side in the y direction is referred to as the y1 side, and the second side opposite the y1 side is referred to as the y2 side.

[0016] Sealing resin 9 is omitted in Figure 1 and Figures 4 to 7. Sealing resin 9 is indicated by an imaginary two-dot chain line in Figures 2 and 3. Second power supply terminal 2B, connecting portion 21B, one or more capacitor elements 3, etc. are omitted in Figure 3.

[0017] The use and specific configuration of the semiconductor device according to the present disclosure are not limited in any way. The semiconductor device A1, for example, functions to convert a DC power supply voltage applied to a first power supply terminal 2A and a second power supply terminal 2B into AC power by one or more first semiconductor elements 1A and one or more second semiconductor elements 1B. The converted AC power is input to a power supply target such as a motor from an output terminal 2C. Such a semiconductor device A1 constitutes a part of a power conversion circuit such as an inverter.

[0018] The resistance substrate 4 supports one or more first semiconductor elements 1A. The resistance substrate 4 includes a resistance layer 40. The resistance layer 40 has a main surface 401 and a back surface 402. The main surface 401 faces the z1 side in the z direction. The back surface 402 faces the z2 side in the z direction. The size, shape, etc. of the resistance substrate 4 are not limited in any way. In this embodiment, the resistance substrate 4 is rectangular when viewed in the z direction.

[0019] The resistive layer 40 may include a resistive material. The resistive material may have anisotropic or isotropic electrical resistivity. An example of a resistive material having isotropic electrical resistivity is nichrome, which is an alloy containing nickel and chromium. An example of a resistive material having anisotropic electrical resistivity is graphite, a metal laminate substrate, or the like.

[0020] In this embodiment, the resistance layer 40 includes graphite. The graphite has a structure in which a plurality of graphenes are stacked. The electrical resistivity in the direction in which the plurality of graphenes are stacked is higher than the electrical resistivity in the direction perpendicular to the stacking direction. In this embodiment, the stacking direction of the resistance layer 40 is defined as a high resistance direction N1. As shown in FIG. 6 and FIG. 7, in this embodiment, the high resistance direction N1 is along the y direction.

[0021] The resistance layer 40 containing graphite has a lower thermal conductivity in the high resistance direction N1 than in a direction perpendicular to the high resistance direction N1.

[0022] The resistive substrate 4 may include a first conductive layer 45 and a second conductive layer 46. The first conductive layer 45 is located on the main surface 401 of the resistive layer 40. The first conductive layer 45 includes a conductive material. The conductive material includes, for example, a metal such as Cu (copper), Ni (nickel), Fe (iron), or an alloy thereof.

[0023] As shown in FIGS. 2, 3, 6, and 7, in this embodiment, the first conductive layer 45 has a first portion 451 and a second portion 452. The first conductive layer 45 may have a fifth portion 453. The first portion 451 and the second portion 452 are spaced apart from each other with the first opening 455 interposed therebetween. In this embodiment, the first portion 451 and the second portion 452 are spaced apart in the y direction. That is, the first portion 451 and the second portion 452 are spaced apart in the high resistance direction N1. The second portion 452 is located on the y1 side of the first portion 451 in the y direction.

[0024] The first portion 451 and the fifth portion 453 are spaced apart from each other with the first opening 456 in between. In this embodiment, the first portion 451 and the fifth portion 453 are spaced apart in the y direction. That is, the first portion 451 and the fifth portion 453 are spaced apart in the high resistance direction N1. The fifth portion 453 is located on the y2 side of the first portion 451 in the y direction.

[0025] The second conductive layer 46 is located on the rear surface 402 of the resistive layer 40. The second conductive layer 46 includes a conductive material. The conductive material includes, for example, a metal such as Cu (copper), Ni (nickel), Fe (iron), or an alloy thereof.

[0026] As shown in FIGS. 2, 3, 6, and 7, in this embodiment, the second conductive layer 46 has a third portion 461 and a fourth portion 462. The second conductive layer 46 may have a sixth portion 463. The third portion 461 and the fourth portion 462 are spaced apart from each other with the second opening 465 in between. In this embodiment, the third portion 461 and the fourth portion 462 are spaced apart in the y direction. That is, the third portion 461 and the fourth portion 462 are spaced apart in the high resistance direction N1. The fourth portion 462 is located on the y1 side of the third portion 461 in the y direction.

[0027] The third portion 461 and the sixth portion 463 are spaced apart from each other with the second opening 466 in between. In this embodiment, the third portion 461 and the sixth portion 463 are spaced apart in the y direction. That is, the third portion 461 and the sixth portion 463 are spaced apart in the high resistance direction N1. The sixth portion 463 is located on the y2 side of the third portion 461 in the y direction.

[0028] In this embodiment, as shown in Figures 6 and 7, the first opening 455 and the second opening 465 at least partially overlap each other when viewed in the z direction. The first opening 455 and the second opening 465 may be configured such that one completely overlaps the other when viewed in the z direction. In the illustrated example, the first opening 455 and the second opening 465 completely overlap each other when viewed in the z direction.

[0029] A portion of the resistance layer 40 that overlaps with both the first opening 455 and the second opening 465 when viewed in the z direction configures a resistance portion R1.

[0030] In this embodiment, as shown in Figures 6 and 7, the first opening 456 and the second opening 466 at least partially overlap each other when viewed in the z direction. The first opening 456 and the second opening 466 may be configured such that one completely overlaps the other when viewed in the z direction. In the illustrated example, the first opening 456 and the second opening 466 completely overlap each other when viewed in the z direction.

[0031] A portion of the resistance layer 40 that overlaps with both the first opening 456 and the second opening 466 when viewed in the z direction constitutes a resistance portion R2.

[0032] The insulating substrate 5 of this embodiment may support the resistive substrate 4 and the support substrate 6. The insulating substrate 5 may include an insulating layer 50 and a metal layer 52. The metal layer 52 is located on the z2 side of the insulating layer 50 in the z direction. The second conductive layer 46 of the resistive substrate 4 and the back conductive layer 62 of the support substrate 6 may be bonded to the insulating layer 50.

[0033] The resistor layer 40 is not limited to a configuration including resistor portions R1 and R2, and may include one or more resistor portions. In this embodiment, the resistor portions R1 and R2 function as snubber resistors of the snubber circuit Cs of the semiconductor device A1 shown in Fig. 8. The resistor portions R1 and R2 are electrically connected in series with the capacitor element 3 between the first power supply terminal 2A and the second power supply terminal 2B.

[0034] The support substrate 6 supports one or more second semiconductor elements 1B. The specific configuration of the support substrate 6 is not limited in any way. The support substrate 6 may have mechanical strength, electrical characteristics, and the like required to support one or more second semiconductor elements 1B. In this embodiment, the support substrate 6 includes a resistive layer 60. The resistive layer 60 has a main surface 601 and a back surface 602. The main surface 601 is a surface facing the z1 side in the z direction. The back surface 602 is a surface facing the z2 side in the z direction. The size, shape, and the like of the support substrate 6 are not limited in any way. In this embodiment, the support substrate 6 is rectangular when viewed in the z direction. The support substrate 6 may be disposed on the x1 side in the x direction with respect to the resistive substrate 4.

[0035] The resistive layer 60 may include a resistive material. The resistive material may have anisotropic or isotropic electrical resistivity. An example of a resistive material having isotropic electrical resistivity is nichrome, which is an alloy containing nickel and chromium. An example of a resistive material having anisotropic electrical resistivity is graphite, a metal laminate substrate, or the like.

[0036] In this embodiment, the resistance layer 60 includes graphite. The graphite has a structure in which a plurality of graphenes are stacked. The electrical resistivity in the direction in which the plurality of graphenes are stacked is higher than the electrical resistivity in the direction perpendicular to the stacking direction. In this embodiment, the stacking direction of the resistance layer 60 is, for example, along the x direction or the y direction.

[0037] The resistance layer 60 containing graphite has a lower thermal conductivity in the high resistance direction than in a direction perpendicular to the high resistance direction.

[0038] The support substrate 6 may include a main surface conductive layer 61 and a back surface conductive layer 62. The main surface conductive layer 61 is located on a main surface 601 of the resistance layer 60. The main surface conductive layer 61 includes a conductive material. The conductive material includes metals such as Cu (copper), Ni (nickel), Fe (iron), or alloys thereof. The main surface conductive layer 61 may cover the entire main surface 601.

[0039] The back conductive layer 62 is located on the back surface 602 of the resistive layer 60. The back conductive layer 62 includes a conductive material. The conductive material includes, for example, a metal such as Cu (copper), Ni (nickel), Fe (iron), or an alloy thereof. The back conductive layer 62 may cover the entire back surface 602.

[0040] 1 to 7, insulating substrate 5A is located on the z2 side in the z direction with respect to resistance substrate 4. Insulating substrate 5A may include insulating layer 50, metal layer 51 and metal layer 52.

[0041] The insulating layer 50 includes an insulating material. The insulating material may be, for example, ceramics. The metal layer 51 is located on the z1 side of the insulating layer 50 in the z direction. The metal layer 51 may include a metal such as Cu (copper). The metal layer 52 is located on the z2 side of the insulating layer 50 in the z direction. The metal layer 52 may include a metal such as Cu (copper). In this embodiment, the metal layer 51 may have fourth openings 511 and 512. The fourth opening 511 overlaps with the second opening 465 when viewed in the z direction. The fourth opening 512 overlaps with the second opening 466 when viewed in the z direction.

[0042] The metal layer 51 of the insulating substrate 5A is joined to the second conductive layer 46 by a joining layer 59. The joining layer 59 is a conductive joining layer, an insulating joining layer, or the like. Examples of the conductive joining layer include solder, silver paste, and a sintered metal layer. In this embodiment, the joining layer 59 may have fifth openings 591 and 592. The fifth opening 591 overlaps with the second opening 465 and the fourth opening 511 when viewed in the z direction. The fifth opening 592 overlaps with the second opening 466 and the fourth opening 512 when viewed in the z direction.

[0043] 1 to 5, insulating substrate 5B is located on the z2 side in the z direction with respect to supporting substrate 6. Insulating substrate 5B may include insulating layer 50, metal layer 51 and metal layer 52.

[0044] The insulating layer 50 includes an insulating material. The insulating material may be, for example, ceramics. The metal layer 51 is located on the z1 side of the insulating layer 50 in the z direction. The metal layer 51 may include, for example, a metal such as Cu (copper). The metal layer 52 is located on the z2 side of the insulating layer 50 in the z direction. The metal layer 52 may include, for example, a metal such as Cu (copper).

[0045] The metal layer 51 of the insulating substrate 5B is joined to the back surface conductive layer 62 by a joining layer 59.

[0046] The number of the one or more first semiconductor elements 1A is not limited in any way and may be one or more. The one or more first semiconductor elements 1A may configure an upper arm circuit in the semiconductor device A1 as shown in FIG. 8. In this embodiment, the semiconductor device A1 includes a plurality of first semiconductor elements 1A. The plurality of first semiconductor elements 1A may be the same element or may be different elements. The plurality of first semiconductor elements 1A are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In addition, the plurality of first semiconductor elements 1A may be field effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) and bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors).

[0047] In the description of the semiconductor device A1, the multiple first semiconductor elements 1A are n-channel type MOSFETs having a vertical structure. The multiple first semiconductor elements 1A include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC). The multiple first semiconductor elements 1A are arranged along the y direction.

[0048] As shown in FIGS. 3 and 5, the first semiconductor element 1A has a first electrode 11A, a second electrode 12A, and a third electrode 13A.

[0049] The first electrode 11A is located on the z2 side of the first semiconductor element 1A in the z direction. The first electrode 11A corresponds to a drain electrode of the first semiconductor element 1A. As shown in Fig. 5, the first electrode 11A may be conductively joined to the first portion 451 by a conductive bonding layer 19. The conductive bonding layer 19 is, for example, solder, silver paste, or the like.

[0050] The second electrode 12A is located on the z1 side of the first semiconductor element 1A in the z direction. The second electrode 12A corresponds to a source electrode of the first semiconductor element 1A. As shown in FIGS. 3 to 5, the second electrode 12A may be electrically connected to the main surface conductive layer 61 via a conductive member 81. The conductive member 81 may contain a metal such as Cu (copper), Ni (nickel), Fe (iron), or an alloy thereof. The conductive member 81 may be electrically connected to the second electrode 12A and the main surface conductive layer 61 by a conductive bonding layer 89. The conductive bonding layer 89 is, for example, solder, silver paste, or the like.

[0051] The third electrode 13A is located on the z1 side of the first semiconductor element 1A in the z direction. The third electrode 13A is located on the x2 side of the second electrode 12A in the x direction as viewed in the z direction. A gate voltage for driving the first semiconductor element 1A can be applied to the third electrode 13A. The third electrode 13A corresponds to the gate electrode of the first semiconductor element 1A. As viewed in the z direction, the area of ​​the third electrode 13A is smaller than the area of ​​the second electrode 12A.

[0052] The number of the one or more second semiconductor elements 1B is not limited in any way and may be one or more. The one or more second semiconductor elements 1B may configure a lower arm circuit in the semiconductor device A1 as shown in FIG. 8. In this embodiment, the semiconductor device A1 includes a plurality of second semiconductor elements 1B. The plurality of second semiconductor elements 1B may be the same element or may be different elements. The plurality of second semiconductor elements 1B are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In addition, the plurality of second semiconductor elements 1B may be field effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) and bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors).

[0053] In the description of the semiconductor device A1, the multiple second semiconductor elements 1B are n-channel type MOSFETs having a vertical structure. The multiple second semiconductor elements 1B include a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide (SiC). The multiple second semiconductor elements 1B are arranged along the y direction.

[0054] As shown in FIGS. 3 and 5, the second semiconductor element 1B has a fourth electrode 11B, a fifth electrode 12B and a sixth electrode 13B.

[0055] The fourth electrode 11B is located on the z2 side of the second semiconductor element 1B in the z direction. The fourth electrode 11B corresponds to a drain electrode of the second semiconductor element 1B. As shown in FIG 5, the fourth electrode 11B may be conductively joined to the main surface 601 by a conductive bonding layer 19.

[0056] The fifth electrode 12B is located on the z1 side in the z direction of the second semiconductor element 1B. The fifth electrode 12B corresponds to the source electrode of the second semiconductor element 1B.

[0057] The sixth electrode 13B is located on the z1 side of the second semiconductor element 1B in the z direction. The sixth electrode 13B is located on the x1 side of the fifth electrode 12B in the x direction as viewed in the z direction. A gate voltage for driving the second semiconductor element 1B can be applied to the sixth electrode 13B. The sixth electrode 13B corresponds to the gate electrode of the second semiconductor element 1B. As viewed in the z direction, the area of ​​the sixth electrode 13B is smaller than the area of ​​the fifth electrode 12B.

[0058] The sub-substrate 7A and the sub-substrate 7B can be used to control one or more first semiconductor elements 1A and one or more second semiconductor elements 1B. As shown in Figures 1 to 4, the sub-substrate 7A is located on the first portion 451. The sub-substrate 7A may include, for example, an insulating layer 70A, a conductive layer 71A, and a conductive layer 72A.

[0059] The insulating layer 70A includes an insulating material such as ceramics. The conductive layer 71A is located on the z1 side of the insulating layer 70A in the z direction and includes a metal such as Cu (copper). In the illustrated example, the conductive layer 71A includes two regions spaced apart from each other. The conductive layer 72A is located on the z2 side of the insulating layer 70A in the z direction and includes a metal such as Cu (copper).

[0060] One region of the conductive layer 71A is electrically connected to a third electrode 13A of one or more first semiconductor elements 1A via one or more wires 88. The wires 88 include a metal such as Al (aluminum). Another region of the conductive layer 71A is electrically connected to a second electrode 12A of one or more first semiconductor elements 1A via one or more wires 88.

[0061] 1 to 4, sub-substrate 7B is located on main surface conductive layer 61 of support substrate 6. Sub-substrate 7B may include, for example, insulating layer 70B, conductive layer 71B and conductive layer 72B.

[0062] The insulating layer 70B includes an insulating material such as ceramics. The conductive layer 71B is located on the z1 side of the insulating layer 70B in the z direction and includes a metal such as Cu (copper). In the illustrated example, the conductive layer 71B includes two regions spaced apart from each other. The conductive layer 72B is located on the z2 side of the insulating layer 70B in the z direction and includes a metal such as Cu (copper).

[0063] One region of the conductive layer 71B is electrically connected to a sixth electrode 13B of one or more second semiconductor elements 1B via one or more wires 88. The wires 88 include a metal such as Al (aluminum). Another region of the conductive layer 71B is electrically connected to a fifth electrode 12B of one or more second semiconductor elements 1B via one or more wires 88.

[0064] The first power supply terminal 2A and the second power supply terminal 2B can be electrically connected to a power supply (not shown) that supplies DC power to the semiconductor device A1. The first power supply terminal 2A can be connected to the positive electrode of the power supply. The second power supply terminal 2B can be connected to the negative electrode of the power supply.

[0065] The first power supply terminal 2A may include a metal such as Cu (copper), Ni (nickel), or Fe (iron). The first power supply terminal 2A is conductively joined to the first portion 451. In the illustrated example, the first power supply terminal 2A is conductively joined to the first portion 451 via a conductive member 83. The conductive member 83 may include, for example, a metal. The first power supply terminal 2A may protrude from the resistance substrate 4 and the sealing resin 9 to the x2 side in the x direction.

[0066] The second power supply terminal 2B may include a metal such as Cu (copper), Ni (nickel), or Fe (iron). The second power supply terminal 2B is conductively joined to the fifth electrode 12B of one or more second semiconductor elements 1B. In the illustrated example, the second power supply terminal 2B is conductively joined to the fifth electrode 12B via the connecting portion 21B and a conductive member 82. The conductive member 82 may include, for example, a metal. The conductive member 82 may be conductively joined to the connecting portion 21B and the fifth electrode 12B by, for example, a conductive bonding layer 89. The conductive bonding layer 89 may be, for example, solder, silver paste, or the like. The second power supply terminal 2B may protrude from the resistance substrate 4 and the sealing resin 9 to the x2 side in the x direction.

[0067] The connecting portion 21B may be made of the same metal material as the second power supply terminal 2B. The specific size and shape of the connecting portion 21B are not limited in any way. As shown in FIGS. 2, 4, and 5, in this embodiment, the connecting portion 21B is located so as to straddle the gap between the resistance substrate 4 and the support substrate 6 in the x direction. Moreover, the connecting portion 21B overlaps with the first semiconductor element 1A, the second semiconductor element 1B, and the conductive member 81 when viewed in the z direction.

[0068] The output terminal 2C is electrically connected to a power supply target such as a motor. The output terminal 2C is conductively joined to the main surface conductive layer 61. In the illustrated example, the output terminal 2C is conductively joined to the main surface conductive layer 61 via a conductive member 84. The conductive member 84 may include, for example, a metal. The output terminal 2C may protrude from the support substrate 6 and the sealing resin 9 to the x1 side in the x direction.

[0069] The one or more capacitor elements 3 function as snubber capacitors of the snubber circuit Cs of the semiconductor device A1 shown in Fig. 8. As shown in Figs. 1, 2, 6 and 8, the one or more capacitor elements 3 are electrically connected in series with the resistive layer 40 between the first power supply terminal 2A and the second power supply terminal 2B. The number of the one or more capacitor elements 3 in the present disclosure is not limited in any way and may be one or more. In this embodiment, the semiconductor device A1 includes two capacitor elements 3.

[0070] There is no limitation on the specific configuration of capacitor element 3. Capacitor element 3 may be, for example, an electrolytic capacitor, a film capacitor, a ceramic capacitor, or the like.

[0071] 1, 2 and 6, one capacitor element 3 is conductively joined to the second power supply terminal 2B and the second portion 452. In this embodiment, the capacitor element 3 is conductively joined to the second power supply terminal 2B via the connecting portion 21B. The capacitor element 3 is conductively joined to the second portion 452 via the conductive member 85. The capacitor element 3 is conductively joined to the connecting portion 21B and the conductive member 85 by a conductive bonding layer 39. The conductive bonding layer 39 may be, for example, solder, silver paste, or the like.

[0072] 1, 2, and 6, the other capacitor element 3 is conductively joined to the second power supply terminal 2B and the fifth portion 453. In this embodiment, the capacitor element 3 is conductively joined to the second power supply terminal 2B via the connecting portion 21B. The capacitor element 3 is conductively joined to the fifth portion 453 via the conductive member 85. The capacitor element 3 is conductively joined to the connecting portion 21B and the conductive member 85 by the conductive bonding layer 39.

[0073] The sealing resin 9 covers one or more first semiconductor elements 1A, one or more second semiconductor elements 1B, and at least a part of the resistance substrate 4. The sealing resin 9 may cover one or more capacitor elements 3. In this embodiment, one or more capacitor elements 3 are covered by the sealing resin 9. The sealing resin 9 may be, for example, a black epoxy resin. The metal layer 52 of the insulating substrate 5A and the metal layer 52 of the insulating substrate 5B may be exposed from the sealing resin 9 to the z2 side in the z direction. In this case, a heat sink (not shown) may be joined to the metal layer 52 of the insulating substrate 5A and the metal layer 52 of the insulating substrate 5B.

[0074] Next, the operation of the semiconductor device A1 will be described.

[0075] 8, the resistive layer 40 functions as a snubber resistor of the snubber circuit Cs of the semiconductor device A1. The resistive layer 40 is a component of the resistive substrate 4 that supports one or more first semiconductor elements 1A. Therefore, in the semiconductor device A1, there is no need to secure space for arranging a dedicated resistive element or the like that functions as a snubber resistor of the snubber circuit Cs. This makes it possible to miniaturize the semiconductor device A1.

[0076] Since the electrical resistivity of the resistance layer 40 is anisotropic, the resistance portion R can be configured so that a current flows in a high resistance direction N1 where the electrical resistivity is high, as shown in Figures 7 and 8. This has the advantage that the resistance value of the resistance portion R can be easily set to a desired value.

[0077] Since the resistance layer 40 contains graphite, the thermal conductivity in the z direction, which is a direction intersecting the high resistance direction N1, is higher than the thermal conductivity in the high resistance direction N1. Heat from one or more first semiconductor elements 1A can be dissipated more efficiently to the z2 side in the z direction via the resistance layer 40.

[0078] The first conductive layer 45 has a first portion 451 and a second portion 452 sandwiching the first opening 455, so that the resistance portion R in the resistance layer 40 can be set to a more desired size, shape, position, etc. The second conductive layer 46 has a third portion 461 and a fourth portion 462 sandwiching the second opening 465, so that the resistance portion R in the resistance layer 40 can be set more accurately to a more desired size, shape, position, etc.

[0079] By providing insulating substrate 5A and insulating substrate 5B, it is possible to prevent a current that may flow from side z1 to side z2 in the z direction through resistance substrate 4 and support substrate 6 from further flowing to the z2 side by insulating substrate 5A and insulating substrate 5B. A heat sink made of, for example, a metal can be connected to insulating substrate 5A and insulating substrate 5B.

[0080] 9 to 25 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment. In addition, the configurations of the parts in each modification and each embodiment can be appropriately combined with each other as long as no technical contradiction occurs.

[0081] [Second embodiment] 9 to 13 show a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device A2 of this embodiment may include an insulating substrate 5, a supporting substrate 6A, and a supporting substrate 6B.

[0082] 9 and 10, the support substrate 6A may have a portion located on the x2 side in the x direction with respect to the resistance substrate 4, and a portion located on the y1 side in the y direction. The specific configuration of the support substrate 6A is not limited in any way, and may have a resistance layer 60, a main surface conductive layer 61, and a back surface conductive layer 62 similar to those of the support substrate 6 in the semiconductor device A1. The main surface conductive layer 61 of the support substrate 6A is conductively joined to the fourth electrodes 11B and the output terminals 2C of one or more second semiconductor elements 1B, and is conductively connected to the second electrodes 12A of one or more first semiconductor elements 1A via one or more wires 88. A sub-substrate 7B may be located on the main surface conductive layer 61.

[0083] The support substrate 6B may have a portion located on the x2 side in the x direction with respect to the resistance substrate 4. The support substrate 6B may have a portion located on the y2 side in the y direction with respect to the support substrate 6A. The specific configuration of the support substrate 6B is not limited in any way, and may be a single layer containing a metal such as Cu (copper) or an alloy. The second power supply terminal 2B and the capacitor element 3 are conductively joined to the support substrate 6B, and the fifth electrodes 12B of one or more second semiconductor elements 1B are conductively connected to the support substrate 6B via one or more wires 88.

[0084] The resistive substrate 4 may have a resistive layer 40, a first conductive layer 45, and a second conductive layer 46. The first conductive layer 45 may have a first portion 451 and a second portion 452. As shown in FIG. 12, the high resistance direction N1 of the resistive layer 40 is along the y direction. As shown in FIG. 10, the first electrodes 11A and the first power supply terminals 2A of one or more first semiconductor elements 1A are conductively joined to the first portion 451. The sub-substrate 7A may be located on the first portion 451. The capacitor element 3 is conductively joined to the second portion 452.

[0085] 10, 12, and 13, the first portion 451 and the second portion 452 are spaced apart from each other with the first opening 455 in between. In this embodiment, the first portion 451 and the second portion 452 are spaced apart in the y direction. That is, the first portion 451 and the second portion 452 are spaced apart in the high resistance direction N1. The second portion 452 is located on the y2 side of the first portion 451 in the y direction.

[0086] 12 and 13, in the present embodiment, the second conductive layer 46 may have a third portion 461 and a fourth portion 462. The third portion 461 and the fourth portion 462 are spaced apart from each other with the second opening 465 in between. In the present embodiment, the third portion 461 and the fourth portion 462 are spaced apart in the y direction. That is, the third portion 461 and the fourth portion 462 are spaced apart in the high resistance direction N1. The fourth portion 462 is located on the y2 side in the y direction with respect to the third portion 461.

[0087] In this embodiment, as shown in Figures 12 and 13, the first opening 455 and the second opening 465 at least partially overlap each other when viewed in the z direction. The first opening 455 and the second opening 465 may be configured such that one completely overlaps the other when viewed in the z direction. In the illustrated example, the first opening 455 and the second opening 465 completely overlap each other when viewed in the z direction.

[0088] The portions of the resistance layer 40 that overlap both the first opening 455 and the second opening 465 when viewed in the z direction form resistance portions R.

[0089] The first power supply terminal 2A may protrude from the resistance substrate 4 and the sealing resin 9 to the x1 side in the x direction. The second power supply terminal 2B may protrude from the support substrate 6B and the sealing resin 9 to the y2 side in the y direction. The output terminal 2C may protrude from the support substrate 6A and the sealing resin 9 to the y1 side in the y direction. The control terminal 2D and the control terminal 2F may protrude from the resistance substrate 4 and the sealing resin 9 to the x1 side in the x direction. The control terminal 2E and the control terminal 2G may protrude from the support substrate 6A and the sealing resin 9 to the x2 side in the x direction.

[0090] As shown in FIGS. 9 to 11, capacitor element 3 may be positioned so as to straddle the gap between resistance substrate 4 and support substrate 6B in the x direction.

[0091] This embodiment can reduce the size of the semiconductor device A2. As can be understood from this embodiment, the configurations for mechanically and electrically appropriately arranging one or more first semiconductor elements 1A, one or more second semiconductor elements 1B, and capacitor element 3 are not limited in any way, such as the configurations of the resistance substrate 4 and the support substrate 6 in the first embodiment, and the configurations of the resistance substrate 4, the support substrate 6A, and the support substrate 6B in this embodiment.

[0092] [Third embodiment] 14 to 19 show a semiconductor device according to a third embodiment of the present disclosure. In a semiconductor device A3 of this embodiment, a resistance substrate 4 has a resistance layer 40, a first conductive layer 45, and a second conductive layer 46. The resistance substrate 4 may have a heat transfer layer 42 and a metal layer 47.

[0093] The heat transfer layer 42 is located on the z2 side of the second conductive layer 46 in the z direction. The specific configuration of the heat transfer layer 42 is not limited in any way. The heat transfer layer 42 may contain, for example, graphite. In this case, the high resistance direction of the heat transfer layer 42 may be a direction intersecting the z direction. That is, the heat transfer layer 42 has a higher thermal conductivity in the z direction than in the high resistance direction. The thickness of the heat transfer layer 42 in the z direction is not limited in any way and may be thicker than the thickness of the resistance layer 40 in the z direction.

[0094] The resistive layer 40 may have a third opening 405. The third opening 405 is a hole penetrating the resistive layer 40 in the z direction. A part of the second conductive layer 46 may be exposed from the third opening 405. The first conductive layer 45 may have a first opening 455. The first opening 455 and the third opening 405 at least partially overlap each other when viewed in the z direction. As illustrated, the first opening 455 and the third opening 405 may completely overlap each other when viewed in the z direction.

[0095] The semiconductor device A3 may include a plurality of capacitor elements 3. The plurality of capacitor elements 3 are conductively joined to the connecting portion 21B and the second conductive layer 46. The capacitor elements 3 may be conductively joined to the second conductive layer 46 via a conductive member 85. At least a portion of the conductive member 85 may be accommodated in the first opening 455 and the third opening 405.

[0096] In this embodiment, the high resistance direction N1 of the resistance layer 40 is along the z direction. In the resistance layer 40, a portion overlapping the first conductive layer 45 and the second conductive layer 46 functions as a resistance portion R when viewed in the z direction.

[0097] This embodiment can reduce the size of the semiconductor device A3. As shown in Fig. 17, since the high resistance direction N1 is aligned with the z direction, the current flows in the z direction in the resistance portion R. This is therefore preferable for reducing the size of the semiconductor device A3 in the x and y directions.

[0098] By providing the third opening 405 in the resistive layer 40 and the first opening 455 in the first conductive layer 45, the conductive member 85 can be appropriately conductively joined to the second conductive layer .

[0099] When the resistance layer 40 contains graphite, the thermal conductivity of the resistance layer 40 is low in the z direction along the high resistance direction N1. The semiconductor device A3 is provided with a heat transfer layer 42 having high thermal conductivity in the z direction. The thickness of the heat transfer layer 42 in the z direction is thicker than the thickness of the resistance layer 40. This is therefore preferable for dissipating heat from one or more first semiconductor elements 1A to the z2 side in the z direction.

[0100] [Fourth embodiment] 20 to 25 show a semiconductor device according to a fourth embodiment of the present disclosure. In a semiconductor device A4 of this embodiment, as shown in FIGS. 22 to 25, a resistance layer 40 may include a first direction portion 40y and a second direction portion 40x.

[0101] The first direction portion 40y is a portion having a high resistance direction N1 along the y direction. The second direction portion 40x is a portion having a high resistance direction N2 along the x direction. As in the illustrated example, the first direction portion 40y may have a shape extending in the y direction. The first direction portion 40y may reach both ends of the resistance layer 40 in the y direction. The resistance layer 40 may have two second direction portions 40x. The two second direction portions 40x may be located on both sides of the first direction portion 40y in the x direction.

[0102] 23, the resistance layer 40 may have an insulating layer 49. The insulating layer 49 is interposed between the first direction portion 40y and the second direction portion 40x. The insulating layer 49 includes an insulating material.

[0103] The first conductive layer 45 may have a first portion 451 and a second portion 452. The first portion 451 is separated from the second portion 452 across the first opening 455 when viewed in the z direction. The first portion 451 may have a shape that surrounds the second portion 452 across the first opening 455 when viewed in the z direction. The first portion 451 may be in contact with the first direction portion 40y and two second direction portions 40x.

[0104] The second portion 452 may entirely overlap the first direction portion 40y when viewed in the z direction. The second portion 452 may be included in the first direction portion 40y when viewed in the z direction. The capacitor element 3 is conductively joined to the second portion 452. As illustrated, the capacitor element 3 may be conductively joined to the second portion 452 via a conductive member 85.

[0105] The second conductive layer 46 may have a shape having a second opening 465. The second opening 465 may include the entire first portion 451 when viewed in the z direction. As illustrated, the second conductive layer 46 overlaps at least a portion of the first portion 451 when viewed in the z direction. The second conductive layer 46 and the first portion 451 completely overlap each other when viewed in the z direction.

[0106] As shown in FIG. 25, a portion of the first direction portion 40y that overlaps with the first opening 455 and the second opening 465 functions as a resistor R.

[0107] This embodiment allows the semiconductor device A4 to be miniaturized. The resistance layer 40 has the first direction portion 40y and the second direction portion 40x, so that the resistance portion R shown in Fig. 25 can be appropriately set while reducing unintended current flow in other portions. The provision of the insulating layer 49 shown in Fig. 23 is preferable for reducing unintended current flow.

[0108] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.

[0109] [Appendix 1] A first power terminal (2A); A second power terminal (2B); A capacitor element (3); a resistive substrate (4) including a resistive layer (40); a first semiconductor element (1A) located on the resistance substrate (4); Equipped with The first semiconductor element (1A) is supported by the resistance substrate (4), The semiconductor device (A1), wherein the capacitor element (3) and the resistive layer (40) are electrically connected in series between the first power supply terminal (2A) and the second power supply terminal (2B). [Appendix 2] The semiconductor device (A1) according to appendix 1, wherein the resistive layer (40) has a high resistivity direction (N1) in which the electrical resistivity is higher than the electrical resistivity in other directions. [Appendix 3] The semiconductor device (A1) according to appendix 2, wherein the resistance layer (40) contains graphite. [Appendix 4] The resistance layer (40) has a main surface (401) facing a first side (z1) in a thickness direction (z) and a back surface (402) facing a second side (z2) opposite to the first side (z1), The semiconductor device (A1) according to appendix 2 or 3, wherein the resistance substrate (4) includes a first conductive layer (45) located on the main surface (401) and a second conductive layer (46) located on the back surface (402). [Appendix 5] The high resistance direction (N1) intersects with the thickness direction (z), The semiconductor device (A1) described in Appendix 4, wherein the first conductive layer (45) has a first opening (455) and includes a first portion (451) and a second portion (452) spaced apart in the high resistance direction (N1) across the first opening (455). [Appendix 6] the first power supply terminal (2A) and the first semiconductor element (1A) are conductively joined to the first portion (451); The semiconductor device (A1) according to appendix 5, wherein the capacitor element (3) is conductively joined to the second portion (452). [Appendix 7] The semiconductor device (A1) described in Appendix 6, wherein the second conductive layer (46) has a second opening (465) and includes a third portion (461) and a fourth portion (462) spaced apart in the high resistance direction (N1) on either side of the second opening (465). [Appendix 8] The semiconductor device (A1) according to appended claim 7, wherein the first opening (455) and the second opening (465) at least partially overlap each other when viewed in the thickness direction (z). [Appendix 9] The high resistance direction (N1) is along the thickness direction (z), the resistive layer (40) has a third opening (405) exposing the second conductive layer (46); The semiconductor device (A3) according to appendix 4, wherein the capacitor element (3) is conductively joined to the second conductive layer (46) through the third opening (405). [Appendix 10] The resistance layer (40) includes a first direction portion (40y) and a second direction portion (40x), The high resistance direction (N1) of the first direction portion (40y) is along a first direction (y) intersecting the thickness direction (z), The high resistance direction (N2) of the second direction portion (40x) is along a second direction (x) intersecting the thickness direction (z) and the first direction (y), The first conductive layer (45) includes a first portion (451) and a second portion (452), The second portion (452) overlaps the first portion (451) when viewed in the thickness direction (z) and is spaced apart from the first portion (451), The semiconductor device (A4) described in Appendix 4, wherein the first portion (451) has a first opening (455) and includes a portion separated from the second portion (452) in the high resistance direction (N1) across at least a portion of the first opening (455). [Appendix 11] The semiconductor device (A1) according to appendix 10, wherein the resistance layer (40) includes an insulating layer (49) interposed between the first direction portion (40y) and the second direction portion (40x). [Appendix 12] Further comprising a second semiconductor element (1B), The first semiconductor element (1A) constitutes an upper arm circuit, 12. The semiconductor device (A1) according to any one of claims 1 to 11, wherein the second semiconductor element (1B) constitutes a lower arm circuit. [Appendix 13] a sealing resin (9) for covering the first semiconductor element (1A); 13. The semiconductor device (A1) according to any one of claims 1 to 12, wherein the capacitor element (3) is covered with the sealing resin (9). [Explanation of symbols]

[0110] A1, A2, A3, A4: Semiconductor device 1A: First semiconductor element 1B: Second semiconductor element 2A: 1st power supply terminal 2B: 2nd power supply terminal 2C: Output terminal 2D, 2E, 2F, 2G: Control terminals 3: Capacitor element 4: Resistor board 5, 5A, 5B: Insulating substrate 6,6A,6B: Support board 7A,7B: Sub board 9: Sealing resin 11A: 1st electrode 11B: 4th electrode 12A: 2nd electrode 12B: 5th electrode 13A: 3rd electrode 13B: 6th electrode 19: Conductive bonding layer 21B: Liaison Department 39: Conductive bonding layer 40: Resistance layer 40x: 2nd direction part 40y: 1st direction part 42: Heat transfer layer 45: First conductive layer 46: Second conductive layer 47: Metal layer 49,50: Insulating layer 51,52: Metal layer 59: Bonding layer 60: Resistance layer 61: Main surface conductive layer 62: Back conductive layer 70A, 70B: Insulating layer 71A, 71B, 72A, 72B: Conductive layer 81, 82, 83, 84, 85: Conductive materials 88: Wire 89: Conductive bonding layer 401: Main surface 402: Back side 405: 3rd opening 451: Part 1 452: Part 2 453: Part 5 455, 456: First opening 461: Part 3 462: Part 4 463: Part 6 465, 466: Second opening 511, 512: 4th opening 591, 592: 5th opening 601: Main surface 602: Back side Cs: Snubber circuit N1,N2: High resistance direction R, R1, R2: Resistance section z: thickness direction

Claims

1. A first power supply terminal; A second power supply terminal; A capacitor element; a resistive substrate including a resistive layer; a first semiconductor element located on the resistance substrate; the capacitor element and the resistive layer are electrically connected in series between the first power supply terminal and the second power supply terminal.

2. The semiconductor device according to claim 1 , wherein the resistive layer has a high resistivity direction in which the electrical resistivity is higher than the electrical resistivity in other directions.

3. The semiconductor device according to claim 2 , wherein the resistive layer comprises graphite.

4. the resistance layer has a main surface facing a first side in a thickness direction and a back surface facing a second side opposite to the first side, 3. The semiconductor device according to claim 2, wherein said resistance substrate includes a first conductive layer located on said main surface and a second conductive layer located on said back surface.

5. the high resistance direction intersects with the thickness direction, 5. The semiconductor device according to claim 4, wherein said first conductive layer has a first opening, and includes a first portion and a second portion spaced apart from each other in said high resistance direction with said first opening sandwiched therebetween.

6. the first power supply terminal and the first semiconductor element are conductively joined to the first portion; The semiconductor device according to claim 5 , wherein the capacitor element is conductively joined to the second portion.

7. 7. The semiconductor device according to claim 6, wherein said second conductive layer has a second opening, and includes a third portion and a fourth portion spaced apart from each other in said high resistance direction with said second opening sandwiched therebetween.

8. The semiconductor device according to claim 7 , wherein the first opening and the second opening at least partially overlap each other when viewed in the thickness direction.

9. The high resistance direction is along the thickness direction, the resistive layer has a third opening exposing the second conductive layer; The semiconductor device according to claim 4 , wherein the capacitor element is conductively joined to the second conductive layer through the third opening.

10. the resistive layer includes a first direction portion and a second direction portion, The high resistance direction of the first direction portion is along a first direction intersecting the thickness direction, the high resistance direction of the second direction portion is along a second direction intersecting the thickness direction and the first direction, the first conductive layer includes a first portion and a second portion; The second portion overlaps the first portion when viewed in the thickness direction and is spaced apart from the first portion, 5 . The semiconductor device according to claim 4 , wherein said first portion has a first opening, and includes a portion separated from said second portion in said high resistance direction with at least a part of said first opening sandwiched therebetween.

11. The semiconductor device according to claim 10 , wherein the resistive layer includes an insulating layer interposed between the first direction portion and the second direction portion.

12. Further comprising a second semiconductor element; the first semiconductor element constitutes an upper arm circuit, The semiconductor device according to claim 1 , wherein the second semiconductor element constitutes a lower arm circuit.

13. a sealing resin for covering the first semiconductor element; The semiconductor device according to claim 1 , wherein the capacitor element is covered with the sealing resin.

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