Semiconductor device

Abstract

To provide a semiconductor device capable of improving heat dissipation in a portion close to a surface electrode.SOLUTION: A wiring member 50 has a bonded surface 55 in contact with a bonding member 60. In a plan view along a direction perpendicular to a surface electrode 10, the bonded surface 55 covers at least a part of each of a plurality of diode regions 2. The plurality of diode regions 2 have a first diode region 21, a second diode region 22, and a third diode region 23. In the plan view, the second diode region 22 is located in a first direction 101 with respect to the first diode region 21 and is spaced apart from the first diode region 21. In the plan view, the third diode region 23 is located in a second direction 102 perpendicular to the first direction 101 with respect to the first diode region 21 and is spaced apart from each of the first diode region 21 and the second diode region 22.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Semiconductor elements such as insulated gate bipolar transistors (IGBTs) and reverse conducting-insulated gate bipolar transistors (RC-IGBTs) generate heat when current is applied, when current is started, and when current is stopped. This heat can shorten the life of a semiconductor device in which the semiconductor elements are mounted, which in turn reduces the reliability of the semiconductor device. Therefore, there is a demand for technology to dissipate the heat generated by the heat generated by semiconductor elements.

[0003] As an example of a semiconductor device, JP 2022-158037 A (Patent Document 1) describes a semiconductor device having an RC-IGBT chip arranged on a copper circuit pattern. In the semiconductor device, a wire is bonded to the surface electrode (emitter electrode) of the RC-IGBT. The wire is used as an external wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-158037 Summary of the Invention [Problem to be solved by the invention]

[0005] When an RC-IGBT is short-circuited, the IGBT region of the RC-IGBT generates heat. In particular, heat is generated in a portion of the IGBT region close to the surface electrode. According to the semiconductor device described in the above Patent Document 1, the surface of the RC-IGBT is electrically connected to the outside using a wire. Therefore, heat generated in a portion of the RC-IGBT chip close to the surface electrode is not sufficiently dissipated. The present disclosure has been made in view of the above, and has an object to provide a semiconductor device capable of improving heat dissipation in a portion close to the surface electrode. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes an insulated gate bipolar transistor region, a plurality of diode regions, a surface electrode, a bonding member, and a wiring member. The plurality of diode regions are in contact with the insulated gate bipolar transistor region. The surface electrode is in contact with the insulated gate bipolar transistor region and the plurality of diode regions. The bonding member is provided on the surface electrode. The wiring member is bonded to the surface electrode by the bonding member. The insulated gate bipolar transistor region and the plurality of diode regions form a reverse conducting insulated gate bipolar transistor. The wiring member has a bonded surface in contact with the bonding member. In a plan view seen along a direction perpendicular to the surface electrode, the bonded surface covers at least a portion of each of the plurality of diode regions. The plurality of diode regions include a first diode region, a second diode region, and a third diode region. In a plan view, the second diode region is located in a first direction with respect to the first diode region and is spaced apart from the first diode region. In a plan view, the third diode region is located in a second direction perpendicular to the first direction relative to the first diode region, and is spaced apart from each of the first diode region and the second diode region. Effect of the Invention

[0007] In the semiconductor device according to the present disclosure, the second diode region is located in a first direction relative to the first diode region, and the third diode region is located in a second direction relative to the first diode region. This makes it easier to dissipate heat using the wiring member while transferring heat from the insulated gate bipolar region to the multiple diode regions. This makes it possible to provide a semiconductor device that can improve heat dissipation in a portion close to the front electrode. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a schematic plan view showing the configuration of a semiconductor element. [Figure 4] FIG. 2 is a schematic cross-sectional view showing a configuration of a semiconductor element. [Diagram 5] 1 is a schematic plan view showing a configuration of a semiconductor element according to a first modified example of the first embodiment. FIG. [Figure 6] 11 is a schematic plan view showing a configuration of a semiconductor element according to a second modification of the first embodiment. FIG. [Figure 7] FIG. 13 is a schematic plan view showing a configuration of a semiconductor device according to a third modification of the first embodiment. [Figure 8] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a second embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view taken along line IX-IX in FIG. [Figure 10] 11 is a plan view showing a configuration of a semiconductor element according to a third embodiment. FIG. [Figure 11] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a third embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment. [Figure 14]FIG. 13 is a plan view showing a configuration of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment. [Figure 16] FIG. 23 is a cross-sectional view illustrating a configuration of a semiconductor device according to a modification of the sixth embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment. [Figure 18] FIG. 13 is a plan view showing a configuration of a semiconductor device according to an eighth embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

[0010] Embodiment 1

[0011] <Configuration of Semiconductor Device>

[0012] First, the configuration of a semiconductor device 100 according to a first embodiment will be described with reference to Figures 1 and 2. For ease of explanation, a plurality of diode regions 2, which will be described later, are indicated by dashed lines in Figure 1.

[0013] 1 and 2, the semiconductor device 100 according to the first embodiment mainly includes a semiconductor element 30, a bonding member 60, and a wiring member 50. The bonding member 60 bonds the semiconductor element 30 and the wiring member 50. The wiring member 50 electrically connects the semiconductor element 30 to an external device (not shown).

[0014] 2 and 3, the semiconductor element 30 has a front electrode 10, a back electrode 11, an insulated gate bipolar transistor region 1, a plurality of diode regions 2, and a termination region 4. In the following, the insulated gate bipolar transistor region 1 will also be referred to as an IGBT region 1.

[0015] As shown in FIG. 2, the semiconductor element 30 has a first surface 71 and a second surface 72. The second surface 72 is opposite to the first surface 71. The direction from the first surface 71 toward the second surface 72 is a third direction 103. The third direction 103 is a direction perpendicular to the surface electrode 10. A surface electrode 10 is provided on the first surface 71. The surface electrode 10 is an emitter electrode. A back surface electrode 11 is provided on the second surface 72. The back surface electrode 11 is a collector electrode.

[0016] The IGBT region 1 and the multiple diode regions 2 constitute a first surface 71 and a second surface 72. The IGBT region 1 is in contact with each of the front surface electrode 10 and the back surface electrode 11. The IGBT region 1 is electrically connected to each of the front surface electrode 10 and the back surface electrode 11.

[0017] 2, each of the multiple diode regions 2 is in contact with the IGBT region 1. Each of the multiple diode regions 2 is in contact with each of the front surface electrode 10 and the back surface electrode 11. Each of the multiple diode regions 2 is electrically connected to each of the front surface electrode 10 and the back surface electrode 11.

[0018] The plurality of diode regions 2 are spaced apart from one another. When viewed along a direction perpendicular to the surface electrode 10 (hereinafter also referred to as a plan view), each of the plurality of diode regions 2 has, for example, a rectangular shape.

[0019] The termination region 4 is in contact with the IGBT region 1. The termination region 4 surrounds the IGBT region 1 and the plurality of diode regions 2. The termination region 4 forms a part of the second surface 72. A detailed configuration of the termination region 4 will be described later.

[0020] 2, the bonding member 60 is provided on the surface electrode 10. The bonding member 60 is, for example, solder. In a plan view, the bonding member 60 is surrounded by the termination region 4. The bonding member 60 transfers heat from the surface electrode 10 to the wiring member 50.

[0021] The wiring member 50 is metallically joined to the surface electrode 10 by the joining member 60. Specifically, the wiring member 50 is electrically connected to the surface electrode 10 by the joining member 60. The wiring member 50 is made of metal.

[0022] As shown in FIG. 1 and FIG. 2, the wiring member 50 has a flat plate portion 49 and a conductive plate portion 51. The wiring member 50 is a DLB (Direct Lead Bonding) electrode. In a plan view, the flat plate portion 49 has a rectangular shape. The flat plate portion 49 is in contact with a bonding member 60. In a third direction 103, the bonding member 60 is provided between the flat plate portion 49 and the surface electrode 10. The flat plate portion 49 may be spaced apart from the surface electrode 10. In a plan view, the flat plate portion 49 is surrounded by the termination region 4.

[0023] 1 and 2, the flat plate portion 49 has a first end portion 81 and a second end portion 82. The first end portion 81 extends, for example, along the direction in which the long sides of the multiple diode regions 2 extend. In the flat plate portion 49, the second end portion 82 is provided on the opposite side to the first end portion 81. The extension direction of the second end portion 82 may be, for example, substantially parallel to the extension direction of the first end portion 81.

[0024] 2, the flat plate portion 49 has a joining surface 55 and a front surface 56. The joining surface 55 is the surface of the flat plate portion 49 that is in contact with the joining member 60. In other words, the joining surface 55 is in contact with the joining member 60 of the flat plate portion 49. The joining surface 55 is, for example, planar. The front surface 56 is opposite to the joining surface 55. From another point of view, the front surface 56 is provided in a direction opposite to the third direction 103 with respect to the joining surface 55.

[0025] 1, in a plan view, the flat plate portion 49 covers at least a portion of each of the plurality of diode regions 2. From another perspective, in a plan view, the bonded surface 55 (see FIG. 2) covers at least a portion of each of the plurality of diode regions 2.

[0026] As shown in Figs. 1 and 2, the conductive plate portion 51 is connected to the flat plate portion 49. Specifically, for example, at the first end portion 81, the conductive plate portion 51 is connected to the flat plate portion 49. The conductive plate portion 51 is provided, for example, in a direction opposite to the third direction 103 with respect to the flat plate portion 49. The conductive plate portion 51 is spaced apart from the joining member 60. The interface between the conductive plate portion 51 and the flat plate portion 49 is defined as a connection portion 59. In other words, the conductive plate portion 51 is connected to the flat plate portion 49 at the connection portion 59. The conductive plate portion 51 forms a path for a current flowing between the surface electrode 10 and an external device (not shown).

[0027] The extending direction of the conductive plate portion 51 is substantially parallel to the extending direction of the long sides of the multiple diode regions 2. From another point of view, the connecting portion 59 extends along the extending direction of the long sides of each of the multiple diode regions 2.

[0028] <Configuration of semiconductor element>

[0029] Next, the configuration of the semiconductor element 30 will be described with reference to Figures 3 and 4. For ease of explanation, the surface electrode 10 is not shown in Figure 3. The cross section shown in Figure 4 is a cross section perpendicular to the surface electrode 10.

[0030] 3, the semiconductor element 30 is an island-type RC-IGBT. Specifically, the multiple diode regions 2 are arranged in an island shape. From another perspective, two or more diode regions 2 are arranged side by side along each of the first direction 101 and the second direction 102 in a region overlapping with one surface electrode 10 in a plan view.

[0031] The multiple diode regions 2 include a first diode region 21, a second diode region 22, and a third diode region 23. The first diode region 21 is, for example, a diode region 2 located at a corner of the multiple diode regions 2. The second diode region 22 is spaced apart from the first diode region 21. In a plan view, a direction from the first diode region 21 to the second diode region 22 is defined as a first direction 101. From another perspective, in a plan view, the second diode region 22 is located in the first direction 101 with respect to the first diode region 21.

[0032] The third diode region 23 is spaced apart from each of the first diode region 21 and the second diode region 22. In a plan view, the direction from the first diode region 21 toward the third diode region 23 is defined as a second direction 102. From another perspective, the third diode region 23 is located in the second direction 102 with respect to the first diode region 21. The second direction 102 is a direction perpendicular to the first direction 101. The long side of each of the multiple diode regions 2 may be parallel to the second direction 102, for example.

[0033] As shown in FIG. 3, the plurality of diode regions 2 have a plurality of columns 20. Each of the plurality of columns 20 is composed of a plurality of diode regions 2 aligned along the second direction 102. The number of diode regions 2 included in one column 20 is not particularly limited, but is, for example, four. In the column 20, for example, four diode regions 2 may be aligned at substantially equal intervals along the second direction 102. The plurality of columns 20 are aligned along the first direction 101. The plurality of columns 20 may be aligned at equal intervals along the first direction 101. The number of columns 20 is not particularly limited, but is, for example, eight.

[0034] Each of the multiple diode regions 2 is surrounded by the IGBT region 1. From another perspective, the IGBT region 1 has a portion sandwiched between two diode regions 2 in the first direction 101. The IGBT region 1 has a portion sandwiched between two diode regions 2 in the second direction 102.

[0035] In plan view, the shape of the semiconductor element 30 is, for example, a rectangular shape. In plan view, the direction in which the long sides of the semiconductor element 30 extend is a first direction 101. In plan view, the direction in which the short sides of the semiconductor element 30 extend is a second direction .

[0036] 4, the semiconductor device 30 has a semiconductor substrate 70. The configuration of the diode region 2 will be described. The semiconductor substrate 70 has, for example, an n- type drift layer 43, an n+ type carrier store layer 32, a p-type base layer 35, a p-type anode layer 28, an n- type buffer layer 37, and an n+ type cathode layer 29.

[0037] The n+ type carrier store layer 32 is provided on the n- type drift layer 43. The n+ type carrier store layer 32 has a higher concentration of n-type impurities than the n- type drift layer 43. The p-type base layer 35 is provided on the n+ type carrier store layer 32.

[0038] The p-type anode layer 28 is provided on the p-type base layer 35. The p-type anode layer 28 is provided in the diode region 2. The p-type anode layer 28 has a higher p-type impurity concentration than the p-type base layer 35. The p-type anode layer 28 constitutes a part of the first surface 71 (see FIG. 2).

[0039] The n-type buffer layer 37 is provided in the third direction 103 with respect to the n-type drift layer 43. The n-type buffer layer 37 is in contact with the n-type drift layer 43. The n-type buffer layer 37 has a higher concentration of n-type impurities than the n-type drift layer 43.

[0040] The n+ type cathode layer 29 is provided in the third direction 103 with respect to the n-type buffer layer 37. The n+ type cathode layer 29 is in contact with the n-type buffer layer 37. The n+ type cathode layer 29 is provided in the diode region 2. The n+ type cathode layer 29 is electrically connected to the back surface electrode 11. The n+ type cathode layer 29 constitutes a part of the second surface 72 (see FIG. 2).

[0041] A first trench gate 31a is provided in the semiconductor substrate 70 in the diode region 2. The first trench gate 31a extends from the first surface 71 along the third direction 103. The first trench gate 31a reaches the n-type drift layer 43. The first trench gate 31a is electrically connected to the front surface electrode 10.

[0042] Next, the configuration of the IGBT region 1 will be described. The semiconductor substrate 70 has an n+ type source layer 33, a p+ type contact layer 38, and a p type collector layer 36. The n+ type source layer 33 is provided on the p type base layer 35. The n+ type source layer 33 is provided in the IGBT region 1. The n+ type source layer 33 forms a part of a first surface 71 (see FIG. 2).

[0043] The p+ type contact layer 38 is provided on the p-type base layer 35. The p+ type contact layer 38 is provided in the IGBT region 1 and the termination region 4. The p+ type contact layer 38 is spaced apart from the n+ type source layer 33. The p-type impurity concentration of the p+ type contact layer 38 is higher than the p-type impurity concentration of the p-type base layer 35. The p-type impurity concentration of the p+ type contact layer 38 may be the same as the p-type impurity concentration of the p-type anode layer 28.

[0044] The p-type collector layer 36 is provided in the third direction 103 with respect to the n-type buffer layer 37. The p-type collector layer 36 is in contact with the n-type buffer layer 37. The p-type collector layer 36 is provided in the IGBT region 1. The p-type collector layer 36 constitutes a part of the second surface 72 (see FIG. 2 ). The p-type collector layer 36 is electrically connected to the back surface electrode 11. The p-type collector layer 36 is in contact with the n+ type cathode layer 29. The interface between the p-type collector layer 36 and the n+ type cathode layer 29 is the boundary between the diode region 2 and the IGBT region 1.

[0045] A second trench gate 31b and a third trench gate 31c are provided in a semiconductor substrate 70 in the IGBT region 1. The second trench gate 31b extends from the first surface 71 along a third direction 103. The second trench gate 31b reaches the n- type drift layer 43. The second trench gate 31b is in contact with the n+ type source layer 33. An interlayer insulating film 34 is provided on the second trench gate 31b. The second trench gate 31b and the front surface electrode 10 are electrically insulated from each other by the interlayer insulating film 34.

[0046] The third trench gate 31c extends from the first surface 71 along the third direction 103. The third trench gate 31c reaches the n- type drift layer 43. The third trench gate 31c is in contact with the p+ type contact layer 38. The third trench gate 31c is electrically connected to the front surface electrode 10.

[0047] Next, a description will be given of the configuration of the termination region 4. The semiconductor substrate 70 has a p-type termination well layer 41, an n+ type channel stopper layer 42, and a p-type termination collector layer 36a.

[0048] The p-type termination well layer 41 is provided in the termination region 4. The p-type termination well layer 41 is in contact with the n-type drift layer 43. The p-type termination well layer 41 constitutes a part of the first surface 71 (see FIG. 2). The semiconductor substrate 70 has, for example, three p-type termination well layers 41. Each of the three p-type termination well layers 41 is spaced apart from one another. In a plan view, each of the three p-type termination well layers 41 has an annular shape. Each of the three p-type termination well layers 41 surrounds the IGBT region 1 and the multiple diode regions 2.

[0049] The n+ type channel stopper layer 42 is provided in the termination region 4. The n+ type channel stopper layer 42 constitutes a part of the first surface 71 (see FIG. 2). In a plan view, the n+ type channel stopper layer 42 has an annular shape. The n+ type channel stopper layer 42 surrounds the p-type termination well layer 41.

[0050] A termination electrode 10a is provided on the p-type termination well layer 41 and the n+ type channel stopper layer 42. The termination electrode 10a is electrically connected to the p-type termination well layer 41 and the n+ type channel stopper layer 42.

[0051] A termination protective film 5 is provided in the termination region 4. The termination protective film 5 covers the surface electrode 10, the termination electrode 10a, and the interlayer insulating film 34. The termination protective film 5 is made of, for example, polyimide. An end face of the termination protective film 5 close to the IGBT region 1 is set as the boundary between the termination region 4 and the IGBT region 1.

[0052] The p-type termination collector layer 36a is disposed in the third direction 103 relative to the n-type buffer layer 37. The p-type termination collector layer 36a is in contact with the n-type buffer layer 37. The p-type termination collector layer 36a is disposed in the termination region 4. The p-type termination collector layer 36a constitutes a part of the second face 72 (see FIG. 2). The configuration of the p-type termination collector layer 36a is substantially the same as the configuration of the p-type collector layer 36.

[0053] Next, the effects of the semiconductor device 100 according to the first embodiment will be described.

[0054] The RC-IGBT generates heat while it is energized, when it starts energizing, and when it stops energizing. Specifically, when the IGBT region 1 is energized, the IGBT region 1 generates heat. A copper circuit pattern may be connected to the back electrode 11 of the RC-IGBT. In this case, the copper circuit pattern is used to dissipate heat from a portion of the RC-IGBT close to the back electrode 11. However, when a short circuit occurs in the RC-IGBT, a particularly large amount of heat is generated in a portion of the IGBT region 1 close to the front electrode 10. In this case, the heat generation may instantly damage the RC-IGBT.

[0055] According to the semiconductor device 100 according to the first embodiment, in a plan view, the bonded surface 55 of the wiring member 50 covers at least a part of each of the plurality of diode regions 2. In a plan view, the second diode region 22 is located in a first direction 101 relative to the first diode region 21. The second diode region 22 is spaced apart from the first diode region 21. In a plan view, the third diode region 23 is located in a second direction 102 relative to the first diode region 21. The third diode region 23 is spaced apart from each of the first diode region 21 and the second diode region 22. This makes it possible to increase the contact area between the plurality of diode regions 2 and the IGBT region 1. This allows the heat to be efficiently transferred from the IGBT region 1 to the plurality of diode regions 2 when the IGBT region 1 generates heat. In addition, since the bonded surface 55 covers at least a part of each of the plurality of diode regions 2, the heat can be efficiently transferred from each of the plurality of diode regions 2 to the wiring member 50. As a result, the heat dissipation in the portion of the semiconductor device 100 close to the surface electrode 10 can be improved.

[0056] According to the semiconductor device 100 of the first embodiment, it is possible to improve the heat dissipation in the portion of the semiconductor device 100 close to the front electrode 10. Therefore, when a short circuit occurs in the RC-IGBT, it is possible to prevent the temperature of the semiconductor device 100 from becoming excessively high locally. As a result, it is possible to increase the short circuit resistance of the semiconductor device 100.

[0057] According to the semiconductor device 100 of the first embodiment, the first diode region 21 has a rectangular shape in a plan view. The wiring member 50 has a flat plate portion 49 and a conductive plate portion 51. A connection portion 59 between the flat plate portion 49 and the conductive plate portion 51 extends along the direction in which the long side of the first diode region 21 extends. Therefore, compared to a case in which the connection portion 59 extends along the direction in which the short side of the first diode region 21 extends, the uniformity of the current flowing between the first diode region 21 and the connection portion 59 can be improved. Therefore, an increase in the amount of heat generated due to localized concentration of the current can be suppressed. As a result, the heat dissipation of the semiconductor device 100 can be improved when the multiple diode regions 2 are conducting electricity.

[0058] (First Modification of the First Embodiment)

[0059] Next, the configuration of a semiconductor device 100 according to a first modification of the first embodiment will be described with reference to Fig. 5. For ease of explanation, the surface electrode 10 is not shown in Fig. 5.

[0060] Although the configuration in which each of the multiple diode regions 2 has a rectangular shape in a plan view has been described above, the configuration of the semiconductor device 100 according to the present disclosure is not limited to the above configuration. Specifically, as shown in FIG. 5, each of the multiple diode regions 2 may have a square shape in a plan view. From another perspective, the length of the diode region 2 in the first direction 101 and the length of the diode region 2 in the second direction 102 may be substantially the same. One side of each of the multiple diode regions 2 is substantially parallel to the first direction 101.

[0061] This can reduce the difference between the uniformity of the current flowing between the plurality of diode regions 2 and the connection portion 59 when the connection portion 59 of the wiring member 50 extends along the first direction 101 and the uniformity of the current flowing between the plurality of diode regions 2 and the connection portion 59 when the connection portion 59 extends along the second direction 102. From another perspective, the heat dissipation of the semiconductor device 100 can be sufficiently improved in both cases where the connection portion 59 extends along the first direction 101 and where the connection portion 59 extends along the second direction 102. Therefore, the arrangement of the conductive plate portion 51 can be determined in consideration of the wiring between the conductive plate portion 51 and an external device while maintaining the heat dissipation of the plurality of diode regions 2. As a result, the degree of freedom of wiring can be improved.

[0062] (Second Modification of the First Embodiment)

[0063] Next, a configuration of a semiconductor device 100 according to a second modification of the first embodiment will be described with reference to Fig. 6. In Fig. 6, the front surface electrode 10 is not shown.

[0064] 6, the density of the diode regions 2 may be low in the center of the region where the multiple diode regions 2 are arranged. Specifically, in a plan view, the smallest rectangular region that surrounds all of the multiple diode regions 2 is defined as a virtual region 91. A virtual line located midway between the outer edge (first outer edge 92) of the virtual region 91 and the center (first center 93) of the virtual region 91 is defined as a boundary line 95.

[0065] The virtual region 91 is composed of an outer peripheral region 96 and a central region 97. The outer peripheral region 96 is between the first outer edge 92 and the boundary line 95. The central region 97 is inside the boundary line 95. The central region 97 is continuous with the outer peripheral region 96. The central region 97 is surrounded by the outer peripheral region 96.

[0066] In a plan view, the density of the multiple diode regions 2 in the central region 97 is smaller than the density of the multiple diode regions 2 in the peripheral region 96. The size of the diode regions 2 in the central region 97 may be smaller than the size of the diode regions 2 in the peripheral region 96. Specifically, for example, the length in the second direction 102 of the diode regions 2 in the central region 97 is shorter than the length in the second direction 102 of the diode regions 2 in the peripheral region 96.

[0067] The length in the first direction 101 of the diode region 2 in the central region 97 may be substantially the same as the length in the first direction 101 of the diode region 2 in the peripheral region 96. In a plan view, the multiple diode regions 2 may include a diode region 2 that is square-shaped and a diode region 2 that is rectangular-shaped.

[0068] When the multiple diode regions 2 are conducting, the temperature is more likely to rise in the central region 97 than in the peripheral region 96. According to the semiconductor device 100 according to the second modification of the first embodiment, the density of the multiple diode regions 2 in the central region 97 is smaller than the density of the multiple diode regions 2 in the peripheral region 96 in a plan view. Therefore, when the multiple diode regions 2 are conducting, it is possible to prevent the temperature of the central region 97 from becoming excessively higher than the temperature of the peripheral region 96. As a result, when the multiple diode regions 2 are conducting, it is possible to improve the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10.

[0069] (Third Modification of the First Embodiment)

[0070] Next, the configuration of the semiconductor device 100 according to the third modified example of the first embodiment will be described with reference to FIG. 7. As shown in FIG. 7, the wiring member 50 may cover the entirety of each of the plurality of diode regions 2. Specifically, in a plan view, the bonded surface 55 (see FIG. 2) may cover the entirety of each of the plurality of diode regions 2. In a plan view, the bonding member 60 (see FIG. 2) may cover the entirety of each of the plurality of diode regions 2. From another perspective, in a plan view, the plurality of diode regions 2 are surrounded by the outer edge of the flat plate portion 49.

[0071] This can further increase the thermal energy transferred from the plurality of diode regions 2 to the wiring member 50 via the surface electrode 10 and the bonding member 60. This can further improve the heat dissipation in the portion of the semiconductor device 100 close to the surface electrode 10.

[0072] In the above, the configuration in which the first diode region 21 is located at a corner of the plurality of diode regions 2 has been described, but the position of the first diode region 21 does not have to be at a corner of the plurality of diode regions 2. The diode region 2 may be provided in the direction opposite to the first direction 101 and the direction opposite to the second direction 102 with respect to the first diode region 21.

[0073] Embodiment 2

[0074] Next, the configuration of the semiconductor device 100 according to the second embodiment will be described with reference to Figures 8 and 9. The semiconductor device 100 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that it has a protective film 6, and is substantially the same as the semiconductor device 100 according to the first embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the first embodiment.

[0075] As shown in FIG. 8 and FIG. 9, the semiconductor device 100 may have a protective film 6. The protective film 6 is provided on the termination region 4. The protective film 6 covers the termination region 4. The protective film 6 is in contact with the front electrode 10. The protective film 6 covers a part of the front electrode 10. In a plan view, the protective film 6 surrounds a plurality of diode regions 2. The protective film 6 is made of, for example, a nitride film such as polyimide, a silicon nitride film (SiN: Silicon Nitride) and a semi-insulating silicon nitride film (SInSiN: Semi-Insulating Silicon Nitride), or an oxide film such as SIPOS (Semi-Insulating Poly-crystalline Silicon). The protective film 6 is provided on the termination region 4, so that the concentration of the electric field in the termination region 4 can be alleviated.

[0076] Embodiment 3

[0077] Next, the configuration of a semiconductor device 100 according to a third embodiment will be described with reference to Figures 10 to 12. The semiconductor device 100 according to the third embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that the distances in a plan view between the outer edge of the bonded surface 55 and each of the termination region 4 and the multiple diode regions 2 are sufficiently long, but in other respects, the semiconductor device 100 according to the third embodiment is substantially the same as the semiconductor device 100 according to the first embodiment. The following description will focus on the differences from the semiconductor device 100 according to the first embodiment.

[0078] 10, the shortest distance between termination region 4 and the multiple diode regions 2 in a planar view is set to be a first distance L1. Specifically, first distance L1 is the shortest distance between termination protective film 5 (see FIG. 4) of termination region 4 and n+ type cathode layer 29 (see FIG. 4) in a planar view. First distance L1 is, for example, the shortest distance between termination region 4 and the multiple diode regions 2 in first direction 101.

[0079] 11 and 12, the shortest distance between the outer edge (second outer edge 98) of the joined surface 55 (see FIG. 12) and the plurality of diode regions 2 in a plan view is set to be a second distance L2. Specifically, the second distance L2 is the shortest distance between the second outer edge 98 and the n+ type cathode layer 29 (see FIG. 4) in a plan view. The second distance L2 is, for example, the shortest distance between the second outer edge 98 and the plurality of diode regions 2 in the first direction 101. In a plan view, the second outer edge 98 may substantially overlap with the outer edge of the flat plate portion 49.

[0080] 12, the distance between the first surface 71 and the second surface 72 in the third direction 103 is set to a thickness H of the IGBT region 1 in the third direction 103. The thickness H is the thickness of the semiconductor substrate 70 (see FIG. 4) in the third direction 103. The thickness H is substantially the same as the thickness of the diode region 2 in the third direction 103.

[0081] 10 to 12, the first distance L1 is equal to or greater than the thickness H. The second distance L2 is equal to or greater than the thickness H. The second distance L2 is shorter than the first distance L1.

[0082] According to the semiconductor device 100 of the third embodiment, the first distance L1 is equal to or greater than the thickness H. In this manner, the distance between the termination region 4 and the plurality of diode regions 2 is sufficiently long. This makes it possible to suppress the inflow of holes from the termination region 4 to the plurality of diode regions 2. This makes it possible to suppress power loss when the plurality of diode regions 2 are conducting.

[0083] When the multiple diode regions 2 are conducting, carriers diffuse from the diode regions 2 along a direction inclined at an angle of 45° or less with respect to the third direction 103. Heat is generated in the region where the carriers diffuse. According to the semiconductor device 100 of the third embodiment, the second distance L2 is equal to or greater than the thickness H. Therefore, in a plan view, the joined surface 55 can cover the region where the carriers diffuse when the multiple diode regions 2 are conducting. This can further improve the heat dissipation performance of the semiconductor device 100.

[0084] Embodiment 4

[0085] Next, the configuration of the semiconductor device 100 according to the fourth embodiment will be described with reference to Fig. 13. The semiconductor device 100 according to the fourth embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that it has diode regions 2 arranged to sandwich the gate pad 7, and is substantially the same as the semiconductor device 100 according to the first embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the first embodiment.

[0086] 13, the semiconductor device 100 has a gate pad 7. In a plan view, the gate pad 7 is provided, for example, in a first direction 101 with respect to the center (second center 94) of the surface electrode 10. The gate pad 7 is adjacent to, for example, the termination region 4. In a plan view, an imaginary line passing through the second center 94 and parallel to the first direction 101 is set as a center line A. In a plan view, the center line A passes through, for example, the gate pad 7. The gate pad 7 is configured to receive a signal that controls the conduction of the IGBT region 1 (see FIG. 2).

[0087] In the semiconductor device 100, the gate pad 7 is provided on the opposite side to the back surface electrode 11. From another point of view, the gate pad 7 is provided in the direction opposite to the third direction 103 with respect to the IGBT region 1.

[0088] The plurality of diode regions 2 include two sets of pad-sandwiched diode regions. Specifically, the plurality of diode regions 2 include a fourth diode region 24, a fifth diode region 25, a sixth diode region 26, and a seventh diode region 27. The fourth diode region 24, the fifth diode region 25, the sixth diode region 26, and the seventh diode region 27 are spaced apart from each other.

[0089] The fifth diode region 25 is provided in the second direction 102 with respect to the fourth diode region 24. In the second direction 102, the fourth diode region 24 and the fifth diode region 25 are disposed to sandwich the gate pad 7. From another perspective, the gate pad 7 is provided between the fourth diode region 24 and the fifth diode region 25 in a plan view.

[0090] The seventh diode region 27 is provided in the second direction 102 with respect to the sixth diode region 26. In the second direction 102, the sixth diode region 26 and the seventh diode region 27 are disposed to sandwich the gate pad 7. From another perspective, the gate pad 7 is provided between the sixth diode region 26 and the seventh diode region 27 in a plan view.

[0091] The flat plate portion 49 does not cover the gate pad 7. From another perspective, in a plan view, the bonded surface 55 (see FIG. 2) is spaced apart from the gate pad 7. In a plan view, the part of the flat plate portion 49 close to the gate pad 7 is bifurcated. Specifically, the flat plate portion 49 has a main body portion 80, a first portion 61, and a second portion 62. The first portion 61 is continuous with the main body portion 80. The first portion 61 is provided in a first direction 101 with respect to the main body portion 80. In a plan view, the first portion 61 overlaps each of the fourth diode region 24 and the sixth diode region 26.

[0092] The second portion 62 is continuous with the main body 80. The second portion 62 is provided in a first direction 101 relative to the main body 80. The second portion 62 is spaced apart from the first portion 61. The second portion 62 is provided in a second direction 102 relative to the first portion 61. The second portion 62 overlaps with each of the fifth diode region 25 and the seventh diode region 27 in a plan view. The gate pad 7 is provided between the first portion 61 and the second portion 62 in a plan view.

[0093] In plan view, the conductive plate portion 51 is provided, for example, in a direction opposite to the gate pad 7 with respect to the second center 94. From another perspective, in plan view, the conductive plate portion 51 is provided, for example, in a direction opposite to the first direction 101 with respect to the second center 94. In plan view, the second center 94 is, for example, between the conductive plate portion 51 and the gate pad 7.

[0094] According to the semiconductor device 100 of the fourth embodiment, the plurality of diode regions 2 include a fourth diode region 24 and a fifth diode region 25. The gate pad 7 is provided between the fourth diode region 24 and the fifth diode region 25. Therefore, compared to a case where the fourth diode region 24 and the fifth diode region 25 are not provided, when the total area of ​​the plurality of diode regions 2 in a plan view is the same, the density of the plurality of diode regions 2 can be reduced. Therefore, when the plurality of diode regions 2 are conducting, the heat dissipation of the portion of the semiconductor device 100 close to the front electrode 10 can be improved.

[0095] According to the semiconductor device 100 of the fourth embodiment, the flat plate portion 49 has a first portion 61 and a second portion 62. In a plan view, the first portion 61 overlaps the fourth diode region 24. In a plan view, the second portion 62 overlaps the fifth diode region 25. This makes it possible to increase the amount of thermal energy transferred from each of the fourth diode region 24 and the fifth diode region 25 to the wiring member 50. This makes it possible to improve the heat dissipation properties of the fourth diode region 24 and the fifth diode region 25.

[0096] According to the semiconductor device 100 of the fourth embodiment, in a plan view, the conductive plate portion 51 is provided in the opposite direction to the gate pad 7 with respect to the second center 94. This makes it possible to prevent interference between the gate wiring connected to the gate pad 7 and the conductive plate portion 51. This improves the degree of freedom in wiring.

[0097] It should be noted that the plurality of diode regions 2 may have one set of pad-sandwiching diode regions. In other words, the plurality of diode regions 2 may not have the sixth diode region 26 and the seventh diode region 27.

[0098] Embodiment 5.

[0099] Next, the configuration of the semiconductor device 100 according to the fifth embodiment will be described with reference to Fig. 14. The semiconductor device 100 according to the fifth embodiment differs from the semiconductor device 100 according to the fourth embodiment mainly in that the bonded surface 55 covers the temperature sensing diode 8, and is substantially the same as the semiconductor device 100 according to the fourth embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the fourth embodiment.

[0100] As shown in FIG. 14, the semiconductor device 100 has a temperature sensing diode 8, an anode pad 12, and a cathode pad 13. In a plan view, the temperature sensing diode 8 is provided between any two of the plurality of diode regions 2. The temperature sensing diode 8 is provided, for example, near the center of the semiconductor device 100. Specifically, in a plan view, the second center 94 may overlap with the temperature sensing diode 8. In a plan view, the center line A may pass through the temperature sensing diode 8. In a plan view, the flat plate portion 49 covers the temperature sensing diode 8. From another perspective, in a plan view, the joined surface 55 (see FIG. 2) covers the temperature sensing diode 8.

[0101] The anode pad 12 is electrically connected to the temperature sensing diode 8. The cathode pad 13 is electrically connected to the temperature sensing diode 8. In plan view, the flat plate portion 49 does not cover either the anode pad 12 or the cathode pad 13. In other words, in plan view, the joined surface 55 (see FIG. 2) is spaced apart from either the anode pad 12 or the cathode pad 13.

[0102] In a plan view, the conductive plate portion 51 may be provided in the first direction 101 with respect to the second center 94. In a plan view, the conductive plate portion 51 may be provided between the second center 94 and the gate pad 7. When the semiconductor device 100 has a plurality of surface electrodes 10, the second center 94 is set to be the center of the smallest rectangular area that surrounds all of the plurality of surface electrodes 10 in a plan view.

[0103] According to the semiconductor device 100 of the fifth embodiment, the bonded surface 55 covers the temperature sensing diode 8. This makes it easier to transfer heat from the temperature sensing diode 8 to the wiring member 50. This improves the heat dissipation properties of the temperature sensing diode 8.

[0104] The temperature sensing diode 8 may be provided along the gate pad 7. The temperature sensing diode 8 may be provided in the first direction 101 with respect to the second center 94.

[0105] Embodiment 6

[0106] Next, the configuration of the semiconductor device 100 according to the sixth embodiment will be described with reference to Fig. 15. The semiconductor device 100 according to the sixth embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that the wiring member 50 has a rising portion 52, and is substantially the same as the semiconductor device 100 according to the first embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the first embodiment. The cross section shown in Fig. 15 corresponds to the cross section shown in Fig. 2.

[0107] 15, the wiring member 50 has a rising portion 52. The rising portion 52 is continuous with the flat plate portion 49. The rising portion 52 is different from the conductive plate portion 51. At the second end portion 82, the rising portion 52 is continuous with the flat plate portion 49. The rising portion 52 is spaced apart from the conductive plate portion 51. The rising portion 52 is inclined with respect to the flat plate portion 49 in a direction from the surface electrode 10 toward the flat plate portion 49. The inclination angle of the rising portion 52 with respect to the flat plate portion 49 is not particularly limited.

[0108] According to the semiconductor device 100 of the sixth embodiment, the wiring member 50 has the rising portion 52. Therefore, the surface area of ​​the wiring member 50 can be increased compared to a case where the wiring member 50 does not have the rising portion 52. This can improve the heat dissipation from the wiring member 50 to the outside of the semiconductor device 100.

[0109] (Modification of the sixth embodiment)

[0110] As shown in FIG. 16, a first uneven portion 53 may be provided on a surface 56 of the flat plate portion 49. Specifically, a plurality of first recesses 75 and a plurality of first protrusions 76 may be provided on the surface 56. Each of the plurality of first protrusions 76 is spaced apart from each other. In the first direction 101, the plurality of first protrusions 76 are provided between the conductive plate portion 51 and the rising portion 52. The first recess 75 is provided between two adjacent first protrusions 76. Each of the plurality of first protrusions 76 extends, for example, along the second direction 102. The size of each of the plurality of first recesses 75 and the plurality of first protrusions 76 is not particularly limited.

[0111] According to the semiconductor device 100 according to the modification of the sixth embodiment, the first uneven portion 53 is provided on the surface 56 of the flat plate portion 49. This can further increase the surface area of ​​the wiring member 50. As a result, the heat dissipation property of the semiconductor device 100 can be further improved.

[0112] Embodiment 7

[0113] Next, the configuration of the semiconductor device 100 according to the seventh embodiment will be described. The semiconductor device 100 according to the seventh embodiment differs from the semiconductor device 100 according to the sixth embodiment mainly in that the flat plate portion 49 has a third protrusion 79, and is substantially the same as the semiconductor device 100 according to the sixth embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the sixth embodiment.

[0114] As shown in FIG. 17, the flat plate portion 49 has a plate-shaped portion 48 and a third convex portion 79. The plate-shaped portion 48 is a portion that constitutes the surface 56, the first end portion 81, and the second end portion 82. The third convex portion 79 is provided in a third direction 103 with respect to the plate-shaped portion 48. The third convex portion 79 is convex along the third direction 103. The plate-shaped portion 48 and the third convex portion 79 constitute the joined surface 55. The third convex portion 79 is in contact with the joining member 60. The bottom surface of the third convex portion 79 may be, for example, flat or convex along the third direction 103. The third convex portion 79 may be spaced apart from the surface electrode 10. In a plan view, the third convex portion 79 is, for example, surrounded by the joining member 60. In a plan view, the third convex portion 79 may cover all of each of the multiple diode regions 2.

[0115] According to the semiconductor device 100 of the seventh embodiment, the flat portion 49 has the third protrusion 79. Therefore, in the process of manufacturing the semiconductor device 100, the third protrusion 79 pushes the pre-solidified bonding members 60 outward along an in-plane direction perpendicular to the third direction 103. This makes it possible to effectively bond the flat portion 49 and the bonding members 60 to each other. As a result, the generation of voids at the boundary between the flat portion 49 and the bonding members 60 is suppressed.

[0116] Embodiment 8

[0117] Next, the configuration of the semiconductor device 100 according to the eighth embodiment will be described with reference to Figures 18 and 19. The semiconductor device 100 according to the eighth embodiment differs from the semiconductor device 100 according to the sixth embodiment mainly in that a through hole 99 is provided in the flat plate portion 49, and is substantially the same as the semiconductor device 100 according to the sixth embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the sixth embodiment.

[0118] 18 and 19, at least one or more through holes 99 are provided in the flat plate portion 49. Specifically, the number of through holes 99 may be one, or may be two or more. The through hole 99 extends along the third direction 103. The through hole 99 penetrates between the front surface 56 and the joined surface 55. A part of the joining member 60 is located in the through hole 99.

[0119] In the process of manufacturing the semiconductor device 100, when the surface electrode 10 and the wiring member 50 are joined using the bonding member 60, the bonding member 60 is heated. As a result, due to thermal expansion of the bonding member 60, pressure is applied from the bonding member 60 to the semiconductor element 30. According to the semiconductor device 100 of the eighth embodiment, at least one through hole 99 is provided in the flat plate portion 49. Therefore, when the surface electrode 10 and the wiring member 50 are joined using the bonding member 60, the bonding member 60 wets and spreads inside the through hole 99. This makes it possible to reduce the pressure applied from the bonding member 60 to the semiconductor element 30 when the surface electrode 10 and the wiring member 50 are joined. As a result, cracking of the semiconductor element 30 can be suppressed.

[0120] Embodiment 9

[0121] Next, the configuration of the semiconductor device 100 according to the ninth embodiment will be described with reference to Fig. 20. The semiconductor device 100 according to the ninth embodiment differs from the semiconductor device 100 according to the sixth embodiment mainly in that the second uneven portion 54 is provided on the joining surface 55, and is substantially the same as the semiconductor device 100 according to the sixth embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the sixth embodiment.

[0122] As shown in FIG. 20, the second uneven portion 54 is provided on the joined surface 55. Specifically, the second recesses 77 and the second protrusions 78 are provided on the joined surface 55. The second protrusions 78 are spaced apart from each other. In the first direction 101, the second protrusions 78 are provided between the conductive plate portion 51 and the rising portion 52. The second recesses 77 are provided between two adjacent second protrusions 78. Each of the second protrusions 78 extends, for example, along the second direction 102. The second uneven portion 54 is in contact with the joining member 60. The size of each of the second recesses 77 and the second protrusions 78 is not particularly limited.

[0123] According to the semiconductor device 100 of the ninth embodiment, the second uneven portion 54 is provided on the joined surface 55. Therefore, due to the anchor effect, it is possible to improve the bonding strength between the surface electrode 10 and the wiring member 50 using the bonding member 60. Specifically, when the surface electrode 10 and the wiring member 50 are joined using the bonding member 60, the molten bonding member 60 enters the second uneven portion 54. This makes it possible to effectively bring the wiring member 50 and the bonding member 60 into close contact with each other. As a result, it is possible to improve the bonding strength between the surface electrode 10 and the wiring member 50.

[0124] In the modified example of the sixth embodiment and the seventh to ninth embodiments, the wiring member 50 has the rising portion 52. However, the configuration of the wiring member 50 is not limited to the above configuration. Specifically, the wiring member 50 does not have to have the rising portion 52.

[0125] The embodiments disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include the meaning equivalent to the claims and all modifications within the scope.

[0126] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) an insulated gate bipolar transistor region; a plurality of diode regions in contact with the insulated gate bipolar transistor region; a surface electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions; a bonding member provided on the surface electrode; a wiring member joined to the surface electrode by the joining member, the insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse conducting insulated gate bipolar transistor; the wiring member has a joined surface in contact with the joining member, In a plan view seen along a direction perpendicular to the front surface electrode, the joined surface covers at least a portion of each of the plurality of diode regions, In the plan view, the plurality of diode regions are A first diode region; a second diode region located in a first direction relative to the first diode region and spaced apart from the first diode region; a third diode region located in a second direction perpendicular to the first direction relative to the first diode region and spaced apart from each of the first diode region and the second diode region. (Appendix 2) The wiring member is A flat plate portion constituting the joined surface; The semiconductor device described in Appendix 1, further comprising a conductive plate portion connected to the flat plate portion and spaced apart from the joining member. (Appendix 3) In the plan view, the first diode region has a rectangular shape, 3. The semiconductor device according to claim 2, wherein a connection portion between the flat plate portion and the conductive plate portion extends along a direction in which a long side of the first diode region extends. (Appendix 4) a gate pad provided in the insulated gate bipolar transistor region in a direction from the insulated gate bipolar transistor region toward the front electrode, and receiving an input of a signal for controlling conduction of the insulated gate bipolar transistor region; the plurality of diode regions includes a fourth diode region and a fifth diode region spaced apart from the fourth diode region; In the plan view, the gate pad is provided between the fourth diode region and the fifth diode region, In the plan view, the bonded surface is spaced from the gate pad, The flat plate portion is a first portion overlapping the fourth diode region in the plan view; a second portion overlapping the fifth diode region in the plan view, 4. The semiconductor device according to claim 2, wherein the second portion is spaced apart from the first portion. (Appendix 5) In the plan view, the gate pad is provided in the first direction with respect to a center of the surface electrode, 5. The semiconductor device according to claim 4, wherein, in the plan view, the conductive plate portion is provided in a direction opposite to the gate pad with respect to a center of the surface electrode. (Appendix 6) the wiring member has a rising portion connected to the flat plate portion and different from the conductive plate portion, 6. The semiconductor device according to claim 2, wherein the raised portion is inclined with respect to the flat portion in a direction from the front surface electrode toward the flat portion. (Appendix 7) The flat portion has a surface opposite the joined surface, 7. The semiconductor device according to claim 2, wherein a first uneven portion is provided on the surface. (Appendix 8) the flat plate portion has a protrusion that is protruding in a direction from the flat plate portion toward the surface electrode, 8. The semiconductor device according to claim 2, wherein the protrusion constitutes a part of the surface to be joined. (Appendix 9) 9. The semiconductor device according to claim 2, wherein at least one through hole is provided in the flat plate portion. (Appendix 10) A second uneven portion is provided on the joining surface, 10. The semiconductor device according to claim 2, wherein the second uneven portion is in contact with the bonding member. (Appendix 11) 3. The semiconductor device according to claim 1, wherein each of the plurality of diode regions has a square shape in the plan view. (Appendix 12) In the plan view, when a minimum rectangular region that surrounds all of the plurality of diode regions is defined as a virtual region, and a virtual line located midway between an outer edge of the virtual region and a center of the virtual region is defined as a boundary line, The virtual area is an outer circumferential area between the outer edge of the virtual area and the boundary line; a central region that is inside the boundary line and is connected to the outer circumferential region, 12. The semiconductor device according to claim 1, wherein, in the plan view, a density of the plurality of diode regions in the central region is lower than a density of the plurality of diode regions in the peripheral region. (Appendix 13) 13. The semiconductor device according to claim 1, wherein, in the plan view, the bonded surface covers each of the plurality of diode regions entirely. (Appendix 14) a termination region in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions; 14. The semiconductor device according to claim 1, further comprising a protective film provided on the termination region. (Appendix 15) a termination region in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions; 14. The semiconductor device according to claim 1, wherein a shortest distance between the termination region and the plurality of diode regions in the planar view is equal to or greater than a thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode. (Appendix 16) 16. The semiconductor device according to claim 1, wherein a shortest distance between an outer edge of the joined surface and the plurality of diode regions in the planar view is equal to or greater than a thickness of the insulated gate bipolar transistor region in a direction perpendicular to the front surface electrode. (Appendix 17) a temperature sensing diode provided between any two of the plurality of diode regions in the plan view; 17. The semiconductor device according to claim 1, wherein, in the plan view, the joined surface covers the temperature sensing diode. [Explanation of symbols]

[0127] 1 Insulated Gate Bipolar Transistor Region (IGBT Region), 2 Diode Region, 4 Termination Region, 5 Termination Protective Film, 6 Protective Film, 7 Gate Pad, 8 Temperature Sensing Diode, 10 Front Surface Electrode, 10a Termination Electrode, 11 Rear Surface Electrode, 12 Anode Pad, 13 Cathode Pad, 20 Column, 21 First Diode Region, 22 Second Diode Region, 23 Third Diode Region, 24 Fourth Diode Region, 25 Fifth Diode Region, 26 Sixth Diode Region, 27 Seventh Diode Region, 28 P-type Anode Layer, 29 N+-type Cathode Layer, 30 Semiconductor Element, 31a First Trench Gate, 31b Second Trench Gate, 31c Third Trench Gate, 32 N+-type Carrier Store Layer, 33 N+-type Source Layer, 34 Interlayer Insulating Film, 35 P-type Base Layer, 36 P-type Collector Layer, 36a P-type Termination Collector Layer, 37 N-type Buffer Layer, 38 p+ type contact layer, 39 tip surface, 41 p type termination well layer, 42 n+ type channel stopper layer, 43 n- type drift layer, 48 plate-like portion, 49 flat plate portion, 50 wiring member, 51 conductive plate portion, 52 rising portion, 53 first uneven portion, 54 second uneven portion, 55 bonded surface, 56 surface, 59 connection portion, 60 bonding member, 61 first portion, 62 second portion, 70 semiconductor substrate, 71 first surface, 72 second surface, 75 first recess, 76 first protrusion, 77 second recess, 78 second protrusion, 79 third protrusion, 80 main body, 81 first end, 82 second end, 91 virtual region, 92 first outer edge, 93 first center, 94 second center, 95 boundary line, 96 outer periphery region, 97 central region, 98 second outer edge, 99 Through hole, 100 semiconductor device, 101 first direction, 102 second direction, 103 third direction, A center line, H thickness, L1 first distance, L2 second distance.

Claims

1. an insulated gate bipolar transistor region; a plurality of diode regions in contact with the insulated gate bipolar transistor region; a surface electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions; a bonding member provided on the surface electrode; a wiring member joined to the surface electrode by the joining member, the insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse conducting insulated gate bipolar transistor; the wiring member has a joined surface in contact with the joining member, In a plan view seen along a direction perpendicular to the front surface electrode, the joined surface covers at least a portion of each of the plurality of diode regions, In the plan view, the plurality of diode regions are A first diode region; a second diode region located in a first direction relative to the first diode region and spaced apart from the first diode region; a third diode region located in a second direction perpendicular to the first direction with respect to the first diode region and spaced apart from each of the first diode region and the second diode region.

2. The wiring member is A flat plate portion constituting the joined surface; The semiconductor device according to claim 1 , further comprising: a conductive plate portion connected to said flat plate portion and spaced apart from said joining member.

3. In the plan view, the first diode region has a rectangular shape, The semiconductor device according to claim 2 , wherein a connection portion between said flat plate portion and said conductive plate portion extends along a direction in which a long side of said first diode region extends.

4. a gate pad provided in the insulated gate bipolar transistor region in a direction from the insulated gate bipolar transistor region toward the front electrode, and receiving an input of a signal for controlling conduction of the insulated gate bipolar transistor region; the plurality of diode regions includes a fourth diode region and a fifth diode region spaced apart from the fourth diode region, In the plan view, the gate pad is provided between the fourth diode region and the fifth diode region, In the plan view, the bonded surface is spaced from the gate pad, The flat plate portion is a first portion overlapping the fourth diode region in the plan view; a second portion overlapping the fifth diode region in the plan view, The semiconductor device according to claim 2 , wherein the second portion is spaced apart from the first portion.

5. In the plan view, the gate pad is provided in the first direction with respect to a center of the surface electrode, The semiconductor device according to claim 4 , wherein the conductive plate portion is provided in a direction opposite to the gate pad with respect to a center of the front surface electrode in the plan view.

6. the wiring member has a rising portion connected to the flat plate portion and different from the conductive plate portion, 4. The semiconductor device according to claim 2, wherein the rising portion is inclined with respect to the flat plate portion in a direction from the front electrode toward the flat plate portion.

7. The flat portion has a surface opposite the joined surface, The semiconductor device according to claim 2 , wherein a first uneven portion is provided on the surface.

8. the flat plate portion has a protrusion that is protruding in a direction from the flat plate portion toward the surface electrode, 4. The semiconductor device according to claim 2, wherein the protrusion constitutes a part of the surface to be joined.

9. The semiconductor device according to claim 2 , wherein the flat plate portion is provided with at least one through hole.

10. A second uneven portion is provided on the joining surface, The semiconductor device according to claim 2 , wherein the second uneven portion is in contact with the joining member.

11. 3. The semiconductor device according to claim 1, wherein each of the plurality of diode regions has a square shape in the plan view.

12. In the plan view, when a minimum rectangular region that surrounds all of the plurality of diode regions is defined as a virtual region, and a virtual line located midway between an outer edge of the virtual region and a center of the virtual region is defined as a boundary line, The virtual area is an outer circumferential area between the outer edge of the virtual area and the boundary line; a central region that is inside the boundary line and is connected to the outer circumferential region, 4 . The semiconductor device according to claim 1 , wherein in the plan view, a density of the plurality of diode regions in the central region is lower than a density of the plurality of diode regions in the peripheral region.

13. The semiconductor device according to claim 1 , wherein the bonded surface covers an entirety of each of the plurality of diode regions in the plan view.

14. a termination region in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions; The semiconductor device according to claim 1 , further comprising a protective film provided on said termination region.

15. a termination region in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions; 4. The semiconductor device according to claim 1, wherein a shortest distance between the termination region and the plurality of diode regions in the planar view is equal to or greater than a thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

16. 4. The semiconductor device according to claim 1, wherein a shortest distance between an outer edge of the joined surface and the plurality of diode regions in the plan view is equal to or greater than a thickness of the insulated gate bipolar transistor region in a direction perpendicular to the front surface electrode.

17. a temperature sensing diode provided between any two of the plurality of diode regions in the plan view, The semiconductor device according to claim 1 , wherein the joining surface covers the temperature sensing diode in the plan view.

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