Semiconductor device

Abstract

To provide a semiconductor device capable of improving short-circuit withstand capability.SOLUTION: A semiconductor manufacturing equipment of the present disclosure is configured to include: a semiconductor substrate with semiconductor elements formed on a surface; a surface electrode formed on the surface and connected to the semiconductor elements; a metal film formed on the surface electrode; a suppression film formed on the surface electrode to inhibit the spread of solder applied onto the metal film; and a thermal conductive film formed closer to an outer peripheral side than the metal film and the suppression film on the surface electrode, thicker than the metal film and having thermal conductivity higher than that of the suppression film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] A technique has been disclosed in which the end of a surface electrode formed on a conductive region of a semiconductor device is covered with a protective film, and the surface electrode is joined to an external electrode by soldering (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4640345 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the protective film has low thermal conductivity, the overlapping area between the protective film and the conductive area will heat up due to an overload such as a short circuit withstand test, which can reduce the short circuit withstand capability in the overlapping area.

[0005] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device capable of improving short-circuit resistance. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a semiconductor substrate having a semiconductor element formed on its surface, a surface electrode formed on the surface and connected to the semiconductor element, a metal film formed on the surface electrode, an inhibitor film formed on the surface electrode and inhibiting the spreading of solder applied to the metal film, and a thermally conductive film formed on the surface electrode on the outer periphery of the metal film and the inhibitor film, having a thickness greater than that of the metal film and a thermal conductivity greater than that of the inhibitor film. Effect of the Invention

[0007] According to the present disclosure, the short circuit resistance of a semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a top view showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 3] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. [Figure 4] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present disclosure. [Diagram 5] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 6] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 7] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 8] FIG. 13 is a top view showing a configuration of a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 9] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to an eighth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] First embodiment

[0010] 1 is a top view showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. A first region 101 is provided in the center of a semiconductor device 100. The first region 101 is a region where soldering is performed.

[0011] The second region 102 surrounds the first region 101. The second region 102 is a region that suppresses the spread of the solder.

[0012] A third region 103 surrounds the second region 102. The third region 103 is a region that improves short circuit withstand capability.

[0013] The fourth region 104 surrounds the third region 103. A gate pad is formed in a fifth region 105 at a corner of the semiconductor device 100. The first region 101, the second region 102, the third region 103, and the fifth region 105 are located inside a conductive region 111. The fourth region 104 covers the outer periphery of the conductive region 111 and the outside of the conductive region 111.

[0014] 2 is a cross-sectional view showing a configuration of the semiconductor device according to the first embodiment of the present disclosure, and is an enlarged view of a portion of the cross section of the semiconductor device 100 shown in FIG.

[0015] The semiconductor device 100 includes a semiconductor substrate 1. The semiconductor substrate 1 is made of, for example, Si. A back surface electrode 3 is connected to the back surface of the semiconductor substrate 1.

[0016] In addition, a semiconductor element is formed on the surface of the semiconductor substrate 1. The semiconductor element is, for example, an IGBT. Note that the conductive region 111 shown in FIG.

[0017] The semiconductor substrate 1 may be made of a material having a larger band gap than Si. That is, the semiconductor element may be made of a wide band gap semiconductor. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride material, or diamond.

[0018] A surface electrode 2 is formed on the surface of the semiconductor substrate 1 above the semiconductor element. The surface electrode 2 is made of, for example, AlSi. The surface electrode 2 is connected to the semiconductor element.

[0019] A metal film 21 is formed on the center of the surface electrode 2. The metal film 21 is configured to be solderable, and is, for example, a metal film containing Ni or Au. The metal film 21 may be formed, for example, by a plating method or a sputtering method. The metal film 21 allows the surface electrode 2 and an external electrode to be directly joined with solder. The first region 101 shown in FIG. 1 is a region where the metal film 21 is formed and where solder can be applied.

[0020] In addition, an inhibitory film 22 is formed on the surface electrode 2 so as to surround the outer periphery of the metal film 21 in a plan view. The inhibitory film 22 is formed of a material having poor solder wettability compared to the metal film 21, for example, a non-metallic material. The inhibitory film 22 inhibits the spread of the solder applied on the metal film 21. The second region 102 shown in FIG. 1 is the region where the inhibitory film 22 is formed.

[0021] A thermally conductive film 23 is formed on the surface electrode 2 on the outer periphery side of the metal film 21 and the suppression film 22. The thermally conductive film 23 is thicker than the metal film 21 and is formed of a material having a higher thermal conductivity than the suppression film 22. The thermally conductive film 23 is a metal film containing, for example, Ni or Au. The third region 103 shown in FIG. 1 is a region where the thermally conductive film 23 is formed.

[0022] Here, the heat dissipation path from the third region 103 is considered. In the absence of the thermally conductive film 23, the main heat dissipation path for the heat generated in the conductive region 111 is the first path via the surface electrode 2, the metal film 21, the solder, and the external electrode. However, the semiconductor device 100 of the present disclosure has the thermally conductive film 23. Therefore, the heat dissipation path for the heat generated in the conductive region 111 is the second path via the surface electrode 2, the thermally conductive film 23, and a module sealing material (not shown) in addition to the first path. In other words, the thermally conductive film 23 increases the number of heat dissipation paths, so that heat generation due to overload can be suppressed and short circuit resistance can be improved. Note that, as a test involving heat generation due to overload, a test in which a short pulse is applied, such as a short circuit breakdown test, can be exemplified.

[0023] An insulating film 7 is formed on the surface of the semiconductor substrate 1 in an outer peripheral region of the conductive region 111. A gate wiring 6 is disposed on the insulating film 7. A nitride film 4 is formed on the gate wiring 6. The nitride film 4 is made of, for example, silicon nitride. The nitride film 4 is a film that has adhesion to the semiconductor and insulating properties for suppressing discharge on the fourth region 104.

[0024] The end of the surface electrode 2 and the nitride film 4 are covered with a protective film 5. That is, the protective film 5 covers the end of the surface electrode 2 on the outer periphery side of the thermally conductive film 23. The protective film 5 is formed of, for example, polyimide. The protective film 5 is a film having insulation properties for suppressing discharge, strength for protecting the semiconductor device from stress and temperature cycles after module mounting, heat resistance, and a low thermal shrinkage rate. In addition, the protective film 5 is often thicker than the gate wiring 6 in order to prevent stress from concentrating in an area with a difference in thickness by ensuring flatness.

[0025] 1 is a region where a protective film 5 is formed. The nitride film 4 and the protective film 5 are formed to protect the fourth region 104 by maintaining the withstand voltage, improving the moisture resistance, and enabling stress relaxation after the module is mounted. In addition, the nitride film 4 and the protective film 5 are transparent. This allows foreign matter or pattern formation defects on the fourth region 104 to be detected by visual inspection from above.

[0026] Although the case where the gate wiring 6 is located in the fourth region 104, which is a non-conductive region, has been shown here, a termination region or a wiring portion or the like may also be disposed therein.

[0027] Embodiment 2 3 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device 120 according to the second embodiment differs from the semiconductor device 100 in that an inhibiting film 22a formed in the second region 102a is made of the same material as the protective film 5.

[0028] Since the suppression film 22a is made of the same material as the protective film 5, it can be formed at the same time as the protective film 5. That is, the number of steps can be reduced compared to the first embodiment.

[0029] In addition, when the thermal conductivity of the protective film 5 is low, the thermal conductivity of the suppression film 22a is also low, and therefore the short circuit resistance in the second region 102a may decrease. However, since the second region 102a is located between the first region 101 and the third region 103, which have high heat dissipation properties, it is considered that the heat dissipation paths are dispersed. This makes it possible to suppress the decrease in the short circuit resistance.

[0030] 3 shows the case where the second region 102a has the same width as the third region 103, the reduction in short circuit resistance may be further suppressed by making the area of ​​the second region 102a smaller than the area of ​​the third region 103. Theoretically, it is considered that the width of the second region 102a can be set to the minimum dimension at which the protective film 5 can be disposed.

[0031] Third embodiment 4 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present disclosure. A semiconductor device 140 according to the third embodiment differs from the semiconductor device 100 in that a thermally conductive film formed in the third region 103a has a two-layer structure.

[0032] The semiconductor device 140 includes a thermally conductive film 23a. The thermally conductive film 23a is a film having the same characteristics as the thermally conductive film 23. A coating film 24 is formed on the thermally conductive film 23a. The coating film 24 is formed of a material different from that of the thermally conductive film 23a. The coating film 24 may have a configuration that does not prevent heat dissipation from the thermally conductive film 23a, for example. The coating film 24 may also be formed of a material that is difficult to increase in thickness or a material with low thermal conductivity, for example.

[0033] In the manufacturing process of the semiconductor device 100, the material of the film on the outermost surface of the third region 103 may be limited. If the limited material is a material that is difficult to increase in thickness or a material with low thermal conductivity, it becomes difficult to form the thermally conductive film 23.

[0034] However, in the semiconductor device 140, the thermally conductive film formed in the third region 103a has a two-layer structure of the thermally conductive film 23a and the coating film 24. Therefore, the coating film 24 satisfies the material restrictions in the manufacturing process, and the thermally conductive film 23a can solve the problem of the present disclosure.

[0035] Furthermore, the coating film 24 may be formed so as to fill the difference in thickness between the protective film 5 and the thermally conductive film 23a. This ensures flatness of the entire film, thereby preventing stress from concentrating in areas with thickness differences.

[0036] Alternatively, the thermally conductive film formed in the third region 103a may be two-layered by forming the thermally conductive film 23a from the same material as the surface electrode 2 and the coating film 24 from the same material as the metal film 21. In this case, the types of materials and the number of processes required to manufacture the semiconductor device 140 can be reduced.

[0037] Fourth embodiment 5 is a cross-sectional view showing a configuration of a semiconductor device according to embodiment 4 of the present disclosure. A semiconductor device 160 according to embodiment 4 differs from the semiconductor device 100 in that the thermal conduction film 23b formed in the third region 103b is thicker than the suppression film 22.

[0038] The semiconductor device 160 includes a thermally conductive film 23b. The thermally conductive film 23b is thicker than the metal film 21 and the suppression film 22, and is made of a material having a higher thermal conductivity than the suppression film 22. Since the thermally conductive film 23b is thicker than the thermally conductive film 23, the thermal capacity is increased. This can further enhance the effect of improving the short circuit resistance.

[0039] Fifth embodiment 6 is a cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present disclosure. A semiconductor device 180 according to the fifth embodiment differs from the semiconductor device 100 in that the material of the thermally conductive film 23c formed in the third region 103c is the same as that of the other films.

[0040] The semiconductor device 180 includes a thermally conductive film 23c. The thermally conductive film 23c is made of the same material as the front electrode 2, for example, AlSi. This allows the number of types of materials required to manufacture the semiconductor device 180 to be reduced.

[0041] Although the example in which the thermally conductive film 23c is made of the same material as the surface electrode 2 has been shown here, it may be made of the same material as the metal film 21 or the nitride film 4. In this case, it is possible to reduce the types of materials and the number of processes required to manufacture the semiconductor device 180.

[0042] Sixth embodiment 7 is a cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment of the present disclosure. A semiconductor device 200 according to the sixth embodiment differs from the semiconductor device 100 in that an inhibiting film 22a is formed on the outer periphery region of the metal film 21a.

[0043] In the semiconductor device 200, a metal film 21a is formed on the surface electrode 2. The metal film 21a is configured to be solderable, and is a metal film containing, for example, Ni or Au. The metal film 21a may be formed by, for example, a plating method or a sputtering method. The metal film 21a allows the surface electrode 2 and an external electrode to be directly joined by solder.

[0044] An inhibitory film 22a is formed on the outer peripheral region of the metal film 21a. The inhibitory film 22a is made of a material with poor solder wettability, for example, a nonmetallic material. The inhibitory film 22a can inhibit the spread of the solder applied on the metal film 21.

[0045] As described above, the suppression film 22a is formed on the outer peripheral region of the metal film 21a. That is, the metal film 21a having high thermal conductivity is also disposed in the second region 102b. This can further enhance the effect of improving the short circuit resistance.

[0046] Seventh embodiment 8 is a top view showing a configuration of a semiconductor device according to a seventh embodiment of the present disclosure. A semiconductor device 220 according to the seventh embodiment differs from the semiconductor device 100 in that the third region 103d is disposed only in a part of the inner peripheral region of the fourth region 104.

[0047] The semiconductor device 220 includes a third region 103d. The third region 103d is a region that improves short circuit resistance by forming a thermally conductive film 23 on the surface layer. The third region 103d is disposed in the center of each side of a rectangle that forms the inner periphery of the fourth region 104 that is formed in a rectangular frame shape in a plan view. That is, the thermally conductive film 23 is disposed near the center of each side of a rectangle that forms the inner periphery of the protective film 5 that is formed in a rectangular frame shape in a plan view.

[0048] In this way, the third region 103d is selectively disposed in a location that is likely to generate heat, for example, near the center of the conductive region 111. This allows the effect of the third region 103d to be obtained more efficiently, improving the degree of freedom in layout.

[0049] When the resistance component of the gate wiring 6 is taken into consideration, the responsiveness to the on / off of the gate voltage is lower in a location farther from the fifth region 105, which is the gate pad. In other words, the timing at which the gate voltage is turned off becomes slower, and this may cause the location to easily generate heat. For this reason, the third region 103d may be disposed in a location farther from the fifth region 105.

[0050] Embodiment 8

[0051] 9 is a cross-sectional view showing a configuration of a semiconductor device according to an eighth embodiment of the present disclosure. A semiconductor device 240 according to the eighth embodiment differs from the semiconductor device 100 in that the semiconductor element is an RC-IGBT.

[0052] The semiconductor device 240 includes a p-type semiconductor region 31 on the back surface side of the semiconductor substrate 1. The p-type semiconductor region 31 functions as a collector of the IGBT in a region where the IGBT is formed on the front surface of the semiconductor substrate 1. This region where the IGBT is formed is referred to as a conductive region 111a.

[0053] The semiconductor device 240 also includes an n-type semiconductor region 32 on the back surface side of the semiconductor substrate 1. The n-type semiconductor region 32 functions as an anode of the diode in a region where the diode is formed on the front surface of the semiconductor substrate 1. The region where the diode is formed is referred to as a conductive region 111b.

[0054] As described above, the conductive region 111a functions as an IGBT, and the conductive region 111b functions as a diode. That is, the conductive regions 111a and 111b operate as an RC-IGBT. This makes it possible to reduce the chip mounting area and improve the reliability of the semiconductor device.

[0055] Below, aspects of the present disclosure are summarized as appendices.

[0056] (Appendix 1) A semiconductor substrate having a semiconductor element formed on a surface thereof; a surface electrode formed on the surface and connected to the semiconductor element; a metal film formed on the surface electrode; an inhibition film formed on the surface electrode and inhibiting the spread of the solder applied on the metal film; a thermally conductive film that is formed on the surface electrode and is located closer to the outer periphery than the metal film and the suppression film, the thermally conductive film being thicker than the metal film and having a higher thermal conductivity than the suppression film; A semiconductor device comprising: (Appendix 2) a protective film covering an end of the surface electrode on an outer circumferential side of the thermal conductive film; The suppression film is formed of the same material as the protective film. 2. The semiconductor device according to claim 1. (Appendix 3) The heat transfer device further includes a coating film formed on the heat transfer film and made of a material different from that of the heat transfer film. 3. The semiconductor device according to claim 1, (Appendix 4) The thermally conductive film is thicker than the suppression film. 4. The semiconductor device according to claim 1 , (Appendix 5) The thermally conductive film is made of the same material as the surface electrode. 5. The semiconductor device according to claim 1 , (Appendix 6) The suppression film is formed on the surface electrode so as to surround the outer periphery of the metal film in a plan view. 6. The semiconductor device according to claim 1 , (Appendix 7) The suppression film is formed on the outer peripheral region of the metal film. 6. The semiconductor device according to claim 1 , (Appendix 8) The protective film is formed in a rectangular frame shape in a plan view, The thermally conductive film is disposed at the center of each side of a rectangle that forms the inner periphery of the protective film. 3. The semiconductor device according to claim 2. (Appendix 9) The semiconductor device is an RC-IGBT. 9. The semiconductor device according to claim 1 , (Appendix 10) The semiconductor element is formed of a wide band gap semiconductor. 10. The semiconductor device according to claim 1 , (Appendix 11) The wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. 11. The semiconductor device according to claim 10. [Explanation of symbols]

[0057] 1. Semiconductor substrate 2 surface electrode 5 Protective film 21 Metal Film 21a Metal film 22 Inhibition membrane 22a Inhibition membrane 23 Thermal conductive membrane 23a Thermal conductive membrane 23b Thermal conductive membrane 23c Thermal conductive membrane 24 Coating membrane 100 Semiconductor device 120 Semiconductor device 140 Semiconductor devices 160 Semiconductor devices 180 Semiconductor Devices 200 Semiconductor device 220 Semiconductor Devices 240 Semiconductor Devices

Claims

1. A semiconductor substrate having a semiconductor element formed on a surface thereof; a surface electrode formed on the surface and connected to the semiconductor element; a metal film formed on the surface electrode; an inhibition film formed on the surface electrode and inhibiting the spread of the solder applied on the metal film; a thermally conductive film that is formed on the surface electrode and is located closer to the outer periphery than the metal film and the suppression film, the thermally conductive film being thicker than the metal film and having a higher thermal conductivity than the suppression film; A semiconductor device comprising:

2. a protective film covering an end of the surface electrode on an outer circumferential side of the thermal conductive film; The suppression film is formed of the same material as the protective film. The semiconductor device according to claim 1 .

3. The heat transfer device further includes a coating film formed on the heat transfer film and made of a material different from that of the heat transfer film. The semiconductor device according to claim 1 .

4. The thermally conductive film is thicker than the suppression film. The semiconductor device according to claim 1 .

5. The thermally conductive film is made of the same material as the surface electrode. The semiconductor device according to claim 1 .

6. The suppression film is formed on the surface electrode so as to surround the outer periphery of the metal film in a plan view. The semiconductor device according to claim 1 .

7. The suppression film is formed on the outer peripheral region of the metal film. The semiconductor device according to claim 1 .

8. The protective film is formed in a rectangular frame shape in a plan view, The thermally conductive film is disposed at the center of each side of a rectangle that forms the inner periphery of the protective film. The semiconductor device according to claim 2 .

9. The semiconductor element is an RC-IGBT. The semiconductor device according to claim 1 .

10. The semiconductor element is formed of a wide band gap semiconductor. The semiconductor device according to claim 1 .

11. The wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. The semiconductor device according to claim 10.

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