Laminated ceramic capacitor

Abstract

To provide a laminated ceramic capacitor having a high proof pressure reliability.SOLUTION: A laminated ceramic capacitor 1 comprises: a first external electrode 3A arranged on a first end surface of a laminated body 2; and a second external electrode 3B arranged on a second end surface of the laminated body 2. The laminated body 2 comprises: an internal part 11 having both ends of a lamination direction which are internal electrode layers; an outer layer part 22 that is positioned between the internal part 11 and a first main surface and a second main surface; and a side margin part 2121 that coats the internal part 11 and the outer layer part 22 from a side surface. A difference between a particle diameter of a grain contained in the internal part 11 and a particle diameter of a grain contained in at least one of the outer layer part 22 and a side margin part 21 is 100 nm or less. The outer layer part 22 and the side margin part 21 contain Si and Ti. A concentration of Si against Ti of at least one of the outer layer part 22 and the side margin part 21 is 0.5 mol% or less.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] There is known a multilayer ceramic capacitor that is manufactured by stacking a plurality of dielectric layers and a plurality of internal electrode layers alternately and then firing them. In recent years, such multilayer ceramic capacitors have been made smaller and have larger capacitance. In order to achieve a smaller size and larger capacitance, the internal electrode layers and the internal dielectric layers are being made thinner (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-082779 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the internal dielectric layer is made thinner, the contact area between the internal dielectric layer and the dielectric layer in contact with the internal dielectric layer is reduced, making the internal dielectric layer more susceptible to peeling, which may result in a decrease in the breakdown voltage and a decrease in the withstand voltage reliability.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor having high voltage resistance reliability. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate having a first main surface and a second main surface opposed to each other in a lamination direction, a first end surface and a second end surface opposed to each other in a length direction, and a first side surface and a second side surface opposed to each other in a width direction, a first external electrode arranged on the first end surface of the laminate, and a second external electrode arranged on a second end surface of the laminate, the laminate comprising: an inner layer portion having both ends in the lamination direction which are internal electrode layers, an outer layer portion located between the inner layer portion and the first main surface and the second main surface, and a side margin portion covering the inner layer portion and the outer layer portion from side surfaces, wherein a difference between a grain size of grains contained in the inner layer portion and a grain size of grains contained in at least one of the outer layer portion and the side margin portion is 100 nm or less, the outer layer portion and the side margin portion contain Si and Ti, and a concentration of Si relative to Ti in at least one of the outer layer portion and the side margin portion is 0.5 mol % or less. Effect of the Invention

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor having high voltage resistance reliability. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. [Diagram 2] 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 in FIG. [Diagram 3] 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 in FIG. [Figure 4] 1 is an example of an enlarged image of a cross section of an exposed inner layer portion 11. [Diagram 5] FIG. 4 is an enlarged view of the circled portion P in FIG. [Figure 6] 3 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1. [Figure 7] 2A to 2C are diagrams illustrating a method for manufacturing the multilayer ceramic capacitor 1. [Figure 8] 1 is a table showing values ​​of the dielectric breakdown voltage of multilayer ceramic capacitors 1 containing grains g of different particle sizes. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (Multilayer ceramic capacitor 1) Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1 of the embodiment. Fig. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 in Fig. 1.

[0010] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 in which an internal dielectric layer 14 and an internal electrode layer 15 are laminated, and an outer dielectric layer 20 that covers the inner layer portion 11.

[0011] (Dimensions of multilayer ceramic capacitor 1) The dimensions of the multilayer ceramic capacitor 1 are, for example, 0.1 mm to 0.5 mm in the width direction W, 0.1 mm to 0.5 mm in the thickness direction, and 0.05 mm to 1.0 mm in the length direction L.

[0012] In the following description, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 as the length direction L. The direction in which the internal dielectric layers 14 and the internal electrode layers 15 are stacked refers to the stacking direction T. The direction intersecting both the length direction L and the stacking direction T refers to the width direction W. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T. In the multilayer ceramic capacitor 1 of the embodiment, the length direction L is longer than the width direction W and the stacking direction T, but is not limited to this, and the length direction L dimension does not have to be longer than the width direction W and the stacking direction T.

[0013] In the following description, among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T will be referred to as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W will be referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L will be referred to as the first end surface C1 and the second end surface C2. Note that when it is not necessary to distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A, when it is not necessary to distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B, and when it is not necessary to distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0014] (Laminate 2) The laminate 2 includes a laminate chip 10 and side margin portions 21 arranged on both sides in the width direction W of the laminate chip 10. The laminate chip 10 includes an inner layer portion 11 in which an internal dielectric layer 14 and an internal electrode layer 15 are laminated, and two outer layer portions 22 arranged on both sides of the inner layer portion 11 in the stacking direction T. In the embodiment, the outer layer portions 22 and the side margin portions 21 together form an outer dielectric layer 20 that covers the inner layer portion 11.

[0015] The laminate 2 has a substantially rectangular parallelepiped shape, but it is preferable that the corners R1 and ridges R2 are rounded. The corners R1 are the intersections of the main surface A, the side surface B, and the end surface C. The ridges R2 are the intersections of two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C.

[0016] (Inner layer 11) The internal layer portion 11 is a portion in which internal dielectric layers 14 and internal electrode layers 15 are alternately laminated along the lamination direction T, and in the embodiment, both ends of the internal layer portion 11 in the lamination direction T are internal electrode layers 15. That is, the internal layer portion 11 is a portion between the internal electrode layers 15, in which the internal dielectric layers 14 and the internal electrode layers 15 are alternately laminated therebetween.

[0017] (Internal electrode layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. In addition, when there is no need to particularly distinguish between the first internal electrode layers 15A and the second internal electrode layers 15B, they will be collectively referred to as the internal electrode layers 15.

[0018] The internal electrode layer 15 contains, for example, Ni (nickel) as a main component, and may further contain dielectric particles of the same composition as the ceramics contained in the internal dielectric layer 14. S (sulfur) is segregated at the interface with the internal dielectric layer 14. Also, Sn (tin) may be arranged at the interface between the internal electrode layer 15 and the internal dielectric layer 14. In this case, Sn may be in a layered form or may be scattered. Also, Sn may be dissolved in the internal electrode layer 15 side, or may be dissolved in the particles of the dielectric layer side.

[0019] The first internal electrode layer 15A includes a first opposing portion 15Aa facing the second internal electrode layer 15B, and a first lead portion 15Ab drawn from the first opposing portion 15Aa to the first end face C1 side. An end of the first lead portion 15Ab is exposed to the first end face C1 and is electrically connected to the first external electrode 3A described later. The second internal electrode layer 15B includes a second opposing portion 15Ba facing the first internal electrode layer 15A, and a second lead portion 15Bb drawn from the second opposing portion 15Ba to the second end face C2. An end of the second lead portion 15Bb is electrically connected to the second external electrode 3B described later. In the internal electrode layer 15, electric charges are accumulated between the first opposing portion 15Aa of the first internal electrode layer 15A and the second opposing portion 15Ba of the second internal electrode layer 15B, sandwiching the internal dielectric layer 14, and the internal electrode layer 15 functions as a capacitor.

[0020] 3, in a WT cross section, which is a cross section in the width direction W and stacking direction T passing through the center of the laminate 2, the positional deviation d in the stacking direction T of the ends in the width direction W of two first internal electrode layers 15A and second internal electrode layers 15B adjacent to each other vertically in the stacking direction T is preferably 5 μm or less, and more preferably 0.5 μm or less. In other words, the ends in the width direction W of the first internal electrode layer 15A and second internal electrode layer 15B adjacent to each other vertically in the stacking direction T are at approximately the same position in the width direction W, and the positions of the ends are aligned in the stacking direction T.

[0021] The number of the internal electrode layers 15 is preferably 10 or more and 1000 or less.

[0022] The thickness of the internal electrode layer 15 is preferably 0.3 μm or more and 0.4 μm or less, and more preferably 0.3 μm or more and 0.35 μm or less.

[0023] The thickness of the internal electrode layer 15 is measured, for example, as follows. First, the LT cross section passing through the center of the multilayer ceramic capacitor 1 is polished to expose the internal layer portion 11. If necessary, the exposed cross section at the observation position is etched to remove the conductive layer stretched by polishing.

[0024] 4 is an example of an enlarged image of the cross section of the exposed inner layer portion 11. In the illustrated enlarged image, for example, a number of straight lines La, Lb, Lc, Ld, and Le extending in the lamination direction T are drawn at equal intervals with a pitch S. The pitch S is preferably about 5 to 10 times the thickness of the internal electrode layer 15 to be measured, and for example, when measuring an internal electrode layer 15 with a thickness of about 1 μm, the pitch S is set to 5 μm.

[0025] Next, on each of the five straight lines La, Lb, Lc, Ld, and Le, the thicknesses da, db, dc, dd, and de of the internal electrode layer 15 are measured. However, if the internal electrode layer 15 is missing on the straight lines La, Lb, Lc, Ld, and Le and the internal dielectric layers 14 sandwiching the internal electrode layer 15 are connected to each other, or if the enlarged view of the measurement position is unclear, a new straight line is drawn and the thickness of the internal electrode layer 15 is measured.

[0026] In addition, when the number of laminations of the internal electrode layers 15 is less than five layers, the thicknesses of all the internal electrode layers 15 are measured by the above method, and the average value is the average thickness of the multiple internal electrode layers 15. The thickness of the internal dielectric layer 14 can also be measured in the same manner as the internal electrode layers 15.

[0027] (internal dielectric layer 14) The internal dielectric layer 14 is, for example, a dielectric ceramic containing Ba and Ti components, and contains Si. In addition, a component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, which is contained in a smaller amount than the main component, may be added to these components. The molar ratio of Si to Ti in the internal dielectric layer 14 is 0.8 mol% or more and 1.4 mol% or less in the embodiment, but is not limited thereto. The Si content can be calculated by TEM analysis.

[0028] The internal dielectric layer 14 also includes a plurality of grains (particulate matter) 14g. Fig. 5 is an enlarged view of the circled portion P in Fig. 3. The grains 14g are barium titanate ceramics such as perovskite-type compounds containing Ba and Ti, and contain Si and other auxiliary components. The auxiliary components are at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y. The grain size of the grains 14g included in the internal dielectric layer 14 is 140 nm or more and 270 nm or less.

[0029] (Method of measuring particle size) The grain size of the grain 14g of the internal dielectric layer 14 is the grain size at the center in the width direction W and the center in the length direction L. The grain size of the grain 22g of the outer layer portion 22 described later is the grain size at the center in the width direction W and the center in the length direction L, and the grain size of the grain 21g of the side margin portion 21 is the grain size at the center in the width direction W and the center in the stacking direction T. When the side margin portion 21 is a multi-layered portion, it is divided into multiple regions of 20 nm each from the side surface B side in the width direction W, and the area of ​​each grain 21g in each region is measured and converted into a circle equivalent diameter, and the average grain size in each region is the grain size of each region. For a region less than 20 nm, the average grain size in the region less than 20 nm is the grain size of that region. The grain size of the grain 21g of the entire side margin portion 21 is the grain size obtained by further averaging the average grain sizes of each region. Hereinafter, when there is no need to distinguish between the grains 14g of the inner dielectric layer 14, the grains 22g of the outer layer portion 22, and the grains 21g of the side margin portion 21, they will be described as grains g.

[0030] The measurement of each grain size can be performed using a transmission electron microscope (TEM). For example, the area of ​​each grain g within a 10 μm × 10 μm field of view is measured, the circle-equivalent diameter of each grain g is calculated, and the average of the circle-equivalent diameters is taken as the grain size.

[0031] (Number of inner dielectric layers 14) The total number of the internal dielectric layers 14 and the external layers 22 is preferably 100 or more and 2000 or less.

[0032] (Thickness of the inner dielectric layer 14) The thickness of the internal dielectric layer 14 is preferably 0.4 μm or more and 0.5 μm or less, and more preferably 0.4 μm or more and 0.45 μm or less. As described above, the thickness of the internal dielectric layer 14 can be obtained by measuring and averaging the thicknesses Da, Db, Dc, Dd, and De of the internal dielectric layer 14 on each of the five straight lines La, Lb, Lc, Ld, and Le, like the internal electrode layer 15.

[0033] (Outer dielectric layer 20) The outer dielectric layer 20 covering the inner layer portion 11 includes an outer layer portion 22 and a side margin portion 21. The outer dielectric layer 20 is made of the same material as the inner dielectric layer 14, and includes a plurality of grains 22g and grains 21g, respectively. However, the molar ratio of Si to Ti in the outer dielectric layer 20 is lower than that of the inner dielectric layer 14, and is 0.8 mol % or less, and preferably 0.5 mol % or less. The outer dielectric layer 20 also contains Ni.

[0034] The grain size of the grains g contained in the internal dielectric layer 14 and the external dielectric layer 20 is 140 nm or more and 270 nm or less. The average grain size of the grains 14g contained in the internal dielectric layer 14 and the average grain size of the grains 22g and grains 21g contained in the external dielectric layer 20 are substantially equal to each other, and the difference in grain size is 100 nm or less. Moreover, the difference in percentage between the average grain size of the grains 14g contained in the internal dielectric layer 14 and the average grain size of the grains 22g and grains 21g contained in the external dielectric layer 20 is within 36%.

[0035] (Outer layer part 22) The outer layer portions 22 are located on both main surface A sides of the laminate 2, and are dielectric layers located between the main surface A and the internal electrode layer 15 closest to the main surface A.

[0036] (Side margin part 21) The side margin portions 21 are disposed on both side surfaces B of the laminate chip 10, i.e., on both side surfaces B of the outer layer portion 22 and the inner layer portion 11, and cover the side surfaces B of the outer layer portion 22 and the inner layer portion 11. The side margin portions 21 are areas of a certain width on the side surfaces B of the laminate chip 10.

[0037] The side margin portion 21 of the embodiment has a two-layer structure consisting of an outer layer 21a located on the outside and an inner layer 21b located on the internal electrode layer 15 side. However, the present invention is not limited to this, and the side margin portion 21 may have one layer or two or more layers. When the side margin portion 21 has multiple layers, the fact that it is multiple layers can be confirmed in the dark field of an optical microscope, and can also be determined by additives that segregate between layers. The inner layer 21b of the embodiment has a thickness of, for example, about 1 / 10 of the outer layer 21a, which is considerably thinner than the outer layer 21a.

[0038] As described above for the outer dielectric layer 20, the molar ratio of Si to Ti in the side margin portion 21, averaged as a whole, is less than that of the inner dielectric layer 14, being 0.8 mol% or less, and preferably 0.5 mol% or less. The Si content in the entire side margin portion 21 may be determined by calculating the Si contents of the outer layer 21a and the inner layer 21b separately and then adding them up.

[0039] When the side margin portion 21 has two layers, the molar ratio of Si to Ti in the inner layer 21b is smaller than the molar ratio of Si to Ti in the outer layer 21a. When the side margin portion 21 has multiple layers, if the outermost side margin portion is the outer layer 21a and the innermost side margin portion is the inner layer 21b, the molar ratio of Si to Ti in the inner layer 21b is smaller than the molar ratio of Si to Ti in the outer layer 21a. Specifically, the molar ratio of Si to Ti in the inner layer 21b is 0.01 to 0.1 mol%, and preferably is approximately zero. The molar ratio of Si to Ti in the outer layer 21a is 0.8 mol% or less, and preferably 0.5 mol% or less.

[0040] Moreover, in the side margin portion 21, the grain size of the dielectric material constituting the side margin portion 21 decreases from the inner layer toward the outer side.

[0041] (External electrode 3) The external electrodes 3 include a first external electrode 3A provided on a first end face C1 of the laminate 2, and a second external electrode 3B provided on a second end face C2 of the laminate 2. When there is no need to particularly distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively described as the external electrode 3. The external electrode 3 covers not only the end face C, but also a portion of the main face A and the side face B on the end face C side.

[0042] As described above, the end of the first lead portion 15Ab of the first internal electrode layer 15A is exposed to the first end face C1 and is electrically connected to the first external electrode 3A. Moreover, the end of the second lead portion 15Bb of the second internal electrode layer 15B is exposed to the second end face C2 and is electrically connected to the second external electrode 3B. This results in a structure in which a plurality of capacitor elements are electrically connected in parallel between the first external electrode 3A and the second external electrode 3B.

[0043] In this embodiment, the external electrode 3 includes a base electrode layer 30 and a plating layer 31 disposed on the base electrode layer 30 .

[0044] (Base electrode layer 30) The base electrode layer 30 includes at least one layer selected from a baked layer 30a, a conductive resin layer 30b, a thin film layer 30c, etc. In the embodiment, the base electrode layer 30 includes three layers: the baked layer 30a, the conductive resin layer 30b, and the thin film layer 30c.

[0045] (Baking layer 30a) The metal of the baked layer 30a includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer 30a may be one layer or multiple layers. The baked layer 30a is formed by applying a conductive paste containing glass and metal to the laminate 2 and baking it. In the embodiment, the baked layer 30a is baked simultaneously with the internal electrode layer 15, but is not limited thereto, and may be baked after the internal electrode layer 15 is baked.

[0046] (Conductive resin layer 30b) In the embodiment, the conductive resin layer 30b contains conductive particles and a thermosetting resin. Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. The metal component may be, for example, Ag or a metal powder in which the surface of a base metal powder is coated with Ag. When the conductive resin layer 30b is formed, it may be formed directly on the laminate 2 without forming the baked layer 30a. The conductive resin layer 30b may be a single layer or multiple layers.

[0047] Since the conductive resin layer 30b contains a thermosetting resin, it is more flexible than the baked layer 30a made of, for example, a plating film or a baked product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock caused by a thermal cycle, the conductive resin layer 30b functions as a buffer layer to prevent the occurrence of cracks in the multilayer ceramic capacitor 1, and is easy to absorb piezoelectric vibrations, thereby suppressing "squeaks."

[0048] (thin film layer 30c) The thin film layer 30c is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of metal particles deposited to a thickness of 1 μm or less.

[0049] (Plating layer 31) The plating layer 31 preferably includes a plating of one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, and Ag-Pd alloy, or an alloy containing the metal. The plating layer 31 is preferably formed of a plurality of layers, and in the embodiment, the plating layer 31 includes a first plating layer 31a and a second plating layer 31b provided on the first plating layer 31a. In the embodiment, the first plating layer 31a is Ni plating, and the second plating layer 31b is Sn plating. The Ni plating layer 31 can prevent the base electrode layer 30 from being eroded by solder when mounting a ceramic electronic component. The Sn plating layer 31 improves the wettability of the solder when mounting a ceramic electronic component, and allows easy mounting.

[0050] Moreover, the external electrode 3 does not include the base electrode layer 30. The plating layer 31 may be provided directly on the laminate 2. In this case, the internal electrode layer 15 and the plating layer 31 are directly connected. In this case, a catalyst may be provided on the laminate 2 as a pretreatment.

[0051] In this case, the plating layer 31 preferably includes a first plating layer 31a and a second plating layer 31b provided on the first plating layer 31a. The first plating layer 31a and the second plating layer 31b preferably include plating of one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing the metal. For example, when Ni is used as the internal electrode layer 15, it is preferable to use Cu, which has good bonding properties with Ni, as the first plating layer 31a. It is preferable to use Sn or Au, which has good solder wettability, as the second plating layer 31b, and it is preferable to use Ni, which has solder barrier properties, as the first plating layer 31a. The second plating layer 31b is formed as necessary, and the external electrode 3 may be composed of the first plating layer 31a. The second plating layer 31b may be provided as the outermost layer of the plating layer 31, or another plating layer may be provided on the second plating layer 31b. It is preferable that the plating layer 31 does not contain glass. It is preferable that the metal ratio per unit volume of the plating layer 31 is 99 volume % or more.

[0052] (Method of manufacturing multilayer ceramic capacitor 1) Fig. 6 is a flow chart illustrating a method for manufacturing the multilayer ceramic capacitor 1. Fig. 7 is a diagram illustrating a method for manufacturing the multilayer ceramic capacitor 1.

[0053] (Material sheet production process S1) First, ceramic powder containing Ba and Ti components, a binder, a solvent, and a ceramic slurry for an internal dielectric layer containing Si are prepared. The molar ratio of Si to Ti in the ceramic slurry for the internal dielectric layer is 0.8 mol% or more and 1.4 mol% or less. The ceramic slurry for the internal dielectric layer is formed into a sheet shape on a carrier film using a die coater, a gravure coater, a microgravure coater, or the like to produce a ceramic green sheet 101 for an internal dielectric layer.

[0054] Next, a conductive paste containing Ni is printed in a strip-like pattern on the ceramic green sheet 101 for the internal dielectric layer by screen printing, inkjet printing, gravure printing, or the like to form a conductive pattern 102. In this way, a material sheet 103 is produced in which the conductive pattern 102 to become the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101 for the internal dielectric layer to become the internal dielectric layer 14.

[0055] Similarly to the ceramic slurry for the internal dielectric layers, ceramic powder containing Ba and Ti components, a binder, a solvent, and a ceramic slurry for the external layer containing Si are prepared. This ceramic slurry for the external layer is formed into a sheet shape on a carrier film using a die coater, a gravure coater, a microgravure coater, or the like to produce a ceramic green sheet for the external layer 112. The molar ratio of Si to Ti in the ceramic slurry for the external layer is less than that of the ceramic slurry for the internal dielectric layers, being 0.8 mol% or less, and preferably 0.5 mol% or less.

[0056] (Lamination process S2) Next, a plurality of material sheets 103 are laminated. As shown in Fig. 7, the plurality of material sheets 103 are laminated such that the strip-shaped conductive patterns 102 face the same direction and are shifted by half a pitch in the width direction W between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer portions 22 are laminated on both sides of the plurality of laminated material sheets 103.

[0057] Next, the outer layer ceramic green sheet 112 and the stacked material sheets 103 are thermocompression bonded together, thereby producing the mother block 110.

[0058] (Mother block cutting process S3) Next, the mother block 110 is cut along cutting lines X and cutting lines (not shown) intersecting with cutting line X shown in Fig. 7 corresponding to the dimensions of the laminated chips 10. In this way, a plurality of laminated chips 10 are manufactured.

[0059] (Side margin ceramic green sheet attachment process S4) A ceramic slurry for an inner layer containing ceramic powder containing Ba and Ti components, a binder, a solvent, and a trace amount of Si, and a ceramic slurry for an outer layer containing ceramic powder containing Ba and Ti components, a binder, a solvent, and a larger amount of Si than the ceramic green sheet for the inner layer are prepared. Specifically, the molar ratio of Si to Ti contained in the ceramic slurry for the inner layer is preferably 0.01 to 0.1 mol %, and the molar ratio of Si to Ti contained in the ceramic slurry for the outer layer is preferably 0.8 mol % or less, more preferably 0.5 mol % or less.

[0060] A ceramic green sheet having a two-layer structure is produced by applying the ceramic slurry for the outer layer to the surface of a carrier film and drying it, and then applying the ceramic slurry for the inner layer on top of that and drying it.

[0061] Thereafter, the ceramic green sheet is peeled off from the carrier film, and the ceramic green sheet for the inner layer is placed opposite the side of the laminate chip 10, and the ceramic green sheet for the side margin is attached to the side of the laminate chip 10 by pressing and punching.

[0062] (Baking layer material application process S5) The material of the fired layer 30a of the base electrode layer 30 is applied to both end faces C of the laminate chip 10 with the side margin ceramic green sheets attached.

[0063] (Firing process S6) The laminate chip 10 with the material of the baking layer 30a attached thereto is then degreased under specified conditions in a nitrogen atmosphere, and then fired and sintered at a specified temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to form the laminate 2 in which the baking layer 30a and the conductive resin layer 30b are formed.

[0064] In this firing process, dielectric grains g are formed in the external dielectric layer 20, which is a combination of the outer layer portion 22 and the side margin portion 21, and in the internal dielectric layer 14. The grain size of the grains g can be adjusted by the Si content. If the Si content is high, the grain size of the grains g becomes small, and if the Si content is low, the grain size of the grains g becomes large. For example, when the laminate 2 is fired, the grain size of the grains g of the laminate 2 tends to become smaller toward the outer surface of the laminate 2. By adjusting the Si content of the laminate 2, excessive changes in the grain size of the grains g of the laminate 2 can be suppressed.

[0065] In an embodiment, the inner dielectric layer 14 and the outer dielectric layer 20 contain Si and Ti. The molar ratio of Si to Ti in the inner dielectric layer 14 is greater than the molar ratio of Si to Ti in the outer dielectric layer 20. Specifically, the molar ratio of Si to Ti in the inner dielectric layer 14 is 0.8 mol% or more and 1.4 mol% or less. The molar ratio of Si to Ti in the outer dielectric layer 20 is 0.8 mol% or less.

[0066] Therefore, it is considered that the grain size of the grains 21g and grains 22b of the outer dielectric layer 20, which has a lower Si content than the inner dielectric layer 14, is larger than that of the grains 14g of the inner dielectric layer 14. However, when fired, even if the Si content is the same, the grains 21g and grains 22b of the outer dielectric layer 20 located on the outside tend to be smaller than those located on the inside. In addition, the outer dielectric layer 20 contains Ni, which also suppresses the growth of grains in the outer dielectric layer 20. Therefore, according to the embodiment, after sintering, the grain size of the outer dielectric layer 20 and the grain size of the outer dielectric layer 20 are substantially equal, that is, the difference in grain size is 100 nm or less.

[0067] In addition, since the inner layer 21b is considerably thinner than the outer layer 21a, the Si content of the inner layer 21b does not contribute much to determining the grain size of the grains 21g. Therefore, the Si content of the outer layer 21a is dominant in forming the grain size before sintering.

[0068] (Conductive resin layer process S7) Next, a material for the conductive resin layer 30b containing conductive particles and a thermosetting resin is applied onto the baked layer 30a.

[0069] (Thin film layer formation step S8) Furthermore, in the laminate 2, on the material of the conductive resin layer 30b, a thin film layer 30c is formed, which is a layer of 1 μm or less in which metal particles are deposited by a thin film formation method such as sputtering or vapor deposition.

[0070] (Plating layer formation process S9) In the embodiment, a first plating layer 31a which is a Ni plating layer and a second plating layer 31b which is a Sn plating layer are formed on the first plating layer 31a, as the plating layer 31. Through the above steps, the multilayer ceramic capacitor 1 is manufactured.

[0071] (effect) As described above, the multilayer ceramic capacitor 1 of the embodiment has the following effects. On both side surfaces B of the inner layer portion 11, there is an interface where the inner dielectric layer 14 and the side margin portion 21 of the outer dielectric layer 20 come into contact. On the end surface C side to which the lead portion 15b does not extend, in the inner electrode layer 15 arranged on both main surfaces A of the inner layer portion 11, there is an interface where the inner dielectric layer 14 and the outer layer portion 22 of the outer dielectric layer 20 come into contact. If the grain size difference of the grains g contained in the dielectric layer is large at such an interface where the inner dielectric layer 14 and the outer dielectric layer 20 come into contact, the difference in compressive stress becomes large, the interface is likely to peel off, and the dielectric breakdown voltage may be reduced.

[0072] However, in the embodiment, the average grain size of the grains 14g contained in the inner dielectric layer 14 and the average grain size of the grains 21g and grains 22g contained in the outer dielectric layer 20 are substantially equal to each other, and the difference in grain size is 100 nm or less.

[0073] Therefore, a difference in compressive stress is unlikely to occur at the interface between the inner dielectric layer 14 and the outer dielectric layer 20, a decrease in the breakdown voltage can be prevented, and the withstand voltage reliability can be improved as well as the electrostatic capacitance can be improved.

[0074] Furthermore, since the electric field also wraps around the side margins 21 at both ends in the width direction W, this becomes a weak point if the grain size in the side margins 21 is large. This can be improved by reducing the grain size difference.

[0075] (Experimental Example) By adjusting the Si content contained in each of the internal electrode layers 15 and the external dielectric layers 20, multilayer ceramic capacitors 1 were manufactured in which the grain size of the grains g contained in each of the internal electrode layers 15 and the external dielectric layers 20 was different. Then, a voltage was applied between the external electrodes 3 of each multilayer ceramic capacitor 1 at a voltage rise rate of 50 V / sec, and the voltage at which dielectric breakdown occurred was measured. Figure 8 is a table showing the values ​​of the dielectric breakdown voltage.

[0076] As shown in the table, the particle size difference is 100 nm or less in each of Examples 1 to 8. At this time, the dielectric breakdown voltage (BVD) is 40 V or more in each of the examples.

[0077] In contrast, the comparative example has a particle size difference of 137 nm, and the dielectric breakdown voltage (BVD) is a low value of 27 V.

[0078] As described above, the multilayer ceramic capacitor 1 according to the embodiment of the present invention, in which the grain size difference between the grains g contained in the internal electrode layer 15 and the external dielectric layer 20 is 100 nm or less, can improve the breakdown voltage compared to the comparative example in which the grain size difference between the grains g is greater than 100 nm, and a multilayer ceramic capacitor 1 with high voltage resistance reliability can be provided.

[0079] Although the embodiment of the present invention has been described above, the present invention is not limited to this embodiment and may be modified in various ways within the scope of the gist of the invention. [Explanation of symbols]

[0080] g grain 1. Multilayer ceramic capacitors 2. Laminate 3 External electrode 10 Stacked chip 11 Inner Layer 14 Inner Dielectric Layer 14g grain 15 Internal electrode layer 20 Outer dielectric layer 21 Side margin 21a Outer layer 21b Inner layer 21g grain 22 Outer layer 22g grain 30 Base electrode layer 31 Plating layer

Claims

1. a laminate including a first main surface and a second main surface facing each other in a stacking direction, a first end surface and a second end surface facing each other in a length direction, and a first side surface and a second side surface facing each other in a width direction; a first external electrode disposed on a first end surface of the laminate; a second external electrode disposed on a second end surface of the laminate; Equipped with The laminate comprises: an inner layer portion having internal electrode layers at both ends in the lamination direction; an outer layer portion located between the inner layer portion and the first and second main surfaces; a side margin portion covering the inner layer portion and the outer layer portion from the side surfaces; Equipped with a difference between a grain size of the grains contained in the inner layer portion and a grain size of the grains contained in at least one of the outer layer portion and the side margin portion is 100 nm or less; the outer layer portion and the side margin portion contain Si and Ti, a concentration of Si relative to Ti in at least one of the outer layer portion and the side margin portion is 0.5 mol % or less.

2. a laminate including a first main surface and a second main surface facing each other in a stacking direction, a first end surface and a second end surface facing each other in a length direction, and a first side surface and a second side surface facing each other in a width direction; a first external electrode disposed on a first end surface of the laminate; a second external electrode disposed on a second end surface of the laminate; Equipped with The laminate comprises: an inner layer portion having internal electrode layers at both ends in the lamination direction; an outer layer portion located between the inner layer portion and the first and second main surfaces; a side margin portion covering the inner layer portion and the outer layer portion from the side surfaces; Equipped with a difference between a grain size of the grains contained in the inner layer portion and a grain size of the grains contained in at least one of the outer layer portion and the side margin portion is 100 nm or less; the inner layer portion contains Si and Ti, The concentration of Si relative to Ti in the inner layer portion is 0.8 mol % or more and 1.4 mol % or less.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein a difference between a grain size of the grains contained in said inner layer portion and a grain size of the grains contained in said outer layer portion and said side margin portion is 100 nm or less.

4. 4. The multilayer ceramic capacitor according to claim 1, wherein a difference between a grain size of the grains contained in said outer layer portion and a grain size of the grains contained in said side margin portion is 100 nm or less.

5. 5. The multilayer ceramic capacitor according to claim 1, wherein the grain size of the grains contained in the side margin portion decreases from the inner layer toward the outer side.

6. 6. The multilayer ceramic capacitor according to claim 1, wherein said outer layer portion contains Ni.

7. 7. The multilayer ceramic capacitor according to claim 1, wherein said side margin portion contains Ni.

8. 8. The multilayer ceramic capacitor according to claim 1, wherein the grain size of said grains contained in said inner layer portion is 140 nm or more and 270 nm or less.

9. 9. The multilayer ceramic capacitor according to claim 1, wherein a difference between an average grain size of the grains contained in said inner layer portion and an average grain size of the grains contained in said outer layer portion is within 36%.

10. 10. The multilayer ceramic capacitor according to claim 1, wherein a difference between an average grain size of the grains contained in said inner layer portion and an average grain size of the grains contained in said side margin portion is within 36%.

11. 11. The multilayer ceramic capacitor according to claim 1, wherein in a cross section that passes through a center of the laminate in the width direction and the lamination direction, a positional deviation in the lamination direction of ends in the width direction of two internal electrodes that are adjacent to each other vertically in the lamination direction is 5 μm or less.

12. 12. The multilayer ceramic capacitor according to claim 11, wherein in a cross section that passes through a center of the laminate, which is a cross section in the width direction and the stacking direction, a positional deviation in the stacking direction of ends in the width direction of two internal electrodes that are adjacent to each other vertically in the stacking direction is 0.5 μm or less.

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