Display device

Abstract

To provide a display device in which the decrease in display quality can be suppressed.SOLUTION: A display device in an embodiment includes a base material, a plurality of pixels disposed in a matrix in first and second directions that intersect with each other in a display region on the base material, control signal lines that supply control signals to the pixels, and power source lines that supply initialization voltage to the pixels. Each of the pixels includes a pixel circuit including a plurality of transistors, and a light-emitting element driven by the pixel circuit. The transistors included in the pixel circuit include a first transistor that is disposed between the power source line and the light-emitting element and is turned on based on the control signal. The control signal lines extend to be connected to the pixels arranged in the first direction and are arranged in the second direction. The power source lines extend to be connected to the pixels arranged in the second direction and are arranged in the first direction.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] 2. Description of the Related Art In recent years, display devices that use organic light-emitting diodes (OLEDs), which are light-emitting elements that function as display elements, have been put to practical use.

[0003] In such a display device, the light emitting element is driven by a pixel circuit. When a short circuit occurs between the anode and cathode of the light emitting element, the display quality deteriorates starting from a dark spot caused by the short circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-036290 A [Patent Document 2] JP 2019-211665 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of suppressing deterioration in display quality. [Means for solving the problem]

[0006] A display device according to an embodiment includes a substrate, a plurality of pixels arranged in a matrix along a first and second directions intersecting each other in a display region on the substrate, a control signal line that supplies a control signal to each of the plurality of pixels, and a power supply line that supplies an initialization voltage to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors, and a light-emitting element driven by the pixel circuit. The plurality of transistors that configure the pixel circuit include a first transistor that is arranged between the power supply line and the light-emitting element and is turned on based on the control signal. The control signal line extends so as to be connected to the plurality of pixels arranged in the first direction, and is arranged side by side in the second direction. The power supply line extends so as to be connected to the plurality of pixels arranged in the second direction, and is arranged side by side in the first direction. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the layout of a plurality of sub-pixels included in a pixel. [Diagram 3] FIG. 13 is a diagram showing another example of the layout of a plurality of sub-pixels included in a pixel. [Figure 4] FIG. 3 is a schematic cross-sectional view of the display device taken along the line AA in FIG. 2. [Diagram 5] FIG. [Figure 6] FIG. 11 is a schematic cross-sectional view for explaining a light-emitting element formed by utilizing a partition wall. [Figure 7] FIG. 11 is a schematic cross-sectional view for explaining a light-emitting element formed by utilizing a partition wall. [Figure 8] FIG. 11 is a schematic cross-sectional view for explaining a light-emitting element formed by utilizing a partition wall. [Figure 9] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel circuit. [Figure 10] 4A and 4B are diagrams for explaining an example of the operation of a pixel circuit. [Figure 11]FIG. 4 is a diagram illustrating various wirings connected to a pixel circuit in a comparative example of the present embodiment. [Figure 12] 13 is a diagram for explaining a case where a short circuit occurs between the anode and cathode of a light-emitting element in a comparative example of the present embodiment. FIG. [Figure 13] 11A and 11B are diagrams showing an example of horizontal streaks that occur in a display area in a comparative example of the embodiment. [Figure 14] FIG. 2 is a diagram illustrating various wirings connected to a pixel circuit in the embodiment. [Figure 15] FIG. 2 is a diagram showing an example of a layout of a pixel circuit according to the embodiment. [Figure 16] 5 is a diagram for explaining a case where a short circuit occurs between the anode and cathode of a light-emitting element in the embodiment. FIG. [Figure 17] 5A to 5C are diagrams for explaining luminance fluctuations of light-emitting elements occurring in the embodiment. [Figure 18] 5A and 5B are diagrams showing an example of vertical streaks that occur in a display area in the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in terms of width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0009] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device having organic light emitting diodes (OLEDs) as display elements (light emitting elements), and is mounted on televisions, personal computers, mobile terminals, mobile phones, and the like.

[0011] 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA surrounding the display area DA, on an insulating base material 10. The base material 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y that intersect with each other. The pixels PX include a plurality of subpixels SP. In one example, the subpixels SP include a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The subpixels SP may include subpixels of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3. The subpixels SP may also include subpixels of other colors instead of any of the subpixels SP1, SP2, and SP3.

[0014] Each of the sub-pixels SP includes a pixel circuit and a light-emitting element driven by the pixel circuit, the details of which will be described later. The pixel circuit is composed of, for example, a plurality of transistors (switching elements constituted by thin film transistors). The light-emitting element is the above-mentioned organic light-emitting diode. For example, the sub-pixel SP1 includes a light-emitting element that emits light so as to emit light in the red wavelength range, the sub-pixel SP2 includes a light-emitting element that emits light so as to emit light in the green wavelength range, and the sub-pixel SP3 includes a light-emitting element that emits light so as to emit light in the blue wavelength range.

[0015] 2 shows an example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in a pixel PX. Here, the following description focuses on four pixels PX.

[0016] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are each formed in a substantially rectangular shape extending in the second direction Y, and are aligned in the first direction X. When focusing on two pixels PX aligned in the first direction X, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. When focusing on two pixels PX aligned in the second direction Y, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are the same. The areas of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0017] FIG. 3 shows another example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in the pixel PX.

[0018] Subpixels SP1 and SP2 constituting one pixel PX are aligned in the second direction Y, subpixels SP1 and SP3 are aligned in the first direction X, and subpixels SP2 and SP3 are aligned in the first direction X. Subpixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and subpixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of ​​subpixel SP2 is larger than the area of ​​subpixel SP1, and the area of ​​subpixel SP3 is larger than the area of ​​subpixel SP2. The shape and area of ​​subpixel SP1 may be the same as those of subpixel SP2.

[0019] Focusing on two pixels PX aligned in the first direction X, in a region where subpixels SP1 and SP3 are alternately arranged and in a region where subpixels SP2 and SP3 are alternately arranged, the colors displayed in the subpixels SP adjacent in the first direction X are different from each other. On the other hand, focusing on two pixels PX aligned in the second direction Y, in a region where subpixels SP1 and SP2 are alternately arranged, the colors displayed in the subpixels SP adjacent in the second direction Y are different from each other. Also, in a region where multiple subpixels SP3 are aligned, the colors displayed in the subpixels SP adjacent in the second direction are the same.

[0020] Note that the outlines of the subpixels SP1, SP2, and SP3 shown in Figures 2 and 3 correspond to the outlines of the areas in which colors are displayed in the subpixels SP (i.e., the light-emitting areas), but are shown in a simplified form and do not necessarily reflect the actual shapes.

[0021] Here, although details will be described later, ribs and partition walls are arranged in the display area DA in this embodiment. The ribs have openings in the sub-pixels SP1, SP2, and SP3, respectively. The partition walls are arranged at the boundaries between adjacent sub-pixels SP and overlap with the ribs in a plan view. Specifically, the partition walls are arranged between adjacent openings (sub-pixels SP) in the first direction X and between adjacent openings (sub-pixels SP) in the second direction Y. As a result, the partition walls have a lattice shape formed so as to separate the sub-pixels SP1, SP2, and SP3 as a whole. In other words, the partition walls have openings in the sub-pixels SP1, SP2, and SP3, similar to the ribs.

[0022] Fig. 4 is a schematic cross-sectional view of the display device DSP taken along the line AA in Fig. 2. In the display device DSP, an insulating layer 11 called an undercoat layer is disposed on a light-transmitting substrate 10 such as the above-mentioned glass (on the surface on which light-emitting elements and the like are disposed).

[0023] The insulating layer 11 has a three-layered structure including, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). Note that the insulating layer 11 is not limited to a three-layered structure. The insulating layer 11 may have a layered structure of more than three layers, or may have a single-layered structure or a two-layered structure.

[0024] The circuit layer 12 is disposed on the insulating layer 11. The circuit layer 12 has pixel circuits (various circuits and wiring) that drive the light-emitting elements included in each of the subpixels SP1, SP2, and SP3 as described above. The circuit layer 12 is covered with the insulating layer 13.

[0025] The insulating layer 13 functions as a planarizing film that flattens unevenness caused by the circuit layer 12. Although not shown in Fig. 4, the insulating layer 13 is provided with a contact hole for connecting the lower electrode LE to the pixel circuit.

[0026] The lower electrodes LE (LE1, LE2, and LE3) are disposed on the insulating layer 13. The rib 5 is disposed on the insulating layer 13 and the lower electrodes LE. An end (part) of the lower electrode LE is covered by the rib 5.

[0027] The partition wall 6 has a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61 in the first direction X and the second direction Y. As a result, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 can be said to be an overhanging shape.

[0028] The organic layers OR (OR1, OR2, and OR3) and the upper electrodes UE (UE1, UE2, and UE3), together with the lower electrodes LE (LE1, LE2, and LE3), constitute a light-emitting element included in the subpixel SP.

[0029] As shown in FIG. 4, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through an opening AP1 (an opening in the rib 5 in the subpixel SP1) and covers a part of the rib 5. The second organic layer OR1b is located on the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts a side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0030] As shown in FIG. 4, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through an opening AP2 (an opening in the rib 5 in the subpixel SP2) and covers a part of the rib 5. The second organic layer OR2b is located on the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts a side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0031] As shown in FIG. 4, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through an opening AP3 (an opening in the rib 5 in the subpixel SP3) and covers a part of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts a side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0032] In the example shown in FIG. 4, the subpixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical properties of the light emitted from the light emitting layers of the organic layers OR1, OR2, and OR3.

[0033] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b spaced apart from each other. The first cap layer CP1a is located in the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0034] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b spaced apart from each other. The first cap layer CP2a is located in the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0035] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b spaced apart from each other. The first cap layer CP3a is located in the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0036] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers each component of the subpixel SP1, including the first cap layer CP1a, the partition wall 6, and the second cap layer CP1b. The sealing layer SE2 continuously covers each component of the subpixel SP2, including the first cap layer CP2a, the partition wall 6, and the second cap layer CP2b. The sealing layer SE3 continuously covers each component of the subpixel SP3, including the first cap layer CP3a, the partition wall 6, and the second cap layer CP3b.

[0037] 4, the second organic layer OR1b, the second upper electrode UE1b, the second cap layer CP1b, and the sealing layer SE1 on the partition 6 between the subpixels SP1 and SP2 are spaced apart from the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer SE2 on the partition 6 between the subpixels SP2 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer SE3 on the partition 6.

[0038] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15. The sealing layer 15 is further covered with a resin layer 16.

[0039] The insulating layer 13 and the resin layers 14 and 16 are made of an organic material. The rib 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are made of an inorganic material such as silicon nitride (SiNx).

[0040] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may be made of a conductive oxide such as ITO.

[0041] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE corresponds to an anode (electrode) and the upper electrode UE corresponds to a cathode (electrode). When the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE corresponds to an anode (electrode) and the lower electrode LE corresponds to a cathode (electrode).

[0042] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layer OR has a structure in which a hole injection layer, a hole import layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order.

[0043] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multiple thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. Furthermore, these multiple thin films have different refractive indices. The material of the thin films constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. The cap layer CP may be omitted.

[0044] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to each of the lower electrodes LE (LE1, LE2, and LE3) through a pixel circuit included in each of the subpixels SP (SP1, SP2, and SP3).

[0045] When a potential difference is generated between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength region. When a potential difference is generated between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength region. When a potential difference is generated between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength region.

[0046] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of colors corresponding to the subpixels SP1, SP2, and SP3.

[0047] Fig. 5 is a schematic enlarged cross-sectional view of the partition wall 6. Elements other than the rib 5, the partition wall 6, the insulating layer 13, and the pair of lower electrodes LE are omitted in Fig. 5. The pair of lower electrodes LE corresponds to any one of the above-mentioned lower electrodes LE1, LE2, and LE3.

[0048] In the example shown in FIG. 5, the lower portion 61 of the partition wall 6 includes a barrier layer (bottom portion) 611 disposed on the rib 5, and a metal layer (shaft portion) 612 disposed on the barrier layer 611. The barrier layer 611 is formed of a material different from that of the metal layer 612, and is formed of a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed to be thicker than the barrier layer 611. The metal layer 612 may have a single-layer structure or a laminated structure of different metal materials. As an example, the metal layer 612 is formed of aluminum (Al), for example.

[0049] The upper portion (top portion) 62 is thinner than the lower portion 61. In the example shown in Fig. 5, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is made of, for example, titanium (Ti), and the second layer 622 is made of, for example, ITO.

[0050] 5, the width of the lower portion 61 decreases toward the upper portion 62. That is, side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the third direction Z. The upper portion 62 has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b.

[0051] The protrusion amount D of the ends 62a and 62b from the side surfaces 61a and 61b (hereinafter referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in this embodiment corresponds to the distance in the width direction (first direction X or second direction Y) perpendicular to the third direction Z of the partition wall 6 between the lower ends (barrier layers 611) of the side surfaces 61a and 61b and the ends 62a and 62b.

[0052] 5, the side surface of the barrier layer 611 and the side surface of the metal layer 612 are aligned to form a flat surface without any steps, but for example, the side surface of the barrier layer 611 may be slightly recessed from the side surface of the metal layer 612 or may protrude from the side surface of the metal layer 612. Also, in FIG. 5, the side surfaces of the barrier layer 611 and the metal layer 612 (i.e., the side surfaces 61a and 61b of the lower portion 61) are inclined with respect to the third direction Z, but the side surfaces may be parallel to the third direction Z.

[0053] The structure of the partition walls 6 and the material of each portion of the partition walls 6 can be appropriately selected in consideration of, for example, the method of forming the partition walls 6, etc.

[0054] Here, in this embodiment, the partition wall 6 is formed so as to partition the sub-pixels SP in a plan view. The above-mentioned organic layer OR is formed, for example, by an anisotropic or directional vacuum deposition method. When an organic material for forming the organic layer OR is deposited over the entire substrate 10 with the partition wall 6 disposed, the organic layer OR is hardly formed on the side surface of the partition wall 6 because the partition wall 6 has a shape as shown in Figures 4 and 5. This makes it possible to form an organic layer OR (light-emitting element) that is divided into sub-pixels SP by the partition wall 6.

[0055] 6 to 8 are schematic cross-sectional views for explaining a light-emitting element formed by utilizing the partition wall 6. Note that the base material 10, the insulating layer 11, and the circuit layer 12 are omitted in Figs. 6 to 8. Also, the subpixels SPα, SPβ, and SPγ shown in Figs. 6 to 8 correspond to any one of the subpixels SP1, SP2, and SP3.

[0056] First, in a state where the partition 6 is disposed as described above, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are sequentially formed by vapor deposition on the entire substrate 10 as shown in FIG. 6. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the subpixel SPα. The overhanging partition 6 divides the organic layer OR into a first organic layer ORa that contacts the lower electrode LE through the opening AP and a second organic layer ORb on the partition 6, the upper electrode UE into a first upper electrode UEa that covers the first organic layer ORa and a second upper electrode UEb that covers the second organic layer ORb, and the cap layer CP into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa is in contact with the lower portion 61 of the partition 6. The sealing layer SE continuously covers the first cap layer CPa, the partition 6, and the second cap layer CPb.

[0057] Next, as shown in Fig. 7, a resist R is formed on the sealing layer SE. The resist R covers the subpixel SPα. That is, the resist R is disposed directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located in the subpixel SPα. The resist R is also located directly above the portions of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixel SPα and the subpixel SPβ that are closer to the subpixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0058] Furthermore, by etching using the resist R as a mask, the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE are removed in portions exposed from the resist R, as shown in Fig. 8. As a result, a light-emitting element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa is formed in the subpixel SPα. Meanwhile, the lower electrode LE is exposed in the subpixels SPβ and SPγ. The above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0059] After the light-emitting element of the subpixel SPα is formed as described above, the resist R is removed, and the light-emitting elements of the subpixels SPβ and SPγ are formed in sequence in the same manner as the subpixel SPα.

[0060] The structure of the display device DSP shown in Figure 4 is realized by forming light-emitting elements of sub-pixels SP1, SP2, and SP3 as exemplified above for sub-pixels SPα, SPβ, and SPγ, and then forming resin layer 14, sealing layer 15, and resin layer 16.

[0061] Here, as described above, each of the sub-pixels SP includes a pixel circuit that drives a light-emitting element. An example of a circuit configuration of the pixel circuit will be described below with reference to Fig. 9. Note that the pixel circuit 100 shown in Fig. 9 is a 7Tr1C pixel circuit that includes seven transistors Tr1 to Tr7 and one storage capacitor Cst.

[0062] In the following description, one of the source-drain terminals of each of the transistors Tr1 to Tr7 shown in Fig. 9 is referred to as a first terminal, and the other is referred to as a second terminal. In addition, one terminal of the storage capacitor Cst (a capacitive element realizing the storage capacitor Cst) shown in Fig. 9 is referred to as a first terminal, and the other terminal is referred to as a second terminal.

[0063] A first terminal of the transistor Tr1 is connected to a first terminal of the transistor Tr2 and a second terminal of the transistor Tr5 via a node n3. The second terminal of the transistor Tr1 is connected to a data signal line that supplies a data signal Data. The data signal Data corresponds to a signal (pixel signal) that is written to a pixel. The transistor Tr1 is, for example, an n-channel transistor.

[0064] The transistor Tr2 corresponds to a drive transistor (DRT) that supplies a current to the light-emitting element 20 included in the subpixel SP (i.e., the light-emitting element 20 driven by the pixel circuit 100). A first terminal of the transistor Tr2 is connected to a first terminal of the transistor Tr1 and a second terminal of the transistor Tr5 via a node n3. A second terminal of the transistor Tr2 is connected to a second terminal of the transistor Tr3, a first terminal of the transistor Tr4, and a first terminal of the transistor Tr7 via a node n1. The transistor Tr2 is, for example, an n-channel transistor.

[0065] A first terminal of the transistor Tr3 is connected to the gate terminal of the transistor Tr2 and the second terminal of the storage capacitor Cst via a node n2. A second terminal of the transistor Tr3 is connected to the second terminal of the transistor Tr2, the first terminal of the transistor Tr4, and the first terminal of the transistor Tr7 via a node n1. The transistor Tr3 is, for example, an n-channel transistor.

[0066] A first terminal of the transistor Tr4 is connected to a second terminal of the transistor Tr2, a second terminal of the transistor Tr3, and a first terminal of the transistor Tr7 via a node n1. A second terminal of the transistor Tr4 is connected to a power supply line that supplies a power supply voltage VDDEL. The transistor Tr4 is, for example, a p-channel transistor.

[0067] A first terminal of the transistor Tr5 is connected to a first terminal of the transistor Tr6, a first terminal of the storage capacitor Cst, and an anode terminal of the light-emitting element 20 via a node n4. A second terminal of the transistor Tr5 is connected to a first terminal of the transistor Tr1 and a first terminal of the transistor Tr2 via a node n3. The transistor Tr5 is, for example, a p-channel transistor.

[0068] A first terminal of the transistor Tr6 is connected to a first terminal of the transistor Tr5, a first terminal of the storage capacitor Cst, and an anode terminal of the light-emitting element 20 via a node n4. A second terminal of the transistor Tr6 is connected to a power supply line that supplies an initialization voltage Vini. The transistor Tr6 is, for example, an n-channel transistor.

[0069] A first terminal of the transistor Tr7 is connected to a second terminal of the transistor Tr2, a second terminal of the transistor Tr3, and a first terminal of the transistor Tr4 via a node n1. A second terminal of the transistor Tr7 is connected to a power supply line that supplies a power supply voltage VSH. The transistor Tr7 is, for example, an n-channel transistor.

[0070] 9, the gate terminal of transistor Tr1 is connected to a gate signal line that supplies a gate signal Scan2. The gate terminal of transistor Tr3 is connected to a gate signal line that supplies a gate signal Scan1. The gate terminals of transistors Tr4 to Tr6 are connected to a control signal line that supplies a control signal EM. The gate terminal of transistor Tr7 is connected to a gate signal line that supplies a gate signal Scan3.

[0071] A first terminal of the storage capacitor Cst is connected, via a node n4, to a first terminal of the transistor Tr5, a first terminal of the transistor Tr6, and the anode terminal of the light-emitting element 20. A second terminal of the storage capacitor Cst is connected, via a node n2, to the gate terminal of the transistor Tr2 and the first terminal of the transistor Tr3.

[0072] The anode terminal of the light-emitting element 20 is connected to a first terminal of the transistor Tr5, a first terminal of the transistor Tr6, and a first terminal of the storage capacitor Cst via a node n4. The cathode terminal of the light-emitting element 20 is connected to a power supply line that supplies a power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL corresponds to the anode voltage supplied to the light-emitting element 20, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the light-emitting element 20.

[0073] An example of the operation of the pixel circuit 100 (7Tr1C pixel circuit) shown in Fig. 9 will be briefly described below with reference to Fig. 10. Fig. 10 is a timing chart showing an example of output of gate signals Scan1 to Scan3 and a control signal EM to the pixel circuit 100 (including the sub-pixel SP).

[0074] The multiple transistors constituting the pixel circuit 100 include n-channel transistors and p-channel transistors, and the n-channel transistor is a switching element that is turned off (non-conductive) when a low (level) signal is supplied to its gate terminal and turned on (conductive) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switching element that is turned off (non-conductive) when a high (level) signal is supplied to its gate terminal and turned on (conductive) when a low (level) signal is supplied to the gate terminal.

[0075] During a period t0 shown in FIG. 10, the control signal EM is low, so that of the seven transistors included in the pixel circuit 100, the transistors Tr4 and Tr5 are in an on state, and the transistor Tr6 is in an off state.

[0076] During the period t0, the gate signals Scan1 to Scan3 are low, so that the transistors Tr1, Tr3 and Tr7 are in the off state.

[0077] As a result, a current controlled by the gate voltage of transistor Tr2 (a voltage supplied to the gate terminal of transistor Tr2 based on the data signal Data of the previous frame) flows to the light-emitting element 20 (OLED), and the light-emitting element 20 is maintained in an emitting state.

[0078] At the end of the period t0, the control signal EM is switched from low to high.

[0079] 10 corresponds to a reset period. During the period t1, the control signal EM is high, so that the transistors Tr4 and Tr5 are in an off state, and the transistor Tr6 is in an on state. In this case, the initialization voltage Vini is supplied to the node n4 via the transistor Tr6, but since the initialization voltage Vini is set to a value that does not allow a current to flow through the light-emitting element 20, no current flows through the light-emitting element 20 during the period t1.

[0080] Furthermore, at the start of period t1, the gate signal Scan1 is switched from low to high. Therefore, during period t1, the transistor Tr3 is in the ON state. Furthermore, after the end of period t0 and before the start of period t1, the gate signal Scan3 is switched from low to high. Therefore, during period t1, the transistor Tr7 is in the ON state. As a result, the power supply voltage VSH is supplied to the gate terminal of the transistor Tr2 via the transistors Tr7 and Tr3. In this case, a voltage of VSH-Vini is applied to the storage capacitor Cst (between the first and second terminals), and the information of the previous frame is reset.

[0081] At the end of the period t1, the gate signal Scan3 is switched from high to low.

[0082] Next, the period t2 shown in FIG. 10 corresponds to a sampling period. At the start of the period t2, the gate signal Scan2 is switched from low to high. Therefore, during the period t2, the transistor Tr1 is in an on state. Also, during the period t2, the gate signal Scan3 is low, so the transistor Tr7 is in an off state.

[0083] In this case, the gate terminal of the transistor Tr2 is supplied with the data signal Data (corresponding voltage Vdata) and the threshold voltage Vth of the transistor Tr2 (i.e., a voltage equivalent to Vdata+Vth) via the transistors Tr1 to Tr3. As a result, a voltage of Vdata+Vth-Vini is applied to the storage capacitor Cst, and information on Vdata and Vth is written to the storage capacitor Cst (i.e., the voltage that controls the current supplied by the transistor Tr2 to the light-emitting element 20 is stored in the storage capacitor Cst).

[0084] At the end of the period t2, the gate signal Scan1 is switched from high to low.

[0085] Next, the period t3 shown in FIG. 10 corresponds to the light emission period. During the period t3, the gate signal Scan1 is low, so the transistor Tr3 is in the off state. Also, the gate signal Scan2 is switched from high to low before the period t3 starts, so the transistor Tr1 is in the off state. Furthermore, the control signal EM is switched from high to low at the timing when the period t3 starts. Therefore, the transistors Tr4 and Tr5 are in the on state, and the transistor Tr6 is in the off state.

[0086] Here, if the first terminal of the transistor Tr2 is the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n2 to node n3) of the transistor Tr2 becomes the voltage (Vdata+Vth-Vini) of the storage capacitor Cst. In this case, the transistor Tr2 is turned on, and a current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of the transistor Tr4 to the node n4. As a result, the potential of the node n4 starts to rise, and when the potential exceeds the threshold value of the light-emitting element 20 (OLED), a current starts to flow to the light-emitting element 20, and the light-emitting element 20 starts to emit light. Finally, when the current Ioled flowing through the light-emitting element 20 reaches the output current Idrt provided by the transistor Tr2 (the output current in the saturation region of the transistor Tr2), the rise in the potential of the node n4 stops, and the light-emitting element 20 enters a steady light-emitting state.

[0087] Here, the voltage Vgs=Vdata+Vth-Vini between the gate terminal and the source terminal of the transistor Tr2 is expressed by the TFT saturation formula Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 Substituting this, Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini) 2 Here, Cox is the gate capacitance per unit area, μ is the carrier mobility, W is the channel width of the transistor Tr2, and L is the channel length of the transistor Tr2.

[0088] This means that Idrt becomes a value that is independent of the threshold voltage Vth of transistor Tr2 (i.e., a current that is independent of the threshold voltage Vth of transistor Tr2 flows through the light-emitting element 20), and it can be seen that the effect of variations in the threshold voltage Vth on Idrt can be eliminated.

[0089] That is, it can be said that the pixel circuit 100 (7Tr1C pixel circuit) shown in FIG. 9 has a function of correcting the variation in the threshold voltage Vth of the transistor Tr2 (Vth correction function).

[0090] 11 shows a schematic diagram of various wirings connected to pixel circuits 100 included in each of a plurality of subpixels SP arranged in a display area DA of a display device DSP according to a comparative example of this embodiment. Note that, in FIG. 11, of the plurality of wirings connected to the pixel circuit 100, gate signal lines for supplying gate signals Scan1 to Scan3, a control signal line for supplying a control signal EM, a power supply line for supplying an initialization voltage Vini, and a data signal line for supplying a data signal Data are shown.

[0091] 11, in the comparative example of this embodiment, the gate signal lines that supply the gate signals Scan1 to Scan3, the control signal lines that supply the control signals EM, and the power supply lines that supply the initialization voltage Vini extend in the first direction X and are connected to the pixel circuits 100 included in each of the plurality of sub-pixels SP arranged in the first direction X. Furthermore, the gate signal lines that supply the gate signals Scan1 to Scan3, the control signal lines that supply the control signals EM, and the power supply lines that supply the initialization voltage Vini are arranged side by side in the second direction Y for each row formed by the plurality of sub-pixels SP arranged in the first direction X in the display area DA.

[0092] On the other hand, the data signal lines supplying the data signals Data extend in the second direction Y and are connected to the pixel circuits 100 included in each of the sub-pixels SP arranged in the second direction Y. Moreover, the data signal lines supplying the data signals Data are arranged side by side in the first direction X for each column of the sub-pixels SP arranged in the second direction Y in the display area DA.

[0093] 12 shows a plurality of pixel circuits 100 included in a plurality of subpixels SP constituting one row in the display area DA (i.e., a plurality of pixel circuits 100 connected to one power supply line that supplies an initialization voltage Vini in a comparative example of this embodiment). In FIG 12, it is assumed that a short circuit (EL short circuit between the anode electrode and the cathode electrode) occurs between the anode and cathode of the light-emitting element 20 driven by one pixel circuit 100a of the plurality of pixel circuits 100.

[0094] As described above, if a short circuit occurs between the anode and cathode of the light-emitting element 20, the light-emitting element 20 cannot emit light, and therefore, as shown in Figure 13, the sub-pixel SP including the light-emitting element 20 is perceived as a dark spot 201 on the display area DA (the screen displayed on the display area DA).

[0095] Incidentally, as explained in FIG. 10 above, in order to cause the light-emitting element 20 in the pixel circuit 100 to emit light, a voltage of Vdata+Vth-Vini needs to be applied to the storage capacitance Cst, and the transistor Tr6 in the pixel circuit 100 is turned on.

[0096] In this case, a control signal line that supplies a control signal EM for turning on the transistor Tr6 extends in the first direction X, and the pixel circuits 100 included in the multiple sub-pixels SP that make up one row (i.e., arranged in the first direction X) turn on the transistors Tr6 at the same timing.

[0097] In addition, in the comparative example of this embodiment, the power supply line that supplies the initialization voltage Vini extends in the first direction X, and the initialization voltage Vini is supplied in common to a plurality of pixel circuits 100 included in a plurality of sub-pixels SP that constitute one row. In this case, as described in Fig. 9, the initialization voltage Vini is supplied to the node n4 via the transistor Tr6, but since the initialization voltage Vini is set to a value that does not cause a current to flow through the light-emitting element 20, no current flows through the light-emitting element 20, and the pixel circuit 100 can operate appropriately.

[0098] However, when a short circuit occurs between the anode and cathode of the light-emitting element 20 driven by the pixel circuit 100a shown in FIG. 12 described above, when the transistor Tr6 in the pixel circuit 100a is turned on, a current flows through the short circuit from the power line supplying the initialization voltage Vini to the power line supplying the power supply voltage VSSEL, resulting in a potential fluctuation in the initialization voltage Vini supplied through the power line connected to the pixel circuit 100a.

[0099] Since the power supply line supplying the initialization voltage Vini is connected to each of the pixel circuits 100 included in the multiple sub-pixels SP that make up one row, the initialization voltage Vini in which the potential fluctuation has occurred as described above is also supplied to pixel circuits 100b other than pixel circuit 100a.

[0100] As described above, the output current Idrt provided from the transistor Tr2 in the pixel circuit 100 is 1 / 2Cox*μ*W / L*(Vdata-Vini) 2 Therefore, the potential fluctuation occurring in the initialization voltage Vini affects the output current Idrt. That is, in another subpixel SP (i.e., the subpixel SP including the pixel circuit 100b) arranged in the same row as the subpixel SP including the pixel circuit 100a, the luminance of the light-emitting element 20 varies in response to the potential fluctuation occurring in the initialization voltage Vini as described above.

[0101] In addition, such a luminance fluctuation of the light-emitting element 20 can be said to occur in the sub-pixel SP where the period during which the potential fluctuation of the initialization voltage Vini occurs (i.e., the period during which the transistor Tr6 of the pixel circuit 100 that drives the light-emitting element 20 in which a short circuit has occurred is in the on state) overlaps with the above-mentioned sampling period (the period during which the data signal Data is written).

[0102] According to this, in the comparative example of this embodiment, as shown in FIG. 13, a streak 202 extending in the first direction X from the above-mentioned dark spot 201 is visible on the display area DA (i.e., a thin horizontal streak appears across one row), and the display quality of the display device DSP is degraded.

[0103] 14, in this embodiment, the power supply line supplying the initialization voltage Vini is arranged to extend in the second direction Y instead of the first direction X. With this configuration, even if a short circuit occurs between the anode and cathode of a light-emitting element 20 included in one subpixel SP, for example, the initialization voltage Vini with potential fluctuation is not supplied to the pixel circuits 100 included in the subpixels SP constituting the same row as the subpixel SP, so that it is possible to prevent thin horizontal stripes as shown in FIG.

[0104] Fig. 15 shows an example of the layout of the pixel circuit 100 in this embodiment. Fig. 15 shows each element of the pixel circuit 100 (transistors Tr1 to Tr7, storage capacitor Cst, gate signal lines, control signal lines, data signal lines, and various power supply lines) formed in a circuit layer 12 composed of, for example, first to third layers.

[0105] The first layer is a layer formed below the second layer, and the second layer is a layer formed below the third layer. In other words, the first to third layers are stacked in order, with the first layer being the bottom layer and the third layer being the top layer.

[0106] The first layer is a layer in which a semiconductor layer is formed, and the second and third layers are layers in which electrodes constituting transistors and wiring connected to the transistors are formed.

[0107] Specifically, the transistors Tr1 to Tr7 are formed across the first and second layers. Similarly to the transistors Tr1 to Tr7, the storage capacitor Cst is formed across the first and second layers.

[0108] Moreover, the gate signal lines and the control signal lines are formed in the second layer, and the data signal lines and various power supply lines are formed in the third layer.

[0109] The connections between the elements of the pixel circuit 100 described above are as described in FIG. 9, so a detailed description thereof will be omitted here. However, as shown in FIG. 15, elements formed on different layers are connected via contact holes CH.

[0110] It should be noted that the layout of the pixel circuit 100 shown in FIG. 15 is just an example, and part of the layout of the pixel circuit 1000 may differ from the example shown in FIG.

[0111] 16 shows a plurality of pixel circuits 100 included in a plurality of subpixels SP constituting one column in the display area DA (i.e., a plurality of pixel circuits 100 connected to one power supply line that supplies an initialization voltage Vini in this embodiment). In FIG 16, it is assumed that a short circuit occurs between the anode and cathode of a light-emitting element 20 driven by one pixel circuit 100a among the plurality of pixel circuits 100.

[0112] In this case, in this embodiment, since the power supply line supplying the initialization voltage Vini extends in the second direction Y (connected to multiple pixel circuits 100 arranged in the second direction Y), when the transistor Tr6 of the pixel circuit 100a shown in FIG. 16 is turned on, a short circuit occurs between the anode and cathode of the light-emitting element 20 driven by the pixel circuit 100a, causing a potential fluctuation in the initialization voltage Vini supplied via the power supply line connected to the pixel circuit 100a.

[0113] Since the power supply line supplying the initialization voltage Vini is connected to each of the pixel circuits 100 included in the multiple sub-pixels SP that make up one column, the initialization voltage Vini in which the potential fluctuation has occurred as described above is also supplied to pixel circuits 100c other than pixel circuit 100a.

[0114] As described above, the output current Idrt provided from the transistor Tr2 in the pixel circuit 100 is 1 / 2Cox*μ*W / L*(Vdata-Vini) 2Therefore, potential fluctuations occurring in the initialization voltage Vini affect the output current Idrt. That is, in the multiple subpixels SP (i.e., the subpixel SP including the pixel circuit 100c) arranged in the same column as the subpixel SP including the pixel circuit 100a, the luminance of the light-emitting element 20 varies in response to the potential fluctuations occurring in the initialization voltage Vini as described above.

[0115] According to this, in this embodiment, it is considered that a streak (thin vertical streak) extending in the second direction Y will occur starting from a dark spot that is visible due to a short circuit occurring between the anode and cathode of the light-emitting element 20 on the display area DA.

[0116] Here, FIG. 17 shows an example of output of gate signals Scan1 to Scan3 and control signals EM for each row constituted by a plurality of sub-pixels SP arranged in the display area DA.

[0117] In addition, Figure 17 shows that, for example, a short circuit occurring between the anode and cathode of a light-emitting element 20 included in one of the multiple sub-pixels SP that make up row n causes a potential fluctuation in the initialization voltage Vini during a period T (hereinafter referred to as the fluctuation period) during which transistor Tr6 of the pixel circuit 100 included in the sub-pixel SP is in an on state.

[0118] Incidentally, as described above, the luminance of the light-emitting element 20 fluctuates due to the effect of potential fluctuation in the initialization voltage Vini when the sampling period overlaps with the fluctuation period T, but the timing at which the gate signals Scan1 to Scan3 and the control signal EM are output differs for each row in the display area DA, as shown in Fig. 17. In other words, since the timing at which the sampling period starts and ends differs for each row in the display area DA, in this embodiment, the luminance of the light-emitting element 20 does not fluctuate in all sub-pixels SP arranged in the same column as the sub-pixel SP including the light-emitting element 20 having a short circuit between the anode and cathode (i.e., connected to a power supply line that supplies the same initialization voltage Vini as that sub-pixel SP).

[0119] Specifically, for example, assuming that the gate signals Scan1 to Scan3 and the control signal EM are output (supplied) in accordance with a predetermined horizontal period (1H), in the example shown in FIG. 17, the period (i.e., the fluctuation period) T during which a potential fluctuation occurs in the initialization voltage Vini by supplying a control signal EM that turns on the transistor Tr6 of the pixel circuit 100 included in the multiple sub-pixels SP constituting n rows is 4 horizontal periods (4H), and the fluctuation period T overlaps with the sampling period only in rows n-2, n-1, and n+1.

[0120] In other words, according to the example shown in FIG. 17, even if a short circuit occurs between the anode and cathode of a light-emitting element 20 included in one of the multiple sub-pixels SP constituting row n, the luminance of only the light-emitting element 20 included in the sub-pixels SP constituting rows n-2, n-1, and n+1 of the sub-pixels SP arranged in the same column as the sub-pixel SP changes, and the luminance of the sub-pixels SP constituting the other rows does not change.

[0121] In this case, as shown in Figure 18, in the display area DA, only a short vertical streak 203 occurs, starting from the dark spot 201 and spanning two sub-pixels SP located in the opposite direction to the second direction Y (i.e., upward) and one sub-pixel SP located in the second direction Y (i.e., downward).

[0122] As described above, the display device DSP according to this embodiment includes a substrate 10, a plurality of sub-pixels SP arranged in a matrix shape along a first direction X and a second direction Y intersecting each other in a display area DA on the substrate 10, a control signal line that supplies a control signal EM to each of the sub-pixels SP, and a power supply line that supplies an initialization voltage Vini to each of the sub-pixels SP. Each of the sub-pixels SP includes a pixel circuit 100 composed of a plurality of transistors and a light-emitting element 20 driven by the pixel circuit 100. The plurality of transistors that configure the pixel circuit 100 are arranged between the power supply line that supplies the initialization voltage Vini and the light-emitting element 20, and include a transistor Tr6 (first transistor) that is turned on based on the control signal EM. The control signal line that supplies the control signal EM extends so as to be connected to the sub-pixels SP arranged in the first direction X, and is arranged side by side in the second direction Y. The power supply line that supplies the initialization voltage Vini extends so as to be connected to the sub-pixels SP arranged in the second direction Y, and is arranged side by side in the first direction X.

[0123] In addition to a plurality of transistors, the pixel circuit 100 further comprises a storage capacitance Cst, the plurality of transistors including a transistor Tr2 (second transistor) that supplies a current to the light-emitting element 20, the storage capacitance Cst being configured to store a voltage that controls the current that the transistor Tr2 supplies to the light-emitting element 20, and the transistor Tr6 being connected to the storage capacitance Cst.

[0124] The multiple transistors constituting the pixel circuit 100 include a transistor Tr1 (third transistor) that is connected to a data signal line that supplies a data signal Data and is turned on based on a gate signal Scan2. The data signal line that supplies the data signal Data extends so as to be connected to the multiple sub-pixels SP arranged in the second direction Y, and is arranged side by side in the first direction X. The gate signal line that supplies the gate signal Scan2 extends so as to be connected to the multiple sub-pixels SP arranged in the first direction X, and is arranged side by side in the second direction Y.

[0125] In this embodiment, the above-mentioned configuration allows writing the data signal Data for each of the sub-pixels SP (rows formed by the sub-pixels SP) arranged in the first direction X, so that even when the transistors Tr6 of the pixel circuits 100 included in the sub-pixels SP are turned on, it is possible to avoid horizontal stripes that occur across one row on the display area DA as shown in FIG. 13. Furthermore, in this embodiment, only short vertical stripes 203 as shown in FIG. 18 occur on the display area DA, and such vertical stripes 203 are not visible. That is, according to this embodiment, it is possible to suppress a decrease in the display quality of the display device DSP compared to a configuration in which the power supply line that supplies the initialization voltage Vini is arranged to extend in the first direction X as in the comparative example of this embodiment described above.

[0126] In this embodiment, the control signal line that supplies the control signal EM is described as extending in the first direction X, and the power supply line that supplies the initialization voltage Vini is described as extending in the second direction Y. However, the control signal line and the power supply line may be arranged in intersecting directions. For example, the control signal line may extend in the second direction Y, and the power supply line may extend in the first direction X.

[0127] However, in order to efficiently drive the light-emitting elements 20 included in the multiple sub-pixels SP arranged in a matrix as described above, it is preferable that the control signal line that supplies the control signal EM and the gate signal lines that supply the gate signals Scan1 to Scan3 are arranged to extend in the same direction, and that the power supply line that supplies the initialization voltage Vini and the data signal line that supplies the data signal Data are arranged to extend in the same direction.

[0128] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention are within the scope of the present invention as long as they include the gist of the present invention.

[0129] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0130] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0131] DSP...display device, DA...display area, NDA...non-display area, PX...pixel, SP, SP1, SP2, SP3...sub-pixel, AP, AP1, AP2, AP3...opening, LE, LE1, LE2, LE3...lower electrode, UE, UE1, UE2, UE3...upper electrode, OR, OR1, OR2, OR3...organic layer, SE, SE1, SE2, SE3...sealing layer, Tr1 to Tr7...transistor, Cst...storage capacitance, 5...rib, 6...partition, 10...substrate, 11...insulating layer, 12...circuit layer, 13...insulating layer, 14...resin layer, 15...sealing layer, 16...resin layer, 20...light-emitting element, 61...lower part, 62...upper part, 100...pixel circuit.

Claims

1. A substrate; a plurality of pixels arranged in a matrix along first and second directions intersecting each other in a display region on the substrate; a control signal line for supplying a control signal to each of the plurality of pixels; a power supply line for supplying an initialization voltage to each of the plurality of pixels; Equipped with Each of the plurality of pixels includes a pixel circuit including a plurality of transistors and a light-emitting element driven by the pixel circuit; the plurality of transistors constituting the pixel circuit include a first transistor that is disposed between the power supply line and the light emitting element and is turned on based on the control signal; the control signal lines extend so as to be connected to a plurality of pixels arranged in the first direction, and are arranged side by side in the second direction; The power supply line extends so as to be connected to a plurality of pixels arranged in the second direction, and is arranged side by side in the first direction. Display device.

2. the pixel circuit further includes a storage capacitor in addition to the plurality of transistors, the plurality of transistors constituting the pixel circuit include a second transistor that supplies a current to the light emitting element, a storage capacitor constituting the pixel circuit is configured to store a voltage for controlling a current supplied from the second transistor to the light emitting element, The first transistor is connected to the storage capacitor. The display device according to claim 1.

3. a data signal line for supplying a data signal to each of the plurality of pixels; a gate signal line for supplying a gate signal to each of the plurality of pixels; Further comprising: the plurality of transistors constituting the pixel circuit include a third transistor that is connected to the data signal line and is turned on based on the gate signal; the data signal lines extend so as to be connected to a plurality of pixels arranged in the second direction, and are arranged side by side in the first direction; The gate signal lines extend so as to be connected to a plurality of pixels arranged in the first direction, and are arranged side by side in the second direction. The display device according to claim 2.

4. The data signal is written to each of the plurality of pixels arranged in the first direction, The first transistor is turned on to write the data signal to a plurality of pixels arranged in the first direction. The display device according to claim 3.

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