Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device with wiring that can be easily cut by trimming, etc.SOLUTION: A semiconductor device has a semiconductor substrate, a circuit element formed on the semiconductor substrate, wiring electrically connected to the circuit element, an insulating film to protect the circuit element and wiring, and fuse wiring with tunnel-shaped recesses formed on rough surfaces formed on the insulating film and including metal wiring electrically connected to at least one of the circuit element and wiring.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having wiring and a manufacturing method thereof. [Background technology]

[0002] Laser trimming of wiring may be performed on semiconductor devices to adjust the product characteristics or individual output signal levels. Laser trimming is a technique for trimming wiring formed in a wiring layer by irradiating the wiring with laser light to heat and evaporate it. Laser trimming of wiring is used for circuit modification to use redundant circuits in memory products such as SRAMs and driver ICs.

[0003] In a semiconductor device with multi-layer wiring, metal wiring mainly made of aluminum or the like is likely to be used as a fuse structure for laser light trimming in wiring above deeper layers of the device.

[0004] In fuse structures intended for laser trimming, after laser trimming, most of the wiring material in the irradiated area is scattered and removed from the irradiated area due to evaporation by the laser light, but some of the scattered material is thermally evaporated around the fuse and on the underlying layer, remaining as residue, and this residual metal can cause a short circuit.

[0005] Patent Document 1 discloses a circuit cutting method in which a fuse structure is irradiated with laser light a first time, and then a second or third laser light irradiation is performed at a different position in the width direction of the fuse, thereby cutting off a circuit connected to the fuse structure for trimming. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 6-326195 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the method disclosed in Patent Document 1 mentioned above, in which the metal wiring of the fuse structure is irradiated with laser light a first time, and then a second and a third time by shifting the position in the width direction of the fuse, to completely cut off the fuse, if the areas irradiated with laser light in the three laser irradiations partially overlap, the insulating film on the sides of the fuse may collapse or cracks may occur in the fuse base, which may result in contamination of the underlying semiconductor element or the generation of leakage current.

[0008] The present invention has been made in consideration of the above-mentioned problems with the conventional technology, and has as an object to provide a semiconductor device having wiring that can be easily cut, and a method for manufacturing the same. [Means for solving the problem]

[0009] The semiconductor device of the present invention is characterized by having a semiconductor substrate, a circuit element formed on the semiconductor substrate, wiring electrically connected to the circuit element, an insulating film protecting the circuit element and the wiring, and a fuse wiring having a tunnel-shaped recess formed on a rough surface portion formed on the insulating film, the fuse wiring including a metal wiring electrically connected to at least one of the circuit element and the wiring.

[0010] A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a semiconductor substrate, a circuit element formed on the semiconductor substrate, wiring electrically connected to the circuit element, an insulating film protecting the circuit element and the wiring, and a fuse wiring including a metal wiring electrically connected to at least one of the circuit element and the wiring, forming a rough surface portion on the insulating film after the insulating film forming step; forming the metal wiring intersecting the rough surface portion; a step of performing wet etching while exposing a side surface of the metal wiring on the rough surface portion of the insulating film to form the fuse wiring having a tunnel-shaped recess in the metal wiring on the rough surface portion; The present invention is characterized by comprising: Effect of the Invention

[0011] According to the semiconductor device of the present invention, since the wiring has a recess that forms a tunnel in contact with the upper surface of the insulating film, the wiring can be easily melted and cut by irradiating the wiring in the recess with laser light or by applying a predetermined voltage across the recessed portion of the wiring. The above-mentioned configuration makes it possible to easily thin a portion of the metal wiring and, in the case of a fuse, to reduce metal scattering.

[0012] In the semiconductor device according to the present invention, the portion in which the tunnel that does not melt the wiring is formed can form at least a part of a capacitor or resistor. [Brief description of the drawings]

[0013] [Figure 1] 1 is a partial cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 5] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 6] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 7]1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 8] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 9] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 10] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 11] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 12] 1 is a cutaway perspective view showing a main portion on a semiconductor substrate in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 13] 11 is a partial cross-sectional view showing a main part of a semiconductor device according to a modified example of the present embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In the embodiments, components having substantially the same functions and configurations are designated by the same reference numerals and will not be described repeatedly.

[0015] FIG. 1 is a partial cross-sectional view showing a main part of a semiconductor device 10 according to an embodiment of the present invention.

[0016] The semiconductor device 10 has a semiconductor substrate 11 (also simply referred to as a substrate), a circuit element 12 formed on the surface of the semiconductor substrate 11, and an insulating film 13 which is an interlayer insulating film formed on the surface of the semiconductor substrate 11 and on the circuit element 12. Furthermore, the insulating film 13 is provided with a contact 14 which penetrates it, and the contact 14 electrically connects the circuit element 12 mounted on the semiconductor substrate 11 to a wiring 16 made of a metal material containing aluminum as a main component, for example. The wiring 16 is formed so as to be in contact with the insulating film 13, and is formed so as to cross a rough surface portion 15 (two grooves) which has a rougher surface than other portions.

[0017] For example, the circuit element 12 mounted on the semiconductor substrate 11 of a silicon wafer may have a structure in which, for example, a source region, a drain region, a well region, etc. are formed, and then an element isolation insulating film and a gate oxide film made of a silicon oxide film are formed on the gate oxide film, and a gate electrode made of polysilicon is formed on the gate oxide film. Although not shown, the pattern of the wiring 16 is electrically connected to the gate electrode, the source region, or the drain region via the contact 14.

[0018] The wiring 16 formed on the insulating film 13 has a recess that forms a tunnel 17 in contact with the upper surface of the insulating film 13 .

[0019] The rough surface portion 15 facing the recess of the tunnel 17 is, for example, a mechanical scratch mark or a groove of a physical or chemical etching mark on the surface of the insulating film 13 .

[0020] The recessed portion of the wiring 16 where the tunnel 17 is formed functions as, for example, a fuse for trimming that can be blown. The wiring 16 can be blown to form a disconnected state by irradiating the portion where the tunnel 17 is formed with laser light.

[0021] A protective insulating film 18 made of a transparent silicon oxide or the like is formed on the pattern of the wiring 16 and the insulating film 13. That is, the wiring 16 is formed so as to be exposed through the transparent metal oxide film. The protective insulating film 18 can protect the surroundings from scattering wiring material when the portion where the tunnel 17 of the recess of the wiring 16 is formed is melted.

[0022] As a modification of this embodiment, the recessed portion of the wiring 16 where the tunnel 17 is formed can also constitute at least a part of a capacitor or resistor.

[0023] That is, since the wiring 16 has a structure in which a part of the wiring 16 is raised above the insulating film 13, the wiring 16 itself can function as a variable resistor or variable capacitance (capacitor) with an adjustable wiring surface area.

[0024] (Other variations) Another modification of the above embodiment is the same as the above embodiment except that the wiring 16 is formed mainly of polysilicon instead of aluminum. That is, the wiring 16 can be opened by applying a predetermined voltage across the portion where the recessed tunnel 17 is formed. The recessed tunnel 17 portion of the wiring 16 functions as, for example, a power fuse that can be blown.

[0025] In the above configuration, when melting the polysilicon wiring 16P, if a predetermined melting voltage is applied between two points straddling the tunnel 17 in the recess of the wiring 16, the current mainly concentrates in the tunnel 17 in the recess of the wiring 16, causing melting. In other words, this actively utilizes the fact that melting occurs easily in metal wiring mainly composed of polysilicon. As a result, the tunnel 17 in the recess of the wiring 16 will move and disappear, creating a place where it can easily be broken.

[0026] According to the modified example, by performing necessary wiring cutting on a product in a characteristic test process such as a probe test, it contributes to easy, efficient, reliable and sure wiring cutting. As a result, it is possible to provide a semiconductor device having a fuse that can be reliably cut and a manufacturing method thereof.

[0027] Thus, the wiring 16 can contain aluminum or polysilicon as a main component.

[0028] A method for manufacturing a semiconductor device 10 having wiring 16 formed on an insulating film 13 that covers and protects a circuit element 12 and electrically connected to the circuit element 12 will be described.

[0029] In the method for manufacturing the semiconductor device 10, a circuit element forming process is performed as a pre-process.

[0030] 2, a predetermined circuit element 12 is formed on the surface of a semiconductor substrate 11. Although not shown, in the circuit element formation process, for example, a source region, a drain region, a well region, etc. are formed, an element isolation insulating film made of a silicon oxide film and a gate oxide film are formed, and a gate electrode made of polysilicon is formed on the gate oxide film.

[0031] The post-process flow is as follows: (1) Interlayer insulating film deposition process (2) Contact photolithography process (3) Contact etching process (4) Rough surface formation process (5) Metal wiring sputtering process (6) Metal wiring photolithography process (7) Metal wiring wet etching process (tunnel formation process) (8) Protective insulating film formation process Each of these steps will be described below.

[0032] (1) Interlayer insulating film deposition process 3, in this process, an insulating film 13 is formed on the mounting surface of the circuit element 12. A silicon oxide film (BPSG: Boro-Phospho Silicate Glass) containing B (boron) and P (phosphorus) is used as the insulating film 13 that covers the circuit element 12 because of its good step filling properties. For example, a BPSG film is grown over the entire mounting surface of the circuit element 12 using an atmospheric pressure CVD (Chemical Vapor Deposition) device to form the insulating film 13.

[0033] (2) Contact photolithography process In this process, a photoresist film (not shown) made of a photosensitive material in which a predetermined contact hole pattern is formed is patterned on the insulating film 13. First, a thin film (not shown) of a predetermined surface hydrophobicity modifier is applied to the insulating film 13 by coating. A photoresist (not shown) dissolved in an organic solvent is applied onto the thin film. The photoresist (not shown) is fixed to the insulating film 13 (heated to a predetermined temperature (pre-baked) to evaporate the organic solvent). The contact hole pattern of a photomask (reticle) (not shown) is transferred (exposed) to the photoresist (not shown) fixed to the insulating film 13 by light (ultraviolet rays). The exposed substrate is immersed in a developer (not shown) for development, and after development, washed with a rinse solution (not shown). The substrate is heated to a temperature higher than that of the pre-baked to completely remove the rinse solution and bake the contact hole pattern photoresist film (not shown) onto the insulating film 13 (post-baked).

[0034] (3) Contact etching process Contact holes are formed in the insulating film 13 via a contact hole pattern photoresist film (not shown). For example, a reactive ion etching device or a high density plasma dry etching device (not shown) such as ICP (Inductively Coupled Plasma) is used. Argon or oxygen-added fluorocarbon gas is mainly used for dry etching. The surface (contact hole portion) exposed from the photoresist film (not shown) is cut by dry etching. After dry etching, the photoresist film (not shown) is washed and removed from the insulating film 13 with a rinse solution, and contact holes are formed that penetrate to the predetermined portions of the circuit elements 12 to be electrically connected, as shown in FIG. 4.

[0035] (4) Rough surface formation process 5, in this step, a rough surface portion 15 is formed, which is rougher than the other portions (except the contact holes) of the insulating film 13. For example, two grooves (scratches) are made as the rough surface portion 15 at predetermined positions (positions that intersect with wiring, which will be described later) on the BPSG film of the insulating film 13. The predetermined positions are predetermined tunnel formation positions on the insulating film 13.

[0036] The rough surface forming step may be performed immediately after the interlayer insulating film forming step, and two grooves (scars caused by mechanical scratches) may be formed as rough surface 15 before the contact holes are formed, as shown in Fig. 6. That is, it is sufficient that rough surface 15 is formed at a predetermined tunnel formation position on insulating film 13 after the interlayer insulating film forming step and before the next metal wiring sputtering step.

[0037] The rough surface portion 15 may be formed as a groove by physical etching such as etching or chemical etching of the surface of the insulating film 13, in addition to mechanical scratches.

[0038] (5) Metal wiring sputtering process The substrate is set with the insulating film 13 facing an aluminum (or its alloy) target in a sputtering film formation device. In this process, argon ions are collided with the target under plasma discharge, and aluminum particles knocked out by the collision are attached to the opposing substrate, forming an aluminum film 16a on the insulating film 13 of the substrate, as shown in Fig. 7. After the insulating film 13 is thus formed, aluminum that will become the upper layer wiring is poured into contact holes that penetrate to the lower layer circuit elements 12, conductive layers, and wiring at desired locations, to make electrical contact with the lower layer circuit elements 12, etc.

[0039] (6) Metal wiring photolithography process On the surface of the aluminum film, a pattern of wiring 16 that crosses the rough surface portion 15, i.e., crosses the rough surface portion 15, is patterned. First, a thin film (not shown) of a surface hydrophobic modifier such as HMDS (bis(trimethylsilyl)amine) is applied to the surface of the aluminum film 16a by coating. A photoresist RST dissolved in an organic solvent is applied to the thin film and prebaked. The wiring pattern of the photomask is exposed to light (ultraviolet rays) on the photoresist RST fixed to the aluminum film. The exposed substrate is immersed in a developer for development, and after development, the substrate is washed with a rinse solution to completely remove the rinse solution, and the photoresist RST is post-baked on the aluminum film 16a of the substrate as shown in FIG. 8. Next, the surface of the exposed portion from the photoresist RST (portion other than the wiring 16) is cut by dry etching to form the wiring 16 on the insulating film 13 across the rough surface portion 15, and the side surface of the wiring 16 on the rough surface portion 15 of the insulating film 13 is exposed. After the dry etching, the substrate is washed with a rinse liquid, and a pattern of wiring 16 with a photoresist RST is formed on the insulating film 13 as shown in FIG.

[0040] (7) Metal wiring wet etching process (tunnel formation process) In this step, a metal wiring wet etching step (tunnel formation step) is performed while the photoresist RST is left as it is. By this step, the side surface of the wiring 16 on the rough surface portion 15 of the insulating film 13 is exposed while wet etching is performed to form a tunnel 17 on the side surface of the lower part of the wiring 16 on the rough surface portion 15, thereby forming a recess.

[0041] This process utilizes the fact that grooves (scratches) are made on the insulating film 13 to form the rough surface portion 15, and therefore, during the metal wiring sputtering process, the sputtered metal does not fill in the stepped portions of the grooves in the rough surface portion 15. This process allows the etching solution to seep into the lower portion of the wiring 16 from the grooves (rough surface portion 15) during the metal wiring wet etching process, and a tunnel can be formed under the wiring 16 by so-called side etching, achieving a thin wiring 16.

[0042] In this way, in the wet etching process in which wiring 16 is formed, an etching solution having a higher etching rate for wiring 16 than for insulating film 13 is used to soak into the groove (rough surface portion 15), etching a recess of tunnel 17 from the side of wiring 16 on rough surface portion 15 of insulating film 13 to the inside.

[0043] (8) Protective insulating film formation process In this process, a protective insulating film 18 made of a metal oxide film such as silicon oxide is formed on the wiring 16 and the insulating film 13. In this manner, the wiring 16 is formed so as to be exposed to laser light via the light-transmitting metal oxide film. The protective insulating film 18 protects the surroundings from metal splatter caused by laser light irradiation.

[0044] As described above, according to this embodiment, a portion of the wiring 16 can be made thin and the lower portion of the wiring 16 is missing as a tunnel, so that it is possible to reduce metal splatter when the portion of the wiring 16 above the tunnel 17 is blown by irradiating it with laser light as a trimming fuse.

[0045] In the above embodiments and modifications, the wiring and power fuse may be mainly composed of conductive materials such as Al, Cu, Au, or Al with Cu added, etc. In this case, the barrier layer may be made of metals such as Ti, Ta, Ni, Co, Ru, or compounds containing these metals such as TiN. [Explanation of symbols]

[0046] 10 Semiconductor device 11 Semiconductor substrate 12 Circuit elements 13. Insulating film 14 Contact 15 Rough surface area 16 Wiring 17 Tunnel 18 Protective insulating film

Claims

1. A semiconductor substrate; an insulating film formed on a surface of the semiconductor substrate; a wiring formed on the insulating film and having a recessed portion forming a tunnel in contact with an upper surface of the insulating film; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein a rough surface portion having a rougher surface than other portions is formed in a portion of the insulating film facing the recess of the tunnel.

3. 3. The semiconductor device according to claim 2, wherein the rough surface portion is a mechanical scratch mark or a groove formed by physical or chemical etching on the surface of the insulating film.

4. 2. The semiconductor device according to claim 1, wherein the wiring has a contact connected to a circuit element mounted on the semiconductor substrate.

5. 2. The semiconductor device according to claim 1, wherein the recessed portion of the wiring is a fuse.

6. 2. The semiconductor device according to claim 1, wherein the portion of the wiring where the recess is formed constitutes at least a part of a capacitor or a resistor.

7. 2. The semiconductor device according to claim 1, wherein the wiring is formed so as to be exposed through a light-transmitting metal oxide film.

8. 4. The semiconductor device according to claim 3, wherein the wiring is disconnected by irradiating a portion where the recess is formed with laser light.

9. 2. The semiconductor device according to claim 1, wherein the wiring is disconnected by applying a predetermined voltage across the portion where the recess is formed.

10. 2. The semiconductor device according to claim 1, wherein the wiring contains aluminum or polysilicon as a main component.

11. 1. A method for manufacturing a semiconductor device having metal wiring formed on an insulating film that covers and protects a circuit element and electrically connected to the circuit element, comprising the steps of: forming a rough surface portion on the insulating film after the insulating film forming step; forming the metal wiring on the insulating film across the rough surface portion; a step of forming a recess by forming a tunnel on the side surface of the metal wiring on the rough surface portion of the insulating film by performing wet etching while exposing the side surface of the metal wiring on the rough surface portion; 2. A method for manufacturing a semiconductor device comprising the steps of:

12. 12. The method of claim 11, wherein the rough surface portion is formed as a groove by mechanically scratching or physically or chemically etching the surface of the insulating film.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein in the wet etching in the process of forming the metal wiring, the recess is etched inward from the side of the metal wiring on the rough portion of the insulating film by penetrating into the groove with an etching solution having an etching rate for the metal wiring higher than an etching rate for the insulating film.

14. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the metal wiring contains aluminum or polysilicon as a main component.

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