Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing a defect caused by a residual plating solution while improving the durable life of a main terminal.SOLUTION: A semiconductor element is disposed on a substrate 50, and a drain electrode is electrically connected to a front surface metal body 52. A solid-phase-bonding bonding part 120 is formed between a main terminal 91 and the front surface metal body 52. A plating film 130 is provided on the front surface metal body 52 and the main terminal 91 so as to cover the bonding part 120. The main terminal 91 includes, as an overlapping region 911 that overlaps the front surface metal body 52, a bonding region 912 that provides the bonding part and a non-bonding region 913 that is provided to be adjacent to the bonding region 912 in at least a width direction of the main terminal 91. The main terminal 91 is a wide terminal in which the overlapping region 911 is wider than the bonding part 120.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes a substrate (insulating substrate), a semiconductor element having main electrodes on both sides, and a main terminal (terminal for external connection). One of the main electrodes of the semiconductor element is connected to a surface metal body (metal foil) of the substrate via a solder layer. The main terminal is connected to the surface metal body by ultrasonic bonding or the like. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-60410 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a configuration in which a main terminal is joined to a substrate, the durability of the main terminal may be reduced due to electric field concentration near the joint. In addition, in consideration of the wettability of the solder layer and the bondability of the main terminal, it is possible to apply a plating film after joining the main terminal to the surface metal body. In this case, there is a risk that residual plating solution will be generated and the plating solution will seep out in a later process, causing a decrease in the wettability of the solder layer. In the above-mentioned viewpoints and other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0005] One disclosed object is to provide a semiconductor device capable of improving the durability life of a main terminal while suppressing defects caused by plating solution residue. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises: A semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on a back surface opposite to the one surface in a plate thickness direction; a substrate (50) having an insulating base material (51), a front surface metal body (52) disposed on a front surface of the insulating base material and electrically connected to a first main electrode, and a back surface metal body (53) disposed on a surface of the insulating base material opposite to the front surface; a bonding material (100) interposed between the first main electrode and the surface metal body and bonding the first main electrode and the surface metal body; a main terminal (91, 92, 93) forming a solid-phase joint (120) with a surface metal body; a plating film (130) provided on the surface metal body and the main terminal so as to cover the solid-state welded portion; The main terminals are There is one solid-phase weld formed between the surface metal body, The main terminal has a joining region (912) that provides a solid-state joining portion as an overlapping region with the surface metal body in a plan view in the plate thickness direction, and a non-joining region (913) that is a region other than the joining region and is provided adjacent to the joining region at least in the width direction of the main terminal, The width of the overlapping region is made wider than the width of the solid-state joint, and includes wide terminals (91, 93).

[0007] According to the disclosed semiconductor device, the main terminal includes a wide terminal. The wide terminal has a non-bonded region. The non-bonded region is adjacent to the bonded region at least in the width direction. This makes the width of the overlapping region wider than the width of the solid-state bonded portion. This makes it possible to suppress electric field concentration, and thus improve the durability life of the main terminal (wide terminal).

[0008] Moreover, the plating film is provided so as to cover the solid-state bonded portion. That is, the plating film is formed after solid-state bonding. However, the wide terminal has only one solid-state bonded portion between the wide terminal and the surface metal body. The non-bonded region opens to the side. Therefore, even if plating solution enters between the non-bonded region and the surface metal body, the plating solution is easily discharged. The plating solution is unlikely to remain between the non-bonded region and the surface metal body. Therefore, it is possible to suppress the generation of plating solution residue. By suppressing the plating solution residue, it is possible to suppress a decrease in the connection reliability between, for example, a semiconductor element and a surface metal body. In this way, it is possible to suppress defects caused by plating solution residue.

[0009] The various aspects disclosed in this specification adopt different technical means to achieve their respective objectives. The claims and the parenthetical symbols described in this section are merely illustrative of the corresponding relationship with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied; [Diagram 2] FIG. 1 is a perspective view showing a semiconductor device. [Diagram 3] FIG. 1 is a plan view showing a semiconductor device. [Figure 4] FIG. 2 is a plan view showing the substrate on the drain electrode side. [Diagram 5] FIG. 2 is a plan view showing the substrate on the source electrode side. [Figure 6] FIG. 4 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 4 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] 13 is a perspective view showing a state in which a substrate on the drain electrode side and a lead frame are joined together. FIG. [Figure 9]4 is a plan view showing a connection structure between a substrate on the drain electrode side and a main terminal. FIG. [Figure 10] FIG. 10 is an enlarged view of region X in FIG. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] FIG. 11 is a cross-sectional view showing a reference example. [Figure 17] FIG. 11 is a cross-sectional view showing a reference example. [Figure 18] FIG. 11 is a cross-sectional view showing a reference example. [Figure 19] 11 is an enlarged perspective view of the periphery of a joint between a main terminal and a surface metal body in a semiconductor device according to a second embodiment. FIG. [Figure 20] 20 is a cross-sectional view taken along the line XX-XX in FIG. 19. [Figure 21] 1A to 1C are cross-sectional views showing the ultrasonic bonding process. [Figure 22] 13 is a cross-sectional view showing ultrasonic bonding between a main terminal and a surface metal body in a manufacturing method of a semiconductor device according to a third embodiment. FIG. [Diagram 23] 1 is a cross-sectional view showing an example of a semiconductor device. [Figure 24] FIG. 11 is a cross-sectional view showing a modified example. [Diagram 25] 13 is a cross-sectional view showing the periphery of a joint between a main terminal and a surface metal body in a semiconductor device according to a fourth embodiment. FIG. [Figure 26] 13 is a cross-sectional view showing the periphery of an isolation portion of a back surface metal body in a semiconductor device according to a fifth embodiment. FIG. [Figure 27] FIG. 4 is a plan view showing an example of a pattern of a back surface metal body. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, several embodiments will be described with reference to the drawings. In addition, by assigning the same reference numerals to corresponding components in each embodiment, duplicated explanations may be omitted. When only a part of the configuration is described in each embodiment, the configuration of the other embodiment described above can be applied to the other parts of the configuration. In addition to the combination of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination.

[0012] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a moving body using a rotating electric machine as a drive source. The moving body is, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0013] (First embodiment) First, a schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

[0014] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0015] The DC power supply 2 is a DC voltage source composed of a chargeable and dischargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0016] <Power conversion device> Next, a circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 which is the power conversion circuit.

[0017] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7 which is a power supply line on the high potential side and an N line 8 which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 upon receiving rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

[0019] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. A connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a part of each of the P line 7, the N line 8, and the output line 10 is configured with a conductive member such as a bus bar.

[0020] In this embodiment, an n-channel MOSFET 11 is used as a switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited. There may be one or more. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0021] As an example, in this embodiment, each arm has one MOSFET 11. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0022] A freewheeling diode 12 is connected in anti-parallel to each of the MOSFETs 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0023] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. A freewheeling diode is also connected in inverse parallel to the IGBT.

[0024] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. With this configuration, voltage can be increased and decreased. The power conversion device 4 may include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

[0025] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0026] The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0027] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured to include, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0028] <Semiconductor device> Next, a schematic configuration of the semiconductor device will be described with reference to Figs. 2 to 8. Fig. 2 is a perspective view of the semiconductor device. Fig. 3 is a plan view of the semiconductor device. In Fig. 3, elements covered by the sealing body are indicated by dashed lines. Fig. 4 is a plan view of the substrate on the drain electrode side. Fig. 5 is a plan view of the substrate on the source electrode side. Figs. 4 and 5 show the pattern of the surface metal body. In Figs. 4 and 5, the semiconductor element, the conductive spacer, and the substrate connection part are indicated by two-dot chain lines to show the positional relationship with the surface metal body. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 3. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 3. Fig. 8 is a perspective view showing a state in which a lead frame is joined to the substrate on the drain electrode side.

[0029] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction, and the arrangement direction of the semiconductor elements is defined as the X direction. The direction perpendicular to both the Z direction and the Y direction is defined as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as the planar shape.

[0030] 2 and 3 constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuits 9. The semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, substrate connection portions 80 and 81, and an external connection terminal 90.

[0031] The encapsulant 30 encapsulates a part of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of the resin is an epoxy resin. The encapsulant 30 is made of a resin and molded by, for example, a transfer molding method. Such an encapsulant 30 may be called an encapsulating resin body, a molded resin, a resin molded body, or the like. The encapsulant 30 may be formed by using, for example, a gel. The gel is filled (placed) in, for example, the opposing regions of the pair of substrates 50, 60.

[0032] As shown in FIG. 2 and FIG. 3, the sealing body 30 has a substantially rectangular shape in plan view. The sealing body 30 has one surface 30a and a back surface 30b, which is the surface opposite to the one surface 30a in the Z direction, as surfaces forming an outer periphery. The one surface 30a and the back surface 30b are, for example, flat surfaces. The sealing body 30 also has side surfaces 30c, 30d, 30e, and 30f, which are surfaces connecting the one surface 30a and the back surface 30b. The side surface 30c is a surface from which main terminals 91, 92, and 93, which are main terminals, of the external connection terminals 90 protrude. The side surface 30d is a surface opposite to the side surface 30c in the Y direction. The side surface 30d is a surface from which a signal terminal 94 protrudes. The side surfaces 30e and 30f are surfaces from which the external connection terminals 90 do not protrude. The side surface 30e is a surface opposite to the side surface 30f in the X direction.

[0033] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide band gap semiconductor with a wider band gap than silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 may be called a power element, a semiconductor chip, or the like.

[0034] The semiconductor element 40 of this embodiment is formed by forming the n-channel MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), that is, in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides in the Z direction, which is the thickness direction of the semiconductor element 40. Specifically, as main electrodes, the semiconductor element 40 has a drain electrode 40D on one side and a source electrode 40S on a back side, which is the opposite side in the Z direction from the one side. The main current flows between the drain electrode 40D and the source electrode 40S. The drain electrode 40D corresponds to a first main electrode, and the source electrode 40S corresponds to a second main electrode.

[0035] When the diode 12 is a parasitic diode, the source electrode 40S also serves as an anode electrode, and the drain electrode 40D also serves as a cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 40D is a main electrode on the high potential side, and the source electrode 40S is a main electrode on the low potential side.

[0036] The semiconductor element 40 has a substantially rectangular shape in plan view, for example, a substantially square shape. As shown in FIG. 3 and FIG. 7, the semiconductor element 40 has a pad 40P, which is an electrode for signals, on the back surface. The pad 40P is formed at a position different from the source electrode 40S on the back surface. The pad 40P includes at least a gate pad. The semiconductor element 40 of this embodiment has three pads 40P. As an example, the pad 40P includes a pad for gate, a pad for Kelvin source, and a pad for current sense. The pad for gate is a pad 40P for applying a drive voltage to the gate electrode of the MOSFET 11. The pad for Kelvin source is a pad 40P for detecting the source potential of the MOSFET 11, that is, the potential of the source electrode 40S. The pad for current sense is a pad 40P for detecting a sense current proportional to a main current, and thus detecting the main current.

[0037] The semiconductor element 40 includes a semiconductor element 40H constituting the upper arm 9H and a semiconductor element 40L constituting the lower arm 9L. The semiconductor elements 40H, 40L have a common configuration. As an example, the number of semiconductor elements 40H, 40L is one each. As shown in FIG. 3 etc., the semiconductor elements 40H, 40L are aligned in the X direction. The semiconductor elements 40 are disposed at approximately the same positions as each other in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0038] The substrates 50 and 60 are disposed in the Z direction so as to sandwich the semiconductor element 40. The substrates 50 and 60 are disposed so as to at least partially face each other in the Z direction. The substrates 50 and 60 include the entire semiconductor elements 40 (40H, 40L) therein in a plan view.

[0039] The substrate 50 is disposed on the drain electrode 40D side of the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side of the semiconductor element 40. The substrate 50 is electrically connected to the drain electrode 40D as described below, and provides a wiring function. Similarly, the substrate 60 is electrically connected to the source electrode 40S, and provides a wiring function. For this reason, the substrates 50 and 60 are sometimes referred to as wiring members, wiring substrates, etc. The substrate 50 is sometimes referred to as a drain substrate, and the substrate 60 is sometimes referred to as a source substrate. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 are sometimes referred to as heat dissipation members.

[0040] The substrate 50 has an opposing surface 50a facing the semiconductor element 40 and a back surface 50b opposite to the opposing surface 50a. The substrate 50 includes an insulating base material 51, a front metal body 52, and a back metal body 53. The substrate 60 has an opposing surface 60a facing the semiconductor element 40 and a back surface 60b opposite to the opposing surface 60a. The substrate 60 includes an insulating base material 61, a front metal body 62, and a back metal body 63. Hereinafter, the front metal bodies 52, 62 and the back metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63. The substrate 50 is a substrate in which the insulating base material 51 and the metal bodies 52, 53 are laminated. The substrate 60 is a substrate in which the insulating base material 61 and the metal bodies 62, 63 are laminated.

[0041] The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. The insulating substrates 51, 61 are sometimes referred to as insulating layers. The material of the insulating substrates 51, 61 is resin or ceramic, which is an inorganic material. For example, epoxy resin or polyimide resin can be used as the resin. For example, Al2O3 (alumina) or Si3N4 (silicon nitride) can be used as the ceramic. When the insulating substrates 51, 61 are resin, the substrates 50, 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51, 61 are ceramic, the substrates 50, 60 are sometimes referred to as metal-ceramic substrates.

[0042] Considering heat dissipation and insulation, in the case of a resin-based material, the thickness of each of the insulating base materials 51, 61, i.e., the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of a ceramic-based material, the thickness of the insulating base materials 51, 61 is preferably about 200 μm to 500 μm. In the Z direction, the front surface of the insulating base materials 51, 61 is the inner surface, i.e., the surface on the semiconductor element 40 side, and the back surface opposite the front surface in the Z direction is the outer surface. The insulating base materials 51, 61 may be made of the same material or may be made different from each other. In this embodiment, the insulating base materials 51, 61 are made of the same material.

[0043] The metal bodies 52, 53, 62, 63 are provided as, for example, a metal plate or a metal foil. The metal bodies 52, 53, 62, 63 are formed of a metal material having good electrical conductivity and thermal conductivity, such as Cu. The thickness of each of the metal bodies 52, 53, 62, 63 is, for example, about 0.1 mm to 3 mm. The front metal body 52 is disposed on the front surface of the insulating base material 51 in the Z direction. The back metal body 53 is disposed on the back surface of the insulating base material 51. Similarly, the front metal body 62 is disposed on the front surface of the insulating base material 61 in the Z direction. The back metal body 63 is disposed on the back surface of the insulating base material 61.

[0044] The thickness relationship between the front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 is not particularly limited. The thickness of the front surface metal body 52 may be thicker than the back surface metal body 53 or may be approximately equal to the back surface metal body 53. The thickness of the front surface metal body 52 may be thinner than the back surface metal body 53. Similarly, the thickness of the front surface metal body 62 may be thicker than the back surface metal body 63 or may be approximately equal to the back surface metal body 63. The thickness of the front surface metal body 62 may be thinner than the back surface metal body 63. The thickness relationship between the front surface metal bodies 52, 62 is not particularly limited, and the thickness relationship between the back surface metal bodies 53, 63 is not particularly limited.

[0045] The surface metal bodies 52, 62 are patterned. The surface metal bodies 52, 62 provide wiring, i.e., a circuit. For this reason, the surface metal bodies 52, 62 may be referred to as a circuit pattern, a wiring layer, a circuit conductor, or the like. The surface of the surface metal body 52 and a region on the surface of the insulating base material 51 where the surface metal body 52 is not disposed form the opposing surface 50a of the substrate 50. Similarly, the surface of the surface metal body 62 and a region on the surface of the insulating base material 61 where the surface metal body 62 is not disposed form the opposing surface 60a of the substrate 60.

[0046] For example, the front surface metal body 52, 62 may be prepared by patterning into a predetermined shape by pressing or etching, and then attached to a two-layer laminate of the insulating base material 51, 61 and the back surface metal body 53, 63 to form the substrate 50, 60. After forming a three-layer laminate of the front surface metal body 52, 62, the insulating base material 51, 61, and the back surface metal body 53, 63, the front surface metal body 52, 62 may be patterned by cutting or etching.

[0047] 3, 4, 6, and 7, the front surface metal body 52 has a P wiring 54, a relay wiring 55, and an N wiring 56. The P wiring 54, the relay wiring 55, and the N wiring 56 are electrically isolated from each other by a predetermined interval (gap). The gap is filled with the sealing body 30.

[0048] The P wiring 54 is connected to the main terminal 91 and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the main terminal 91 and the drain electrode 40D of the semiconductor element 40H. As an example, the P wiring 54 has a base 541 and extensions 542 and 543. The base 541 contains the semiconductor element 40H in a plan view. The base 541 has a generally rectangular shape in plan with the Y direction as the longitudinal direction.

[0049] The extensions 542 and 543 extend in the Y direction from the base 541. The length in the X direction of each of the extensions 542 and 543, i.e., the width, is narrower than the width of the base 541. The extensions 542 and 543 provide at least a part of an area to which a lead frame element including an external connection terminal 90 is connected. The extension 542 is connected to one side of the base 541 having a substantially rectangular shape in plan view, and the extension 543 is connected to the side opposite to the extension 542. The main terminal 91 is connected to the extension 542, and the support frame 98, which will be described later, is connected to the extension 543. The lead frame element may be connected only to the extensions 542 and 543, or may be connected across the base 541 and the extensions 542 and 543. The extensions 542 and 543 may be eliminated, and the lead frame element may be connected to the base 541.

[0050] The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the substrate connection portion 80, and the main terminal 93. The relay wiring 55 electrically connects the substrate connection portion 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L to the main terminal 93. As an example, the relay wiring 55 has a base portion 551 and extension portions 552, 553, and 554. The base portion 551 contains the semiconductor element 40L in a plan view. The base portion 551 has a substantially rectangular shape in plan with the Y direction as the longitudinal direction.

[0051] The extensions 552 and 553 extend in the Y direction from the base 551. The length in the X direction of each of the extensions 552 and 553, i.e., the width, is narrower than the width of the base 551. The extensions 552 and 553 provide at least a part of an area to which the lead frame elements including the external connection terminal 90 are connected. The extension 552 is connected to one side of the base 551 having a substantially rectangular shape in plan view, and the extension 553 is connected to the side opposite to the extension 552. The main terminal 93 is connected to the extension 552, and the support frame 98 is connected to the extension 553. The lead frame elements may be connected only to the extensions 552 and 553, or may be connected across the base 551 and the extensions 552 and 553. The extensions 552 and 553 may be eliminated, and the lead frame elements may be connected to the base 551.

[0052] The extension portion 554 includes the board connection portion 80 in a plan view. The extension portion 554 is connected to one of the sides of the base portion 551 which has a generally rectangular shape in plan view. The extension portion 554 extends in the X direction from the side of the base portion 551 facing the P wiring 54 toward the base portion 541. In the Y direction, the length of the extension portion 554 is shorter than the length of the base portion 551. The relay wiring 55 has a generally generally L-shape in plan view.

[0053] The N wiring 56 is connected to the substrate connection portion 81 and the main terminal 92. The N wiring 56 electrically connects the substrate connection portion 81 and the main terminal 92. The N wiring 56 includes the substrate connection portion 81 in a plan view. As an example, the N wiring 56 has a generally rectangular shape in plan view with the Y direction as the longitudinal direction.

[0054] In the front surface metal body 52, the P wiring 54 and the relay wiring 55 are arranged side by side in the X direction. The N wiring 56 is arranged between the base portions 541, 551 in the X direction. The N wiring 56 is arranged side by side with the extension portion 554 in the Y direction.

[0055] The surface metal body 62 has an N wiring 64 and a relay wiring 65. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined interval (gap). The sealing body 30 is filled in this gap.

[0056] The N wiring 64 is connected to the source electrode 40S of the semiconductor element 40L and the substrate connection portion 81. The N wiring 64 electrically connects the source electrode 40S of the semiconductor element 40L and the substrate connection portion 81. The N wiring 64, together with the N wiring 56 of the substrate 50 and the substrate connection portion 81, electrically connects the source electrode 40S of the semiconductor element 40L and the main terminal 92.

[0057] The N wiring 64 has a base 641 and an extension portion 642. The N wiring 64 has a generally L-shape in plan view. The base 641 has a generally rectangular shape in plan view with the Y direction as the longitudinal direction. The base 641 contains the semiconductor element 40L in plan view. The extension portion 642 is connected to one side of the generally rectangular base 641 in plan view. The extension portion 642 extends from a side of the base 641 facing the relay wiring 65 toward the base 651 in the X direction. At least a portion of the extension portion 642 overlaps with the N wiring 56 in plan view.

[0058] The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the substrate connection portion 80. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the substrate connection portion 80. The relay wiring 65 has a base portion 651 and an extension portion 652. The relay wiring 65 is substantially L-shaped in plan view. The base portion 651 is substantially rectangular in plan view. The base portion 651 contains the semiconductor element 40H in plan view. The extension portion 652 is connected to one side of the base portion 651, which is substantially rectangular in plan view. The extension portion 652 extends from the side of the base portion 651 facing the N wiring 64 toward the base portion 641 in the Y direction. At least a portion of the extension portion 652 overlaps with the extension portion 554 of the relay wiring 55 in plan view.

[0059] The N wiring 64 and the relay wiring 65 are arranged side by side in the X direction. The bases 641, 651 are arranged side by side in the X direction. The source electrode 40S of the semiconductor element 40L is electrically connected to the base 641. The source electrode 40S of the semiconductor element 40H is electrically connected to the base 651. The extensions 642, 652 are arranged side by side in the Y direction.

[0060] The back metal body 53, 63 is electrically isolated from the semiconductor element 40 and the circuit including the front metal body 52, 62 by the insulating base material 51, 61. The back metal body 53, 63 is sometimes referred to as a metal base substrate. Heat generated by the semiconductor element 40 is transferred to the back metal body 53, 63 via the front metal body 52, 62 and the insulating base material 51, 61. The back metal body 53, 63 provides a heat dissipation function.

[0061] As an example, the back surface metal body 53, 63 has a substantially rectangular shape in plan view. The back surface metal body 53, 63 is a so-called solid conductor disposed over substantially the entire back surface of the insulating base material 51, 61. Alternatively, the back surface metal body 53, 63 may be patterned so as to substantially coincide with the front surface metal body 52, 62 in plan view.

[0062] To further improve the heat dissipation effect, at least one of the back surface metal bodies 53, 63 may be exposed from the sealing body 30. In this embodiment, the back surface metal body 53 is exposed from one surface 30a of the sealing body 30, and the back surface metal body 63 is exposed from the back surface 30b. The exposed surface of the back surface metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back surface metal body 63 is approximately flush with the back surface 30b. The back surface metal bodies 53, 63 form the back surfaces 50b, 60b of the substrates 50, 60.

[0063] The conductive spacer 70 provides a spacer function that ensures a predetermined distance between the semiconductor element 40 and the substrate 60. The conductive spacer 70 ensures a wire height for electrically connecting the corresponding signal terminal 94 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical conduction and thermal conduction paths between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides a wiring function and a heat dissipation function. The conductive spacer 70 contains a metal material with good electrical and thermal conductivity, such as Cu.

[0064] The conductive spacer 70 may be referred to as a terminal, a terminal block, a metal block, or the like. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the semiconductor device 20 includes two conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40. The conductive spacers 70 are columnar bodies having a size substantially the same as or slightly smaller than the source electrode 40S in a plan view. One of the conductive spacers 70 electrically connects the source electrode 40S of the semiconductor element 40H to the relay wiring 65. The other conductive spacer 70 electrically connects the source electrode 40S of the semiconductor element 40L to the N wiring 64.

[0065] The substrate connection parts 80 and 81 electrically connect the front metal body 52 of the substrate 50 and the front metal body 62 of the substrate 60. That is, they connect the substrates together. The substrate connection part 80 electrically connects the relay wirings 55 and 65. The substrate connection part 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the X direction. The substrate connection part 80 is provided in an overlapping region between the extension part 554 of the relay wiring 55 and the extension part 652 of the relay wiring 65 in a plan view. The substrate connection part 81 is also provided between the semiconductor element 40H and the semiconductor element 40L in the X direction. The substrate connection part 81 is provided in an overlapping region between the N wiring 56 and the extension part 642 of the N wiring 64 in a plan view.

[0066] As an example, each of the substrate connecting portions 80 and 81 is a metal columnar body. In the Z direction, a bonding material 103 is interposed between one of the ends of the substrate connecting portion 80 and the relay wiring 55, and a bonding material 103 is interposed between the other of the ends and the relay wiring 65. In the Z direction, a bonding material 103 is interposed between one of the ends of the substrate connecting portion 81 and the N wiring 56, and a bonding material 103 is interposed between the other of the ends and the N wiring 64.

[0067] Alternatively, the board connection parts 80, 81 may be continuously connected to at least one of the front surface metal bodies 52, 62. In other words, the board connection parts 80, 81 may be provided integrally with the front surface metal bodies 52, 62 as part of the boards 50, 60. The board connection parts 80, 81 may be configured to include only the bonding material 103.

[0068] The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to an external device. The external connection terminals 90 are formed using a metal material with good conductivity, such as copper. The external connection terminals 90 are, for example, a plate material. The external connection terminals 90 are sometimes called leads. The external connection terminals 90 include main terminals 91, 92, and 93 and a signal terminal 94. The main terminals 91, 92, and 93 are external connection terminals 90 that are electrically connected to main electrodes of the semiconductor element 40. The signal terminal 94 includes a signal terminal 94H on the upper arm 9H side and a signal terminal 94L on the lower arm 9L side.

[0069] The main terminals 91, 92 are external connection terminals 90 electrically connected to the power supply lines 7, 8 described above. The main terminal 91 is electrically connected to the positive terminal of the smoothing capacitor 5. The main terminal 91 may be referred to as a positive terminal, a high potential power supply terminal, a P terminal, or the like. The main terminal 91 is connected to the P wiring 54 of the front metal body 52. ​​That is, the main terminal 91 is electrically connected to the drain electrode 40D of the semiconductor element 40H constituting the upper arm 9H. The main terminal 91 is connected to the vicinity of one end of the P wiring 54 in the Y direction. The main terminal 91 extends in the Y direction and protrudes outside the sealing body 30 from the side surface 30c.

[0070] The main terminal 92 is electrically connected to the negative terminal of the smoothing capacitor 5. The main terminal 92 may be referred to as a negative terminal, a low potential power supply terminal, an N terminal, etc. The main terminal 92 is connected to the N wiring 56 of the front surface metal body 52. ​​In other words, the main terminal 92 is electrically connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L. The main terminal 92 is connected to the vicinity of one end of the N wiring 56 in the Y direction. The main terminal 92 extends in the Y direction and protrudes outside the sealing body 30 from the side surface 30c.

[0071] The main terminal 93 is electrically connected to the winding 3a (stator coil) of the corresponding phase of the motor generator 3. The main terminal 93 may be referred to as an O terminal, an AC terminal, etc. The main terminal 93 is connected to the relay wiring 55 of the surface metal body 52. ​​In other words, the main terminal 93 is electrically connected to the connection point between the upper arm 9H and the lower arm 9L. The main terminal 93 is connected to the vicinity of one end of the relay wiring 55 in the Y direction. The main terminal 93 extends in the Y direction and protrudes outside the sealing body 30 from the side surface 30c.

[0072] The three main terminals 91, 92, and 93 are arranged side by side in the X direction. The main terminals 91, 92, and 93 are arranged in the X direction in the following order: main terminal 91, main terminal 92, and main terminal 93. The side surfaces of adjacent main terminals face each other over most of their entire length. For example, the side surface of main terminal 91 faces the side surface of main terminal 92.

[0073] The signal terminals 94 are electrically connected to the corresponding pads 40P of the semiconductor element 40 via connecting members such as bonding wires 110. The signal terminals 94H are connected to the pads 40P of the semiconductor element 40H via bonding wires 110. The signal terminals 94L are connected to the pads 40P of the semiconductor element 40L via bonding wires 110. The signal terminals 94 extend in the Y direction and protrude from the side surface 30d to the outside of the sealing body 30. The signal terminals 94 extend in the Y direction on the opposite side to the main terminals 91, 92, and 93. As an example, the signal terminals 94 include three signal terminals 94H and three signal terminals 94L.

[0074] 8, the external connection terminals 90 are configured as part of a lead frame 95. The lead frame 95 includes the external connection terminals 90, an outer periphery frame 96, tie bars 97, and a support frame 98. Each of the external connection terminals 90 is fixed in series to the outer periphery frame 96 and / or indirectly fixed via the tie bars 97. The outer periphery frame 96 and the tie bars 97 are removed as unnecessary parts during the manufacturing process of the semiconductor device 20.

[0075] The support frame 98 is connected to the front metal body 52 together with the main terminals 91, 92, and 93. The support frame 98 supports the substrate 50 together with the main terminals 91, 92, and 93. The support frame 98 is connected to the substrate 50 on the opposite side to the main terminals 91, 92, and 93 in the Y direction in order to stably support the substrate 50. The support frame 98 is separated from the outer frame 96 and the tie bar 97 when removing unnecessary portions. The semiconductor device 20 includes two support frames 98. One of the support frames 98 is connected to a portion of the P wiring 54 including the extension portion 543, and the other is connected to a portion of the relay wiring 55 including the extension portion 553. The support frame 98 extends in the Y direction and protrudes from the side surface 30d to the outside of the sealing body 30.

[0076] The number of signal terminals 94 provided on the lead frame 95 is not particularly limited. For example, the number may be the same as the total number of pads 40P of the semiconductor elements 40 arranged on the substrate 50. By connecting the same type of pads 40P of multiple semiconductor elements 40 to a common signal terminal 94, the number of signal terminals 94 may be less than the total number of pads 40P of the semiconductor elements 40.

[0077] As an example, the lead frame 95 has five signal terminals 94H, 94L. Then, depending on the number of pads 40P of the semiconductor element 40 mounted on the substrate 50, unnecessary signal terminals 94 are cut off after molding of the sealing body 30. In this embodiment, since the number of pads 40P of the semiconductor element 40H is three, three of the signal terminals 94H are provided for connection with the pads 40P, and the remaining two are cut off. Similarly, three of the signal terminals 94L are provided for connection with the pads 40P, and the remaining two are cut off. Therefore, the semiconductor device 20 has a terminal remainder 99 that is the remaining portion after a part is cut off. The semiconductor device 20 has four terminal remainders 99.

[0078] The signal terminals 94H, 94L are arranged such that the distance between the tip position of each terminal and the center of the corresponding pads 40P of the semiconductor element 40 is approximately equal to each other. The center is the center position of the pads 40P in the arrangement direction (X direction) of the pads 40P. Each of the signal terminals 94H, 94L has a straight portion 941 and an extension portion 942. The straight portion 941 is a portion that extends in the Y direction, and at least a part of the straight portion 941 is arranged outside the sealing body 30. The extension portion 942 is a portion that is continuously connected to one of the ends of the straight portion 941 and extends toward the corresponding pad 40P. At least a part of the extension portion 942 is covered by the sealing body 30. The multiple extension portions 942 extend radially from the center of the corresponding pad 40P of the semiconductor element 40, and are arranged in a substantially fan-shaped manner as a whole. This allows the lengths of the bonding wires 110 to be approximately equal to each other.

[0079] As described above, in the semiconductor device 20 of this embodiment, the multiple semiconductor elements 40 constituting the upper and lower arm circuits 9 for one phase are encapsulated by the encapsulant 30. The encapsulant 30 integrally encapsulates the multiple semiconductor elements 40, part of the substrate 50, part of the substrate 60, the multiple conductive spacers 70, the substrate connection portions 80, 81, and parts of the external connection terminals 90. The encapsulant 30 encapsulates the insulating base materials 51, 61 and the surface metal bodies 52, 62 of the substrates 50, 60.

[0080] The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60 disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is substantially flush with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0081] <Manufacturing method> Next, an example of a method for manufacturing the above-mentioned semiconductor device 20 will be described.

[0082] First, the semiconductor element 40, the substrates 50 and 60, the conductive spacer 70, the substrate connecting portions 80 and 81, and the lead frame 95 are prepared. As shown in Fig. 8, the lead frame 95 includes external connection terminals 90. The lead frame 95 is formed by subjecting a metal plate to processing such as pressing. The external connection terminals 90 are supported by an outer peripheral frame 96 directly and / or via tie bars 97.

[0083] Next, the substrate 50 and the lead frame 95 are bonded. First, the substrate 50 and the lead frame 95 are positioned relative to each other so that the bonding points of the lead frame 95 and the front surface metal body 52 overlap. Then, in this positioned state, the front surface metal body 52 and the lead frame 95 are solid-state bonded. Specifically, the main terminals 91, 92, 93 and the support frame 98 are bonded to the front surface metal body 52. ​​Figure 8 shows this bonded state.

[0084] Examples of solid-state bonding include ultrasonic bonding, room temperature bonding, friction stir bonding, diffusion bonding, and friction welding. In this embodiment, ultrasonic bonding is used as an example. In solid-state bonding, particularly ultrasonic bonding, bonding is easier when no plating film is formed on the metal surfaces of the surface metal body 52 and the lead frame 95. Therefore, the substrate 50 and the lead frame 95 are bonded before plating.

[0085] Next, a plating process is performed. A plating film is formed on the surfaces of the front surface metal body 52 and the lead frame 95 so as to cover the joint (solid-state joint) between the front surface metal body 52 and the lead frame 95. The plating film includes, for example, a film containing nickel as a main component. As an example, in this embodiment, a base film is formed by electroless Ni plating containing P (phosphorus), and then a top film is formed by Au plating.

[0086] Next, the semiconductor element 40 and the substrate connection parts 80, 81 are bonded to the substrate 50. Also, the conductive spacer 70 is bonded to the semiconductor element 40. That is, the connection objects are bonded to the substrate 50 using the bonding materials 100, 101, 103. Specifically, the drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 by the bonding material 100. The source electrode 40S is bonded to the conductive spacer 70 by the bonding material 101. The substrate connection parts 80, 81 are bonded to the surface metal body 52 by the bonding material 103. As an example, in this embodiment, solder is used as the bonding materials 100, 101, 103, so that the bonding can be performed all at once by reflow.

[0087] Next, wire bonding is performed. Specifically, the pads 40P of the semiconductor element 40H and the signal terminals 94H are electrically connected by bonding wires 110. Similarly, the pads 40P of the semiconductor element 40L and the signal terminals 94L are electrically connected by bonding wires 110.

[0088] Next, the substrate 60 is bonded. The conductive spacer 70 and the front surface metal body 62 are bonded via a bonding material 102. The substrate connection parts 80, 81 and the front surface metal body 62 are bonded via a bonding material 103. For example, in the case of solder, bonding can be performed all at once by reflow.

[0089] Next, the sealing body 30 is formed. In this embodiment, the sealing body 30 is molded by a transfer molding method. For example, the sealing body 30 is molded so that the substrates 50, 60 are completely covered, and cutting is performed after molding. The sealing body 30 is cut together with a part of the rear metal body 53, 63 of the substrate 50, 60. This exposes the rear surfaces 50b, 60b. The rear surface 50b is approximately flush with one surface 30a of the sealing body 30, and the rear surface 60b is approximately flush with the rear surface 30b. Alternatively, at least one of the rear surfaces 50b, 60b may be pressed against the cavity wall surface of a molding die and molded in a state of close contact. In this case, at least one of the rear surfaces 50b, 60b is exposed from the sealing body 30 when the sealing body 30 is molded.

[0090] Next, unnecessary portions of the lead frame 95, such as the outer peripheral frame 96, the tie bars 97, and unused signal terminals 94, are removed. In this manner, the semiconductor device 20 can be obtained.

[0091] <Joints and surrounding structures> Fig. 9 is a plan view showing a connection structure between the surface metal body 52 of the substrate 50 and the main terminals 91, 92, and 93. In Fig. 9, the surface metal body 52 and the main terminals 91, 92, and 93 are illustrated in a simplified form. Fig. 10 is an enlarged view of the region X shown by the dashed dotted line in Fig. 9. Fig. 11 is a cross-sectional view taken along the line XI-XI shown in Fig. 10.

[0092] As shown in FIG. 9, the main terminal 91 has a length in a direction (X direction) perpendicular to the extending direction (Y direction), that is, a width that is almost constant. The main terminal 93 also has a width that is almost constant, like the main terminal 91. The width of each of the main terminals 91 and 93 is wider than the width of the joint 120 formed between the front metal body 52. ​​On the other hand, the main terminal 92 has a widened portion 921 and a narrowed portion 922 that is narrower than the widened portion 921. The narrowed portion 922 is continuously connected to the widened portion 921 and forms the tip of the main terminal 92. In the main terminal 92, the width of the narrowed portion 922 is almost the same as the width of the joint 120. The width of the widened portion 921 is wider than the width of the joint 120. Of the main terminals 91, 92, and 93, the main terminals 91 and 93 correspond to wide terminals. The joint 120 corresponds to a solid-state joint.

[0093] As shown in Figs. 10 and 11, the main terminal 91, which is a wide terminal, has a bonding region 912 and a non-bonding region 913 as an overlapping region 911 with the front surface metal body 52 in a plan view. The bonding region 912 is a region that overlaps with the bonding portion 120 in a plan view. The bonding region 912 is a region that provides the bonding portion 120. The bonding portion 120 and the bonding region 912 have, for example, a substantially rectangular shape in plan view. The non-bonding region 913 is a remaining region of the overlapping region 911 excluding the bonding region 912. In Fig. 10, the part inside the dashed line indicating the bonding portion 120 is the bonding region 912, and the part outside the dashed line is the non-bonding region 913.

[0094] The non-bonding region 913 is provided so as to be adjacent to the bonding region 912 at least in the width direction. As an example, the non-bonding region 913 in this embodiment surrounds the bonding region 912 as shown in FIG. 10. The non-bonding region 913 surrounds the bonding region 912 all around. In the overlapping region 911, the bonding region 912 is provided in the center, and the non-bonding region 913 is provided on the periphery. In the overlapping region 911, the non-bonding region 913 is provided at both ends in the width direction and both ends in the extension direction. The non-bonding region 913 is provided adjacent to each of the four sides of the bonding region 912, which is substantially rectangular in plan view.

[0095] As shown in FIG. 11, the bonding region 912 forms a bonding portion 120 with the P wiring 54, which is the surface metal body 52. ​​The bonding portion 120 in this embodiment is an ultrasonic bonding portion. The non-bonding region 913 does not form a bonding portion 120, and has a gap 121 with the P wiring 54. The gap 121 is very small, on the order of several tens of μm. The gap 121 formed by ultrasonic bonding is 30 μm or less.

[0096] The semiconductor device 20 includes a plating film 130. The plating film 130 is provided on the lead frame 95 including the main terminal 91 and on the surface metal body 52 so as to cover the joint 120. The plating film 130 is formed by a plating process after ultrasonic bonding. The plating film 130 includes nickel as described above. The plating film 130 may be disposed in the gap 121. That is, the plating film 130 may be provided on the opposing surface of the non-bonded region 913 and the P wiring 54 that constitute the gap 121. The plating film 130 may be provided only in a part of the gap 121, or may be provided deep into the gap 121 so as to contact the joint 120. As an example, in this embodiment, the plating film 130 is provided only in a part of the gap 121 from the opening.

[0097] The thickness of the main terminal 91 may be substantially uniform over the entire area, or may vary in parts. As an example, the overlapping area 911 in this embodiment has a thin portion 914 and a thick portion 915. The thin portion 914 includes at least the bonding area 912. The thin portion 914 is a portion that comes into contact with an ultrasonic tool during ultrasonic bonding. The thin portion 914 is provided so as to include the bonding area 912, and therefore the bonding portion 120, in a plan view. The portion of the thin portion 914 near the outer circumferential end is a non-bonding area 913.

[0098] The thick portion 915 includes the bonding region 912. The thick portion 915 is provided on both ends of the main terminal 91 in the width direction. In other words, the thin portion 914 is located between the thick portions 915. The thickness of the thick portion 915 is approximately equal to the thickness of the main terminal 91 other than the overlapping region 911. A major portion of the non-bonding region 913 is thicker than the bonding region 912. The region between the dashed dotted lines shown in FIG. 11 is the bonding region 912.

[0099] Of the wide terminals, the main terminal 91 has been described above, but the main terminal 93 has a similar configuration.

[0100] <Summary of the First Embodiment> It is conceivable that the main terminal to be joined to the surface metal body of the substrate has a structure in which the tip portion providing the joint has the same width as the joint portion, and the rear end portion is wider than the joint portion. By making the tip portion thin, for example, it becomes easier to control the precision of the inclination of the joint surface. By making the rear end portion thicker, for example, it becomes possible to pass a large current. For example, the inductance can be reduced. However, there is a risk that the electric field will concentrate at the corner of the boundary between the tip portion and the rear end portion, which will reduce the durability life.

[0101] In this embodiment, the semiconductor device 20 includes a main terminal 91 that is a wide terminal. The main terminal 91 has a non-bonding region 913. The non-bonding region 913 is adjacent to the bonding region 912 at least in the width direction (X direction). That is, the width of the main terminal 91 (the width of the overlapping region 911) is wider than the width of the bonding portion 120. This results in less change in width of the main terminal 91. This suppresses electric field concentration, and ultimately improves the durability life of the main terminal 91. In addition, the main terminal 91 is capable of passing a large current. Inductance can be reduced. Since the width of the bonding portion 120 (bonding region 912) is narrower than the width of the overlapping region 911, it is easy to control the accuracy of the inclination of the bonding surface.

[0102] In a configuration in which a plating film is provided to cover the joints, that is, in a configuration in which the plating film 130 is formed after solid-state bonding, plating solution residue can be a problem. If plating solution residue is generated, it may seep out in a later process, for example, a solder reflow process, and may cause, for example, a decrease in the adhesion between the surface metal body and the sealing body and a decrease in the wettability of the solder (joint material). If the main terminal has multiple joints, plating solution is likely to remain between the joints, and plating solution residue is likely to be generated.

[0103] In this embodiment, the main terminal 91 has one joint portion 120. The non-jointed region 913 opens to the side. Therefore, even if plating solution gets into between the non-jointed region 913 and the front-surface metal body 52, the plating solution is easily discharged. The plating solution is less likely to remain in the gap 121 between the non-jointed region 913 and the front-surface metal body 52. ​​This makes it possible to prevent plating solution from remaining in the gap 121, that is, to prevent plating solution residue from being generated.

[0104] As described above, the semiconductor device 20 according to this embodiment can prevent problems caused by plating solution residue while improving the durability life of the main terminal 91. The semiconductor element 40 is connected to the front surface metal body 52 via the bonding material 100. By preventing plating solution residue, it is possible to prevent a decrease in the reliability of the connection between the semiconductor element 40 and the front surface metal body 52. ​​The same applies to the main terminal 93, which is a wide terminal.

[0105] The positional relationship between the main terminals 91, 93, which are wide terminals, and the semiconductor element 40 is not particularly limited. In this embodiment, the main terminals 91, 93 and the corresponding semiconductor elements 40H, 40L are arranged side by side in the extension direction (Y direction) of the main terminals 91, 93. In such a configuration, if plating solution residue is generated, the wettability of the solder, which is the bonding material 100, may decrease, and the connection reliability between the semiconductor element 40 and the front-surface metal body 52 may decrease. However, the above-mentioned configuration can suppress the generation of plating solution residue. Therefore, the decrease in the connection reliability between the semiconductor element 40 and the front-surface metal body 52 can be suppressed.

[0106] The semiconductor device 20 of this embodiment includes a sealing body 30. The above-described configuration suppresses the seepage of plating solution residue onto the surface of the front-surface metal body 52. ​​This makes it possible to suppress a decrease in adhesion of the sealing body 30 to the front-surface metal body 52.

[0107] The non-bonding region 913 in this embodiment surrounds the bonding region 912. Specifically, the non-bonding region 913 surrounds the bonding region 912 all around. The bonding region 912 is located inside the non-bonding region 913. The gap 121 formed between the non-bonding region 913 and the front surface metal body 52 is open to the outside all around. This effectively prevents plating solution from remaining in the gap 121. Furthermore, with this configuration, the bonding area can be ensured even if a positional deviation occurs in any direction.

[0108] The joint 120 in this embodiment is an ultrasonic joint. In the case of ultrasonic bonding, friction is not possible from the second point onwards in a multi-point joint, and the joint strength decreases. As described above, the joint 120 of each of the main terminals 91, 93 is one (one point). Therefore, it is possible to ensure the joint strength while employing ultrasonic bonding. In other words, it is possible to improve durability.

[0109] The non-bonding region 913 of this embodiment includes a portion that is thicker than the bonding region 912. In this manner, the bonding region 912 is thin. Therefore, the bonding portion 120 can be formed with a small load. In other words, the load during ultrasonic bonding can be reduced, and damage to the substrate 50 can be reduced. Since the non-bonding region 913 includes a portion that is thicker than the bonding region 912, the rigidity of the overlapping region 911, and therefore the main terminal 91, can be ensured.

[0110] In this embodiment, the gap 121 between the non-bonded region and the surface metal body is 30 μm or less. By narrowing the gap 121 in this manner, it becomes difficult for the plating solution to enter the gap 121, and it is possible to suppress the occurrence of plating solution residue. Also, in a configuration employing a sealing body 30 in which a filler is mixed into a resin, it becomes difficult for the filler to enter the gap 121. This makes it possible to suppress a decrease in durability due to a local increase in stress caused by the filler being caught.

[0111] <Modification> The configuration in which the non-bonding region 913 surrounds the bonding region 912 is not limited to the example in which it surrounds the entire periphery as shown in Fig. 10. For example, as shown in Fig. 12, the non-bonding region 913 may be provided so as to be adjacent to three sides of the bonding region 912. In Fig. 12, the bonding region 912 is provided over a predetermined range from the tip of the main terminal 91. The non-bonding region 913 is adjacent to three of the four sides of the bonding region 912 except for the side that coincides with the tip of the main terminal 91.

[0112] For example, as shown in FIG. 13, in a configuration in which the non-bonding region 913 surrounds the bonding region 912 all around, the bonding region 912 may be provided biased toward the tip side of the main terminal 91 from the center position of the overlapping region 911. The non-bonding region 913 has a tip portion 913a located on the tip side of the main terminal 91 in the extension direction, and a horizontally arranged portion 913b adjacent to the bonding region 912 in the width direction. The length L1 of the tip portion 913a is shorter than the length L2 of the horizontally arranged portion 913b. That is, the non-bonding region 913 is smaller on the semiconductor element 40 side in the extension direction (Y direction) than in the width direction (X direction). As a result, the gap 121 on the semiconductor element 40 side is small, so that it is possible to effectively suppress the plating solution from seeping out to the semiconductor element 40 side. Therefore, it is possible to effectively suppress the decrease in the connection reliability between the semiconductor element 40 and the front surface metal body 52.

[0113] 12 does not have the tip portion 913a. As a result, the non-bonding region 913 is smaller on the semiconductor element 40 side in the extension direction (Y direction) than in the width direction (X direction). This makes it possible to effectively prevent a decrease in the connection reliability between the semiconductor element 40 and the front surface metal body 52.

[0114] In the overlapping region 911, the positions of the bonding region 912 and the non-bonding region 913 are not particularly limited. The non-bonding region 913 may be provided adjacent to the bonding region 912, of which the overlapping region 911 has only one, at least in the width direction. For example, as shown in FIG. 14, the non-bonding region 913 may be provided adjacent to two sides of the bonding region 912. The bonding region 912 is provided over a predetermined range from the tip of the main terminal 91 in the Y direction. The bonding region 912 is provided over a predetermined range from one end of the main terminal 91 in the X direction. The non-bonding region 913 is adjacent to one of the sides of the bonding region 912 in the X direction. The non-bonding region 913 is adjacent to one of the sides of the bonding region 912 in the Y direction.

[0115] Although the example in which the central main terminal 92 among the main terminals 91, 92, and 93 is excluded from the wide terminal has been shown, the present invention is not limited to this. As shown in Fig. 15, the main terminal 92 may be a wide terminal like the main terminals 91 and 93.

[0116] Second embodiment This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to eliminate problems associated with ultrasonic bonding, various improvements may be made to the main terminal and / or the substrate.

[0117] <Semiconductor device> The basic configuration of the semiconductor device 20 according to this embodiment is similar to the schematic configuration of the semiconductor device 20 shown in the preceding embodiment (see FIGS. 2 to 8).

[0118] Although not shown, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, substrate connecting portions 80 and 81, and an external connection terminal 90. The semiconductor device 20 includes bonding materials 100 to 103 and a bonding wire 110.

[0119] A joint 120 is formed by solid-state bonding between the substrate 50 and the main terminals 91, 92, and 93. In this embodiment, ultrasonic bonding is used as the solid-state bonding. The joint 120 is an ultrasonic bonding portion. The other configurations are similar to the schematic configuration of the semiconductor device 20 shown in the preceding embodiment.

[0120] <Board damage> Fig. 16 is a cross-sectional view showing a reference example. In the reference example, the symbol of each element is the symbol of the related element of the semiconductor device 20 with r added to the end. In Fig. 16, the energy applied by the ultrasonic tool and the energy transmitted to the joining object are shown by solid arrows. The size of the solid arrow indicates the magnitude of the energy. Fig. 16 shows ultrasonic joining between a main terminal 93r and a surface metal body 52r (relay wiring 55r) as an example.

[0121] As shown in Fig. 16, the ultrasonic tool 140r has a plurality of convex portions 141r on the contact surface. The plurality of convex portions 141r are provided at a predetermined interval. On the other hand, the main terminal 93r has a plurality of concave portions 931r on the upper surface with which the ultrasonic tool 140r comes into contact. The plurality of concave portions 931r are provided at a predetermined interval. The convex portions 141r and the concave portions 931r are provided so that the convex portions 141r and the concave portions 931r mesh with each other.

[0122] With the projections and recesses engaged, the ultrasonic tool 140r vibrates in a direction perpendicular to the Z direction. Energy is transmitted from the ultrasonic tool 140r to the main terminal 93r, and then to the front metal body 52r located below the main terminal 93r. This vibration energy causes a relative displacement between the front metal body 52r and the back metal body 53r in a direction perpendicular to the Z direction. In other words, stress is generated in the substrate 50r. The ultrasonic vibration also generates heat in the substrate 50r.

[0123] Therefore, the substrate 50r, for example, the insulating base material 51r, is damaged. If the insulating base material 51r is damaged, there is a risk that the insulation reliability will decrease. In particular, the greater the energy applied by the ultrasonic tool 140r, the greater the damage to the substrate 50r.

[0124] <Bali> Fig. 17 is a cross-sectional view showing a reference example. Fig. 17 corresponds to Fig. 20 described later. In the example shown in Fig. 17, a main terminal 93r is formed by pressing a metal plate material of a certain thickness, that is, a flat metal plate material.

[0125] The main terminal 93r has a recess 931r for ultrasonic bonding. The recess 931r is formed by pressing. The main terminal 93 has a burr 932r due to pressing near the open end of the recess 931r. By ultrasonically bonding the lead frame having such a main terminal 93r to the substrate 50r, a bonded body 150r of the lead frame and the substrate 50r is formed.

[0126] Fig. 18 is a cross-sectional view showing a reference example. Fig. 18 shows a packed state of the bonded body 150r. As shown in Fig. 18, a plurality of bonded bodies 150r are stacked in the Z direction and packed. For simplicity, Fig. 18 shows two bonded bodies 150r.

[0127] In this packed state, in two joint bodies 150r adjacent to each other in the Z direction, the burrs 932r of the lower main terminal 93r come into contact with the back metal body 53 of the upper board 50r. This may cause scratches on the back metal body 53r or generate foreign matter.

[0128] <Structure around the joint> Fig. 19 is a perspective view showing the periphery of the joint between the main terminal 93 and the relay wiring 55 of the front surface metal body 52 in the semiconductor device 20 of this embodiment. Fig. 19 corresponds to the region XIX shown by the dashed dotted line in Fig. 8. Fig. 20 is a cross-sectional view taken along the line XX-XX in Fig. 19.

[0129] The main terminal 93 has a recess 933 provided to include the joint portion 120 in a plan view. The recess 933 opens on the upper surface of the main terminal 93 and has a predetermined depth in the Z direction. As a result, the thickness between the bottom surface 933a of the recess 933 and the lower surface (joint surface) of the main terminal 93, i.e., the thickness of the portion where the recess 933 is provided, is thinner than the other portions of the main terminal 93. A thickness T1 of a thick portion 934, which is a portion of the main terminal 93 excluding the portion where the recess 933 is provided, is thicker than a thickness T2 of the front metal body 52. ​​On the other hand, a thickness T3 of a thin portion 935, which is a portion where the recess 933 is provided, is thinner than a thickness T2 of the front metal body 52. ​​The thickness T3 of the thin portion 935 is the thickness of a portion where the recess 931 is not provided.

[0130] An ultrasonic tool comes into contact with a bottom surface 933a of the recess 933. The recess 933 provides an area in which the ultrasonic tool can ultrasonically vibrate. A part of the ultrasonic tool is disposed in the recess 933. As an example, the recess 933 in this embodiment is provided at the tip of the main terminal 93. The recess 933 is also open to the tip surface of the main terminal 93.

[0131] In the X direction, which is the width direction, the main terminal 93 has thick portions 934 at both ends. The thin portions 935 have a generally rectangular shape in plan view. Side surfaces 933b of the recess 933 are provided on the remaining three sides of the main terminal 93 excluding the side on the tip side.

[0132] A plurality of recesses 931 are formed in a bottom surface 933a of the recess 933. The rectangular area indicated by the solid line in FIG. 19 indicates a formation area 931a of the recesses 931. The height of burrs 932 present near the open end of the recess 931 is shorter than the depth of the recess 933. The entire burr 932 is disposed within the recess 933.

[0133] <Summary of the second embodiment> In this embodiment, the thickness T3 of the thin portion 935 including the joint portion 120 is thinner than the thickness T2 of the surface metal body 52 (T3 < T2). Thereby, even if the energy applied by the ultrasonic tool is reduced, the joint portion 120 can be formed. By reducing the energy, for example, the relative displacement between the surface metal body 52 and the back metal body 53 can be suppressed. Therefore, the damage to the substrate 50, for example, the damage to the insulating base material 51 can be reduced.

[0134] In this embodiment, the thickness T1 of the thick portion 934 is thicker than the thickness T2 of the surface metal body 52 (T1 > T2). The thin portion 935 is provided locally. Thereby, the rigidity around the joint portion can be ensured at the main terminal 93. In particular, the thick portions 934 are located on both sides in the width direction with respect to the thin portion 935. Therefore, when gripping and transporting the lead frame 95, the thick portions 934 on both sides function as beams, and the concentration of stress on the joint portion 120 can be suppressed.

[0135] In this embodiment, the height of the burr 932 provided on the bottom surface 933a of the recess 933 is shorter than the depth of the recess 933. Thereby, similar to the reference example shown in FIG. 18, when laminating and packing the joined body of the ultrasonically joined substrate 50 and the lead frame 95, the burr 932 of the lower joined body does not contact the back metal body 53 of the upper joined body. Therefore, it is possible to suppress damage to the back metal body 53 and the generation of foreign matters.

[0136] The angle θ formed by the bottom surface 933a and the side surface 933b of the recess 933 is not particularly limited, but is preferably 45 degrees or more. Further, the corner portion between the bottom surface 933a and the side surface 933b is preferably formed in an R shape. According to this, in the main terminal 93 provided with the thin portion 935, stress concentration at the corner portion can be avoided. For example, it is possible to suppress the occurrence of cracks in the main terminal 93 due to stress concentration.

[0137] Although the main terminal 93 has been described above, the same applies to the other main terminals 91 and 92 that are ultrasonically joined.

[0138] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0139] <Third embodiment> This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used for the present embodiment. In this embodiment, another configuration is proposed that can suppress damage to the substrate caused by ultrasonic bonding.

[0140] <Ultrasonic bonding process> 21 is a cross-sectional view showing the ultrasonic bonding process. As an example, the objects to be bonded are the surface metal body 52 and the main terminal 93.

[0141] Before ultrasonic bonding, contamination 160 exists on the bonding surfaces of the front surface metal body 52 and the main terminal 93. In ultrasonic bonding, an ultrasonic tool applies vibration energy to the main terminal 93 while applying pressure. This causes the contact points 122 between the front surface metal body 52 and the main terminal 93, which serve as the bonding starting points, to come into contact at high speed, forming a metallic bond due to friction and plastic flow. The metallic bond then expands, forming a bond 120.

[0142] <Method of Manufacturing Semiconductor Device> Fig. 22 is a cross-sectional view showing a manufacturing method of the semiconductor device 20 according to this embodiment. Fig. 22 corresponds to Fig. 20. Fig. 22 shows ultrasonic bonding between the surface metal body 52 (relay wiring 55) of the substrate 50 and the main terminal 93.

[0143] In this embodiment, before ultrasonic bonding, an uneven portion 936 is provided on the lower surface (bonding surface) of the main terminal 93. The uneven portion 936 is sometimes referred to as a roughened portion. Then, vibration energy is applied to the main terminal 93 having the uneven portion 936 while applying pressure with an ultrasonic tool.

[0144] The uneven portion 936 is formed by, for example, a roughening treatment. Specifically, laser roughening, roughening plating, sandblasting, chemical treatment, etc. are possible. The finer the pitch of the unevenness of the uneven portion 936, the more preferable. The pitch of the unevenness is, for example, on the order of nm or μm. The uneven portion 936 has very fine unevenness.

[0145] <Summary of the third embodiment> In this embodiment, ultrasonic bonding is performed using main terminal 93 having uneven portions 936 on the bonding surface. This makes it possible to obtain sufficient bonding with weaker pressure and amplitude than the ultrasonic bonding conditions for flat surfaces. In other words, even if the energy applied by the ultrasonic tool is reduced, it is possible to form bonded portion 120. The reduction in energy reduces the stress generated in substrate 50 and the heat generated by substrate 50. This makes it possible to reduce damage to substrate 50, for example, damage to insulating base material 51.

[0146] Fig. 23 shows an example of a semiconductor device 20 formed by the above-mentioned manufacturing method. Fig. 23 is an enlarged view of the periphery of the joint between the main terminal 93 and the substrate 50 in the semiconductor device 20. Fig. 23 corresponds to Fig. 20. The other configurations are similar to the schematic configuration of the semiconductor device 20 described in the preceding embodiment.

[0147] The uneven portion 936 is provided so as to include an area for forming the bonding portion 120 before ultrasonic bonding. The uneven portion 936 is provided taking into consideration misalignment. In the semiconductor device 20, the uneven portion 936 surrounds the bonding portion 120. The uneven portion 936 is adjacent to the bonding portion 120. The uneven portion 936 of the semiconductor device 20 is a portion that remains without being ultrasonically bonded.

[0148] There is no particular limitation on the number of sides to which the uneven portion 936 is adjacent to the bonding portion 120. For example, the uneven portion 936 may be adjacent to only one side of the bonding portion 120. All of the uneven portion 936 may contribute to the formation of the bonding portion 120, and the semiconductor device 20 may be configured not to have the uneven portion 936.

[0149] Although the main terminal 93 has been described above, the other main terminals 91 and 92 that are ultrasonically bonded are similarly described.

[0150] <Modification> Although an example has been shown in which the energy during ultrasonic bonding is reduced by providing the uneven portion 936 on the main terminal 93, the present invention is not limited to this. As shown in Fig. 24, an uneven portion 521 may be provided on the upper surface (bonding surface) of the front metal body 52. ​​Fig. 24 corresponds to Fig. 20.

[0151] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0152] <Fourth embodiment> This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used for the present embodiment. In this embodiment, another configuration is proposed that can suppress damage to the substrate caused by ultrasonic bonding.

[0153] 25 is an enlarged cross-sectional view of the periphery of the joint between the main terminal 93 and the substrate 50 in the semiconductor device 20 according to this embodiment. FIG. 25 corresponds to FIG.

[0154] As shown in Fig. 25, a plating film 131 is formed on the surface of the main terminal 93. A part of the plating film 131 constitutes a joint 120. The joint 120 contains the metal that constitutes the plating film 131. In Fig. 25, the joint 120 is illustrated in a simplified form.

[0155] The plating film 131 is mainly composed of a metal material different from that of the surface metal body 52 and the main terminal 93. The main metal component is, for example, Pd or Au.

[0156] <Summary of the Fourth Embodiment> According to this embodiment, the bonding time can be shortened by diffusing the different metals. Therefore, even if the energy applied by the ultrasonic tool is reduced, the bonded portion 120 can be formed. By reducing the energy, damage to the substrate 50, for example, damage to the insulating base material 51, can be reduced.

[0157] Although the main terminal 93 has been described above, the other main terminals 91 and 92 that are ultrasonically bonded are similarly described.

[0158] Although an example in which the plating film 131 is provided on the main terminal 93 has been shown, the present invention is not limited to this. A plating film mainly composed of a metal material different from that of the surface metal body 52 and the main terminal 93 may be provided on the surface of the surface metal body 52.

[0159] The configuration described in this embodiment can be combined with the configurations described in the preceding embodiments, except for the configuration in which the plating film 130 is formed after bonding and the configuration in which unevenness is provided on the bonding surface.

[0160] <Fifth embodiment> This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used for the present embodiment. In this embodiment, another configuration is proposed that can suppress damage to the substrate caused by ultrasonic bonding.

[0161] FIG. 26 is an enlarged cross-sectional view of the periphery of the joint between the main terminal 93 and the substrate 50 in the semiconductor device 20 according to this embodiment.

[0162] The back metal body 53 of the substrate 50 is patterned. The back metal body 53 has a main portion 531 and a separation portion 532. The main portion 531 occupies most of the back metal body 53. The main portion 531 is sometimes referred to as a main heat dissipation portion. The main portion 531 encapsulates the semiconductor element 40 in a plan view.

[0163] The separation portion 532 is electrically separated from the main portion 531. Between the separation portion 532 and the main portion 531, there is a gap formed by removing the metal body. The separation portion 532 may be referred to as an island. The separation portion 532 is provided directly below the joint portion 120. The separation portion 532 includes the joint portion 120 in a plan view. The other configurations are similar to the schematic configuration of the semiconductor device 20 described in the preceding embodiment.

[0164] The semiconductor device 20 is cooled by the cooler 170. The cooler 170 cools the semiconductor device 20 by circulating a refrigerant through a flow path inside the cooler 170. The refrigerant that flows through the flow path may be a refrigerant that changes phase, such as water or ammonia, or a refrigerant that does not change phase, such as an ethylene glycol-based refrigerant. A heat conductive member 180 such as silicone gel is disposed between the cooler 170 and the semiconductor device 20. The heat conductive member 180 is sometimes referred to as a thermal interface material (TIM). The heat conductive member 180 conforms to the opposing surfaces of the cooler 170 and the semiconductor device 20, and fills the gap between the opposing surfaces.

[0165] As an example, the coolers 170 are arranged on both sides of the semiconductor device 20 in the Z direction. The coolers 170 are arranged in a stacked manner on the semiconductor device 20. One of the coolers 170 is arranged so as to overlap the main portion 531 of the back surface metal body 53 in a plan view and not to overlap the separation portion 532. The cooler 170 is thermally connected to the main portion 531 of the back surface metal body 53. The cooler 170 cools the semiconductor device 20 via the main portion 531. The other of the coolers 170 is arranged so as to overlap the back surface metal body 63 in a plan view. The cooler 170 is thermally connected to the back surface metal body 63. The cooler 170 cools the semiconductor device 20 via the back surface metal body 63.

[0166] 27 shows an example of the pattern of the back surface metal body 53. The back surface metal body 53 has one main portion 531 and one separation portion 532. The separation portion 532 is provided so as to include the joint portions 120 of the main terminals 91, 92, and 93. The separation portion 532 is a common area for the main terminals 91, 92, and 93.

[0167] <Summary of the Fifth Embodiment> According to this embodiment, the separation portion 532 is provided directly below the joint portion 120. That is, the separation portion 532 is provided directly below the portion to which a load is applied during ultrasonic bonding. The separation portion 532 is separated from the other portion of the back surface metal body 53 (main portion 531). Compared to an integrated structure, the separation portion 532 is more easily deformed. This makes it possible to suppress the occurrence of stress in the substrate 50 during ultrasonic bonding. Therefore, damage to the substrate 50, for example damage to the insulating base material 51, can be reduced.

[0168] Moreover, the separating portion 532 provided directly below the bonding portion 120 is electrically separated from the main portion 531. Therefore, even if a crack occurs in the insulating base material 51 at a position overlapping with the separating portion 532 during ultrasonic bonding, the insulation properties of the semiconductor device 20 can be ensured on the main portion 531 side.

[0169] The pattern of the back metal body 53 is not limited to the example shown in Fig. 27. For example, the separation portion 532 may be provided individually for each of the main terminals 91, 92, and 93. In other words, a plurality of separation portions 532 may be provided.

[0170] The configuration described in this embodiment can be combined with the configuration described in the preceding embodiment.

[0171] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure includes the exemplified embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the omission of parts and / or elements of the embodiments. The disclosure includes the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are indicated by the description of the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the description of the claims.

[0172] The disclosure in the specification and drawings is not limited by the claims. The disclosure in the specification and drawings includes the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings without being bound by the claims.

[0173] When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, there are no intervening elements or layers. Other words used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0174] Spatially relative terms such as "inside," "outside," "back," "bottom," "low," "top," "top," and the like are utilized herein to facilitate the description of the relationship of one element or feature to another element or feature as depicted in the figures. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "directly below" other elements or features would be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0175] The vehicle drive system 1 is not limited to the above-mentioned configuration. For example, although an example has been shown in which one motor generator 3 is provided, the present invention is not limited to this. A plurality of motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion circuit, the present invention is not limited to this. For example, a configuration may be provided with a plurality of inverters. A configuration may be provided with at least one inverter and a converter. A configuration may be provided with only a converter.

[0176] Although an example has been shown in which the semiconductor element 40 has the MOSFET 11 as a switching element, the present invention is not limited to this. For example, an IGBT may also be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0177] The semiconductor device 20 may include a plurality of semiconductor elements 40 constituting each arm. The semiconductor device 20 may include a plurality of semiconductor elements 40H constituting the upper arm 9H, and a plurality of semiconductor elements 40L constituting the lower arm 9L. The drain electrodes 40D of the plurality of semiconductor elements 40H are connected to a common P wiring 54. The drain electrodes 40D of the plurality of semiconductor elements 40L are connected to a common relay wiring 55.

[0178] Although an example in which the semiconductor device 20 constitutes the upper and lower arm circuits 9 for one phase has been described, the present invention is not limited to this. The semiconductor device 20 may constitute only one of the arms. The semiconductor device 20 may constitute the upper and lower arm circuits 9 for multiple phases.

[0179] There is no particular limitation on the number of main terminals joined to the front surface metal body 52 of the substrate 50. The semiconductor device 20 only needs to include at least one main terminal joined to the front surface metal body 52.

[0180] The pattern of the surface metal body 52 and the arrangement of the surface metal body 52 and the main terminals 91, 92, 93 are not limited to the example given above.

[0181] Although an example in which the source electrode 40S is electrically connected to the surface metal body 62 of the substrate 60 has been described, the present invention is not limited to this. A metal plate may be used instead of the substrate 60. A configuration in which the substrate 60 is eliminated, that is, a one-sided heat dissipation structure may be used.

[0182] Although an example in which the semiconductor device 20 includes the conductive spacer 70 has been described, the present invention is not limited to this. A configuration without the conductive spacer 70 is also possible. For example, instead of the conductive spacer 70, the surface metal body 62 of the substrate 60 may have a protrusion.

[0183] Although an example in which the semiconductor device 20 includes the sealing body 30 has been described, the present invention is not limited to this. [Explanation of symbols]

[0184] 1... drive system, 2... DC power supply, 3... motor generator, 4... power conversion device, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11... MOSFET, 12... diode, 20... semiconductor device, 30... sealing body, 30a... one side, 30b... back side, 30c, 30d, 30e, 30f... side, 40, 40H, 40L... semiconductor element, 40D... drain electrode, 40S... source electrode, 4 0P...pad, 50...substrate, 50a...opposing surface, 50b...rear surface, 51...insulating base material, 52...front metal body, 521...concave and convex portion, 53...rear metal body, 531...main portion, 532...separation portion, 54...P wiring, 541...base portion, 542, 543...extension portion, 55...relay wiring, 551...base portion, 552, 553, 554...extension portion, 56...N wiring, 60...substrate, 60a...opposing surface, 60b...rear surface, 61...insulating base material, 62...front metal body, 63...rear metal body, 64...N wiring, 641...base portion, 642...extension portion, 65 ... relay wiring, 651... base, 652... extension portion, 70... conductive spacer, 80, 81... board connection portion, 90... external connection terminal, 91, 92, 93... main terminal, 911... overlapping region, 912... bonding region, 913... non-bonding region, 913a... tip portion, 913b... horizontally arranged portion, 914... thin portion, 915... thick portion, 921... widened portion, 922... narrowed portion, 931... recess, 931a... forming region, 932... burr, 933... recess, 933a... bottom surface, 933b... side surface, 934... thick portion, 935... thin portion, 936 ...concave and convex portion, 94, 94H, 94L...signal terminal, 941...straight portion, 942...extension portion, 95...lead frame, 96...peripheral frame, 97...tie bar, 98...support frame, 99...remaining terminal portion, 100, 101, 102, 103...bonding material, 110...bonding wire, 120...bonding portion, 121...gap, 122...contact, 130, 131...plating film, 140r...ultrasonic tool, 141r...protruding portion, 150...bonded body, 160...contamination, 170...cooler, 180...thermal conductive member

Claims

1. A semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on a back surface opposite to the one surface in a plate thickness direction; a substrate (50) having an insulating base material (51), a front surface metal body (52) disposed on a front surface of the insulating base material and electrically connected to the first main electrode, and a back surface metal body (53) disposed on a surface of the insulating base material opposite to the front surface; A bonding material (100) interposed between the first main electrode and the surface metal body and bonding the first main electrode and the surface metal body; A main terminal (91, 92, 93) forming a solid-phase welded portion (120) between the main terminal and the surface metal body; a plating film (130) provided on the surface metal body and the main terminal so as to cover the solid-state welded portion; The main terminal is The solid-phase welded portion formed between the surface metal body is one, The main terminal has a joining region (912) that provides the solid-phase welded portion as an overlapping region with the surface metal body in a plan view in the plate thickness direction, and a non-joining region (913) that is a region other than the joining region and is provided adjacent to the joining region at least in the width direction of the main terminal, A semiconductor device comprising wide terminals (91, 93) in which the width of the overlapping region is wider than the width of the solid-state welded portion.

2. 2. The semiconductor device according to claim 1, further comprising an encapsulant (30) that encapsulates the semiconductor element, at least a portion of the substrate including the surface metal body, the bonding material, and a portion of the main terminal including the solid-state bonded portion.

3. 3. The semiconductor device according to claim 1, wherein the solid-state welded portion is an ultrasonic welded portion.

4. The semiconductor device according to claim 3 , wherein the non-bonded region includes a portion that is thicker than the bonded region.

5. 5. The semiconductor device according to claim 1, wherein the semiconductor element and the wide terminal are arranged side by side in a direction perpendicular to the plate thickness direction and the plate width direction.

6. The semiconductor device according to claim 5 , wherein the non-bonded region is smaller on a side of the semiconductor element in the direction perpendicular to the width direction.

7. 7. The semiconductor device according to claim 1, wherein a gap between said non-bonding region of said wide terminal and said surface metal body is 30 μm or less.

8. 8. The semiconductor device according to claim 1, wherein the non-bonding region surrounds the bonding region.

9. The semiconductor device according to claim 8 , wherein the non-bonded region completely surrounds the bonded region.

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