Manufacturing method of semiconductor device and semiconductor device manufactured by the method

Abstract

To provide a manufacturing method of a semiconductor device, in which a post is arranged.SOLUTION: A manufacturing method of a semiconductor device includes steps of: providing a lower mold; arranging a plurality of semiconductor chips on the lower mold; arranging a plurality of first metal members on the lower mold, each first metal member being arranged to both sides of each semiconductor chip; providing an upper mold that faces the lower metal mold, and houses each semiconductor chip and each first metal member; filling a material between the lower metal mold and the upper metal mold; and removing the upper metal mold, the lower metal mold, and the first metal member, and forming a plurality of penetration holes in a seal material that is positioned on both sides of the semiconductor chip.SELECTED DRAWING: Figure 3H

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having posts arranged therein. [Background technology]

[0002] At present, the structural features of the power module molded with epoxy resin are designed in the mold. However, different molds need to be designed for products with different structural features, which means that the molds are not interchangeable in use, which increases the manufacturing cost of the molds. In addition, when it is desired to manufacture products with more complex structural features, the capabilities of the mold process are often limited. Summary of the Invention [Problem to be solved by the invention]

[0003] A method for manufacturing a semiconductor device having posts arranged thereon is provided. [Means for solving the problem]

[0004] According to one embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, the method including the steps of: providing a lower mold; arranging a plurality of semiconductor chips on the lower mold; arranging a plurality of first metal members on the lower mold, the first metal members being arranged on both sides of the semiconductor chip; providing an upper mold facing the lower mold and accommodating the semiconductor chip and the first metal members; filling an encapsulation material between the lower mold and the upper mold; and removing the upper mold, the lower mold, and the first metal members, and forming a plurality of through holes in the encapsulation material located on both sides of the semiconductor chip.

[0005] In some embodiments, the step of arranging a plurality of semiconductor chips and a plurality of first metal members on the lower mold includes the steps of providing a carrier, placing a tape on the carrier, placing the semiconductor chips and the first metal members on the tape, and placing the carrier on the lower mold.

[0006] In some embodiments, arranging a plurality of semiconductor chips on the lower die includes providing a carrier, placing the semiconductor chips on the carrier, and transferring the semiconductor chips from the carrier to the lower die. In some embodiments, the method for manufacturing a semiconductor device further includes fixing the semiconductor chips on the lower die with a plurality of second metal members arranged on the lower die. In some embodiments, arranging a plurality of first metal members on the lower die includes fixing the first metal members to the upper die, and bringing the upper die and the lower die into contact with each other.

[0007] In some embodiments, the method of manufacturing the semiconductor device further includes cutting the encapsulation material to form a plurality of semiconductor devices, each semiconductor device further including the semiconductor chip, the encapsulation material covering the semiconductor chip, and a through hole extending through the encapsulation material. In some embodiments, for each semiconductor device, the encapsulation material has a first sidewall and a second sidewall, the second sidewall is located on an opposite side of the semiconductor chip from the first sidewall, and the first sidewall and the second sidewall form an included angle of 90 degrees with a horizontal plane.

[0008] According to an embodiment of the present disclosure, there is provided a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device.

[0009] In some embodiments, the encapsulation material has a first sidewall and a second sidewall, the second sidewall being located on an opposite side of the semiconductor chip from the first sidewall, and the first sidewall and the second sidewall form an included angle of 90 degrees with a horizontal plane.

[0010] In some embodiments, the semiconductor chip further includes a plurality of alignment holes located on either side of the semiconductor chip, the alignment holes being closer to the semiconductor chip than the through holes.

[0011] In the present disclosure, when producing products with different sizes or different structural features, it is not necessary to design different molds, i.e., the same mold can be shared for different products, and the required products can be produced only by designing structurally removable posts and the subsequent cutting process. The process technology disclosed herein can increase the shareability of the mold, and the process technology disclosed herein can increase the shareability of the mold and save the development cost of the mold. In addition, since the structural features of the product do not need to be designed on the mold, the structural strength of the mold is also improved, and the durability of the mold is improved. Furthermore, the present disclosure can easily produce products with vertical sides using cutting and forming technology after demolding, overcoming the limitations of the traditional manufacturing process.

[0012] The present invention may be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: In accordance with standard industry practice, various features have not been drawn to scale, and in fact dimensions of various features have been arbitrarily expanded or reduced for clarity of illustration. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 3C] FIG. 3C is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3D] FIG. 3D is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3E] FIG. 3E is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3F] FIG. 3F is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3G] FIG. 3G is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 3H] FIG. 3H is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4C] FIG. 4C is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4D] FIG. 4D is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4E] FIG. 4E is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4F] FIG. 4F is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The following disclosure provides various different embodiments for implementing different features of the present disclosure. The following disclosure describes specific examples of each component and its arrangement for the sake of simplicity, and these specific examples are not intended to be limiting. For example, when a first feature component is described as being formed on or above a second feature component in an embodiment of the present disclosure, it may mean that the embodiment includes an embodiment in which the first feature component and the second feature component are in direct contact with each other, and may also mean that the embodiment includes an embodiment in which an additional feature component is formed between the first feature component and the second feature component so that the first feature component and the second feature component are not in direct contact with each other.

[0015] Additional steps may be performed before, during, or after the illustrated methods, and in other embodiments of the illustrated methods, some steps may be replaced or omitted.

[0016] Additionally, (in the detailed description below) spatially relative terms such as "lower", "below", "bottom", "up", "upper", "top" and the like are used for simplicity of description to describe the relationship of one element or feature to another element(s) and feature(s) in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 45 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted accordingly. In some embodiments of the present disclosure, the terms "approaching" such as "facing" may refer to structures directly contacting each other or not directly contacting each other, unless otherwise defined, and the terms facing and pressing may include a relationship in which the two structures are movable or the two structures are fixed.

[0017] As used herein, the terms "about", "approximately", "approximately", "substantially", "same", and "similar" generally indicate a range in which a property value is within + / - 15%, or within + / - 10%, or within + / - 5%, or within + / - 3%, or within + / - 2%, or within + / - 1%, or within + / - 0.5% of a stated value. Values ​​stated herein are approximate values, i.e., in the absence of a specific description of "about", "approximately", "approximately", "nearly", or "substantially", the meaning of "about", "approximately", "approximately", "nearly", or "substantially" may be implied.

[0018] In the present specification, terms such as "first", "second", "third" and the like are used to describe various components, parts, regions, layers and / or sections, but it should be understood that these terms should not be limited by these terms. These terms may be used only to distinguish one component, part, region, layer or section from another porous element, part, region, layer or section. Therefore, hereinafter, a first component, part, region, layer or section may be referred to as a second component, part, region, layer or section, without departing from the technology of the present disclosure.

[0019] Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by those skilled in the art. It will be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning that fits the relevant art and background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner unless otherwise defined.

[0020] As shown in Figure 1. According to one embodiment of the present disclosure, a semiconductor device 10 including mold-cladding is provided. Figure 1 is a schematic cross-sectional view of a semiconductor device 10 including mold-cladding.

[0021] As shown in FIG. 1, a semiconductor device 10 including a mold clad includes a lower mold 12, a carrier 14, a tape 16, a plurality of semiconductor chips 18, a plurality of first metal members 20, an encapsulation material 22, and an upper mold 24. The semiconductor chip 18 is disposed on the lower mold 12. The carrier 14 is disposed between the lower mold 12 and the semiconductor chip 18. The tape 16 is disposed between the carrier 14 and the semiconductor chip 18. The first metal members 20 are disposed on the lower mold 12 and are located on both sides of the semiconductor chip 18. More specifically, the semiconductor chip 18 and the first metal members 20 are disposed on the tape 16 and contact the tape 16. The encapsulation material 22 is filled between the lower mold 12 and the upper mold 24. The first metal member 20 penetrates the encapsulation material 22. The upper mold 24 and the lower mold 12 face each other and accommodate the semiconductor chip 18 and the first metal member 20.

[0022] In some embodiments, carrier 14 may comprise a metal, although the disclosure is not so limited and other suitable rigid materials having heat resistance, pressure resistance and support properties are also applicable to the present disclosure. In some embodiments, tape 16 may comprise a heat resistant tape, although the disclosure is not so limited and other suitable materials having heat resistance, pressure resistance and adhesive properties are also applicable to the present disclosure.

[0023] In some embodiments, the semiconductor chip 18 can include power components, although the disclosure is not limited thereto. In some embodiments, the semiconductor chip 18 can include a substrate 26, a first metal layer 28, a second metal layer 30, a conductive component 32, and a chip 33. The first metal layer 28 and the second metal layer 30 are disposed on opposite sides of the substrate 26, the first metal layer 28 contacts the tape 16, the conductive component 32 is disposed on the second metal layer 30 and connects to an external circuit (not shown), and the chip 33 is disposed on the second metal layer 30, as shown in FIG.

[0024] In some embodiments, the first metal member 20 may include a columnar metal structure, for example, a cylindrical metal structure, but the present disclosure is not limited thereto, and other suitable three-dimensional shapes are also applicable to the present disclosure and can be designed according to product requirements. In some embodiments, the first metal member 20 may include having a plurality of first metal members 20 between adjacent semiconductor chips 18, for example, an even number of first metal members 20, so that the semiconductor device formed after cutting between the adjacent semiconductor chips 18 has symmetrical through holes for subsequent screw attachment, but the present disclosure is not limited thereto, and other suitable arrangement positions and quantities of the first metal members 20 are also applicable to the present disclosure and can be designed according to product requirements.

[0025] In some embodiments, the encapsulation material 22 may include a solid molding material, a liquid molding material, an anisotropic conductive film (ACF), or a sheet molding material, although the present disclosure is not limited thereto and other suitable molding materials are also applicable to the present disclosure.

[0026] As shown in Figure 2. According to one embodiment of the present disclosure, a semiconductor device 100 including a mold cladding is provided. Figure 2 is a schematic cross-sectional view of the semiconductor device 100 including a mold cladding.

[0027] As shown in FIG. 2, the semiconductor device 100 including the mold cladding includes a lower mold 120, a plurality of semiconductor chips 180, a plurality of first metal members 200, a plurality of second metal members 210, an encapsulation material 220, and an upper mold 240. The semiconductor chip 180 is disposed on the lower mold 120. The first metal structure 200 is disposed on the lower mold 120 and is located on both sides of the semiconductor chip 180. The second metal member 210 is disposed on the lower mold 120 and is located on both sides of the semiconductor chip 180. More specifically, the semiconductor chip 180, the first metal member 200, and the second metal member 210 are disposed on the lower mold 120 and contact the lower mold 120, and the second metal member 210 is located closer to the semiconductor chip 180 than the first metal member 200. The encapsulation material 220 is filled between the lower mold 120 and the upper mold 240. The first metal member 200 penetrates the encapsulation material 220. The upper mold 240 and the lower mold 120 face each other and accommodate a semiconductor chip 180 , a first metal member 200 , and a second metal member 210 .

[0028] In some embodiments, the semiconductor chip 180 may include a power component, but the disclosure is not limited thereto. In some embodiments, the semiconductor chip 180 may include a substrate 260, a first metal layer 280, a second metal layer 300, a conductive component 320, and a chip 330. The first metal layer 280 is disposed on the lower layer of the substrate 260, the second metal layer 300 is disposed on the upper layer of the substrate 260, the first metal layer 280 contacts the lower die 120, the conductive component 320 is disposed on the second metal layer 300, and connects to an external circuit (not shown), and the chip 330 is disposed on the second metal layer 300, as shown in FIG. 2.

[0029] In some embodiments, the first metal member 200 may include a columnar metal structure, for example, a cylindrical metal structure, but the present disclosure is not limited thereto, and other suitable three-dimensional shapes are also applicable to the present disclosure and can be designed according to product requirements. In some embodiments, the first metal member 200 may include having a plurality of first metal members 200 between adjacent semiconductor chips 180, for example, an even number of first metal members 200, so that the semiconductor device formed after cutting between the adjacent semiconductor chips 180 has symmetrical through holes for subsequent screw attachment, but the present disclosure is not limited thereto, and other suitable arrangement positions and quantities of the first metal members 200 are also applicable to the present disclosure and can be designed according to product requirements.

[0030] In some embodiments, the second metal member 210 may include a columnar metal structure, for example, a cylindrical metal structure, but the present invention is not limited thereto, and other suitable three-dimensional shapes are also applicable to the present disclosure and may be designed according to product requirements. In the present disclosure, the second metal member 210 is disposed at a specific position on the lower mold 120, and serves as a positioning post for transferring the semiconductor chip 180 onto the lower mold 120, so that the semiconductor chip 180 is smoothly disposed at a predetermined position on the lower mold 120.

[0031] In some embodiments, the encapsulation material 220 may include a solid molding material, a liquid molding material, an anisotropic conductive film (ACF), or a sheet molding material, although the present disclosure is not limited thereto and other suitable molding materials are also applicable to the present disclosure.

[0032] 3A to 3H, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is provided, which are schematic cross-sectional views of the method for manufacturing a semiconductor device.

[0033] 3A, a carrier 14 is provided. A tape 16 is applied onto the carrier 14.

[0034] 3B, a semiconductor chip 18 is attached onto the tape 16. The semiconductor chip 18 includes a substrate 26, a first metal layer 28, a second metal layer 30, a conductive component 32, and a chip 33. The first metal layer 28 is disposed on the lower layer of the substrate 26, and the second metal layer 30 is disposed on the upper layer of the substrate 26, the first metal layer 28 contacts the tape 16, the conductive component 32 is disposed on the second metal layer 30 for subsequent connection of an external circuit, and the chip 33 is disposed on the second metal layer 30.

[0035] 3C, a plurality of first metal members 20 are attached to the tape 16 such that the first metal members 20 are located on both sides of the semiconductor chip 18. The positions where the first metal members 20 are attached to the tape 16 are positions where through holes will be formed subsequently.

[0036] 3D, a lower die 12 is provided. The carrier 14 having the tape 16, the semiconductor 18, and the first metal member 20 disposed thereon is disposed on the lower die 12, i.e., the semiconductor chip 18 and the first metal member 20 are disposed on the lower die 12.

[0037] 3E, an upper mold 24 is provided, and the upper mold 24 and the lower mold 12 face each other to accommodate the semiconductor chip 18 and the first metal member 20. After the upper mold 24 and the lower mold 12 are pressed together, an encapsulating material 22 is injected and filled between the lower mold 12 and the upper mold 24.

[0038] As shown in FIG. 3F, after filling with the sealing material 22, the upper mold 24, the lower mold 12, the first metal member 20, the carrier 14, and the tape 16 are removed, and multiple through holes 34 are formed in the sealing material 22 located on both sides of the semiconductor chip 18.

[0039] 3G, the encapsulation material 22 is cut, for example by laser cutting, to form a plurality of first semiconductor devices 36. Each of the first semiconductor devices 36 includes a semiconductor chip 18, an encapsulation material 22 covering the semiconductor chip 18, and a through hole 34 penetrating the encapsulation material 22.

[0040] 3H, in each first semiconductor device 36, the encapsulation material 22 has a first sidewall 22a and a second sidewall 22b, the second sidewall 22b being located on the opposite side of the semiconductor chip 18 from the first sidewall 22a, and the first sidewall 22a and the second sidewall 22b form an included angle of 90 degrees with a horizontal plane P. A first included angle α1 between the first sidewall 22a of the encapsulation material 22 and the horizontal plane P is 90 degrees, and a second included angle α2 between the second sidewall 22b of the encapsulation material 22 and the horizontal plane P is 90 degrees. At this point, the fabrication of the disclosed semiconductor device is completed.

[0041] 4A to 4F provide a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 4A to 4F are schematic cross-sectional views of the method for manufacturing a semiconductor device.

[0042] As shown in Fig. 4A, a carrier 140 is provided. A plurality of semiconductor chips 180 are disposed on the carrier 140. The semiconductor chip 180 includes a substrate 260, a first metal layer 280, a second metal layer 300, a conductive component 320, and a chip 330. The first metal layer 280 and the second metal layer 300 are disposed on opposite sides of the substrate 260, the conductive component 320 is disposed on the second metal layer 300 for subsequent connection of an external circuit, and the chip 330 is disposed on the second metal layer 300.

[0043] 4B, a lower mold 120 is provided. A plurality of second metal members 210 are arranged at specific positions on the lower mold 120 to serve as positioning posts for transferring the semiconductor chip 180 on the carrier 140 onto the lower mold 120. The second metal members 210 arranged on the lower mold 120 transfer the semiconductor chip 180 onto the lower mold 120, and the semiconductor chip 180 is arranged at a predetermined position on the lower mold 120.

[0044] As shown in FIG. 4C, an upper mold 240 is provided. A first metal member 200 is fixed to the upper mold 240. The upper mold 240 to which the first metal member 200 is fixed faces the lower mold 120, and accommodates the semiconductor chip 180, the first metal member 200, and the second metal member 210. That is, the semiconductor chip 180, the first metal member 200, and the second metal member 210 are disposed on the lower mold 120, the first metal member 200 and the second metal member 210 are located on both sides of the semiconductor chip 180, respectively, and the second metal member 210 is located closer to the semiconductor chip 180 than the first metal member 200. The position of the first metal member 200 is a position where a through hole will be formed later, and the upper mold 240 and the lower mold 120 are pressed against each other, and then the sealing material 220 is injected and filled between the lower mold 120 and the upper mold 240.

[0045] As shown in FIG. 4D, after filling with sealing material 220, upper mold 240, lower mold 120, first metal member 200, and second metal member 210 are removed, and multiple through holes 340 and multiple positioning holes 380 are formed in sealing material 220, with through holes 340 and positioning holes 380 located on both sides of semiconductor chip 180, respectively, and positioning holes 380 located closer to semiconductor chip 180 than through holes 340.

[0046] 4E, the encapsulation material 220 is cut, for example by laser cutting, to form a plurality of second semiconductor devices 360. Each second semiconductor device 360 ​​includes a semiconductor chip 180, an encapsulation material 220 covering the semiconductor chip 180, a through hole 340 penetrating the encapsulation material 220, and a positioning hole 380 adjacent to the semiconductor chip 180.

[0047] 4F, in each second semiconductor device 360, the encapsulation material 220 has a first sidewall 220a and a second sidewall 220b, the second sidewall 220b is located on the opposite side of the semiconductor chip 180 from the first sidewall 220a, and the first sidewall 220a and the second sidewall 220b form an included angle of 90 degrees with the horizontal plane P. A first included angle β1 between the first sidewall 220a of the encapsulation material 220 and the horizontal plane P is 90 degrees, and a second included angle β2 between the second sidewall 220b of the encapsulation material 220 and the horizontal plane P is 90 degrees. At this point, the fabrication of the disclosed semiconductor device is completed.

[0048] In the present disclosure, if it is desired to manufacture products with different sizes or different structural features, it is not necessary to design different molds, i.e., the same mold can be shared for different products, and the required products can be manufactured only by designing structurally removable posts and the subsequent cutting process. The process technology disclosed herein can increase the commonality of the mold, and the process technology disclosed herein can increase the commonality of the mold and save the development cost of the mold. In addition, since the structural features of the product do not need to be designed on the mold, the structural strength of the mold is also improved, and the durability of the mold is improved. Furthermore, the present disclosure can easily manufacture products with vertical sides using the cutting and forming technology after demolding, overcoming the limitations of the conventional manufacturing process.

[0049] The foregoing outlines the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to carry out the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure. Thus, the scope of protection must be determined through the claims. Moreover, although some embodiments of the present disclosure have been disclosed above, they are not intended to limit the scope of the present disclosure.

[0050] References to features, advantages, or similar language throughout this specification do not mean that all features and advantages that may be realized in the present disclosure should or can be realized in any single embodiment of the present disclosure. Rather, language referring to features and advantages is understood to mean that the particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same embodiment.

[0051] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Based on the description herein, one skilled in the art will recognize that the present disclosure can be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. [Explanation of symbols]

[0052] 10, 100 Semiconductor device including mold clad 12, 120 Lower mold 14, 140 Career 16 Tape 18, 180 Multiple semiconductor chips 20, 200: A plurality of first metal members 22, 220 Sealing material 22a, 220a first side wall of sealing material 22b, 220b second side wall of sealing material 24, 240 Upper mold 26, 260 board 28, 280 1st metal layer 30, 300 second metal layer 32, 320 Conductive components 33,330 chips 34, 340 through hole 36 First semiconductor device 210 Second metal member 360 Second semiconductor device 380 Positioning hole P Horizontal plane α1, β1 First included angle between the first side wall of the sealing material and the horizontal plane α2, β2: Second included angle between the second side wall of the encapsulating material and the horizontal plane

Claims

1. providing a lower mold; placing a plurality of semiconductor chips on the lower die; arranging a plurality of first metal members on the lower die, the first metal members being positioned on both sides of the semiconductor chip; providing an upper mold facing the lower mold and housing the semiconductor chip and the first metal member; filling a sealing material between the lower mold and the upper mold; and A method for manufacturing a semiconductor device, comprising the steps of removing the upper mold, the lower mold, and the first metal member, and forming a plurality of through holes in the sealing material located on both sides of the semiconductor chip.

2. The step of arranging a plurality of semiconductor chips and a plurality of first metal members on the lower die includes: Steps to provide a career, placing a tape on the carrier; placing the semiconductor chip and the first metal member on the tape; and The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of placing the carrier on the lower die.

3. The step of disposing a plurality of semiconductor chips on the lower die includes: Steps to provide a career, placing the semiconductor chip on the carrier; and 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of transferring the semiconductor chip from on the carrier onto the lower die.

4. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor chip is fixed onto the lower die by a plurality of second metal members arranged on the lower die.

5. The step of placing a plurality of first metal members on the lower die includes: fixing the first metal member to the upper die; and The method for manufacturing a semiconductor device according to claim 3 , further comprising a step of placing the upper mold and the lower mold opposite each other.

6. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of cutting the encapsulating material to form a plurality of semiconductor devices, each semiconductor device including the semiconductor chip, the encapsulating material covering the semiconductor chip, and a through hole penetrating the encapsulating material.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein in each semiconductor device, the sealing material has a first sidewall and a second sidewall, the second sidewall is located on the opposite side of the semiconductor chip from the first sidewall, and the first sidewall and the second sidewall form an included angle of 90 degrees with a horizontal plane.

8. 7. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 6, wherein the sealing material has a first sidewall and a second sidewall, the second sidewall is located on the opposite side of the semiconductor chip from the first sidewall, and the first sidewall and the second sidewall form an included angle of 90 degrees with a horizontal plane.

9. 7. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 6, further comprising a plurality of positioning holes located on both sides of the semiconductor chip, the positioning holes being located closer to the semiconductor chip than the through hole.

Images