Semiconductor device

Abstract

To provide a semiconductor device with a metal-insulator-metal (MIM) capacitor, in which the wiring area can be reduced to enable the size reduction.SOLUTION: A semiconductor device includes a substrate having a main surface and a back surface facing opposite to the main surface, a first metal film provided on the main surface of the substrate, a first insulating layer provided on the first metal film and in contact with the first metal film, a second metal film provided on the first insulating layer and in contact with the first insulating layer, a plurality of first vias penetrating the first insulating layer and connecting the first metal film and the second metal film, a second insulating layer provided on the second metal film and in contact with the second metal film, a third metal film provided on the second insulating layer, in contact with the second insulating layer, and insulated from the second metal film by the second insulating layer, a fourth metal film provided on the back surface of the substrate, and a second via penetrating the substrate to connect the first metal fil and the fourth metal film and provided at a position overlapping with the second metal film when viewed from a normal direction of the main surface. The second metal film, the second insulating layer, and the third metal film form a metal-insulator-metal (MIM) capacitor.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a wiring board incorporating a capacitive element. This wiring board includes two capacitive element electrode layers. The outer peripheral edge of one capacitive element electrode layer is located outside the outer peripheral edge of the other capacitive element electrode layer. A frame-shaped auxiliary capacitive element electrode layer connected to one capacitive element electrode layer surrounds the other capacitive element electrode layer. The inner peripheral edge of the auxiliary capacitive element electrode layer is located inside the outer peripheral edge of one capacitive element electrode layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, in a semiconductor device such as a monolithic microwave integrated circuit (MMIC), a metal-insulator-metal (MIM) capacitor may be provided in a wiring layer. Since the capacitance of the MIM capacitor is proportional to the area, depending on the capacitance of the MIM capacitor, the area of the MIM capacitor becomes large. On the other hand, in a semiconductor device such as an MMIC, miniaturization by reducing the wiring area is required.

[0005] The present disclosure has been made in view of such problems, and an object thereof is to enable miniaturization by reducing the wiring area in a semiconductor device having a MIM capacitor.

Means for Solving the Problems

[0006] In order to solve the above-described problems, a semiconductor device according to the present disclosure includes a substrate having a main surface and a back surface facing opposite to the main surface, a first metal film provided on the main surface of the substrate, a first insulating layer provided on the first metal film and in contact with the first metal film, a second metal film provided on the first insulating layer and in contact with the first insulating layer, a plurality of first vias penetrating the first insulating layer to connect the first metal film and the second metal film, a second insulating layer provided on the second metal film and in contact with the second metal film, a third metal film provided on the second insulating layer and in contact with the second insulating layer and insulated from the second metal film by the second insulating layer, a fourth metal film provided on the back surface of the substrate, and a second via penetrating the substrate to connect the first metal film and the fourth metal film. The second metal film, the second insulating layer, and the third metal film constitute a MIM capacitor. The plurality of first vias, the first metal film, and the second via are arranged side by side with the MIM capacitor in the normal direction of the main surface.

Advantages of the Invention

[0007] According to the present disclosure, in a semiconductor device having a MIM capacitor, miniaturization can be achieved by reducing the wiring area.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. [1] A semiconductor device according to one aspect of the present disclosure includes a substrate having a main surface and a back surface facing opposite to the main surface, a first metal film provided on the main surface of the substrate, a first insulating layer provided on the first metal film and in contact with the first metal film, a second metal film provided on the first insulating layer and in contact with the first insulating layer, a plurality of first vias penetrating the first insulating layer to connect the first metal film and the second metal film, a second insulating layer provided on the second metal film and in contact with the second metal film, a third metal film provided on the second insulating layer and in contact with the second insulating layer and insulated from the second metal film by the second insulating layer, a fourth metal film provided on the back surface of the substrate, and a second via penetrating the substrate to connect the first metal film and the fourth metal film. The second metal film, the second insulating layer, and the third metal film constitute a MIM capacitor. The plurality of first vias, the first metal film, and the second via are arranged side by side with the MIM capacitor in the normal direction of the main surface.

[0010] In the semiconductor device of [1] above, the plurality of first vias, the first metal film, and the second via are arranged side by side with the MIM capacitor in a direction perpendicular to the main surface of the substrate (i.e., the thickness direction of the substrate). Thereby, for example, compared with the case where a wiring (for example, a ground wiring) drawn from one electrode of the MIM capacitor is juxtaposed with the MIM capacitor as in the structure described in Patent Document 2, the wiring area can be reduced. Therefore, miniaturization of the semiconductor device having the MIM capacitor becomes possible.

[0011] [2]In the semiconductor device of [1] above, the third metal film may be provided avoiding the regions above each of the plurality of first vias. Each of the plurality of first vias is formed by forming a hole in the first insulating layer and filling the hole with a metal material. When filling the hole in the first insulating layer with a metal material, irregularities may occur on the upper surface of the first via. In that case, the upper surface of the second metal film formed on the first via and the upper surface of the second insulating layer formed on the second metal film will also inherit the irregularities. If the third metal film is formed on such irregularities, the breakdown voltage of the MIM capacitor may decrease. By providing the third metal film avoiding the regions above each of the plurality of first vias, a decrease in the breakdown voltage of the MIM capacitor can be avoided.

[0012] [3]In the semiconductor device of [1] or [2] above, the substrate may be a silicon carbide substrate.

[0013] [4]In the semiconductor device of [1] or [3] above, when each of the plurality of first vias is cut in a cross-section along the main surface of the substrate, the cross-sectional shape of each of the plurality of first vias is a polygon, and each of the plurality of corner portions of the polygon may be larger than 90 degrees. When the cross-sectional shape of each of the plurality of first vias is a polygon, the smaller the angle of each of the plurality of corner portions of the polygon, the slower the deposition rate of the metal material at the plurality of corner portions when filling the hole in the first insulating layer with the metal material, and irregularities occur on the upper surface of the first via. And the irregularities on the upper surface of the first via become prominent when each of the plurality of corner portions of the polygon is 90 degrees or less. Therefore, if each of the plurality of corner portions of the polygon is made larger than 90 degrees, the irregularities on the upper surface of the first via can be suppressed to be small. Thus, the irregularities on the upper surface of the second metal film formed on the first via and the upper surface of the second insulating layer formed on the second metal film can also be suppressed to be small, and a decrease in the breakdown voltage of the MIM capacitor can be suppressed.

[0014] [5]In the semiconductor device of [4] above, the polygon may be a regular polygon. In that case, when filling the hole in the first insulating layer with a metal material, the growth rate of the metal material can be made closer to uniform along the circumferential direction of the hole, and the irregularities on the upper surface of the first via can be further suppressed.

[0015] [6] In the semiconductor device according to [1] to [5] above, the plurality of first vias may include at least one metal material selected from the group consisting of Au, Cu, W, Ti, Al, Ru, and Co. In that case, film formation of the material of the first via by a CVD process or a plating process becomes easy with respect to the side wall portion of the hole having a high aspect ratio.

[0016] [Details of Embodiments of the Present Disclosure] Specific examples of the semiconductor device of the present disclosure will be described below with reference to the drawings. Note that the present invention is not limited to these examples, and is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and redundant descriptions are omitted.

[0017] FIG. 1 is a plan view showing a semiconductor device 10 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view of the semiconductor device 10 taken along line II-II shown in FIG. 1. As shown in FIGS. 1 and 2, the semiconductor device 10 of the present embodiment includes a substrate 20, a semiconductor layer 21, a first metal film 41, a plurality of first vias 42, a second metal film 31, a third metal film 33, a first insulating layer 51, a second insulating layer 52, a fourth metal film 61, and a second via 62.

[0018] The substrate 20 has a main surface 201 and a back surface 202 facing the opposite side of the main surface 201. Both the main surface 201 and the back surface 202 are flat and parallel to each other. The substrate 20 is an insulating substrate such as a silicon carbide (SiC) substrate or a sapphire substrate, for example.

[0019] The semiconductor layer 21 is a semiconductor layer provided on the main surface 201 of the substrate 20 by epitaxial growth. The semiconductor layer 21 contains, for example, a III-V group compound semiconductor as its composition. In one embodiment, the semiconductor layer 21 contains a GaN-based semiconductor as its composition. The semiconductor layer 21 may include a channel layer and a barrier layer for a high electron mobility transistor (HEMT). The channel layer and the barrier layer may be a GaN layer and an AlGaN layer, respectively. The combined thickness of the substrate 20 and the semiconductor layer 21 is, for example, 10 μm.

[0020] The first metal film 41 is a metal film provided on the main surface 201 of the substrate 20. In one example, the first metal film 41 is provided on the semiconductor layer 21 and is in contact with the semiconductor layer 21. The first metal film 41 has conductivity. The first metal film 41 is formed by laminating, for example, a nickel (Ni) layer and a gold (Au) layer in this order. The thickness of the first metal film 41 is, for example, 0.1 μm or more and 10 μm or less. The first metal film 41 has a planar shape such as a rectangle when viewed from the normal direction of the main surface 201 (hereinafter also referred to as a plan view). When referring to the planar shape hereinafter, it represents the shape in a plan view. The length of the short side of the first metal film 41 is, for example, 1 μm or more and 1000 μm or less. The length of the long side of the first metal film 41 is, for example, 1 μm or more and 1000 μm or less. Note that the planar shape of the first metal film 41 is not limited to a rectangle.

[0021] The first insulating layer 51 is an insulating layer provided on the first metal film 41 and on the region of the main surface 201 where the first metal film 41 is not provided. The first insulating layer 51 is in contact with other surfaces (the upper surface and the side surfaces) excluding the surface in contact with the main surface 201 of the first metal film 41 and the region of the main surface 201. In other words, the first insulating layer 51 covers the first metal film 41 on the main surface 201. The first insulating layer 51 is provided over the entire surface on the main surface 201. The first insulating layer 51 has insulating properties. The first insulating layer 51 is, for example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or a silicon oxynitride film (SiON). The thickness of the first insulating layer 51 on the first metal film 41 is, for example, 0.2 μm or more and 10 μm or less.

[0022] The second metal film 31 is a metal film provided on the first insulating layer 51 and is in contact with the first insulating layer 51. The second metal film 31 includes a portion overlapping with the first metal film 41 when viewed from the normal direction of the main surface 201 of the substrate 20. In the illustrated example, the entire second metal film 31 overlaps with the first metal film 41 in plan view. The second metal film 31 has conductivity. The second metal film 31 is formed, for example, by laminating a first titanium (Ti) layer, a gold (Au) layer, and a second titanium (Ti) layer in this order. The thickness of the second metal film 31 is, for example, 0.1 μm or more and 10 μm or less. The second metal film 31 has a planar shape such as a rectangle, for example. The range of the length of the short side and the range of the length of the long side of the second metal film 31 are the same as those of the first metal film 41 described above, for example. The planar shape of the second metal film 31 is not limited to a rectangle, either.

[0023] A plurality of first vias 42 are arranged in a one-dimensional or two-dimensional manner in a plane along the main surface 201 on the first metal film 41. In the illustrated example, the plurality of first vias 42 are arranged in two rows along the long side direction of the first metal film 41, but the arrangement of the plurality of first vias 42 is not limited to this. The plurality of first vias 42 may be arbitrarily arranged at appropriate intervals from each other in the plane along the main surface 201. The plurality of first vias 42 penetrate the first insulating layer 51 and connect the first metal film 41 and the second metal film 31 to each other. Each first via 42 contains at least one metal material selected from the group consisting of, for example, gold (Au), copper (Cu), tungsten (W), titanium (Ti), aluminum (Al), ruthenium (Ru), and cobalt (Co). The second metal film 31 is electrically connected to the first metal film 41 by the plurality of first vias 42. If the plurality of first vias 42 are not provided, the second metal film 31 is insulated from the first metal film 41 by the first insulating layer 51. The number of the plurality of first vias 42 is at least 2. By increasing the number of the plurality of first vias 42, the second metal film 31 can be more firmly electrically connected to the first metal film 41. For example, four or more of the plurality of first vias 42 may be provided. For example, when the MIM capacitor 70 is used in a high-frequency circuit, by providing four or more of the plurality of first vias 42, the influence of the parasitic inductance of one first via 42 on the high-frequency circuit can be reduced.

[0024] In the illustrated example, when each first via 42 is cut in a cross section along the main surface 201, the cross-sectional shape of each first via 42 is circular. The diameter of each first via 42 is, for example, 0.5 μm or more and 10 μm or less. Each first via 42 is not limited to a circular shape and can have various cross-sectional shapes. FIG. 3 shows, as an example, a case where the cross-sectional shape of each first via 42 is polygonal. Each of the plurality of corners of the polygon is greater than 90 degrees. As in the illustrated example, the polygon may be a regular polygon such as a regular hexagon or a regular octagon.

[0025] The second insulating layer 52 is an insulating layer provided on the second metal film 31 and on the region of the first insulating layer 51 where the second metal film 31 is not provided. The second insulating layer 52 is in contact with the other surfaces (upper surface and side surfaces) of the second metal film 31 except for the surface in contact with the first insulating layer 51, and with the region of the first insulating layer 51. In other words, the second insulating layer 52 covers the second metal film 31 on the first insulating layer 51. The second insulating layer 52 is provided over the entire surface on the first insulating layer 51, that is, over the entire main surface 201. The second insulating layer 52 has insulating properties. The dielectric constant of the second insulating layer 52 is larger than the dielectric constant of the first insulating layer 51. The second insulating layer 52 is, for example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or a silicon oxynitride film (SiON). The thickness of the second insulating layer 52 on the second metal film 31 is smaller than the thickness of the first insulating layer 51 on the first metal film 41, and is, for example, 0.01 μm or more and 0.5 μm or less.

[0026] The third metal film 33 is a metal film provided on the second metal film 31 and on the second insulating layer 52, and is in contact with the second insulating layer 52. The third metal film 33 includes a portion overlapping both the first metal film 41 and the second metal film 31 when viewed in the normal direction of the main surface 201. In the illustrated example, the entire third metal film 33 overlaps both the first metal film 41 and the second metal film 31. Also, in the present embodiment, the third metal film 33 overlaps a plurality of first vias 42 when viewed in the normal direction of the main surface 201. The third metal film 33 has conductivity. The third metal film 33 is insulated from the second metal film 31 by the second insulating layer 52. The second metal film 31, the second insulating layer 52, and the third metal film 33 constitute a MIM capacitor 70. That is, the MIM capacitor 70 is arranged side by side with the first metal film 41 and a plurality of first vias 42 in the normal direction of the main surface 201. The MIM capacitor 70 may be used as a coupling capacitor or a filter capacitor in the semiconductor device 10. Similar to the second metal film 31, the third metal film 33 is formed by laminating, for example, a first titanium (Ti) layer, a gold (Au) layer, and a second titanium (Ti) layer in this order. The thickness of the third metal film 33 is, for example, 0.1 μm or more and 10 μm or less. The third metal film 33 has a planar shape such as a rectangle, for example. The range of the length of the short side and the range of the length of the long side of the third metal film 33 are, for example, the same as those of the first metal film 41 described above. The planar shape of the third metal film 33 is not limited to a rectangle either.

[0027] The fourth metal film 61 is a metal film provided on the back surface 202 of the substrate 20 and is in contact with the back surface 202. The fourth metal film 61 is provided over the entire back surface 202. The fourth metal film 61 has conductivity. When the semiconductor device 10 is mounted on a metal base (not shown) defined as a reference potential, the fourth metal film 61 is joined to the metal base by a conductive adhesive such as silver paste, for example. Thereby, the fourth metal film 61 is defined as the reference potential. The fourth metal film 61 is formed by laminating, for example, a nickel (Ni) layer and a gold (Au) layer on the back surface 202 in this order.

[0028] The second via 62 is a via that penetrates the substrate 20 and the semiconductor layer 21 to interconnect the first metal film 41 and the fourth metal film 61. The second via 62 is provided at a position overlapping the second metal film 31 and the third metal film 33 when viewed from the normal direction of the main surface 201. That is, the second via 62 is aligned with the MIM capacitor 70 in the normal direction of the main surface 201. The second via 62 is composed of, for example, a gold (Au) layer and a copper (Cu) layer deposited on the gold (Au) layer. The maximum diameter of the second via 62 is larger than the diameter of the first via 42 and is, for example, 100 μm. The second via 62 may have a frustum shape that becomes thinner as it approaches the main surface 201 of the substrate 20. In this case, the maximum diameter of the portion of the second via 62 in contact with the first metal film 41 is, for example, 10 μm.

[0029] The operation and effect of the semiconductor device 10 of the present embodiment having the above configuration will be described. In the semiconductor device 10, the second metal film 31, which is the lower electrode of the MIM capacitor 70, and the first metal film 41 provided on the main surface 201 of the substrate 20 are connected by a plurality of first vias 42. In addition, the first metal film 41 and the fourth metal film 61 provided on the back surface 202 of the substrate 20 are connected by the second via 62. In this way, the MIM capacitor 70, the plurality of first vias 42, the first metal film 41, and the second via 62 are aligned in a direction perpendicular to the main surface 201 and the back surface 202 of the substrate 20 (that is, the thickness direction of the substrate 20). Thereby, for example, compared with the case where a wiring (for example, a ground wiring) drawn from one electrode of the MIM capacitor 70 is juxtaposed with the MIM capacitor 70 as in the structure described in Patent Document 2, the wiring area can be reduced. Therefore, the semiconductor device 10 having the MIM capacitor 70 can be miniaturized.

[0030] In addition, in the present embodiment, instead of using the first metal film 41 as the lower electrode of the MIM capacitor 70, the second metal film 31 provided on the first insulating layer 51 is used as the lower electrode of the MIM capacitor 70. Since the flatness is improved during the film formation process of the first insulating layer 51 on the upper surface of the first insulating layer 51, the flatness of the upper surface of the second metal film 31 provided on the first insulating layer 51 is also improved. Therefore, the thickness of the second insulating layer 52 formed on the second metal film 31 can be made closer to uniform, and the quality such as the breakdown voltage of the MIM capacitor 70 can be improved.

[0031] FIG. 4 is a cross-sectional view showing a semiconductor device 11 according to a modified example. The semiconductor device 11 has the same configuration as the semiconductor device 10 except for the points described below. In the semiconductor device 11, each first via 42 has a slight recess 421 on its upper surface. Each first via 42 is formed by forming a hole in the first insulating layer 51 and filling the hole by metal plating or metal CVD. When filling the hole in the first insulating layer 51 with a metal material, the metal material is deposited on the inner surface of the hole at the same deposition rate as the bottom surface of the hole. Therefore, since the deposition of the metal material is delayed near the center of the hole, the upper surface of the first via 42 may be recessed as shown in FIG. 4. In that case, the upper surface of the second metal film 31 formed on the first via 42 and the upper surface of the second insulating layer 52 formed on the second metal film 31 also inherit the recess. For example, a recess may occur on the upper surface of the second metal film 31 due to the recess on the upper surface of the first via 42, thereby causing unevenness on the upper surface of the second metal film 31. Even in such a semiconductor device 11, the same operational effects as those of the semiconductor device 10 can be achieved.

[0032] Note that the smaller the diameter of the hole, the smaller the recess 421 formed on the upper surface of the first via 42. On the other hand, if the ratio (A / B) of the inner diameter A to the depth B of the hole is too small, it becomes difficult for the metal material to enter the hole, and voids are likely to occur in the first via 42. In one example, the ratio (A / B) of the inner diameter A to the depth B, in other words, the ratio (D / L) of the diameter D to the length L of the first via 42 is 0.5 or more and 20 or less.

[0033] As shown in FIG. 3, the cross-sectional shape of each first via 42 is a polygon, and each of the plurality of corner portions of the polygon may be larger than 90 degrees. When the cross-sectional shape of each of the plurality of first vias 42 is a polygon, the smaller the angle of each of the plurality of corner portions of the polygon, the slower the deposition rate of the metal material at the plurality of corner portions when the holes in the first insulating layer 51 are filled with the metal material, and the more likely unevenness occurs on the upper surface of the first via 42. Then, the unevenness on the upper surface of the first via 42 becomes prominent when each of the plurality of corner portions of the polygon is 90 degrees or less. Therefore, if each of the plurality of corner portions of the polygon is made larger than 90 degrees, the unevenness on the upper surface of the first via 42 can be suppressed to a small level. That is, the flatness of the upper surface of the first via 42 can be improved.

[0034] Suppressing the unevenness on the upper surface of the first via 42 leads to suppressing the unevenness that occurs on the upper surface of the second metal film 31 formed on the first via 42 and the upper surface of the second insulating layer 52 formed on the second metal film 31. The unevenness on the upper surface of the second metal film 31 and the upper surface of the second insulating layer 52 causes problems such as a locally increased electric field between the second metal film 31 and the third metal film 33 in the MIM capacitor 70. By suppressing the unevenness on the upper surface of the first via 42, such problems can be eliminated, and a decrease in the breakdown voltage of the MIM capacitor 70 can be suppressed.

[0035] As in this embodiment, the polygon may be a regular polygon. In that case, when the holes in the first insulating layer 51 are filled with the metal material, the growth rate of the metal material can be made closer to uniform along the circumferential direction of the hole, and the unevenness on the upper surface of the first via 42 can be further suppressed.

[0036] [Modification Example] FIG. 5 is a plan view showing a semiconductor device 12 according to a modified example of the present disclosure. FIG. 6 is a cross-sectional view of the semiconductor device 12 taken along line VI-VI shown in FIG. 5. The difference between the semiconductor device 12 and the semiconductor device 10 of the above embodiment lies in the range where the third metal film 33 is provided. That is, the third metal film 33 of this modified example is provided avoiding the region directly above each first via 42. In other words, the third metal film 33 of this modified example is provided in a region that does not overlap with each first via 42 when viewed from the normal direction of the main surface 201. Except for this point, the configuration of the semiconductor device 12 is the same as that of the semiconductor device 10.

[0037] Specifically, the planar shape of the third metal film 33 of this modified example is slightly smaller than the planar shape of the second metal film 31. The third metal film 33 of this modified example is disposed between one row and the other row of a plurality of first vias 42 aligned in two rows when viewed from the normal direction of the main surface 201. In other words, one row of the plurality of first vias 42 is arranged along one long side of the third metal film 33, and the other row of the plurality of first vias 42 is arranged along the other long side of the third metal film 33.

[0038] As described above, irregularities may be formed on the upper surface of each first via 42. In that case, the upper surface of the second metal film 31 formed on the first via 42 and the upper surface of the second insulating layer 52 formed on the second metal film 31 will also inherit the irregularities. When the third metal film 33 is formed on such irregularities, the thickness uniformity of the second insulating layer 52 in the MIM capacitor 70 may be impaired, and the breakdown voltage of the MIM capacitor 70 may decrease. By providing the third metal film 33 avoiding the region directly above each of the plurality of first vias 42 as in this modified example, a decrease in the breakdown voltage of the MIM capacitor 70 can be avoided.

[0039] The semiconductor device according to the present disclosure is not limited to the above-described embodiments, and various other modifications are possible. For example, in the above embodiment, an example is shown in which the semiconductor layer 21 is provided on the substrate 20 and the first metal film 41 is provided on the semiconductor layer 21. However, the first metal film 41 may be in contact with the substrate 20 without the semiconductor layer 21 being provided. Even in that case, the functions and effects of the above embodiment can be suitably achieved.

Explanation of Reference Numerals

[0040] 10, 11, 12... Semiconductor device 20... Substrate 21... Semiconductor layer 31... Second metal film 33... Third metal film 41... First metal film 42... First via 51... First insulating layer 52... Second insulating layer 61... Fourth metal film 62... Second via 70... MIM capacitor 201... Main surface 202... Back surface 421... Depression

Claims

1. A substrate having a main surface and a back surface facing away from the main surface; a first metal film provided on the main surface of the substrate; a first insulating layer provided on the first metal film and in contact with the first metal film; a second metal film provided on the first insulating layer and in contact with the first insulating layer; a plurality of first vias penetrating the first insulating layer and connecting the first metal film and the second metal film; a second insulating layer provided on the second metal film and in contact with the second metal film; a third metal film provided on the second insulating layer, in contact with the second insulating layer, and insulated from the second metal film by the second insulating layer; a fourth metal film provided on the back surface of the substrate; a second via that penetrates the substrate and connects the first metal film and the fourth metal film; Equipped with the second metal film, the second insulating layer and the third metal film constitute an MIM capacitor; the first metal film, the plurality of first vias, and the second via are aligned with the MIM capacitor in a normal direction to the main surface.

2. The semiconductor device according to claim 1 , wherein said third metal film is provided so as to avoid regions above each of said plurality of first vias.

3. 3. The semiconductor device according to claim 1, wherein the substrate is a silicon carbide substrate.

4. 2. The semiconductor device according to claim 1, wherein a cross-sectional shape of each of the plurality of first vias when cut along a cross section along the main surface is polygonal, and each of a plurality of corners of the polygon has an angle greater than 90 degrees.

5. The semiconductor device according to claim 4 , wherein said polygon is a regular polygon.

6. 3. The semiconductor device according to claim 1, wherein the plurality of first vias include at least one metal material selected from the group consisting of Au, Cu, W, Ti, Al, Ru, and Co.

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