Semiconductor device

Abstract

To provide a semiconductor device in which the efficiency of an amplifier does not decrease easily.SOLUTION: A semiconductor device includes a transistor provided on a main surface of a substrate having the main surface and including a first electrode including an ohmic electrode, a metal-insulator-metal (MIM) capacitor formed on the transistor and including a second electrode, a first insulating layer provided on the second electrode, and a third electrode provided on the first insulating layer, a second insulating layer provided between the first electrode and the second electrode, and a plurality of vias penetrating the second insulating layer and electrically connecting the first electrode and the second electrode to each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a technique related to a semiconductor element having a MIM capacitor. The technique includes a MIM capacitor formed on a semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode. On the upper electrode of the MIM capacitor, a first interlayer insulating film having a first via hole and a second interlayer insulating film having a second via hole are formed. On the second interlayer insulating film, a wiring layer connected to the upper electrode through the first via hole and the second via hole is formed, and the vertical distance between the lower electrode of the MIM capacitor and the wiring layer increases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventionally, in an amplifier, a transistor such as a HEMT (High Electron Mobility Transistor) and a MIM (Metal-Insulator-Metal) capacitor are arranged side by side in a direction along the substrate surface on a substrate and connected via a routing wire. As the routing wire becomes longer, the inductance component of the circuit increases. Due to the influence of this inductance component, impedance adjustment becomes complicated, and the wiring length tends to become long. As the wiring length increases, losses increase, and the efficiency of the amplifier tends to decrease.

[0005] An object of the present disclosure is to provide a semiconductor device in which the efficiency of an amplifier is less likely to decrease.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment of the present disclosure is provided on a main surface of a substrate having a main surface, and includes a transistor having a first electrode including an ohmic electrode, and a transistor formed on the transistor, a second electrode, a first insulating layer provided on the second electrode, and a MIM capacitor having a third electrode provided on the first insulating layer, a second insulating layer provided between the first electrode and the second electrode, and a plurality of vias penetrating the second insulating layer and electrically connecting the first electrode and the second electrode to each other.

Effects of the Invention

[0007] According to the present disclosure, a semiconductor device in which the efficiency of an amplifier is less likely to decrease can be provided.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 18

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. [1] A semiconductor device according to an embodiment of the present disclosure is provided on a main surface of a substrate having a main surface, and includes a transistor having a first electrode including an ohmic electrode, a MIM capacitor formed on the transistor and having a second electrode, a first insulating layer provided on the second electrode, and a third electrode provided on the first insulating layer, a second insulating layer provided between the first electrode and the second electrode, and a plurality of vias penetrating the second insulating layer and electrically connecting the first electrode and the second electrode to each other.

[0010] In the semiconductor device of the above [1], the MIM capacitor is formed on the transistor, and the transistor and the MIM capacitor are electrically connected by a plurality of vias. As a result, the distance between the transistor and the MIM capacitor is shorter than the distance between the transistor and the MIM capacitor when the MIM capacitor and the transistor are arranged side by side in a direction along the main surface and the transistor and the MIM capacitor are connected by a routing wire. Therefore, the magnitude of the inductance component between the transistor and the MIM capacitor in the configuration of the semiconductor device of [1] is smaller than that in the case where the transistor and the MIM capacitor are connected by a routing wire. Accordingly, since the loss is reduced, it is possible to realize a semiconductor device in which the efficiency of the amplifier is less likely to decrease.

[0011] Further, since the surface of the ohmic electrode becomes rough due to annealing during manufacturing, the surface of the first electrode also becomes rough. However, in the film formation process of the second insulating layer provided between the first electrode and the second electrode, the surface of the second insulating layer is unlikely to inherit the state of the surface of the first electrode. That is, even if the surface of the first electrode has irregularities, the surface of the second insulating layer can be made close to flat. Thereby, the surface of the second electrode formed on the second insulating layer can also be made flat. Therefore, it is possible to suppress the local increase in the electric field, and the reliability of the MIM capacitor can be improved.

[0012] In addition, since a plurality of vias are interposed between the first electrode and the second electrode, the sum of the cross-sectional areas of the plurality of vias in the plane along the main surface becomes larger than the case where a single via is provided, so that current easily flows between the first electrode and the second electrode. Therefore, losses are reduced, and a decrease in the efficiency of the amplifier can be suppressed.

[0013] [2] In the semiconductor device of [1] above, the MIM capacitor may be provided avoiding the gate electrode of the transistor. Thereby, the parasitic capacitance generated between the MIM capacitor and the gate electrode can be reduced. Therefore, by reducing the inductance component and the parasitic capacitance together, a decrease in the efficiency of the amplifier can be further suppressed.

[0014] [3] In the semiconductor device of [1] above, the MIM capacitor may fit on the first electrode when viewed from a direction perpendicular to the main surface. Thereby, since the portion where the MIM capacitor is formed is limited to the first electrode, the parasitic capacitance generated between the MIM capacitor and the region other than the first electrode can be reduced. Therefore, by reducing the inductance component and the parasitic capacitance together, a decrease in the efficiency of the amplifier can be further suppressed.

[0015] [4] In the semiconductor device of [1] above, the MIM capacitor may have a first portion that fits on the first electrode when viewed from a direction perpendicular to the main surface, and a second portion that is provided outside the transistor when viewed from a direction perpendicular to the main surface and is continuous with the first portion. Thereby, in both the first portion and the second portion, the parasitic capacitance generated between the MIM capacitor and the region other than the first electrode can be reduced. In addition, since the MIM capacitor has the second portion in addition to the first portion, the area of the electrode of the MIM capacitor increases, and the capacitance of the MIM capacitor can be increased. In the semiconductor device of [4], the MIM capacitor is provided, for example, for the purpose of DC cut. When the capacitance of the MIM capacitor increases, the cut-off frequency becomes lower. Therefore, DC cut can be performed at a lower frequency, and DC cut can be performed in a wide frequency band.

[0016] [5] In the semiconductor device according to [1] to [4] above, the transistor may be a HEMT including a III-V semiconductor. Generally, since a HEMT can withstand high voltages and can handle large currents, high-output amplification is possible. Therefore, when the transistor is a HEMT, the efficiency of the amplifier can be further improved.

[0017] [6] In the semiconductor device according to [1] to [5] above, the dielectric constant of the first insulating layer may be larger than that of the second insulating layer. Thereby, the capacitance of the MIM capacitor can be made larger. In the semiconductor device of [6], the MIM capacitor is provided for the purpose of, for example, DC cut. As the capacitance of the MIM capacitor increases, the cut-off frequency becomes lower. Therefore, DC cut can be performed at a lower frequency, and DC cut can be performed in a wide frequency band.

[0018] [7] In the semiconductor device according to [1] to [6] above, the thickness of the first insulating layer in the direction perpendicular to the main surface may be thinner than the thickness of the second insulating layer in the direction perpendicular to the main surface. By making the thickness of the first insulating layer thinner, the capacitance of the MIM capacitor can be increased. In the semiconductor device of [7], the MIM capacitor is provided for the purpose of, for example, DC cut. As the capacitance of the MIM capacitor increases, the cut-off frequency becomes lower. Therefore, DC cut can be performed at a lower frequency, and DC cut can be performed in a wide frequency band.

[0019] [8] In the semiconductor device according to [1] to [7] above, the thickness of the second electrode in the direction perpendicular to the main surface may be thinner than the thickness of the first electrode in the direction perpendicular to the main surface. By making the thickness of the second electrode thinner, the film formation time of the insulating layer embedding the second electrode can be shortened.

[0020] [9] In the semiconductor device of [1] to [8] above, the lengths of a plurality of vias in the direction perpendicular to the main surface may be 0.1 μm or more and 10 μm or less. When connecting a transistor and a MIM capacitor by a routing wire, the distance between the transistor and the MIM capacitor is likely to be a long distance, such as several hundred μm or more. On the other hand, according to the semiconductor device of [1] above, for example, as in [9] above, the distance of the wiring (via) between the transistor and the MIM capacitor can be shortened. Thereby, it is possible to realize a semiconductor device in which the efficiency of the amplifier is less likely to decrease.

[0021] [Details of Embodiments of the Present Disclosure] Specific examples of the semiconductor device of the present disclosure will be described below with reference to the drawings. Note that the present invention is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and redundant descriptions are omitted.

[0022] (First Embodiment) FIG. 1 is a plan view showing a semiconductor device A according to the first embodiment of the present disclosure. FIG. 2 is a circuit diagram of the semiconductor device A according to the first embodiment of the present disclosure. The semiconductor device A includes an amplifier 1, a bias circuit 2, an input terminal 15, and an output terminal 72. The input terminal 15 is provided on the input side of the amplifier 1, and the output terminal 72 is provided on the output side of the amplifier 1.

[0023] Amplifier 1 includes transistor 10 and a plurality (two in the illustrated example) of MIM capacitors 20. Bias circuit 2 includes inductor 40, MIM capacitor 60, external power supply 52 (see FIG. 2), and pad 51 (see FIG. 1) for connecting to external power supply 52. In transistor 10, the gate is connected to input terminal 15. The source is connected to ground potential line 3 (see FIG. 2). The drain is connected to the first electrode of each MIM capacitor 20 and is also connected to one end of inductor 40 of bias circuit 2 via wiring 33. The second electrode of each MIM capacitor 20 is connected to output terminal 72 via wiring 32. The other end of inductor 40 is connected to the first electrode of MIM capacitor 60 and is also connected to the positive electrode of external power supply 52 via pad 51. Inductor 40 is, for example, a spiral inductor. The second electrode of MIM capacitor 60 and the negative electrode of external power supply 52 are connected to ground potential line 3.

[0024] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 1. Amplifier 1 includes substrate 8 having main surface 9 and back surface 18. Transistor 10 is provided on main surface 9 of substrate 8. Transistor 10 includes a plurality (two in the illustrated example) of drain electrodes 11, a plurality (three in the illustrated example) of source electrodes 12, a plurality (four in the illustrated example) of gate electrodes 13, and semiconductor layer 19. The plurality of drain electrodes 11 and the plurality of source electrodes 12 are alternately arranged in a predetermined direction y, and a gap is provided between each drain electrode 11 and each source electrode 12. Each gate electrode 13 is disposed in the gap between drain electrode 11 and source electrode 12. Each of drain electrode 11 (first electrode) and source electrode 12 is configured to include ohmic electrode 35 and wiring 16. Transistor 10 is, for example, a HEMT including a III-V semiconductor in semiconductor layer 19. Semiconductor layer 19 is composed of semiconductors such as GaAs, InGaAs, AlGaAs, and GaN, for example.

[0025] The ohmic electrode 35 is provided on the semiconductor layer 19. The ohmic electrode 35 is in the form of a film. The material of the ohmic electrode 35 is, for example, titanium (Ti) or nickel (Ni). The wiring 16 is provided on the ohmic electrode 35 and is in contact with the ohmic electrode 35. The material of the wiring 16 is, for example, gold (Au). The thickness of the wiring 16 in the direction perpendicular to the main surface 9 is, for example, 0.1 μm or more and 10 μm or less. The width W of the wiring 16 along the y direction, which is the arrangement direction of the drain electrode 11, the source electrode 12, and the gate electrode 13, is, for example, 1 μm or more and 1000 μm or less. The area of the wiring 16 as viewed from the direction perpendicular to the main surface 9 is, for example, 1 μm 2 or more and 1000000 μm 2 or less.

[0026] The amplifier 1 further includes a field plate 14, a back surface electrode 37, and a via 17. The field plate 14 is provided on the gate electrode 13 and between the gate electrode 13 and the drain electrode 11. The field plate 14 is defined at the reference potential and controls the distribution of the electric field. The back surface electrode 37 is provided over the entire back surface 18 of the substrate 8. The back surface electrode 37 is defined at the reference potential by being connected to the ground potential line 3 shown in FIG. 2. The via 17 is provided so as to penetrate the substrate 8 and the semiconductor layer 19 from the back surface 18 of the substrate 8 toward the source electrode 12. The via 17 is in contact with the ohmic electrode 35 of the back surface electrode 37 and the source electrode 12. That is, the source electrode 12 is connected to the ground potential line 3 via the via 17 and the back surface electrode 37.

[0027] FIG. 4 is a plan view showing the transistor 10. Each drain electrode 11 and each source electrode 12 have a long rectangular shape along the x direction intersecting the y direction and along the main surface 9. One ends of the wirings 16 of the plurality of source electrodes 12 in the x direction are connected to each other by a wiring 91 long in the y direction provided in a region outside the ohmic electrode 35. One ends of the plurality of gate electrodes 13 in the x direction are connected to each other by a wiring 92 long in the y direction. The input terminal 15 (see FIGS. 1 and 2) is connected to the gate electrode 13 via the wiring 92.

[0028] Refer to FIG. 3 again. The amplifier 1 further includes a plurality of vias 81, a wiring 32, and insulating layers 38 and 39. The insulating layer 38 (second insulating layer) is provided between the wiring 16 and a lower electrode 21 (described later) of the MIM capacitor 20. That is, the insulating layer 38 is provided on the drain electrode 11 and the source electrode 12. Further, the insulating layer 38 is also provided on the gate electrode 13 and is provided over the entire semiconductor layer 19. The material of the insulating layer 38 is, for example, an insulating material containing Si such as SiO 2 , SiN, SiON or a resin material such as polyimide. The insulating layer 39 is provided on the insulating layer 38. The insulating layer 39 is provided over the entire insulating layer 38. The material of the insulating layer 39 is, for example, an insulating material containing Si such as SiO 2 , SiN, SiON or a resin material such as polyimide. The plurality of vias 81 penetrate the insulating layer 38 and electrically connect the wiring 16 and the lower electrode 21. That is, the plurality of vias 81 are interposed between the wiring 16 and the lower electrode 21. The plurality of vias 81 are located on the drain electrode 11 when viewed from a direction perpendicular to the main surface 9. The length of the via 81 in the direction perpendicular to the main surface 9 is, for example, 0.1 μm or more and 10 μm or less. Also, the diameter of each via 81 is, for example, 0.5 μm or more and 10 μm or less. The number of vias 81 is, for example, 1 or more and 1,000,000 or less. The material of the member constituting the via 81 is, for example, at least one of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd, Cr, Co, and Ru.

[0029] Each MIM capacitor 20 includes a lower electrode 21 (second electrode), a dielectric layer 22 (first insulating layer), and an upper electrode 23 (third electrode). Each MIM capacitor 20 is formed on each drain electrode 11. The MIM capacitor 20 has a rectangular shape that is long along the x direction when viewed from a direction perpendicular to the main surface 9 (see FIG. 1). Each MIM capacitor 20 of the present embodiment is provided in the amplifier 1 for the purpose of DC cut.

[0030] Each MIM capacitor 20 is provided avoiding the gate electrode 13 of the transistor 10. As in this embodiment, in one example, each MIM capacitor 20 is located on the drain electrode 11 of the transistor 10 when viewed from a direction perpendicular to the main surface 9. The lower electrode 21 is provided between the insulating layer 38 and the insulating layer 39. The material of the lower electrode 21 is, for example, at least one of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd, and Cr. In the y direction, the width of the lower electrode 21 is the same as or less than the width of the drain electrode 11. The width of the lower electrode 21 along the y direction is, for example, 1 μm or more and 1000 μm or less. The area of the lower electrode 21 when viewed from a direction perpendicular to the main surface 9 is, for example, 1 μm 2 or more and 1000000 μm 2 or less. The thickness of the lower electrode 21 in the direction perpendicular to the main surface 9 is thinner than the thickness of the wiring 16 in the same direction. The thickness of the lower electrode 21 in the same direction is, for example, 0.1 μm or more and 10 μm or less.

[0031] The dielectric layer 22 is provided between the insulating layer 38 and the insulating layer 39 and is formed over the insulating layer 38 and the lower electrode 21. The dielectric layer 22 is in contact with the entire area of the surface of the lower electrode 21 facing the upper electrode 23. In other words, the lower electrode 21 is in contact with the insulating layer 38 on the surface connected to the plurality of vias 81, and is in contact with the dielectric layer 22 on all of the surfaces along the x direction among the other surfaces. The material of the dielectric layer 22 is, for example, an insulating material containing Si such as SiO 2 , SiN, SiON, or a resin material such as polyimide, or a metal oxide such as hafnium oxide (HfO) or aluminum oxide (Al 2 O 3 ).

[0032] The upper electrode 23 is provided on the lower electrode 21 and on the dielectric layer 22. The upper electrode 23 has a portion provided on the insulating layer 39 and a portion provided along the surface of the opening 39a formed in the insulating layer 39. In addition, the upper electrode 23 further has a portion in contact with the dielectric layer 22 at the bottom of the opening 39a. The opening 39a is located above the lower electrode 21 when viewed from a direction perpendicular to the main surface 9. The material of the upper electrode 23 is, for example, at least one of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd, and Cr.

[0033] The thickness of the dielectric layer 22 in the direction perpendicular to the main surface 9 is thinner than the thicknesses of the insulating layers 38 and 39 in the same direction. The thickness of the dielectric layer 22 in the direction perpendicular to the main surface 9 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the insulating layer 38 in the same direction is, for example, 0.2 μm or more and 10 μm or less. The thickness of the insulating layer 39 in the same direction is, for example, 0.1 μm or more and 10 μm or less. Also, the dielectric constant of the dielectric layer 22 is larger than the dielectric constants of the insulating layers 38 and 39. The dielectric constant of the dielectric layer 22 is, for example, 20 p (pico) F / m or more and 500 p (pico) F / m or less. The dielectric constant of the insulating layer 38 is, for example, 10 p (pico) F / m or more and 200 p (pico) F / m or less. The dielectric constant of the insulating layer 39 is, for example, 10 p (pico) F / m or more and 200 p (pico) F / m or less.

[0034] FIG. 5 is a cross-sectional view taken along the V-V line shown in FIG. 1. FIG. 6 is a cross-sectional view taken along the VI-VI line shown in FIG. 1. In addition to the wiring 32 and the wiring 33 described above, the amplifier 1 includes a plurality of vias 82 and a wiring 34. The wiring 34, the plurality of vias 82, the wiring 33, and the wiring 32 are provided between both the transistor 10 and the MIM capacitor 20 and the output terminal 72. The wiring 34 is integrally formed with the wiring 16 in the same wiring layer as the wiring 16 and extends outward from the wiring 16 to the outside of the transistor 10. The wiring 33 is provided on the wiring 34. The wiring 33 is integrally formed with the lower electrode 21 in the same wiring layer as the lower electrode 21 and extends outward from the lower electrode 21 to the outside of the transistor 10. One end of the wiring 33 is connected to the lower electrode 21. The other ends of the wirings 33 and 34 are connected to one end of the inductor 40 (see FIG. 1) of the bias circuit 2. The wiring 33 functions as a transmission path for direct current. The plurality of vias 82 are interposed between the wiring 34 and the wiring 33 and are dispersed over the entire area of the wiring 34 and the wiring 33. The plurality of vias 82 are provided through the insulating layer 38 (see FIG. 3) and connect the wiring 34 and the wiring 33 to each other. The wiring 32 is provided on the wiring 33. The wiring 32 is integrally formed with the upper electrode 23 in the same wiring layer as the upper electrode 23 and extends outward from the upper electrode 23 to the outside of the transistor 10. Referring to FIG. 1, one end of the wiring 32 is connected to the upper electrode 23 of each MIM capacitor 20. The other end of the wiring 32 is connected to the output terminal 72 via an inductor 90 (omitted in FIG. 1). The wiring 32 functions as a transmission path for the signal (RF signal) amplified in the transistor 10.

[0035] The effects obtained by the semiconductor device A having the above configuration will be described. FIG. 12 is a plan view showing a semiconductor device D which is a comparative example. FIG. 13 is a circuit diagram of the semiconductor device D which is a comparative example. The semiconductor device D differs from the semiconductor device A in the following points. Instead of the amplifier 1, the semiconductor device D includes an amplifier 1D. The amplifier 1D has a MIM capacitor 20D instead of the MIM capacitor 20. The MIM capacitor 20D is not provided on the transistor 10 but is provided outside the transistor 10. Also, the amplifier 1D has a routing wiring portion 100 that connects the transistor 10 and the MIM capacitor 20D. In the semiconductor device D, as the routing wiring portion 100 becomes longer, the inductance component (indicated by an inductor symbol in FIG. 12) in the semiconductor device D becomes larger. Due to the influence of this inductance component, impedance adjustment becomes complicated and the wiring length tends to become longer. As the wiring length becomes longer, the loss increases and the efficiency of the amplifier 1D tends to decrease.

[0036] On the other hand, in the semiconductor device A, the MIM capacitor 20 is formed on the transistor 10, and the drain electrode 11 of the transistor 10 and the lower electrode 21 of the MIM capacitor 20 are electrically connected by a plurality of vias 81. Thereby, the distance between the transistor 10 and the MIM capacitor 20 becomes shorter than the distance between the transistor 10 and the MIM capacitor 20D in the case where the drain electrode 11 and the lower electrode 21 are connected by a routing wiring portion 100. Therefore, the magnitude of the inductance component between the transistor 10 and the MIM capacitor 20 in the configuration of the semiconductor device A is smaller than that in the case where the transistor 10 and the MIM capacitor 20D are connected by a routing wiring portion 100. Therefore, since the loss is reduced, it is possible to realize the semiconductor device A in which the efficiency of the amplifier is less likely to decrease.

[0037] In addition, since the surface of the ohmic electrode 35 becomes rough due to annealing during manufacturing, the surface of the wiring 16 also becomes rough. However, in the film formation process of the insulating layer 38 provided between the wiring 16 and the lower electrode 21, the surface of the insulating layer 38 is unlikely to inherit the state of the surface of the wiring 16. That is, even if the surface of the wiring 16 has irregularities, the surface of the insulating layer 38 can be made close to flat. As a result, the surface of the lower electrode 21 formed on the insulating layer 38 can also be made flat. Therefore, it is possible to suppress the local increase in the electric field, and the reliability of the MIM capacitor 20 can be improved.

[0038] In addition, since a plurality of vias 81 are interposed between the drain electrode 11 and the lower electrode 21, the total cross-sectional area in the plane along the main surface 9 of the plurality of vias 81 as a whole becomes larger compared to the case where a single via is provided. Therefore, current easily flows between the wiring 16 and the lower electrode 21. Therefore, loss is reduced, and a decrease in the efficiency of the amplifier 1 can be suppressed.

[0039] FIG. 14 is a Smith chart showing impedance characteristics in the semiconductor device A according to the first embodiment and the semiconductor device D which is a comparative example. In FIG. 14, a design value S1, an intermediate value S2, and a target value S3 are shown. In the semiconductor device D, due to the influence of the inductance component by the routing wiring portion 100, the impedance follows a movement path that starts from the design value S1, passes through the intermediate value S2, and finally reaches the target value S3. For this reason, the movement path of the impedance tends to be long. On the other hand, in the semiconductor device A, since a plurality of vias 81 are provided instead of the routing wiring portion 100, the impedance follows a movement path that directly reaches the target value S3 from the design value S1. For this reason, since the movement path of the impedance becomes short, it is possible to shorten the wiring length. Since the wiring length is short, loss is reduced. Therefore, according to the present embodiment, it is possible to realize the semiconductor device A in which the efficiency of the amplifier 1 is less likely to decrease.

[0040] FIG. 15 is a circuit diagram of an amplifier circuit E which is a verification example. The amplifier circuit E includes an input terminal 73, an output terminal 74, a filter circuit 4, a bias circuit 2, an amplifier 1D of a comparative example, and a gate bias circuit 7. FIG. 16 is a diagram showing the characteristics (relationship between output and efficiency) of the amplifier circuit E which is a verification example. In FIG. 16, a graph line L1 and a graph line L2 are shown. The graph line L2 shows the characteristics of the amplifier circuit E shown in FIG. 16. The graph line L1 shows the characteristics of the amplifier circuit E when the amplifier 1 of the present embodiment is provided instead of the amplifier 1D. In the graph line L1 of FIG. 16, since a plurality of vias 81 are provided instead of the routing wiring portion 100, the inductance component is reduced and the loss is reduced. Therefore, the efficiency of the amplifier circuit is improved.

[0041] FIG. 17 is a circuit diagram of a Doherty amplifier circuit F which is a verification example. The Doherty amplifier circuit F includes an input terminal 75, an output terminal 76, a splitter 5, a wiring 6, and two amplifier circuits F1, F2. Each of the amplifier circuits F1, F2 has a filter circuit 4, a bias circuit 2, an amplifier 1D of a comparative example, and a gate bias circuit 7. FIG. 18 is a diagram showing the characteristics (relationship between output and efficiency) of the Doherty amplifier circuit F which is a verification example. In FIG. 18, a graph line L3 and a graph line L4 are shown. The graph line L4 shows the characteristics of the Doherty amplifier circuit F shown in FIG. 18. The graph line L3 shows the characteristics of the Doherty amplifier circuit F when the amplifier 1 of the present embodiment is provided instead of the amplifier 1D. In the graph line L3 of FIG. 18, since a plurality of vias 81 are provided instead of the routing wiring portion 100, the inductance component is reduced and the loss is reduced. Therefore, the efficiency of the Doherty amplifier circuit is improved.

[0042] As in the present embodiment, the MIM capacitor 20 may be provided avoiding the gate electrode 13 of the transistor 10. Thereby, the parasitic capacitance generated between the MIM capacitor 20 and the gate electrode 13 can be reduced. Therefore, it is possible to further suppress the efficiency reduction of the amplifier 1 by reducing the parasitic capacitance together with the reduction of the inductance component.

[0043] As in this embodiment, the MIM capacitor 20 may be disposed on the drain electrode 11 of the transistor 10 when viewed from a direction perpendicular to the main surface 9. Thereby, since the portion where the MIM capacitor 20 is formed is limited to the drain electrode 11, the parasitic capacitance generated between the MIM capacitor 20 and the region other than the drain electrode 11 can be reduced. Therefore, by reducing the inductance component and the parasitic capacitance together, it is possible to further suppress the efficiency degradation of the amplifier 1.

[0044] As in this embodiment, the transistor 10 may be a HEMT including a III-V semiconductor. Generally, since a HEMT can withstand high voltages and can handle large currents, high-output amplification is possible. Therefore, when the transistor 10 is a HEMT, the efficiency of the amplifier 1 can be further improved.

[0045] As in this embodiment, the dielectric constant of the dielectric layer 22 may be larger than the dielectric constants of the insulating layers 38 and 39. Thereby, the capacitance of the MIM capacitor 20 can be made larger. Therefore, the cut-off frequency becomes lower. Accordingly, DC cut can be performed at a lower frequency, and DC cut can be performed in a wide frequency band.

[0046] As in this embodiment, the thickness of the dielectric layer 22 in the direction perpendicular to the main surface 9 may be thinner than the thicknesses of the insulating layers 38 and 39 in the same direction. By making the thickness of the dielectric layer 22 thinner, the capacitance of the MIM capacitor 20 can be increased. Therefore, the cut-off frequency becomes lower. Accordingly, DC cut can be performed at a lower frequency, and DC cut can be performed in a wide frequency band.

[0047] As in this embodiment, the thickness of the lower electrode 21 in the direction perpendicular to the main surface 9 may be thinner than the thickness of the wiring 16 in the same direction. By making the thickness of the lower electrode 21 thinner, the film formation time of the insulating layer 39 that embeds the lower electrode 21 can be shortened.

[0048] As in this embodiment, the length of the via 81 in the direction perpendicular to the main surface 9 may be 0.1 μm or more and 10 μm or less. When the routing wiring portion 100 is provided between the transistor 10 and the MIM capacitor 20D as in the above-described comparative example, the distance between the transistor 10 and the MIM capacitor 20D tends to be a long distance such as, for example, several hundred μm or more. In contrast, according to the semiconductor device A, the distance of the wiring (via 81) between the transistor 10 and the MIM capacitor 20 can be made short in this way. Thereby, it is possible to realize a semiconductor device in which the efficiency of the amplifier 1 is less likely to decrease.

[0049] (Second Embodiment) FIG. 7 is a plan view showing a semiconductor device B according to the second embodiment. FIG. 8 is a circuit diagram of the semiconductor device B according to the second embodiment. The semiconductor device B is different from the semiconductor device A in the following points and is the same in other points. The semiconductor device B includes an amplifier 1B instead of the amplifier 1. The amplifier 1B has a MIM capacitor 20A instead of the MIM capacitor 20. Other configurations of the amplifier 1B are the same as those of the amplifier 1. The MIM capacitor 20A has two first portions 24 and a second portion 25. Each first portion 24 is located on the drain electrode 11 when viewed from the direction perpendicular to the main surface 9. Each first portion 24 has the same configuration as the MIM capacitor 20 of the above embodiment. The second portion 25 is provided continuously to the outside of the transistor 10 (specifically, between the transistor 10 and the wiring 32) when viewed from the direction perpendicular to the main surface 9.

[0050] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7. As shown in FIG. 9, the second portion 25 includes a lower electrode 21B, a dielectric layer 22B provided on the lower electrode 21B, and an upper electrode 23B provided on the dielectric layer 22B. The lower electrode 21B of the second portion 25 is integrally formed in the same wiring layer as the lower electrode 21 of the first portion 24. The lower electrode 21B is connected to the wiring 34 via a plurality of vias 81. The dielectric layer 22B of the second portion 25 is a common dielectric layer with the dielectric layer 22 of the first portion 24. The upper electrode 23B of the second portion 25 is integrally formed in the same wiring layer as the upper electrode 23 of the first portion 24. The second portion 25 has a rectangular shape that is long along the direction (y direction) intersecting the extending direction (x direction) of the first portion 24 when viewed from a direction perpendicular to the main surface 9.

[0051] In the present embodiment, one end of the wiring 32 is connected to the upper electrode 23B. The other end of the wiring 32 is connected to the output terminal 72. The wiring 32 functions as a transmission path for a signal (RF signal) amplified by the transistor 10.

[0052] The effects obtained by the semiconductor device B having the above configuration will be described. In the semiconductor device B, it is possible to reduce the parasitic capacitance generated between the MIM capacitor 20B and the region other than the drain electrode 11 in both the first portion 24 and the second portion 25. Further, since the MIM capacitor 20B has the second portion 25 in addition to the first portion 24, the area of the electrodes of the MIM capacitor 20B increases, and the capacitance of the MIM capacitor 20B can be increased. As a result, the cut-off frequency becomes lower. Therefore, it becomes possible to perform DC cut at a lower frequency, and DC cut can be performed in a wide frequency band.

[0053] (Third Embodiment) FIG. 10 is a plan view showing an amplifier 1C of a semiconductor device C according to the third embodiment. The amplifier 1C has a transistor 10 and a plurality of MIM capacitors 20. The transistor 10 of the amplifier 1C has six drain electrodes 11, seven source electrodes 12, and twelve gate electrodes 13. The drain electrodes 11 and the source electrodes 12 are alternately arranged in the y direction, and the gate electrodes 13 are arranged between the drain electrodes 11 and the source electrodes 12. And each MIM capacitor 20 is provided on each drain electrode 11. Note that FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 10. In the present embodiment, the configurations of the wiring 32, the wiring 33, and the wiring 34 are the same as those in the first embodiment.

[0054] Even in the semiconductor device C having the above configuration, the same effects as those of the semiconductor device A can be obtained. Further, in the semiconductor device C, the total area of the electrodes of the MIM capacitor 20 is larger than that of the semiconductor device A. Thereby, the capacitance of the MIM capacitor 20 can be increased. Therefore, the cut-off frequency becomes lower. Therefore, it becomes possible to perform DC cut at a lower frequency, and DC cut can be performed in a wide frequency band.

[0055] The semiconductor device according to the present disclosure is not limited to the above-described embodiments, and various other modifications are possible. For example, in the first embodiment, the MIM capacitor 20 is provided on the drain electrode 11, but depending on the configuration of the circuit in which the semiconductor device is used, the MIM capacitor 20 may be provided on the source electrode 12. Further, in each of the above embodiments, the form in which two or six MIM capacitors 20 are provided on the transistor 10 is exemplified, but the number of MIM capacitors 20 is not limited to these.

Description of Reference Numerals

[0056] 1, 1B, 1C, 1D... Amplifiers 2... Bias circuit 3... Ground potential line 4... Filter circuit 5... Divider 6... Wiring 7… Gate bias circuit 8… Substrate 9… Main surface 10… Transistor 11… Drain electrode 12… Source electrode 13… Gate electrode 14… Field plate 15… Input terminal 16… Wiring 17… Via 20, 20A, 20D… MIM capacitor 21, 21B… Lower electrode 22, 22B… Dielectric layer 23, 23B… Upper electrode 24… First part 25… Second part 32, 33, 34… Wiring 35… Ohmic electrode 37… Backside electrode 38, 39… Insulating layer 39a… Opening 40… Inductor 51… Pad 52… External power supply 60… MIM capacitor 72, 74, 76… Output terminal 73, 75… Input terminal 81, 82… Via 100… Routing wiring part A, B, C, D… Semiconductor device E… Amplification circuit F… Doherty amplification circuit F1, F2… Amplification circuit L1, L2, L3, L4… Graph line S1… Design value S2… Relay value S3… Target value

Claims

1. a transistor provided on a principal surface of a substrate having a principal surface, the transistor having a first electrode including an ohmic electrode; an MIM capacitor formed on the transistor, the MIM capacitor having a second electrode, a first insulating layer provided on the second electrode, and a third electrode provided on the first insulating layer; a second insulating layer provided between the first electrode and the second electrode; a plurality of vias penetrating the second insulating layer and electrically connecting the first electrode and the second electrode to each other; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said MIM capacitor is provided so as to avoid being located above a gate electrode of said transistor.

3. The semiconductor device according to claim 1 , wherein said MIM capacitor is disposed above said first electrode when viewed from a direction perpendicular to said main surface.

4. The MIM capacitor is a first portion that is located on the first electrode when viewed in a direction perpendicular to the main surface; a second portion that is continuous with the first portion and is provided outside the transistor when viewed in a direction perpendicular to the main surface; The semiconductor device according to claim 1 ,

5. 5. The semiconductor device according to claim 1, wherein the transistor is a HEMT including a III-V group semiconductor.

6. The semiconductor device according to claim 1 , wherein the first insulating layer has a dielectric constant greater than a dielectric constant of the second insulating layer.

7. 5 . The semiconductor device according to claim 1 , wherein a thickness of the first insulating layer in a direction perpendicular to the main surface is smaller than a thickness of the second insulating layer in a direction perpendicular to the main surface.

8. The semiconductor device according to claim 1 , wherein a thickness of the second electrode in a direction perpendicular to the main surface is thinner than a thickness of the first electrode in a direction perpendicular to the main surface.

9. 5. The semiconductor device according to claim 1, wherein a length of said plurality of vias in a direction perpendicular to said main surface is not less than 0.1 [mu]m and not more than 10 [mu]m.

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