Display device

Abstract

To provide a display device having a GDM circuit including an oxide semiconductor TFT, preferably used as an in-cell type touch panel.SOLUTION: A display device includes a scan signal line drive circuit capable of alternately switching a drive period and a non-drive period within one vertical scan period. A unit circuit of the scan signal line drive circuit includes a clock terminal, a set terminal, a reset terminal, an output terminal, and first, second and third thin film transistors. A gate electrode of the second thin film transistor is connected to the set terminal, and either of a source electrode or a drain electrode of the second thin film transistor is connected to an internal node. The gate electrode of the second thin film transistor is an upper gate electrode disposed at an upper part of a semiconductor layer, and the other of the source electrode and the drain electrode of the second thin film transistor is connected to a high potential side power supply line. The second thin film transistor further has a lower gate electrode disposed at a lower part of the semiconductor layer, and connected to a low potential side power supply line.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] An active matrix substrate used in a liquid crystal display device, an organic electroluminescence (EL) display device, etc. has a display area having a plurality of pixels and a non-display area (sometimes called a "frame area") located around the display area. In the display area, a thin film transistor (Thin Film Transistor; hereinafter "TFT") is provided for each pixel. Conventionally, as the TFT provided for each pixel, a TFT having an amorphous silicon film as an active layer (hereinafter "amorphous silicon TFT") and a TFT having a polycrystalline silicon film as an active layer (hereinafter "polycrystalline silicon TFT") have been widely used.

[0003] It has been proposed to use an oxide semiconductor as a material for the active layer of the TFT instead of amorphous silicon or polycrystalline silicon. Such a TFT is referred to as an "oxide semiconductor TFT". The oxide semiconductor has a higher mobility than amorphous silicon. Therefore, the oxide semiconductor TFT can operate faster than the amorphous silicon TFT.

[0004] The structure of the TFT is roughly classified into a bottom gate structure and a top gate structure. At present, the bottom gate structure is often adopted for the oxide semiconductor TFT, but the use of the top gate structure has also been proposed (for example, Patent Document 1). In the top gate structure, since the gate insulating layer can be made thin, high current supply performance can be obtained.

[0005] In the non-display area of an active matrix substrate, a peripheral circuit including a TFT may be formed monolithically (integrally). By forming the peripheral circuit monolithically, it is possible to realize narrowing of the non-display area (narrow bezel) and cost reduction due to simplification of the mounting process. For example, in the non-display area, a gate driver circuit may be formed monolithically, and a source driver circuit may be mounted by a COG (Chip on Glass) method. The monolithically formed gate driver circuit is called a GDM (Gate Driver Monolithic) circuit. Patent Document 2 discloses a liquid crystal display device in which a GDM circuit is formed on an active matrix substrate.

[0006] In this specification, the TFT arranged in each pixel of the display area is referred to as a "pixel TFT". Also, the TFT constituting the peripheral circuit provided in the non-display area is referred to as a "peripheral circuit TFT". When the pixel TFT is an oxide semiconductor TFT, from the viewpoint of the manufacturing process, it is preferable that the peripheral circuit TFT is also an oxide semiconductor TFT.

[0007] On the other hand, in recent years, display devices equipped with touch sensors (referred to as "touch panels") have been widely used in smartphones, tablets, etc. As touch sensor methods, various methods such as a resistive film type, a capacitance type, and an optical type are known.

[0008] A display device equipped with a touch sensor (hereinafter referred to as a "touch panel") is roughly classified into a method of externally attaching a touch sensor to the display device ("externally attached type") and a method of incorporating a touch sensor in the display device ("built-in type"). The built-in type touch panel is advantageous in terms of being thinner and lighter than the externally attached type touch panel, and has the advantage of increasing the light transmittance.

[0009] There are two types of built-in touch panels: the "on-cell type" and the "in-cell type". Here, "cell" refers to the display panel. In the "in-cell type", a layer responsible for the touch sensor function is arranged within the display panel. In the "on-cell type", the layer responsible for the touch sensor function is arranged between the display panel and a polarizing plate provided on the observer side of the display panel.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0011] In principle, the in-cell type can realize the thinnest and lightest touch panel. However, when a GDM circuit including an oxide semiconductor TFT is formed on the in-cell type touch panel, various problems as described below will occur.

[0012] Embodiments of the present invention have been made in view of the above problems, and an object thereof is to provide a display device including a GDM circuit including an oxide semiconductor TFT and suitably used as an in-cell type touch panel.

Means for Solving the Problems

[0013] This specification discloses a display device described in the following items.

[0014] [Item 1] A display panel having a plurality of scanning signal lines, A scanning signal line driving circuit for driving the plurality of scanning signal lines, Comprising, The scanning signal line driving circuit can alternately switch between a driving period in which the plurality of scanning signal lines are sequentially selected and a non-driving period in which the plurality of scanning signal lines are not driven within one vertical scanning period, in a display device, The display panel further includes a high-potential side power line and a low-potential side power line. The scanning signal line driving circuit has a shift register circuit including a plurality of stages. Each unit circuit constituting each of the plurality of stages has a clock terminal to which a clock signal is input, a set terminal to which a set signal is input, a reset terminal to which a reset signal is input, an output terminal electrically connected to a corresponding one of the plurality of scanning signal lines and outputting a scanning signal, a first thin film transistor having a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is electrically connected to an internal node, one of the first source electrode and the first drain electrode is electrically connected to the clock terminal, and the other of the first source electrode and the first drain electrode is electrically connected to the output terminal, a second thin film transistor having a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is electrically connected to the set terminal, and one of the second source electrode and the second drain electrode is electrically connected to the internal node, a third thin film transistor having a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode, wherein the third gate electrode is electrically connected to the reset terminal, and one of the third source electrode and the third drain electrode is electrically connected to the internal node, and includes The second gate electrode of the second thin film transistor is an upper gate electrode disposed above the second semiconductor layer with a gate insulating layer therebetween. The other of the second source electrode and the second drain electrode of the second thin film transistor is electrically connected to the high potential side power line. The second thin film transistor is disposed below the second semiconductor layer and has a lower gate electrode facing the channel region of the second semiconductor layer via a lower insulating layer, the lower gate electrode being electrically connected to the low potential side power line. A display device.

[0015] [Item 2] The unit circuit further includes a capacitor including a pair of electrodes. One of the pair of electrodes is electrically connected to the internal node, and the other of the pair of electrodes is electrically connected to the output terminal. The display device according to Item 1.

[0016] [Item 3] A control signal that is a first potential lower than the threshold voltage of the first thin film transistor during the driving period and a second potential higher than the first potential during at least a part of the non-driving period is applied to the other of the third source electrode and the third drain electrode of the third thin film transistor. The display device according to Item 1 or 2.

[0017] [Item 4] The display panel A plurality of electrodes for a touch sensor to which different signals can be applied, A plurality of wirings for a touch sensor, each of which is electrically connected to a corresponding one of the plurality of electrodes, And further has The display device according to any one of Items 1 to 3, wherein the touch sensor is driven during the non-driving period.

[0018] [Item 5] The display panel has an active matrix substrate including the plurality of scanning signal lines. The scanning signal line driving circuit is monolithically formed on the active matrix substrate. The display device according to any one of Items 1 to 4.

[0019] [Item 6] The display device according to any one of Items 1 to 5, wherein each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is an oxide semiconductor layer.

[0020] [Item 7] The display device according to Item 6, wherein the oxide semiconductor layer contains an In-Ga-Zn-O-based semiconductor. [Advantages of the Invention]

[0021] According to an embodiment of the present invention, a display device including a GDM circuit including an oxide semiconductor TFT can be provided, which is suitably used as an in-cell type touch panel. [Brief Description of the Drawings]

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Embodiments for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following, a liquid crystal display device is exemplified as the display device according to the embodiments of the present invention, but the display device according to the embodiments of the present invention is not limited to the liquid crystal display device. Further, the thin film transistor in the following description is an n-type TFT, and the electrical connection relationship in the case of using an n-type TFT will be described. It should be noted that the electrical connection of the source and drain of the p-type TFT is opposite to the electrical connection of the source and drain of the n-type TFT.

[0024] [Schematic Configuration of Liquid Crystal Display Device] First, with reference to FIGS. 1, 2, and 3, the schematic configuration of the liquid crystal display device 100 according to the embodiments of the present invention will be described. The liquid crystal display device 100 is an in-cell type touch panel. FIGS. 1 and 2 are a schematic cross-sectional view and a schematic plan view schematically showing the liquid crystal display device 100, respectively. FIG. 3 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100.

[0025] As shown in FIG. 1, the liquid crystal display device 100 includes a display panel 1. The display panel 1 includes an active matrix substrate (hereinafter referred to as "TFT substrate") 10, a counter substrate (sometimes referred to as "color filter substrate") 20 arranged to face the TFT substrate 10, and a liquid crystal layer 30 provided between the TFT substrate 10 and the counter substrate 20.

[0026] As shown in FIG. 2, the liquid crystal display device 100 has a display area DR and a non-display area (also referred to as "border area") FR. The display area DR is defined by a plurality of pixels P. The plurality of pixels P are arranged in a matrix including a plurality of rows and a plurality of columns. The non-display area FR is located around the display area DR and is an area that does not contribute to display.

[0027] The display panel 1 (more specifically, the TFT substrate 10) of the liquid crystal display device 100 has a plurality of (i) gate bus lines (scanning signal lines) GL1 to GLi and a plurality of (j) source bus lines (video signal lines) SL1 to SLj. The gate bus lines GL1 to GLi (collectively referred to as "gate bus line GL") extend in the row direction, while the source bus lines SL1 to SLj (collectively referred to as "source bus line SL") extend in the column direction (a direction substantially orthogonal to the row direction).

[0028] As shown in FIG. 3, each pixel P is provided with a thin film transistor (pixel TFT) 11 and a pixel electrode PE. The pixel TFT 11 is supplied with a scanning signal (gate signal) from the corresponding gate bus line GL and a display signal (source signal) from the corresponding source bus line SL. The pixel TFT 11 is an oxide semiconductor TFT having an oxide semiconductor layer as an active layer. The pixel electrode PE is electrically connected to the pixel TFT 11. A common electrode CE is arranged so as to face the pixel electrode PE.

[0029] The liquid crystal display device 100 further includes a gate driver (scanning signal line driving circuit) 40 that drives the gate bus lines GL1 to GLi and a source driver (video signal line driving circuit) 50 that drives the source bus lines SL1 to SLj. The gate driver 40 and the source driver 50 are arranged in the non-display area FR.

[0030] The gate driver 40 sequentially sets a plurality of gate bus lines GL1 to GLi to a selected state (a state in which a high-level potential of a scanning signal is applied). The gate driver 40 has a shift register circuit 41 including a plurality of (here, i) stages. The plurality of stages are arranged along the column direction. Each of the plurality of stages is composed of a unit circuit SR. That is, the shift register circuit 41 has a plurality of (here, i) unit circuits SR1 to SRi. Here, the gate driver 40 is formed monolithically on the active matrix substrate 10. That is, the gate driver 40 is a GDM circuit.

[0031] As already described, the liquid crystal display device 100 is an in-cell type touch panel. With reference to FIG. 4, the arrangement of electrodes and wirings for the touch sensor will be described.

[0032] As shown in FIG. 4, in the display region DR, the common electrode CE is divided into a plurality of segments TX. Since different signals (voltages) can be applied to the plurality of segments TX, they can function as electrodes for the touch sensor (hereinafter referred to as "touch sensor electrodes"). That is, the display panel 1 has a plurality of touch sensor electrodes TX. Each touch sensor electrode TX is provided corresponding to two or more pixels P.

[0033] Further, the display panel 1 further has a plurality of wirings for the touch sensor (hereinafter referred to as "touch wirings") TL. Each touch wiring TL is electrically connected to the corresponding touch sensor electrode TX among the plurality of touch sensor electrodes TX. The connection portion TC between the touch sensor electrode TX and the touch wiring TL is called a "touch wiring contact portion". In the illustrated example, the touch wiring TL extends in the column direction (the same direction as the source bus line SL). Some touch wirings TL extend across one or more other touch sensor electrodes TX to the corresponding touch sensor electrode TX.

[0034] Focusing on a certain touch sensor electrode TX, a first touch wiring TL1 for supplying a signal to the touch sensor electrode TX extends to the touch wiring contact portion TC, and a second touch wiring TL2 for supplying a signal to other touch sensor electrodes TX extends so as to cross the touch sensor electrode TX. Note that depending on the position of the touch sensor electrode TX, there may be a case where two or more touch wirings TL are arranged so as to extend across the touch sensor electrode TX, or there may be a case where no touch wiring TL extending across the touch sensor electrode TX is arranged.

[0035] The touch wiring TL is connected to a touch driving unit TD provided in a non-display area FR. The touch driving unit TD is configured to switch, for example, between a display mode in which a plurality of touch sensor electrodes TX function as a common electrode CE and a touch detection mode in which the touch sensor electrodes TX function as touch sensor electrodes TX in a time-division manner. In the display mode, the touch driving unit TD applies a common signal to the touch sensor electrodes TX (common electrode CE) via the touch wiring TL. On the other hand, in the touch detection mode, the touch driving unit TD applies a touch driving signal to the touch sensor electrodes TX via the touch wiring TL.

[0036] FIG. 5 is a timing chart showing an example of a gate clock signal GCK in one vertical scanning period. As shown in FIG. 5, the gate driver 40 can alternately switch between a driving period T1 in which the gate bus lines GL1 to GLi are sequentially selected in one vertical scanning period and a non-driving period T2 in which the gate bus lines GL1 to GLi are not driven (that is, the gate clock signal GCK remains at a low level). In the non-driving period T2, the touch sensor is driven.

[0037] [Configuration of Shift Register Circuit of Gate Driver] While referring to FIG. 6, the configuration of the shift register circuit 41 of the gate driver 40 will be described. FIG. 6 is a block diagram showing the configuration of the shift register circuit 41. In FIG. 6, among the plurality of unit circuits SR1 to SRi included in the shift register circuit 41, the n-th stage unit circuit SRn that supplies a scan signal to the gate bus line GLn in the n-th row is illustrated. As illustrated in FIG. 6, each unit circuit SR is provided with a clock terminal to which a gate clock signal GCK is input, a set terminal to which a set signal S is input, and a reset terminal to which a reset signal R is input. Further, each unit circuit SR is further provided with a high-level power supply terminal to which a high-level power supply potential VDD is input, a low-level power supply terminal to which a low-level power supply potential VSS is input, a control terminal to which a control signal VTP is input, and an output terminal that outputs a scan signal Gout. The display panel 1 has a wiring for supplying a high-level power supply potential VDD (hereinafter referred to as "high-potential side power supply line VDD") and a wiring for supplying a low-level power supply potential VSS (hereinafter referred to as "low-potential side power supply line VSS").

[0038] A gate clock signal GCK is input to each unit circuit SR. As the gate clock signal GCK, a multi-phase clock signal such as a 4-phase, 6-phase, or 8-phase clock signal is used. Further, each unit circuit SR is given a gate start pulse signal or a scan signal Gout output from another stage as the set signal S, and the scan signal Gout output from another stage is given as the reset signal R. Furthermore, a control signal VTP is input to each unit circuit SR. The control signal VTP is a signal that becomes a low-level potential during the driving period T1 and becomes a high-level potential at least in part (typically, throughout the non-driving period T2) of the non-driving period T2. Also, a scan signal Gout is output from each unit circuit SR.

[0039] [Configuration of Unit Circuit] FIG. 7 is a circuit diagram showing an example of the configuration of the unit circuit SR (the configuration of each stage of the shift register circuit 41). As shown in FIG. 7, the unit circuit SR includes a first thin film transistor (hereinafter simply referred to as "first transistor") MA, a second thin film transistor (hereinafter simply referred to as "second transistor") MB, a third thin film transistor (hereinafter simply referred to as "third transistor") MC, and a capacitor Cb.

[0040] The first transistor MA functions as an "output transistor" that outputs a scan signal Gout to the corresponding gate bus line GL. The gate electrode of the first transistor MA is electrically connected to the internal node netA. Also, the drain electrode of the first transistor MA is electrically connected to the clock terminal, and the source electrode of the first transistor MA is electrically connected to the output terminal.

[0041] The second transistor MB functions as a "set transistor" that pre-charges (boosts) the internal node netA. The gate electrode of the second transistor MB (which is a "top gate electrode" as described later) is electrically connected to the set terminal. Also, the drain electrode of the second transistor MB is electrically connected to the high-level power supply terminal (i.e., electrically connected to the high-potential side power line VDD), and the source electrode of the second transistor MB is electrically connected to the internal node netA.

[0042] The third transistor MC functions as a "reset transistor" that discharges the internal node netA. The gate electrode of the third transistor MC is electrically connected to the reset terminal. Also, the drain electrode of the third transistor MC is electrically connected to the internal node netA, and the source electrode of the third transistor MC is electrically connected to the control terminal.

[0043] The capacitor Cb holds the voltage of the internal node netA pre-charged by the second transistor MB. One of the pair of electrodes included in the capacitor Cb is electrically connected to the internal node netA, and the other is electrically connected to the output terminal.

[0044] The semiconductor layers of the first transistor MA, the second transistor MB, and the third transistor MC are oxide semiconductor layers. That is, the first transistor MA, the second transistor MB, and the third transistor MC are oxide semiconductor TFTs.

[0045] Here, the structure of the second transistor MB will be described. FIG. 8 is a cross-sectional view schematically showing a region of the TFT substrate 10 where the second transistor MB is provided. The TFT substrate 10 has a substrate 10a, a light-shielding layer 12, and the second transistor MB in the region shown in FIG. 8.

[0046] The substrate 10a is transparent and insulating. The substrate 10a is, for example, a glass substrate or a plastic substrate. The substrate 10a supports the second transistor MB and the like.

[0047] The light-shielding layer 12 is provided on the substrate 10a. The light-shielding layer 12 is formed of a material having light-shielding properties and conductivity (for example, a metal material). A lower insulating layer 13 is provided so as to cover the light-shielding layer 12.

[0048] The second transistor MB has an oxide semiconductor layer 14 provided on the lower insulating layer 13, a gate insulating layer 15 provided on the oxide semiconductor layer 14, and a gate electrode 16 disposed so as to face the oxide semiconductor layer 14 via the gate insulating layer 15. The second transistor MB further has a source electrode 17 and a drain electrode 18 electrically connected to the oxide semiconductor layer 14.

[0049] The gate electrode 16 is electrically connected to a set terminal. Since the gate electrode 16 is disposed above the semiconductor layer 14 via the gate insulating layer 15, hereinafter, the gate electrode 16 is also referred to as an "upper gate electrode". The source electrode 17 is electrically connected to the internal node netA. The drain electrode 18 is electrically connected to the high-potential side power line VDD (that is, to the high-level power supply terminal).

[0050] On the oxide semiconductor layer 14, a gate insulating layer 15 is formed so as to overlap a part of the oxide semiconductor layer 14 in plan view.

[0051] The oxide semiconductor layer 14 includes a channel region 14a, a first low-resistance region 14b and a second low-resistance region 14c located on both sides of the channel region 14a. The channel region 14a overlaps the gate insulating layer 15 (and the upper gate electrode 16) in plan view. The first low-resistance region 14b and the second low-resistance region 14c do not overlap the gate insulating layer 15 (and the upper gate electrode 16) in plan view and have a lower specific resistance than the channel region 14a. The first low-resistance region 14b is located on the source electrode 17 side of the channel region 14a. The second low-resistance region 14c is located on the drain electrode 18 side of the channel region 14a. The first low-resistance region 14b and the second low-resistance region 14c can be formed, for example, by performing a low-resistance treatment on the oxide semiconductor layer 14 using the upper gate electrode 16 and the gate insulating layer 15 as a mask.

[0052] An upper insulating layer 19 is disposed on the oxide semiconductor layer 14, the gate insulating layer 15, and the upper gate electrode 16. The source electrode 17 is disposed on the upper insulating layer 19 and within an opening (source-side opening) 19a formed in the upper insulating layer 19, and is connected to a part of the oxide semiconductor layer 14 (a part of the first low-resistance region 14b) within the source-side opening 19a. Similarly, the drain electrode 18 is disposed on the upper insulating layer 19 and within an opening (drain-side opening) 19b formed in the upper insulating layer 19, and is connected to another part of the oxide semiconductor layer 14 (a part of the second low-resistance region 14c) within the drain-side opening 19b.

[0053] The light-shielding layer 12 is disposed below the semiconductor layer 14 and faces the channel region 14a of the semiconductor layer 14 via the lower insulating layer 13. Therefore, when a predetermined potential is applied, the light-shielding layer 12 functions as the "lower gate electrode" of the second transistor MB. In the present embodiment, as shown in FIG. 7, the lower gate electrode (light-shielding layer) 12 is electrically connected to the low-potential side power supply line VSS and is supplied with the low-level power supply potential VSS.

[0054] Although not shown here, the second transistor MB is covered with an interlayer insulating layer. In the display region DR, a pixel electrode PE or the like is provided on the interlayer insulating layer. The pixel electrode PE is formed of a transparent conductive material (for example, ITO or IZO). When the display mode of the liquid crystal display device 100 is the FFS mode (a type of horizontal electric field mode), the TFT substrate 10 further includes a common electrode CE that faces the pixel electrode PE via a dielectric layer. The common electrode CE is formed of a transparent conductive material (for example, ITO or IZO).

[0055] [Operation of the unit circuit] With reference to FIG. 9, the operation of the unit circuit SR will be described. FIG. 9 is a timing chart for explaining the operation of the unit circuit SR, and shows the potentials of the gate clock signal GCK, the scan signal Gout, the set signal S, the reset signal R, the internal node netA, the high-potential side power supply line VDD, and the low-potential side power supply line VSS.

[0056] As shown in FIG. 9, in the period before time t1, the potentials of the set signal S, the internal node netA, and the scan signal Gout are maintained at a low level. At time t1, the set signal S changes from a low level to a high level. As a result, the second transistor MB is turned on, so that the capacitor Cb is charged during the period from time t1 to t2 and the potential of the internal node netA rises.

[0057] When time reaches t2, the gate clock signal GCK changes from the low level to the high level. Along with this, the drain potential of the first transistor MA rises. At this time, since the first transistor MA is in the on state, the potential of the scan signal Gout (the potential of the output terminal) also rises. When the potential of the output terminal rises, the potential of the internal node netA further rises via the capacitor Cb (the internal node netA enters a boosted state). As a result, a larger voltage is applied to the gate electrode of the first transistor MA, so the high-level gate clock signal GCK is applied to the output terminal via the first transistor MA at the same level. Thereby, the scan signal Gout becomes high level. And the state where the scan signal Gout is at the high level is maintained until time t3. Note that when time reaches t2, since the set signal S changes from the high level to the low level, the second transistor MB turns off.

[0058] When time reaches t3, the gate clock signal GCK changes from the high level to the low level. At this time, since the first transistor MA is in the on state, along with the decrease in the drain potential (the potential of the clock terminal), the potential of the scan signal Gout (the potential of the output terminal) decreases. When the potential of the output terminal decreases, the potential of the internal node netA also decreases via the capacitor Cb.

[0059] When time reaches t4, the reset signal R changes from the low level to the high level. As a result, since the third transistor MC turns on, the potential of the internal node netA is pulled to the low level.

[0060] [Effect] Since the unit circuit SR of the gate driver 40 in the liquid crystal display device 100 of this embodiment has the above-described configuration, it can be suitably used as an in-cell type touch panel. Hereinafter, the reason will be described while also referring to the configurations of the touch panels of Comparative Examples 1 and 2.

[0061] FIG. 10 is a circuit diagram showing the configuration of a unit circuit of a gate driver (hereinafter simply referred to as the "unit circuit of Comparative Example 1") SRA included in the touch panel of Comparative Example 1. Similar to the unit circuit SR of the present embodiment, the unit circuit SRA of Comparative Example 1 includes a first transistor MA that functions as an "output transistor", a second transistor MB that functions as a "set transistor", a third transistor MC that functions as a "reset transistor", and a capacitor Cb.

[0062] However, in the unit circuit SRA of Comparative Example 1, the drain electrode of the second transistor MB is electrically connected to the set terminal together with the gate electrode (upper gate electrode) (that is, diode-connected). Also, in the unit circuit SRA of Comparative Example 1, the second transistor MB does not include a lower gate electrode to which a low-level power supply potential VSS is applied.

[0063] It can be said that the unit circuit SRA of Comparative Example 1 is a simple application of the configuration of a unit circuit of a gate driver for a general liquid crystal display device to an in-cell type touch panel. In the unit circuit SRA of Comparative Example 1, the following problems occur.

[0064] Here, consider a case where, after the gate bus lines GL1 to GLn-1 of the first to (n-1)th rows are selected during a driving period T1, the touch sensor is driven during a non-driving period T2, and the selection of the gate bus line GLn of the nth row is started during the next driving period T1. For the unit circuit SRAn of the nth stage in this case, the potentials of the internal node netA and each signal during the non-driving period T2 are shown in FIG. 11. In FIG. 11, a high-level potential is represented by "H" and a low-level potential is represented by "L".

[0065] In the unit circuit SRAn of the n-th stage, since the internal node netA and the potentials of the respective signals have the relationship shown in FIG. 11, charge leakage occurs from the internal node netA (pre-charged in the immediately preceding driving period T1) during the non-driving period T2. Therefore, after the end of the non-driving period T2, there is a possibility that the gate bus line GLn cannot be suitably selected in the next driving period T1.

[0066] FIG. 12 is a circuit diagram showing the configuration of a unit circuit (hereinafter simply referred to as the "unit circuit of Comparative Example 2") SRB of the gate driver included in the touch panel of Comparative Example 2. The unit circuit SRB of Comparative Example 2 differs from the unit circuit SRA of Comparative Example 1 in that the drain electrode of the second transistor MB is electrically connected to the high-potential side power supply line VDD.

[0067] Here, similar to the unit circuit SRA of Comparative Example 1, consider a case where, after the selection of the gate bus lines GL1 to GLn-1 of the first to (n-1)-th rows is performed in a certain driving period T1, the touch sensor is driven in the non-driving period T2, and the selection of the gate bus line GLn of the n-th row is started in the next driving period T1. For the unit circuit SRBn of the n-th stage in this case, the potentials of the internal node netA and the respective signals during the non-driving period T2 are shown in FIG. 13.

[0068] In the unit circuit SRBn of the n-th stage, the internal node netA and the potentials of the respective signals have the relationship shown in FIG. 13, and since the drain electrode of the second transistor MB is electrically connected to the high-potential side power supply line VDD, charge leakage from the internal node netA during the non-driving period T2 is prevented. Therefore, after the end of the non-driving period T2, the gate bus line GLn can be suitably selected in the next driving period T1.

[0069] As described above, the problem of charge leakage occurring in the unit circuit SRA of Comparative Example 1 can be solved by electrically connecting the drain electrode of the second transistor MB to the high-potential side power supply line VDD as in the unit circuit SRB of Comparative Example 2. However, according to the study by the inventor of the present application, it has been found that a new problem may occur in the unit circuit SRB of Comparative Example 2, that is, the threshold voltage of the second transistor MB may shift in the negative direction. The reason will be explained below.

[0070] FIG. 14 is a diagram showing the relationship between the potentials of the internal node netA and the set signal S and the presence or absence of bias in the second transistor MB of the unit circuit SRA of Comparative Example 1 during non-selection, charging (pre-charge), boosting, immediately before reset, and non-driving period T2.

[0071] In the unit circuit SRA of Comparative Example 1, as shown in FIG. 14, no bias is applied to the second transistor MB during non-selection, boosting, immediately before reset, and non-driving period T2, and a forward bias is applied to the second transistor MB during charging.

[0072] FIG. 15 is a diagram showing the relationship between the potentials of the internal node netA and the set signal S and the presence or absence of bias in the second transistor MB of the unit circuit SRA of Comparative Example 2 during non-selection, charging (pre-charge), boosting, immediately before reset, and non-driving period T2.

[0073] In the unit circuit SRB of Comparative Example 2, as shown in FIG. 15, no bias is applied to the second transistor MB during non-selection, and a forward bias is applied to the second transistor MB during charging. On the other hand, a reverse bias is applied to the second transistor MB during boosting, immediately before reset, and non-driving period T2.

[0074] Thus, in the unit circuit SRB of Comparative Example 2, since there is a timing when a reverse bias is applied to the second transistor MB, the threshold voltage of the second transistor MB shifts in the negative direction due to the influence of the light irradiated from the back side to the second transistor MB. The shift of the threshold voltage in the negative direction causes an increase in power consumption, and if the degree of the shift in the negative direction becomes severe, there is a possibility that the gate driver may not operate normally.

[0075] On the other hand, in the unit circuit SR of the liquid crystal display device 100 of the present embodiment, the second transistor MB has a lower gate electrode 12 that is electrically connected to the low potential side power supply line VSS and is supplied with a low level power supply potential VSS (which can also be said to be a gate-off potential Vgl). Thereby, the threshold voltage of the second transistor MB can be increased, and the resistance to the shift in the negative direction can be improved. Therefore, it is possible to suppress an increase in power consumption and prevent lighting failure due to the abnormal operation of the gate driver 40.

[0076] Note that the specific configuration of each unit circuit SR is not limited to the example shown in FIG. 7. For example, each unit circuit SR may include four or more TFTs or may include two or more capacitors.

[0077] [Verification of Effects] A second transistor MB having an oxide semiconductor layer formed of an In-Ga-Zn-O-based semiconductor was fabricated, and the effect of the lower gate electrode 12 being electrically connected to the low potential side power supply line VSS (that is, being supplied with a low level power supply potential VSS) was verified. The verification results will be described below.

[0078] Verification was performed for the specifications where the channel width W is 10 μm and the channel length is 5 μm ("Specification A"), and the specifications where the channel width W is 50 μm and the channel length is 5 μm ("Specification B"). In Specification A, the case where a low-level power supply potential VSS is applied to the lower gate electrode 12 is called "Example 1", and in Specification B, the case where a low-level power supply potential VSS is applied to the lower gate electrode 12 is called "Example 2". Specifically, the low-level power supply potential VSS is -15 V. Also, in Specification A, the case where the same potential as the upper gate electrode 16 is applied to the lower gate electrode 12 is called "Reference Example 1", and in Specification B, the case where the same potential as the upper gate electrode 16 is applied to the lower gate electrode 12 is called "Reference Example 2".

[0079] For Example 1 and 2, and Reference Example 1 and 2, the threshold voltage Vth was measured. The source-drain voltage Vds was set to 1 V and 10 V. The measurement results are shown in Table 1 and FIGS. 16 to 19. FIGS. 16 to 19 are graphs showing the relationship between the gate voltage Vg and the drain current Id (gate voltage-drain current characteristics).

[0080] [Table 1]

[0081] From Table 1 and FIGS. 16 to 19, it can be seen that in Example 1, the threshold voltage Vth is higher than that in Reference Example 1, and in Example 2, the threshold voltage Vth is higher than that in Reference Example 2. Thus, it was confirmed that by electrically connecting the lower gate electrode 12 to the low-potential side power supply line VSS, the threshold voltage Vth of the second transistor MB can be increased.

[0082] [Structure of the First Transistor and the Third Transistor] Here, an example of the structure of the first transistor MA and the third transistor MC will be described. FIG. 20 is a cross-sectional view schematically showing the region of the TFT substrate 10 where the first transistor MA is provided, and FIG. 21 is a cross-sectional view schematically showing the region of the TFT substrate 10 where the third transistor MC is provided.

[0083] As shown in FIGS. 20 and 21, each of the first transistor MA and the third transistor MC has an oxide semiconductor layer 14, a gate insulating layer 15, an upper gate electrode 16, a source electrode 17, and a drain electrode 18, similar to the second transistor MB.

[0084] Below the semiconductor layer 14 of the first transistor MA and the third transistor MC, a light-shielding layer 12' facing the channel region 14a is provided via a lower insulating layer 13. The light-shielding layer 12' provided corresponding to the first transistor MA and the third transistor MC may be in an electrically floating state (floating), or may be given a predetermined potential and function as a lower gate electrode. When the light-shielding layer 12' functions as a lower gate electrode, the same potential as the upper gate electrode 16, for example, may be given to the light-shielding layer 12'.

[0085] [Oxide semiconductor] The oxide semiconductor (also referred to as a metal oxide or an oxide material) contained in the oxide semiconductor layer of each TFT in this embodiment may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer plane.

[0086] The oxide semiconductor layer may have a stacked structure of two or more layers. When the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it may include a plurality of crystalline oxide semiconductor layers having different crystal structures. Further, it may include a plurality of amorphous oxide semiconductor layers. When the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the layer located on the gate electrode side (the lower layer in a bottom gate structure and the upper layer in a top gate structure) among the two layers may be smaller than the energy gap of the oxide semiconductor included in the layer located on the side opposite to the gate electrode (the upper layer in a bottom gate structure and the lower layer in a top gate structure). However, when the difference in the energy gaps of these layers is relatively small, the energy gap of the oxide semiconductor in the layer located on the gate electrode side may be larger than the energy gap of the oxide semiconductor in the layer located on the side opposite to the gate electrode.

[0087] The materials, structures, film formation methods of the amorphous oxide semiconductor and each of the above crystalline oxide semiconductors, and the configuration of the oxide semiconductor layer having a stacked structure are described, for example, in Japanese Patent Application Laid-Open No. 2014-007399. For reference, the entire disclosure content of Japanese Patent Application Laid-Open No. 2014-007399 is incorporated herein by reference.

[0088] The oxide semiconductor layer may contain, for example, at least one metal element among In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, a semiconductor of the In-Ga-Zn-O system (for example, indium gallium zinc oxide). Here, the semiconductor of the In-Ga-Zn-O system is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratios (composition ratios) of In, Ga, and Zn are not particularly limited, and include, for example, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing a semiconductor of the In-Ga-Zn-O system.

[0089] The In-Ga-Zn-O-based semiconductor may be amorphous or crystalline. As the crystalline In-Ga-Zn-O-based semiconductor, a crystalline In-Ga-Zn-O-based semiconductor with the c-axis oriented substantially perpendicular to the layer plane is preferred.

[0090] Note that the crystal structure of the crystalline In-Ga-Zn-O-based semiconductor is disclosed, for example, in JP-A Nos. 2014-007399, 2012-134475, and 2014-209727. For reference, the entire disclosure contents of JP-A Nos. 2012-134475 and 2014-209727 are incorporated herein by reference. The TFT having an In-Ga-Zn-O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than 1 / 100 that of an a-Si TFT), and thus is suitably used as a driving TFT (for example, a TFT included in a driving circuit provided on the same substrate as the display area around the display area including a plurality of pixels) and a pixel TFT (a TFT provided in a pixel).

[0091] The oxide semiconductor layer may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, it may contain an In-Sn-Zn-O-based semiconductor (for example, In 2 O 3 -SnO 2 -ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may contain an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), a Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, a Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, an In-W-Zn-O-based semiconductor, and the like.

Industrial Applicability

[0092] According to an embodiment of the present invention, a display device including a GDM circuit including an oxide semiconductor TFT can be provided, which is suitably used as an in-cell type touch panel.

Explanation of Signs

[0093] 1 Display panel 10 Active matrix substrate 10a Substrate 11 Pixel TFT 12 Light-shielding layer (lower gate electrode) 12’ Light-shielding layer 13 Lower insulating layer 14 Semiconductor layer 14a Channel region 14b First low-resistance region 14c Second low-resistance region 15 Gate insulating layer 16 Gate electrode (upper gate electrode) 17 Source electrode 18 Drain electrode 19 Upper insulating layer 19a Source-side opening 19b Drain-side opening 20 Counter substrate 30 Liquid crystal layer 40 Gate driver (scanning signal line driving circuit) 41 Shift register circuit 50 Source driver (video signal line driving circuit) 100 Liquid crystal display device DR Display area FR Non-display area P Pixel PE Pixel electrode CE Common electrode GL Gate bus line (scanning signal line) SL Source bus line (video signal line) TL Touch wiring TX Touch sensor electrode TD Touch driving unit SR Unit circuit MA First transistor MB second transistor MC third transistor Cb capacitor netA internal node VDD high potential side power supply line VSS low potential side power supply line

Claims

1. a display panel having a plurality of scanning signal lines; a scanning signal line driving circuit for driving the plurality of scanning signal lines; Equipped with a scanning signal line driving circuit that can alternately switch, in one vertical scanning period, a driving period in which the plurality of scanning signal lines are sequentially put into a selected state and a non-driving period in which the plurality of scanning signal lines are not driven; The display panel further includes a high potential side power line and a low potential side power line, the scanning signal line driving circuit has a shift register circuit including a plurality of stages; The unit circuits constituting each of the plurality of stages include a clock terminal to which a clock signal is input; a set terminal to which a set signal is input; A reset terminal to which a reset signal is input; an output terminal electrically connected to a corresponding one of the plurality of scanning signal lines and outputting a scanning signal; a first thin film transistor having a first semiconductor layer, a first gate electrode, a first source electrode and a first drain electrode, the first gate electrode being electrically connected to an internal node, one of the first source electrode and the first drain electrode being electrically connected to the clock terminal, and the other of the first source electrode and the first drain electrode being electrically connected to the output terminal; a second thin film transistor having a second semiconductor layer, a second gate electrode, a second source electrode and a second drain electrode, the second gate electrode being electrically connected to the set terminal and one of the second source electrode and the second drain electrode being electrically connected to the internal node; a third thin film transistor having a third semiconductor layer, a third gate electrode, a third source electrode and a third drain electrode, the third gate electrode being electrically connected to the reset terminal, and one of the third source electrode and the third drain electrode being electrically connected to the internal node; Including, the second gate electrode of the second thin film transistor is an upper gate electrode disposed above the second semiconductor layer via a gate insulating layer; the other of the second source electrode and the second drain electrode of the second thin film transistor is electrically connected to the high potential side power line; the second thin film transistor is arranged below the second semiconductor layer, and further has a lower gate electrode facing a channel region of the second semiconductor layer via a lower insulating layer, the lower gate electrode being electrically connected to the low potential side power line.

2. The unit circuit further includes a capacitor including a pair of electrodes, The display device according to claim 1 , wherein one of the pair of electrodes is electrically connected to the internal node, and the other of the pair of electrodes is electrically connected to the output terminal.

3. 3. The display device according to claim 1, wherein a control signal is applied to the other of the third source electrode and the third drain electrode of the third thin film transistor, the control signal being a first potential lower than a threshold voltage of the first thin film transistor during the driving period, and a second potential higher than the first potential during at least a portion of the non-driving period.

4. The display panel includes: A plurality of electrodes for touch sensors to which different signals can be applied; A plurality of wires for a touch sensor, each of which is electrically connected to a corresponding electrode among the plurality of electrodes; and The display device according to claim 1 , wherein the touch sensor is driven during the non-driving period.

5. the display panel includes an active matrix substrate including the plurality of scanning signal lines; 3. The display device according to claim 1, wherein the scanning signal line driving circuit is monolithically formed on the active matrix substrate.

6. The display device according to claim 1 , wherein each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is an oxide semiconductor layer.

7. 7. The display device according to claim 6, wherein the oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

Images