Semiconductor device

Abstract

To improve the short-circuit resistance of a semiconductor device having a carrier accumulation layer.SOLUTION: A semiconductor device includes an emitter layer (4) and a contact layer (11) provided on a surface layer of a base layer (3), a carrier accumulation layer (2) provided between the base layer (3) and a drift layer (1), and a trench in which a gate electrode (5b) is embedded and reaches a position deeper than the carrier accumulation layer (2). The contact layer (11) is deeper than the emitter layer (4). The impurity concentration of the carrier accumulation layer (2) is 1.4E16 / cm3 or less at least in a portion adjacent to the trench.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] For example, in order to reduce inverter losses, it is required to reduce the conduction loss and switching loss of an IGBT (Insulated Gate Bipolar Transistor). Since current flows vertically in the IGBT, it is effective to reduce the resistance of the drift layer that holds the breakdown voltage, and efforts have been made to optimize the cell structure so that carriers are easily accumulated during conduction. As a result, for example, in Patent Document 1 below, an IGBT is proposed in which an N-type layer having an impurity concentration higher than that of the drift layer is provided between a P-type base layer and an N - type drift layer to enhance the carrier accumulation effect. This N-type layer is called a carrier accumulation layer (CS layer).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a carrier accumulation layer is provided in an IGBT as in Patent Document 1, an effect of reducing the collector-emitter saturation voltage Vce(sat) can be obtained. On the other hand, a problem occurs in that the short-circuit withstand current decreases. The short-circuit withstand current is the length of time until a power device reaches breakdown when the load is short-circuited, and is one of the electrical characteristics required for an IGBT. For example, even when the load is in a short-circuit state due to a malfunction or the like and a large current flows through the IGBT, and the gate voltage rises due to the displacement current, it is required to withstand without breakdown for several microseconds.

[0005] The present disclosure has been made to solve such problems, and an object thereof is to improve the short-circuit withstand voltage of a semiconductor device having a carrier accumulation layer.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate on which a drift layer of a first conductivity type is formed, a base layer of a second conductivity type provided in a surface layer portion on the first main surface side of the semiconductor substrate, and a first conductivity type emitter layer selectively provided in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a second conductivity type contact layer selectively provided in a surface layer portion of the base layer and having a higher impurity concentration than the base layer, a first conductivity type carrier accumulation layer provided between the base layer and the drift layer and having a higher impurity concentration than the drift layer, a trench provided on the first main surface side of the semiconductor substrate and reaching a position deeper than the carrier accumulation layer, a gate insulating film provided on an inner surface of the trench, a gate electrode provided on the gate insulating film and embedded in the trench, and a second conductivity type collector layer provided in a surface layer portion on the second main surface side of the semiconductor substrate, wherein the depth of the contact layer is deeper than that of the emitter layer, and the impurity concentration of the carrier accumulation layer is at least 1.4E16 / cm in at least a portion adjacent to the trench. 3 The following.

Advantages of the Invention

[0007] According to the present disclosure, the short-circuit withstand voltage of a semiconductor device having a carrier accumulation layer is improved.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] In the following embodiments, the first conductivity type is described as N-type and the second conductivity type is described as P-type. However, conversely, the first conductivity type may be P-type and the second conductivity type may be N-type. Also, an N-type with a relatively high impurity concentration is referred to as "N + ", an N-type with a relatively low impurity concentration is referred to as "N - ", a P-type with a relatively high impurity concentration is referred to as "P + ", and a P-type with a relatively low impurity concentration is referred to as "P - ". Here, the height of the impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0010] <Embodiment 1> FIG. 1 is a top view of a semiconductor device according to Embodiment 1. In Embodiment 1, it is assumed that the semiconductor device includes a trench gate type IGBT as a semiconductor element.

[0011] As shown in FIG. 1, the semiconductor device according to Embodiment 1 includes a cell region 31 where cells of the IGBT are arranged, a gate pad region 32 where gate pads of the IGBT are arranged, a gate wiring region 33 where gate wiring connecting the gate electrode and the gate pad of the IGBT is arranged, and a termination region 34 provided outside the cell region 31, the gate pad region 32, and the gate wiring region 33. The emitter pads of the IGBT are arranged in the cell region 31. In the termination region 34, a breakdown voltage holding structure such as an FLR (Field Limiting Ring) or a VLD (Variation of Lateral Doping) is appropriately provided according to the breakdown voltage design required for the semiconductor device.

[0012] FIG. 2 is a cross-sectional view showing the structure of the IGBT according to Embodiment 1. That is, FIG. 2 is a cross-sectional view of a part of the cell region 31 shown in FIG. 1.

[0013] As shown in FIG. 2, the IGBT according to Embodiment 1 is formed using a semiconductor substrate 40 in which an N-type drift layer 1 is formed. Hereinafter, the front surface of the semiconductor substrate 40 (the upper surface in FIG. 2) is referred to as the "first main surface", and the back surface of the semiconductor substrate 40 (the lower surface in FIG. 2) is referred to as the "second main surface".

[0014] A P-type base layer 3 is provided in the surface layer portion on the first main surface side of the semiconductor substrate 40. On the surface layer portion of the base layer 3, an N-type emitter layer 4 having a higher impurity concentration than the drift layer 1 and a P-type contact layer 11 having a higher impurity concentration than the base layer 3 are selectively provided respectively. + A P-type contact layer 11 having a higher impurity concentration than the base layer 3 is selectively provided respectively. + An N-type carrier accumulation layer 2 is provided under the base layer 3, that is, between the base layer 3 and the drift layer 1.

[0015] On the first main surface of the semiconductor substrate 40, a trench is formed that penetrates the emitter layer 4, the base layer 3, and the carrier accumulation layer 2 and reaches the drift layer 1. That is, the trench reaches a position deeper than the carrier accumulation layer 2. A gate insulating film 5a is formed on the inner surface of the trench. Also, on the gate insulating film 5a, a gate electrode 5b is formed so as to be embedded in the trench. By forming the trench deeper than the carrier accumulation layer 2, the breakdown voltage between the collector and the emitter can be stabilized.

[0016] On the first main surface of the semiconductor substrate 40, an interlayer insulating film 6 is provided so as to cover the gate electrode 5b, and an emitter electrode 7 is provided on the interlayer insulating film 6. Contact holes reaching the emitter layer 4 and the contact layer 11 are formed in the interlayer insulating film 6, and the emitter electrode 7 is connected to the emitter layer 4 and the contact layer 11 through the contact holes.

[0017] On the surface layer portion on the second main surface side of the semiconductor substrate 40, an N-type buffer layer 8 (hereinafter referred to as "phosphorus buffer layer 8") into which phosphorus is implanted as an impurity is provided, and a P-type collector layer 9 is provided on the surface layer portion of the phosphorus buffer layer 8. That is, the phosphorus buffer layer 8 is provided between the drift layer 1 and the collector layer 9. Further, a collector electrode 10 connected to the collector layer 9 is provided on the second main surface of the semiconductor substrate 40.

[0018] The peak concentration of the impurity in the base layer 3 is approximately 8.0E16 / cm so that the gate threshold voltage Vth when current starts to flow from the collector to the emitter becomes about 6V. 3 ~5.0E17 / cm 3 is set.

[0019] FIG. 3 is a diagram showing the relationship between the impurity concentration of the carrier accumulation layer 2 and the collector-emitter saturation voltage Vce(sat) of the IGBT. When the impurity concentration of the carrier accumulation layer 2 is increased, a potential barrier is formed between the drift layer 1 and the carrier accumulation layer 2, and the accumulation effect of holes from the second main surface of the semiconductor substrate 40 is enhanced, so that the resistance of the drift layer 1 decreases. Therefore, as shown in FIG. 3, when the concentration of the carrier accumulation layer 2 is increased, Vce(sat) can be lowered. However, simply increasing the concentration of the carrier accumulation layer 2 shortens the channel length, so that the current flowing during a short circuit increases, and thus a decrease in short-circuit withstand current is a concern.

[0020] FIG. 4 is a diagram showing the relationship between the impurity concentration of the carrier accumulation layer 2 and the gate voltage Vge immediately before the IGBT in a short-circuit state is destroyed (hereinafter simply referred to as "gate voltage immediately before destruction"). The data used as the basis for FIG. 4 are measured values obtained by fixing the time during a short circuit of the IGBT and increasing the gate voltage. A high gate voltage immediately before destruction corresponds to a high short-circuit withstand current.

[0021] It can also be seen from FIG. 4 that increasing the impurity concentration of the carrier accumulation layer 2 decreases the short-circuit withstand current. However, when the impurity concentration of the carrier accumulation layer 2 is 1.4E16 / cm 3If the following conditions are met, it can be seen that the short-circuit withstand capacity equal to or higher than that of an IGBT without the carrier accumulation layer 2 (i.e., when the impurity concentration of the carrier accumulation layer 2 is 0) can be achieved. Therefore, in the present embodiment, at least in the portion adjacent to the trench, that is, in the portion directly below the channel region where the channel is formed, the impurity concentration of the carrier accumulation layer 2 is set to 1.4E16 / cm 3 or less.

[0022] Here, consider the mechanism by which the short-circuit withstand capacity is improved when the impurity concentration of the carrier accumulation layer 2 is 1.4E16 / cm 3 or less. The diffusion potential Vbi at the PN junction between the carrier accumulation layer 2 and the base layer 3 is obtained by the following equation (1).

[0023]

Equation

[0024] In Equation (1), q is the elementary charge, k B is the Boltzmann constant, T is the temperature, N A is the acceptor density, N D is the donor density, and n i is the intrinsic carrier density. From Equation (1), as the impurity concentration of the carrier accumulation layer 2 increases, the diffusion potential increases, and even when the temperature inside the semiconductor device rises during short-circuit operation, the disappearance of the PN junction is less likely to occur, so it is considered that the short-circuit withstand capacity is improved. This phenomenon can be seen in the graph of FIG. 4 in the range where the impurity concentration of the carrier accumulation layer 2 is lower than 0.7E16 / cm 3 . On the other hand, in the range where the impurity concentration of the carrier accumulation layer 2 exceeds 0.7E16 / cm 3 , since the decrease in the short-circuit withstand capacity due to the shortening of the channel length described above becomes significant, the gate voltage just before breakdown tends to decrease as the impurity concentration of the carrier accumulation layer 2 increases. However, if the impurity concentration of the carrier accumulation layer 2 is suppressed to 1.4E16 / cm 3 or less, the decrease in the short-circuit withstand capacity due to the shortening of the channel length can be suppressed, and a short-circuit withstand capacity equal to or higher than that of an IGBT without the carrier accumulation layer 2 can be ensured.

[0025] Also, in this embodiment, the contact layer 11 is formed deeper than the emitter layer 4. As a result, the resistance of the hole current path from the second main surface of the semiconductor substrate 40 is reduced, and an improvement in the short-circuit withstand capacity is expected. Further, a voltage drop is suppressed, and an effect of preventing the latch-up operation of the parasitic transistor of the IGBT is also obtained.

[0026] Here, the manufacturing method of the IGBT according to Embodiment 1 will be described with reference to the process diagrams of FIGS. 5 to 15.

[0027] First, as shown in FIG. 5, an N-type semiconductor substrate 40 that will become the drift layer 1 is prepared. The specific resistance of the semiconductor substrate 40 is set to 20 Ω·cm or more and 100 Ω·cm or less, which is common for in-vehicle products. The material of the semiconductor substrate 40 may be silicon or a wide-bandgap semiconductor such as silicon carbide (SiC). A semiconductor device formed using a wide-bandgap semiconductor is excellent in operation at high voltage, high current, and high temperature compared to a conventional semiconductor device using silicon. Examples of the wide-bandgap semiconductor include silicon carbide, gallium nitride (GaN)-based materials, and diamond.

[0028] Next, in the region that will become the termination region 34, a P-type impurity region having a breakdown voltage holding structure is formed by heat treatment at a high temperature for a long time so as to surround the cell region 31.

[0029] Thereafter, by selectively implanting impurities into the first main surface of the semiconductor substrate 40 using photolithography technology, as shown in FIGS. 6 and 7, a carrier accumulation layer 2 and a base layer 3 are formed in the surface layer portion on the first main surface side of the semiconductor substrate 40. At this time, in order to form the carrier accumulation layer 2 at a position deeper than the base layer 3, in the ion implantation for forming the carrier accumulation layer 2, it is effective to implant phosphorus at a high energy of MeV or to perform a high-temperature drive after implanting phosphorus.

[0030] Next, the emitter layer 4 is selectively formed on the surface layer portion of the base layer 3 as shown in FIG. 8 by selective ion implantation of phosphorus or arsenic.

[0031] Subsequently, by selective dry etching using photolithography technology, an emitter layer 4, a carrier accumulation layer 2, and a trench penetrating the carrier accumulation layer 2 are formed on the first main surface of the semiconductor substrate 40. Then, as shown in FIG. 9, a gate insulating film 5a is formed on the inner surface of the trench by thermal oxidation or CVD method, and a gate electrode 5b is formed by embedding polysilicon inside the trench by CVD method.

[0032] Thereafter, by selective ion implantation, as shown in FIG. 10, a contact layer 11 is selectively formed on the surface layer portion of the base layer 3. At this time, in order to make the contact layer 11 deeper than the emitter layer 4, it is effective to implant boron at high energy or perform high-temperature heat treatment. Note that the emitter layer 4 may be formed after the formation of the trench.

[0033] Next, as shown in FIG. 11, an interlayer insulating film 6 is formed by forming a TEOS oxide film, a BPTEOS oxide film (a TEOS oxide film containing B and P as impurities), etc., and a contact hole reaching the emitter layer 4 and the contact layer 11 is formed in the interlayer insulating film 6 by selective etching. When the contact hole is formed by dry etching, the etching time may be set so that the first main surface of the semiconductor substrate 40 is slightly over-etched so that the interlayer insulating film 6 does not remain at the bottom of the contact hole. However, if the over-etching becomes excessive, the emitter layer 4 disappears, causing a decrease in current-carrying ability. Therefore, it is desirable that the depth of the over-etch with respect to the first main surface of the semiconductor substrate 40 is shallower than the depth of the emitter layer 4. That is, it is desirable that the position of the bottom of the emitter electrode 7 connected to the emitter layer 4 through the contact hole is shallower than the bottom of the emitter layer 4.

[0034] Next, by forming a film of metals such as Al, AlSi, AlCu, and Cu by sputtering or evaporation, an emitter electrode 7 is formed on the interlayer insulating film 6 as shown in FIG. 12. At this time, the emitter electrode 7 is connected to the emitter layer 4 and the contact layer 11 through a contact hole formed in the interlayer insulating film 6. Further, if necessary, a protective film made of a glass coat or polyimide may be formed on the emitter electrode 7.

[0035] Thereafter, the semiconductor substrate 40 is thinned as shown in FIG. 13 by grinding the second main surface side of the semiconductor substrate 40. Then, as shown in FIG. 14, a phosphorus buffer layer 8 and a collector layer 9 are formed in the surface layer portion on the second main surface side of the semiconductor substrate 40 by ion implantation of impurities into the second main surface of the semiconductor substrate 40. At this time, the ion implantation for forming the phosphorus buffer layer 8 is performed at a high energy of several hundred keV to several MeV so that the phosphorus buffer layer 8 is formed at a position deeper than the collector layer 9. Thereafter, the impurities implanted into the semiconductor substrate 40 are activated by laser annealing or furnace annealing.

[0036] Finally, a collector electrode 10 is formed as shown in FIG. 15 by forming a film of a metal on the second main surface of the semiconductor substrate 40 by sputtering or evaporation. The collector electrode 10 may have a laminated structure composed of a plurality of laminated films such as ASi, Ti, Ni, Au, and Ag in consideration of making an ohmic contact with silicon or performing soldering.

[0037] [Modification Example] In the first embodiment, the semiconductor element formed in the cell region 31 is an IGBT, but the semiconductor device may be an RC-IGBT (Reverse Conducting IGBT) composed of an IGBT and a diode connected in anti-parallel thereto.

[0038] FIG. 16 shows a cross-sectional view of an RC-IGBT as a modification example of the first embodiment. As shown in FIG. 16, the RC-IGBT includes an IGBT region 21 that functions as an IGBT and a diode region 22 that functions as a diode. The structure of the IGBT region 21 is the same as the IGBT shown in FIG. 2.

[0039] On one hand, in the diode region 22, a P-type anode layer 12 is formed on the carrier accumulation layer 2, that is, on the surface layer portion on the first main surface side of the semiconductor substrate 40. Further, on the surface layer portion of the anode layer 12, a P + -type contact layer 13 having a higher impurity concentration than the anode layer 12 is formed. Since both the anode layer 12 and the contact layer 13 are P-type regions, they can be collectively referred to as the "anode layer".

[0040] Also, an N-type cathode layer 14 is formed on the surface layer portion on the second main surface side of the semiconductor substrate 40. Note that it is not necessary to provide the carrier accumulation layer 2 in the diode region 22.

[0041] In the diode region 22, the emitter electrode 7 is connected to the anode layer 12 and the contact layer 13 through a contact hole formed in the interlayer insulating film 6, and the collector electrode 10 is connected to the cathode layer 14. Thereby, the diode in the diode region 22 and the IGBT in the IGBT region 21 are connected in inverse parallel.

[0042] In the RC-IGBT of FIG. 16, in order to stabilize the breakdown voltage, trenches similar to those in the IGBT region 21 are also formed in the diode region 22. However, the potential of the electrode formed in the trench of the IGBT region 21 is set to the emitter potential of the IGBT.

[0043] The anode layer 12 of the diode region 22 is formed deeper from the first main surface of the semiconductor substrate 40 than the base layer 3 of the IGBT region 21. In an IGBT having the carrier accumulation layer 2 under the base layer 3, during the switching operation or short-circuit operation, the electric field becomes high at the lower part of the trench and dynamic avalanche occurs. At this time, if the anode layer 12 is deeper than the base layer 3, carriers can easily escape to the diode side, and it is possible to prevent carriers from concentrating on the IGBT side and destroying the element.

[0044] Also, as shown in FIG. 17, the interlayer insulating film 6 may not be formed in the diode region 22, and the entire upper surface of the diode region 22 may be brought into contact with the emitter electrode 7. Furthermore, carriers can more easily escape, which is effective in improving the breakdown voltage.

[0045] The impurity concentration of the anode layer 12 may be made lower than that of the base layer 3. By doing so, the recovery loss of the diode can be reduced while ensuring the short-circuit withstand voltage.

[0046] Also, as shown in FIG. 18, an N-type buffer layer 15 (hereinafter referred to as "proton buffer layer 15") into which protons are implanted as impurities may be provided between the drift layer 1 and the phosphorus buffer layer 8. By doing so, the supply of holes from the second main surface of the semiconductor substrate 40 during the short-circuit operation is suppressed, an imbalance in the concentration of electrons and holes is likely to occur, and an increase in the electric field on the first main surface side is suppressed. Therefore, it is effective in improving the short-circuit withstand voltage. The proton buffer layer 15 can be formed by implanting protons after grinding the second main surface side of the semiconductor substrate 40 and then subjecting the protons to a heat treatment at about 400 °C to make them donors.

[0047] FIG. 18 shows an example in which the proton buffer layer 15 is provided in the IGBT, but the proton buffer layer 15 is also applicable to the RC-IGBT.

[0048] <Embodiment 2> FIG. 19 is a cross-sectional view showing the structure of the IGBT according to Embodiment 2. As shown in FIG. 19, in Embodiment 2, the carrier accumulation layer 2 adjacent to the trench is locally provided only in the vicinity of the trench in which the gate electrode 5b is embedded, that is, directly below the channel region where the channel is formed. The carrier accumulation layer 2 is not formed in the regions other than the vicinity of the trench. A drift layer 1 or a trench is interposed between adjacent carrier accumulation layers 2. In order to ensure the short-circuit withstand voltage of the IGBT, in at least the portion adjacent to the trench, the impurity concentration of the carrier accumulation layer 2 is 1.4E16 / cm 3 Shall be as follows.

[0049] According to Embodiment 2, compared with Embodiment 1, although the Vce(sat) of the IGBT increases, the turn-off loss Eoff is reduced, so an IGBT suitable for high-speed operation can be obtained.

[0050] [Modification Example] As shown in FIG. 20, the local carrier accumulation layer 2 shown in Embodiment 2 is also applicable to an RC-IGBT. In FIG. 20, the structure of the IGBT region 21 is the same as that of the IGBT in FIG. 19, and the structure of the diode region 22 is the same as that of the diode region 22 in FIG. 16.

[0051] <Embodiment 3> FIG. 21 is a cross-sectional view showing the structure of an IGBT according to Embodiment 3. As shown in FIG. 21, in Embodiment 3, the carrier accumulation layer 2 is composed of a first carrier accumulation layer 2a disposed near the trench in which the gate electrode 5b is embedded, that is, directly below the channel region, and a second carrier accumulation layer 2b disposed in the region between the first carrier accumulation layers 2a. The impurity concentration of the first carrier accumulation layer 2a is 1.4E16 / cm 3 As follows, and thereby the short-circuit withstand capacity of the IGBT is ensured. The impurity concentration of the second carrier accumulation layer 2b is set to a value higher than that of the drift layer 1, thereby reducing the Vce(sat) of the IGBT. The impurity concentration of the second carrier accumulation layer 2b may be higher or lower than the concentration of the first carrier accumulation layer 2a.

[0052] [Modification Example] As shown in FIG. 22, the carrier accumulation layer 2 composed of the first carrier accumulation layer 2a and the second carrier accumulation layer 2b shown in Embodiment 3 is also applicable to an RC-IGBT. In FIG. 22, the structure of the IGBT region 21 is the same as that of the IGBT in FIG. 21, and the structure of the diode region 22 is the same as that of the diode region 22 in FIG. 16.

[0053] It should be noted that the embodiments can be freely combined, or each embodiment can be appropriately modified or omitted.

[0054] <Supplementary Note> Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0055] (Appendix 1) A semiconductor substrate on which a drift layer of a first conductivity type is formed, A base layer of a second conductivity type provided in a surface layer portion on the first main surface side of the semiconductor substrate, An emitter layer of a first conductivity type selectively provided in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, A contact layer of a second conductivity type selectively provided in a surface layer portion of the base layer and having a higher impurity concentration than the base layer, A carrier accumulation layer of a first conductivity type provided between the base layer and the drift layer and having a higher impurity concentration than the drift layer, A trench provided on the first main surface side of the semiconductor substrate and reaching a position deeper than the carrier accumulation layer, A gate insulating film provided on an inner surface of the trench, A gate electrode provided on the gate insulating film and embedded in the trench, A collector layer of a second conductivity type provided in a surface layer portion on the second main surface side of the semiconductor substrate, Comprising The depth of the contact layer is deeper than that of the emitter layer, The impurity concentration of the carrier accumulation layer is 1.4E16 / cm at least in a portion adjacent to the trench 3 Or less, Semiconductor device.

[0056] (Appendix 2) The carrier accumulation layer is locally formed in the vicinity of the trench, The semiconductor device according to Appendix 1.

[0057] (Appendix 3) The carrier accumulation layer is Disposed in the vicinity of the trench and having a first carrier accumulation layer with an impurity concentration of 1.4E16 / cm 3 Or less, A second carrier accumulation layer that is disposed between the first carrier accumulation layers and has an impurity concentration higher than that of the drift layer, comprising the semiconductor device according to Appendix 1.

[0058] (Appendix 4) The position of the bottom of the emitter electrode connected to the emitter layer is shallower than the bottom of the emitter layer. The semiconductor device according to any one of Appendices 1 to 3.

[0059] (Appendix 5) Further comprising a diode region that functions as a diode, The diode region the drift layer, a second-conductivity-type anode layer provided in the surface layer portion on the first main surface side of the semiconductor substrate, a first-conductivity-type cathode layer provided in the surface layer portion on the second main surface side of the semiconductor substrate, and comprising The anode layer is formed deeper from the first main surface of the semiconductor substrate than the base layer. The semiconductor device according to any one of Appendices 1 to 4.

[0060] (Appendix 6) Further comprising a diode region that functions as a diode, The diode region the drift layer, a second-conductivity-type anode layer provided in the surface layer portion on the first main surface side of the semiconductor substrate, a first-conductivity-type cathode layer provided in the surface layer portion on the second main surface side of the semiconductor substrate, and comprising The anode layer has an impurity concentration lower than that of the base layer. The semiconductor device according to any one of Appendices 1 to 4.

[0061] (Appendix 7) A first conductivity type buffer layer in which protons are implanted as impurities is provided between the drift layer and the collector layer. The semiconductor device according to any one of Appendices 1 to 6.

[0062] (Appendix 8) The resistivity of the drift layer is 20 Ω·cm or more and 100 Ω·cm or less. The semiconductor device according to any one of Appendices 1 to 7.

Explanation of Reference Numerals

[0063] 1 Drift layer, 2 Carrier accumulation layer, 2a First carrier accumulation layer, 2b Second carrier accumulation layer, 3 Base layer, 4 Emitter layer, 5a Gate insulating film, 5b Gate electrode, 6 Interlayer insulating film, 7 Emitter electrode, 8 Phosphorus buffer layer, 9 Collector layer, 10 Collector electrode, 11 Contact layer, 12 Anode layer, 13 Contact layer, 14 Cathode layer, 15 Proton buffer layer, 21 IGBT region, 22 Diode region, 31 Cell region, 32 Gate pad region, 33 Gate wiring region, 34 Terminal region, 40 Semiconductor substrate.

Claims

1. a semiconductor substrate having a first conductivity type drift layer formed thereon; a second conductivity type base layer provided on a surface layer portion on a first main surface side of the semiconductor substrate; an emitter layer of a first conductivity type selectively provided on a surface layer portion of the base layer and having an impurity concentration higher than that of the drift layer; a contact layer of a second conductivity type selectively provided on a surface layer portion of the base layer and having an impurity concentration higher than that of the base layer; a carrier accumulation layer of a first conductivity type provided between the base layer and the drift layer and having a higher impurity concentration than the drift layer; a trench provided on the first main surface side of the semiconductor substrate and reaching a position deeper than the carrier accumulation layer; a gate insulating film provided on an inner surface of the trench; a gate electrode provided on the gate insulating film and embedded in the trench; a collector layer of a second conductivity type provided on a surface layer portion on a second main surface side of the semiconductor substrate; Equipped with The contact layer has a depth greater than that of the emitter layer, The impurity concentration of the carrier accumulation layer is 1.4E16 / cm at least in a portion adjacent to the trench. ３ Below is the Semiconductor device.

2. the carrier accumulation layer is locally formed in the vicinity of the trench; The semiconductor device according to claim 1 .

3. The carrier accumulation layer is A semiconductor device is disposed near the trench and has an impurity concentration of 1.4E16 / cm ３ a first carrier accumulation layer, a second carrier accumulation layer disposed between the first carrier accumulation layers and having an impurity concentration higher than that of the drift layer; Including, The semiconductor device according to claim 1 .

4. a bottom of the emitter electrode connected to the emitter layer is located shallower than a bottom of the emitter layer; The semiconductor device according to claim 1 .

5. Further comprising a diode region functioning as a diode, The diode region is The drift layer; a second conductivity type anode layer provided on a surface layer portion on the first main surface side of the semiconductor substrate; a cathode layer of a first conductivity type provided on a surface layer portion of the semiconductor substrate on the second main surface side; Equipped with the anode layer is formed deeper from the first main surface of the semiconductor substrate than the base layer. The semiconductor device according to claim 1 .

6. Further, a diode region functioning as a diode is provided, The diode region is The drift layer; a second conductivity type anode layer provided on a surface layer portion on the first main surface side of the semiconductor substrate; a cathode layer of a first conductivity type provided on a surface layer portion of the semiconductor substrate on the second main surface side; Equipped with The anode layer has a lower impurity concentration than the base layer. The semiconductor device according to claim 1 .

7. a buffer layer of a first conductivity type into which protons are implanted as impurities is provided between the drift layer and the collector layer; The semiconductor device according to claim 1 .

8. The resistivity of the drift layer is 20 Ω cm or more and 100 Ω cm or less. The semiconductor device according to claim 1 .

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