Current generation device and current detection system

Abstract

To provide a current generation device and a current detection system capable of generating current with a highly accurate current ratio.SOLUTION: A current generation device 10, 30 comprises: a current generation circuit 12, 32 that includes first transistors MNo1, MNo3-MNo5 and second transistors MNs1-MNs3, MNs5, and generates a second current according to the current flowing through the second transistor obtained through prescribed multiplication of the first current flowing through the first transistor; and a control circuit 14, 34 that controls the operations of the first transistors and the second transistors. The first transistors or second transistors are provided in plural. The control circuit sequentially changes the transistor that becomes ON state for the plurality of first transistors or the plurality of second transistors.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a current generation device and a current detection system.

Background Art

[0002] Conventionally, a switch device for detecting an output current has been proposed. For example, Patent Documents 1 and 2 disclose a switch device including a power transistor and a mirror transistor for generating a sense current corresponding to the output current flowing through the power transistor. The output current is detected based on this sense current.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

[0004] [Summary] However, the present inventors have come to recognize the following problems. That is, the sense current described in Patent Documents 1 and 2 is a current corresponding to the output current flowing through the power transistor, and if the pairing of the power transistor and the mirror transistor is poor, there will be variations in the current ratio between the output current and the sense current for each switch device.

[0005] The present disclosure has been made in view of such circumstances, and one of its exemplary purposes is to provide a current generation device and a current detection system capable of generating a current with a good current ratio accuracy.

[0006] A current generation device according to an aspect of the present disclosure includes a first transistor and a second transistor, and a current generation circuit that generates a second current corresponding to the current flowing through the second transistor, which is a predetermined multiple of a first current corresponding to the current flowing through the first transistor, and a control circuit that controls the operations of the first transistor and the second transistor. The first transistor or the second transistor is plural. The control circuit sequentially changes the transistor that becomes in an on state for the plural first transistors or the plural second transistors.

[0007] A current detection system according to another aspect of the present disclosure includes the above-described current generation device and a detection device that detects a first current based on the above-described second current.

[0008] Note that any combination of the above-described components, and those obtained by converting the expression of the present disclosure among a method, an apparatus, a system, etc. are also effective as aspects of the present disclosure.

Brief Description of Drawings

[0009]

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[0010] [Detailed Description] (Overview) The overview of some exemplary embodiments of the present disclosure will be described. This overview is for the purpose of providing a basic understanding of the embodiments as a prelude to the detailed description to follow, and simplifies and describes some concepts of one or more embodiments. It does not limit the scope of the invention or the disclosure. This overview is not an all-inclusive overview of all possible embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or variant) or a plurality of embodiments (examples or variants) disclosed in this specification.

[0011] A current generation device according to one embodiment includes a first transistor and a second transistor, and a current generation circuit that generates a second current that is a predetermined multiple of a first current corresponding to the current flowing through the first transistor, and a control circuit that controls the operations of the first transistor and the second transistor. The first transistor or the second transistor is plural. The control circuit sequentially changes the transistor that becomes on for the plurality of first transistors or the plurality of second transistors.

[0012] According to this configuration, the second current can be generated from the first current with a good current ratio accuracy.

[0013] In one embodiment, when K is a value greater than 1, the second current may have a magnitude of 1 / K times the first current.

[0014] In one embodiment, the current generation circuit may include a plurality of second transistors. The control circuit may sequentially change the second transistors that are in the on state for the plurality of second transistors.

[0015] In one embodiment, the control circuit may use the plurality of second transistors as first to nth control transistors, turn on the first to nth control transistors one by one in this order, and turn off the remaining transistors among the first to nth control transistors.

[0016] In one embodiment, the current generation circuit may include a plurality of first transistors. The control circuit may sequentially change the first transistors that are in the on state for the plurality of first transistors.

[0017] In one embodiment, the control circuit may sequentially change the first transistors that are in the on state so that two or more of the plurality of first transistors are in the on state.

[0018] In one embodiment, the current generation circuit may further include a first terminal through which a first current flows, a second terminal through which a second current flows, an operational amplifier, and a P-channel type MOS transistor. The first transistor and the second transistor may each be an N-channel type MOS transistor. The drains of the first transistor and the second transistor may be connected to each other. The source of the first transistor may be connected to the non-inverting input terminal of the operational amplifier and the first terminal. The source of the second transistor may be connected to the inverting input terminal of the operational amplifier and the source of the P-channel type transistor. The output terminal of the operational amplifier may be connected to the gate of the P-channel type transistor. The drain of the P-channel type transistor may be connected to the second terminal.

[0019] A current detection system according to another embodiment includes the above-described current generation device and a detection device that detects the first current based on the second current.

[0020] According to this configuration, the second current can be generated from the first current with a good current ratio, and as a result, the first current can be detected with high accuracy.

[0021] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Further, the embodiments are illustrative and not intended to limit the disclosure and the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and the invention.

[0022] In this specification, the phrase "member A is connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0023] Similarly, the phrase "member C is connected (provided) between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0024] (First Embodiment) FIG. 1 is a diagram for explaining the function and configuration of a current detection system 1 according to the first embodiment. The current detection system 1 according to the present embodiment includes a semiconductor device 10, a power supply 20, an ammeter 22 (measurement device), and a detection device 24.

[0025] The semiconductor device 10 receives a power supply voltage Vbb from the power supply 20 and supplies an output current Io1 (first current) to the load 26. The semiconductor device 10 has a function as a current generation device that generates a sense current Is1 (second current).

[0026] The ammeter 22 measures the sense current Is1 and transmits a signal Sa indicating the measurement result to the detection device 24. The detection device 24 detects the output current Io1 based on the sense current Is1. Specifically, it detects the output current Io1 based on the measurement result of the sense current Is1 by the ammeter 22. More specifically, the detection device 24 calculates the current value of the output current Io1 based on the signal Sa. In this embodiment, the current ratio between the output current Io1 and the sense current Is1 is preset, and the detection device 24 calculates the value obtained by multiplying the current value of the sense current Is1 by the current ratio as the current value of the output current Io1. Note that the detection device 24 may have a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc. as necessary.

[0027] The configuration of the semiconductor device 10 according to this embodiment will be described in detail. The semiconductor device 10 according to this embodiment includes a current generation circuit 12, a control circuit 14, a power supply terminal VBB, a detection terminal SENSE, and an output terminal OUT. A power supply voltage Vbb is supplied to the power supply terminal VBB. A load 26 is connected to the output terminal OUT, and an output current Io1 flows through it. An ammeter 22 is connected to the detection terminal SENSE, and a sense current Is1 flows through it.

[0028] The current generation circuit 12 is configured to generate the output current Io1 and the sense current Is1 in accordance with the control by the control circuit 14. The sense current Is1 is a current obtained by multiplying the output current Io1 by a predetermined multiple. The current generation circuit 12 includes a transistor MNo1 (first transistor), a plurality of transistors MNs1 to MNs3 (second transistors), a transistor MP1, and an operational amplifier 120.

[0029] Transistor MNo1 is a power transistor, and in this embodiment, it is an N-channel type MOS (Metal Oxide Semiconductor) transistor. The on-resistance of transistor MNo1 is Ron_p. The drain of transistor MNo1 is connected to the power supply terminal VBB. The source of transistor MNo1 is connected to the output terminal OUT and the non-inverting input terminal of the operational amplifier 120.

[0030] Transistors MNs1 to MNs3 are respectively sense transistors provided for detecting the output current Io1, and in this embodiment, they are N-channel type MOS transistors. In this embodiment, an example where the number of sense transistors is three will be described, but the number of sense transistors may be two or four or more.

[0031] The on-resistances of transistors MNs1 to MNs3 are Ron_s1 to Ron_s3 respectively. The drains of transistors MNs1 to MNs3 are respectively connected to the drain of transistor MNo1. The sources of transistors MNs1 to MNs3 are respectively connected to the inverting input terminal of the operational amplifier 120.

[0032] In this embodiment, since the sources of transistor MNo1 and transistors MNs1 to MNs3 are connected to both input terminals of the operational amplifier 120, the sources of transistor MNo1 and transistors MNs1 to MNs3 can be made substantially at the same potential. Therefore, currents Ims1 to Ims3 flowing through transistors MNs1 to MNs3 can be generated more accurately according to the current Imo1 flowing through transistor MNo1.

[0033] Note that transistors MNo1, MNs1 to MNs3 are not limited to MOS transistors, and may be bipolar transistors or IGBTs (Insulated Gate Bipolar Transistors), etc., but it is preferably a MOS transistor that can operate at high speed.

[0034] In this embodiment, when the current ratio K is set to a value greater than 1, the sense current Is1 has a magnitude of 1 / K times the output current Io1. In other words, the current generation circuit 12 generates a sense current Is1 that is 1 / K times the output current Io1. The value of K may be, for example, on the order of several hundreds or several thousands. The accuracy required for the current ratio K increases as the output current Io1 increases.

[0035] The current ratio K can be adjusted by adjusting the size ratios of the transistors MNo1, MNs1 to MNs3. For example, the sizes of the transistors MNs1 to MNs3 may be set to about one-hundredth or one-thousandth of the size of the transistor MNo1.

[0036] The transistor MP1 is a P-channel MOS transistor. The source of the transistor MP1 is connected to the respective sources of the transistors MNs1 to MNs3. The gate of the transistor MP1 is connected to the output terminal of the operational amplifier 120. The drain of the transistor MP1 is connected to the detection terminal SENSE.

[0037] The control circuit 14 controls the operation of the current generation circuit 12. Specifically, it controls the operations of the transistors MNo1, MNs1 to MNs3. For example, the control circuit 14 inputs a signal So1 to the base of the transistor MNo1 to control the on / off state of the transistor MNo1. Also, the control circuit 14 inputs the corresponding signals among the signals Ss1 to Ss3 to the respective bases of the transistors MNs1 to MNs3 to control the on / off states of the transistors MNs1 to MNs3.

[0038] When the transistor MNo1 is turned on, a current Imo1 flows through the transistor MNo1. An output current Io1 corresponding to the current Imo1 flows through the load 26. In this embodiment, the output current Io1 is substantially the same as the current Imo1.

[0039] In this embodiment, when transistor MNo1 is in the on state, any one of transistors MNs1 to MNs3 is in the on state, and the remaining transistors among transistors MNs1 to MNs3 are in the off state. For example, when transistor MNs1 is in the on state, transistors MNs2 and MNs3 are in the off state. At this time, current Ims1 flows through transistor MNs1, and no current flows through transistors MNs2 and MNs3 (Ims2 = 0, Ims3 = 0). Current Ims1 flows into transistor MP1 in the on state, and a sense current Is1 corresponding to current Ims1 flows into ammeter 22. At this time, sense current Is1 is substantially the same as current Ims1.

[0040] When current Imo1 flows through transistor MNo1 and current Ims1 flows through transistor MNs1, if the offset between both input terminals of operational amplifier 120 is Vofs, Ron_p × Imo1 = Ron_s1 × Ims1 + Vofs holds.

[0041] Suppose current generation circuit 12 has one sense transistor (for example, only transistor MNs1 among transistors MNs1 to MNs3). In this case, when offset Vofs of operational amplifier 120 is sufficiently small, the pairing property (relationship such as the characteristics of the elements themselves and the arrangement of the elements) between the power transistor and the sense transistor becomes dominant in the current ratio between the sense current and the output current. If there is variation in the pairing property for each semiconductor device, that variation affects the accuracy of the current ratio. In this embodiment, as will be described in detail below, by using a plurality of transistors MNs1 to MNs3, the accuracy of the current ratio can be improved.

[0042] The control circuit 14 sequentially changes the transistors MNs1 to MNs3 that are in the on state. Note that, during this sequential change, the current ratio between the output current Io1 and the sense current Is1 is constant within the range of variations in the pairing between the transistor MNo1 and the transistors MNs1 to MNs3. In the present embodiment, the control circuit 14 turns on one of the transistors MNs1 to MNs3 and turns off the remaining transistors among the transistors MNs1 to MNs3. The control circuit 14 sequentially switches the transistors in the on state at high speed.

[0043] More specifically, the control circuit 14 uses a plurality of second transistors as the first to nth (n: an integer of 2 or more) control transistors, turns on the first to nth control transistors one by one in this order, and turns off the remaining transistors among the first to nth control transistors. In the present embodiment, the control circuit 14 turns on the transistors MNs1 to MNs3 (the first to third control transistors) one by one in this order and turns off the remaining transistors among the transistors MNs1 to MNs3. Thereby, all of the transistors MNs1 to MNs3 can be turned on evenly, and variations in the current ratio for each semiconductor device 10 can be further reduced.

[0044] FIG. 2 is a diagram showing an example of the layout of the transistor MNo1 and the transistors MNs1 to MNs3. As shown in FIG. 2, the transistors MNs1 to MNs3 are provided inside the transistor MNo1. The transistors MNs1 to MNs3 according to the present embodiment are turned on one by one in the order of transistors MNs1, MNs2, MNs3, MNs1, MNs2 ··· as indicated by the arrows in FIG. 2.

[0045] FIG. 3 is a timing chart of the signals Ss1 to Ss3 input to the bases of the transistors MNs1 to MNs3. As shown in FIG. 3, the signals Ss1 to Ss3 are switched to be high in this order, and when one signal is high, the remaining signals are low.

[0046] For example, in the interval T1 from timing t1 to t2, signal Ss1 goes high and signals Ss2 and Ss3 go low. Next, in the interval T2 from timing t2 to t3, signal Ss2 goes high and signals Ss1 and Ss3 go low. Next, in the interval T3 from timing t3 to t4, signal Ss3 goes high and signals Ss1 and Ss2 go low. Thereafter, signals Ss1, Ss2, and Ss3 sequentially go high. Note that intervals T1, T2, and T3 may be different from each other or may be the same. By making intervals T1, T2, and T3 the same, transistors MNs1 to MNs3 can be turned on evenly, and the variation in the current ratio K for the entire semiconductor device 10 can be further reduced.

[0047] The inventors performed Monte Carlo simulations (N = 200) for the cases where the number of sense transistors was 1, 3, and 5, created histograms of the current ratios, and obtained the standard deviation σ of the current ratios. The results of the Monte Carlo simulations showed that the larger the number of sense transistors, the smaller the standard deviation σ. If the standard deviation when the number of sense transistors is 1 is σ1, then when the number of sense transistors is m, the standard deviation σm generally agrees with σ1 / √m. Thus, the larger the number of sense transistors, the smaller the standard deviation σ. Therefore, the larger the number of sense transistors, the more the variation in the current ratio can be suppressed.

[0048] According to the current detection system 1 according to the first embodiment, the current generation circuit 12 generates a sense current Is1 corresponding to currents Ims1 to Ims3 flowing through transistors Ns1 to MNs3, which is a predetermined multiple of the output current Is1 corresponding to the current Imo1 flowing through transistor MNo1. The control circuit 14 sequentially changes the transistors that are turned on for the plurality of transistors MNs1 to MNs3.

[0049] As a result, since the current ratio K is averaged by the plurality of transistors MNs1 to MNs3, the variation in the current ratio K for the entire semiconductor device 10 can be suppressed as compared with the case of using a single sense transistor. As a result, it becomes possible to generate the sense current Is1 with a good current ratio. Further, based on this sense current Is1, it becomes possible to accurately detect the output current Io1.

[0050] Also, according to the current detection system 1 according to the present embodiment, a plurality of transistors MNs1 to MNs3 each functioning as a sense transistor are arranged. The transistors MNs1 to MNs3 are smaller than the transistor MNo1 that functions as a power transistor. Therefore, even when a plurality of transistors MNs1 to MNs3 are arranged, it is less likely to cause inconvenience in layout, and the operation control is also simple, and the accuracy of the current ratio K can be improved more simply.

[0051] With reference to FIGS. 4 and 5, a further effect of the semiconductor device 10 according to the present embodiment will be described. FIG. 4 is a diagram showing an example of a layout when the transistor MNs4 functioning as a single sense transistor is used. FIG. 5 is a diagram showing an example of a layout when the three transistors MNs1 to MNs3 according to the present embodiment are used.

[0052] In the example shown in FIG. 4, the transistor MNs4 is provided inside the transistor MNo2 that functions as a power transistor. The transistor MNo2 is provided with pads 160, 162, 164, 166 (wire bonding pads) for connecting the transistor to external terminals. The pads 162 and 164 are located closer to the transistor MNs4 than the pads 160 and 166. Therefore, the current density between the pads 162 and 164 and the transistor MNo2 is likely to be larger than the current density between the pads 160 and 166 and the transistor MNo2.

[0053] In the example shown in FIG. 5, the transistor MNo1 is provided with pads 180, 182, 184, 186 (wire bonding pads). As shown in FIG. 5, since one of the transistors MNs1 to MNs3 is present near the pads 180, 182, 184, 186, the variation in current density is suppressed. By suppressing this variation in current density, the variation in the current ratio K can be suppressed.

[0054] (Second Embodiment) In the first embodiment, an example in which there are a plurality of sense transistors has been described. In the second embodiment, there are a plurality of power transistors.

[0055] FIG. 6 is a diagram for explaining the function and configuration of the current detection system 2 according to the second embodiment. The current detection system 2 according to the present embodiment includes a semiconductor device 30, a power supply 20, an ammeter 22, and a detection device 24. In FIG. 6, the same reference numerals are given to substantially the same configurations as those in the first embodiment, and the description thereof will be omitted as appropriate.

[0056] The semiconductor device 30 receives a power supply voltage Vbb from the power supply 20 and supplies an output current Io2 (first current) to the load 26. The semiconductor device 30 has a function as a current generation device that generates a sense current Is2 (second current). The semiconductor device 30 includes a current generation circuit 32, a control circuit 34, a power supply terminal VBB, a detection terminal SENSE, and an output terminal OUT.

[0057] The current generation circuit 32 generates an output current Io2 and a sense current Is2 in accordance with the control by the control circuit 34. The sense current Is2 is a current obtained by multiplying the output current Io2 by a predetermined multiple. The current generation circuit 32 includes a plurality of transistors MNo3 to MNo5 (first transistors), a transistor MNs5 (second transistor), a transistor MP2, and an operational amplifier 320.

[0058] Transistors MNo3 to MNo5 are each power transistors, and in this embodiment, they are N-channel MOS transistors. The drains of transistors MNo3 to MNo5 are respectively connected to the power supply terminal VBB. The sources of transistors MNo3 to MNo5 are respectively connected to the output terminal OUT and the non-inverting input terminal of the operational amplifier 320.

[0059] Transistor MNs5 is a sense transistor, and in this embodiment, it is an N-channel MOS transistor. The drain of transistor MNs5 is connected to the respective drains of transistors MNo3 to MNo5. The source of transistor MNs5 is connected to the inverting input terminal of the operational amplifier 320.

[0060] Similar to the first embodiment, by adjusting the size ratio between transistors MNo3 to MNo5 and transistor MNs5, the current ratio between the output current Io2 and the sense current Is2 can be adjusted. For example, the size of transistor MNs5 may be set to about one-hundredth or one-thousandth of the size of transistors MNo3 to MNo5.

[0061] Transistor MP2 is a P-channel MOS transistor. The source of transistor MP2 is connected to the source of transistor MNs5. The gate of transistor MP2 is connected to the output terminal of the operational amplifier 320. The drain of transistor MP2 is connected to the detection terminal SENSE.

[0062] The control circuit 34 controls the operation of the current generation circuit 32. Specifically, it controls the operation of transistors MNo3 to MNo5 and MNs5. For example, the control circuit 34 inputs the corresponding signals among signals So3 to So5 to the respective bases of transistors MNo3 to MNo5 to control the on / off of transistors MNo3 to MNo5. Also, the control circuit 34 inputs signal Ss5 to the base of transistor MNs5 to control the on / off of transistor MNs5.

[0063] In this embodiment, any one of transistors MNo3 to MNo5 is turned on, and the remaining transistors are turned off. For example, when transistor MNo3 is turned on, it is assumed that transistors MNo4 and MNo5 are turned off. At this time, current Imo3 flows through transistor MNo3, and no current flows through transistors MNo4 and MNo5 (Imo4 = 0, Imo5 = 0). An output current Io2 corresponding to current Imo3 flows through load 26.

[0064] When transistor MNs5 is turned on, current Ims5 flows through transistor MNs5. Current Ims5 flows through transistor MP2 in the on state, and a sense current Is2 corresponding to current Ims5 flows through ammeter 22.

[0065] Control circuit 34 sequentially changes the transistors MNo3 to MNo5 that are turned on. Specifically, control circuit 34 turns on one of transistors MNo3 to MNo5 and turns off the remaining transistors among transistors MNo3 to MNo5. Control circuit 34 sequentially changes the transistor in the on state.

[0066] FIG. 7 is a diagram showing an example of the layout of transistors MNo3 to MNo5 and transistor MNs5. As shown in FIG. 7, transistor MNs5 is provided inside transistor MNo4. Note that transistor MNs5 may be provided inside other transistors MNo3 and MNo5. As indicated by the arrows in FIG. 7, the transistors MNo3 to MNo5 according to this embodiment are turned on one by one in the order of transistors MNo3, MNo4, MNo5, MNo3, MNo4, ···.

[0067] According to the current detection system 2 according to the second embodiment, for a plurality of transistors MNo3 to MNo5, the transistors in the on state are sequentially changed. As a result, compared with the case of using one power transistor, the variation in the current ratio for each semiconductor device 30 is suppressed, and the sense current Is2 can be generated with a good current ratio. As a result, it becomes possible to detect the output current Io2 with higher accuracy.

[0068] (Third Embodiment) The current detection system according to the third embodiment includes a plurality of power transistors in the same manner as the second embodiment, but mainly differs from the second embodiment in the configuration of the power transistors.

[0069] FIG. 8 is a diagram showing the layout of the power transistors MNo6 and MNo7 and the sense transistor MNs6 included in the current detection system according to the third embodiment. Each of the power transistors MNo6 and MNo7 according to the present embodiment may be configured in the same manner as one of the transistors MNo1 according to the first embodiment or the transistors MNo3 to MNo5 according to the second embodiment.

[0070] In the third embodiment, the power transistor MNo6 is divided into six divided transistors R11 to R16, and the power transistor MNo7 is divided into six divided transistors R21 to R26. The divided transistors R11 to R16 and R21 to R26 are each configured to be operable as an individual power transistor. These 12 power transistors are configured to be connected in parallel between the power supply terminal VBB and the output terminal OUT. In the present embodiment, six divided transistors R11, R13, R15, R22, R24, and R26 have the same capabilities as one of the power transistors MNo6 or MNo7, and six divided transistors R12, R14, R16, R21, R23, and R25 are configured to have the same capabilities as one of the power transistors MNo6 or MNo7.

[0071] The sense transistor MNs6 is provided in the divided transistor R25 of the power transistor MNo7. Note that the sense transistor MNs6 may be provided inside the power transistor MNo6, or may be provided in other divided transistors R21 to R24, R26 of the power transistor MNo7.

[0072] Also, in the present embodiment, the control circuit according to the third embodiment sequentially changes the power transistors in the on state so that two or more of the plurality of power transistors (first transistors) are in the on state. Specifically, the control circuit alternately sets the divided transistors R11, R13, R15, R22, R24, R26 (hatched divided transistors) and the divided transistors R12, R14, R16, R21, R23, R25 to the on state or the off state. The operations of the divided transistors R11 to R16, R21 to R26 may be controlled by the control circuit.

[0073] Here, a part of the divided transistors R11, R13, R15, R22, R24, R26 (for example, one divided transistor) or a part of the divided transistors R12, R14, R16, R21, R23, R25 (for example, one divided transistor) may always be in the on state. By keeping some of the divided transistors always in the on state, it is possible to suppress the situation where all of the divided transistors R11 to R16, R21 to R26 instantaneously turn off and the output current instantaneously stops flowing.

[0074] Also, when switching the on state and the off state of the divided transistors R11 to R16, R21 to R26, the time during which the divided transistors R11, R13, R15, R22, R24, R26 are in the on state and the time during which the divided transistors R12, R14, R16, R21, R23, R25 are in the on state may overlap. Thereby, it is possible to suppress the situation where all of the divided transistors R11 to R16, R21 to R26 instantaneously turn off and the output current instantaneously stops flowing.

[0075] According to the current detection system according to the third embodiment, compared with the case of using one power transistor (for example, one of the power transistors MNo6 and MNo7), similar to the above embodiment, variations in the current ratio can be suppressed, and a sense current can be generated with a good current ratio. Further, according to the semiconductor device according to the present embodiment, it is possible to reliably suppress the output current from becoming unstable when switching the divided transistors that are turned on.

[0076] (Modification example) In the above embodiment, an example of measuring the sense current mainly using an ammeter has been described. However, the present invention is not limited to this. Between the sense terminal SENSE and the ground, a sense resistor may be connected in series with the ammeter 22, and the sense current may be detected by measuring the voltage of this sense resistor with a voltmeter. For example, in the current detection system 1 according to the first embodiment shown in FIG. 1 or the current detection system 2 according to the second embodiment shown in FIG. 6, a sense resistor may be provided between the sense terminal SENSE and the current source 22, and the sense current may be detected based on the voltage of the sense resistor.

[0077] (Supplementary explanation) Regarding the embodiments according to the present disclosure, specific terms have been used for the description. However, this description is merely an exemplification for facilitating understanding and does not limit the present disclosure or the scope of the claims. The scope of the present invention is defined by the scope of the claims. Further, not only the embodiments but also the embodiments, examples, and modification examples not described here are included in the scope of the present invention.

[0078] One or more elements of one embodiment can be combined with one or more elements of another embodiment. For example, it is also possible to use a plurality of sense transistors as in the first embodiment and a plurality of power transistors as in the second or third embodiment.

[0079] (Supplementary note) The technology disclosed in this specification can be grasped as follows in one aspect.

[0080] (Item 1) A current generation circuit having a first transistor and a second transistor, and generating a second current corresponding to the current flowing through the second transistor, which is a predetermined multiple of a first current corresponding to the current flowing through the first transistor; A control circuit for controlling the operations of the first transistor and the second transistor; and The first transistor or the second transistor is plural; The control circuit sequentially changes the transistor in the on state for a plurality of first transistors or a plurality of second transistors. Current generation device.

[0081] (Item 2) When K is a value greater than 1, the second current has a magnitude of 1 / K times the first current. The current generation device according to Item 1.

[0082] (Item 3) The current generation circuit has a plurality of second transistors; The control circuit sequentially changes the second transistor in the on state for the plurality of second transistors. The current generation device according to Item 1 or 2.

[0083] (Item 4) The control circuit uses the plurality of second transistors as first to nth control transistors, turns on the first to nth control transistors one by one in this order, and turns off the remaining transistors among the first to nth control transistors. The current generation device according to Item 3.

[0084] (Item 5) The current generation circuit has a plurality of first transistors; The control circuit sequentially changes the first transistor in the on state for the plurality of first transistors. The current generation device according to any one of Items 1 to 4.

[0085] (Item 6) The control circuit sequentially changes the first transistors that are turned on so that two or more of the plurality of first transistors are turned on. The current generation device according to Item 5.

[0086] (Item 7) The current generation circuit further includes a first terminal through which the first current flows, a second terminal through which the second current flows, an operational amplifier, and a P-channel type MOS transistor. The first transistor and the second transistor are each an N-channel type MOS transistor. The drains of the first transistor and the second transistor are connected to each other. The source of the first transistor is connected to the non-inverting input terminal of the operational amplifier and the first terminal. The source of the second transistor is connected to the inverting input terminal of the operational amplifier and the source of the P-channel type transistor. The output terminal of the operational amplifier is connected to the gate of the P-channel type transistor. The drain of the P-channel type transistor is connected to the second terminal. The current generation device according to any one of Items 1 to 6.

[0087] (Item 8) The current generation device according to any one of Items 1 to 7, and a detection device that detects the first current based on the second current. A current detection system.

Description of Reference Numerals

[0088] 1,2 current detection system, 10,30 semiconductor device, 12,32 current generation circuit, 14,34 control circuit, 20 power supply, 22 ammeter, 24 detection device, 26 load, 120,320 operational amplifier, 160~166,180~186 pad, MNo1~MNo7,MNs1~MNs5,MP1,MP2 transistor, R11~R16,R21~R26 split transistor.

Claims

1. a current generating circuit having a first transistor and a second transistor, the current generating circuit generating a second current corresponding to a current flowing through the second transistor, the second current being a predetermined multiple of a first current corresponding to a current flowing through the first transistor; a control circuit that controls an operation of the first transistor and the second transistor; the first transistor or the second transistor is a plurality of transistors, the control circuit sequentially changes which of the first transistors or which of the second transistors is turned on; Current generator.

2. The second current has a magnitude 1 / K times that of the first current, where K is a value greater than 1. The current generating device according to claim 1 .

3. the current generating circuit includes a plurality of second transistors; the control circuit sequentially changes the second transistors to be turned on among the plurality of second transistors; The current generating device according to claim 2 .

4. the control circuit sets the plurality of second transistors as first to nth control transistors, turns the first to nth control transistors on one by one in this order, and turns the remaining transistors of the first to nth control transistors off; The current generating device according to claim 3 .

5. the current generating circuit includes a plurality of first transistors; the control circuit sequentially changes the first transistors to be turned on among the plurality of first transistors; The current generating device according to claim 2 .

6. the control circuit sequentially changes the first transistors to be turned on such that two or more of the plurality of first transistors are turned on; The current generating device according to claim 5 .

7. the current generating circuit further includes a first terminal through which the first current flows, a second terminal through which the second current flows, an operational amplifier, and a P-channel MOS transistor; the first transistor and the second transistor are N-channel MOS transistors, a drain of the first transistor and a drain of the second transistor are connected to each other; a source of the first transistor is connected to the non-inverting input terminal of the operational amplifier and the first terminal; a source of the second transistor is connected to an inverting input terminal of the operational amplifier and a source of the P-channel transistor; the output terminal of the operational amplifier is connected to the gate of the P-channel transistor; The drain of the P-channel transistor is connected to the second terminal. The current generating device according to claim 1 .

8. A current generating device according to any one of claims 1 to 7, a detection device that detects the first current based on the second current. Current sensing system.

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