Current sense circuit

Abstract

To provide a current sense circuit that has protection from deterioration or damage provided.SOLUTION: A current sense circuit is configured to: stack current mirror circuits QN1 and QN2 and a diode connection side (QN1, QP1 and QP3) of QP1 and QP2 having bases connected, and QP3 and QP4 in alignment of the current mirror circuit with the diode connection side, and connect an emitter of the QP2 and a collector of the QP4. Further, gates of MP1 and MP2 are connected to the QN2 and the collector of the QP2. Also, a source of MP1 is connected to a drain of MP3 via the drain from a source of MP2. And, an emitter of the QP4 is connected to a source of MP4 via R1, and a drain of the MP4 is connected to a source of a Main MOS (OUT terminal). Gates of the MP3 and MP4 are also connected to the emitters of the QN1 and QN2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to current sensing circuits. [Background technology]

[0002] A sense current is extracted from a power MOS (Metal Oxide Semiconductor) transistor with a current sensing function. The power MOS transistor includes a main MOS (hereinafter, Main MOS) and a sense MOS (hereinafter, Sense MOS), and the VDS of these are matched. Patent Document 1 discloses a technology for configuring a negative feedback control circuit for voltage and current using an operational amplifier. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-145219 A Summary of the Invention [Problem to be solved by the invention]

[0004] When an operational amplifier is used as disclosed in Patent Document 1, the circuit scale becomes large because it is necessary to generate a power supply for the operational amplifier. In addition, in automotive applications, when starting an engine at a low temperature using a deteriorated battery, operation is difficult due to low voltage. In addition, in automotive applications, protection is required when the battery is reverse-connected. Therefore, the object of the present disclosure is to provide a current sense circuit that has a small circuit scale, operates even at low voltage, and protects the circuit when the battery is reverse-connected.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, in a current sense circuit, in a normal power supply polarity state, a transistor is turned on and acts as a resistor, and in a reverse connection, the transistor is turned off and no current flows. Effect of the Invention

[0007] According to the embodiment, it is possible to provide a current sensing circuit that is protected from degradation or destruction. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a circuit diagram of a current sense circuit according to the first embodiment. [Diagram 2] FIG. 11 is a circuit diagram of a current sense circuit according to a second embodiment. [Diagram 3] FIG. 11 is a circuit diagram of a current sense circuit according to a third embodiment. [Figure 4] FIG. 13 is a circuit diagram of a current sense circuit according to a fourth embodiment. [Diagram 5] FIG. 2 is a circuit diagram of a related first current sensing circuit. [Figure 6] FIG. 4 is a circuit diagram of a related second current sensing circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in terms of hardware, by a CPU (Central Processing Unit), memory, and other circuits, and in terms of software, by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on the hardware, or a combination of these. In addition, in each drawing, the same elements are given the same symbols, and duplicate explanations are omitted as necessary.

[0010] The above-mentioned program can be stored and provided to a computer using various types of non-transitory computer readable media. The non-transitory computer readable medium includes various types of tangible storage media. Examples of the non-transitory computer readable medium include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROM (Read Only Memory), CD-R, CD-R / W, and semiconductor memory (e.g., mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may be provided to a computer by various types of transitory computer readable media. Examples of the transitory computer readable medium include electric signals, optical signals, and electromagnetic waves. The transitory computer readable medium can provide the program to a computer via a wired communication path such as an electric wire and an optical fiber, or via a wireless communication path.

[0011] (Description of the Current Sense Circuit According to the First Embodiment) Fig. 1 is a circuit diagram of a current sense circuit according to a first embodiment. Fig. 5 is a circuit diagram of a related first current sense circuit. Fig. 6 is a circuit diagram of a related second current sense circuit. The current sense circuit according to the embodiment will be described with reference to Figs. 1, 5 and 6.

[0012] A power MOS transistor with a current sense function (hereinafter also referred to as power MOS) incorporates a Sense MOS transistor (hereinafter also referred to as Sense MOS) with a small area ratio together with a Main MOS transistor (hereinafter also referred to as Main MOS) of the main current path. When the area of ​​the Sense MOS is 1 / 1000 of the area of ​​the Main MOS, a current of 1 / 1000 of the current flowing through the Main MOS is extracted from the Sense MOS. However, since the power MOS operates as a resistor in the linear region when ON, it is necessary to match the VDS of the Sense MOS and the Main MOS in order to obtain a sense current according to the area ratio. For this reason, in Patent Document 1, voltage negative feedback control is performed using an operational amplifier.

[0013] Also, as shown in Figure 6, current negative feedback control is used to match the VDS of the Sense MOS to the VDS of the Main MOS. When the same current flows through transistors of the same structure and area, the forward voltage (hereinafter, Vf) of the base-emitter diode is the same. Within the range where the influence of the base current of each bipolar transistor and the influence of the collector-emitter voltage of the collector current can be ignored, the diode sides (QN1, QP1, QP3) of the current mirror circuits QN1 and QN2 and QP1 and QP2, which are connected to each other by base connection, and QP3 and QP4, are stacked side by side. The collectors of QN2 and QP2 are connected to the gate of MP1, and the source of MP1 is connected to the emitter of QP3 and the source of the Sense MOS. The emitter of QP4 is connected to the source of the Main MOS (OUT terminal) through resistor R1. In this circuit, a bias current (hereafter referred to as IBIAS) is supplied from the common emitter of QN1 and QN2, and a sense current (hereafter referred to as ISENSE) is taken out from the drain of MP1. At this time, the transistor structure and area of ​​QN1 and QN2 are matched, the transistor structure and area of ​​QP1 and QP2 are matched, and the transistor structure and area of ​​QP3 and QP4 are matched. Also, the resistance value of R1 is matched to the ON resistance of the Sense MOS - the ON resistance of the Main MOS. By doing this, it is possible to obtain a sense current that matches the area ratio of the Main MOS and Sense MOS.

[0014] In this configuration, QP1 and QP2 are configured as a source follower that utilizes the Vf of QP1 for the purpose of ensuring the gate-source voltage (hereinafter, Vgs) necessary for MP1 to turn on and suppressing the voltage dependence of the second terminal current of QP4 associated with the variation in the gate-source voltage of MP1. It can be turned on and off at a higher Vgs compared to the two-stage Vf of QP2 and QP4. Furthermore, when the voltage dependence of the collector current of QP4 can be ignored, QP1 and QP2 can be deleted. In that case, the collector and base of QP3 and the base of QP4 are connected to the collector and base of QN1 and the base of QN2, and the collector of QP4, the collector of QN2, and the gate of MP1 are connected.

[0015] By flowing IBIAS, current flows through the base of QP4 via QN1 and QP1, and the base voltages of QP4 and QP3 are determined from the voltage of the OUT terminal. When the emitter voltage of QP3 = the emitter voltage of QP4, the emitter current of QP4 also becomes the same, so the collector current of QP2 that receives this balances the collector current of QN2. Similarly, when the emitter voltage of QP3 (= source of Sense MOS) > the emitter voltage of QP4 (= source of Main MOS) = OUT terminal - R1×IBIAS / 2), the collector current of QP2 < the collector current of QN2. At this time, the gate voltage of MP1 drops and the Ids current increases, and by drawing current from the Sense MOS, the source voltage of the Sense MOS and the source voltage of the Main MOS drop until they match. Conversely, when the emitter voltage of QP3 < the emitter voltage of QP4, the collector current of QP2 > the collector current of QN2. The gate voltage of MP1 rises and the Ids current decreases, and by reducing the current drawn from the Sense MOS, the source voltage of the Sense MOS and the source voltage of the Main MOS rise until they match. Through this series of negative feedback operations, the VDS of the Sense MOS and the Main MOS can be made equal, and a sense current corresponding to the area ratio can be extracted.

[0016] Current sense circuits are used for protection functions such as monitoring the safety of systems and preventing destruction in the event of an abnormality. They are often required to operate stably under voltage conditions lower than the normal operating power supply voltage range. In particular, in automotive applications, there is an operating limit under low voltage conditions that occurs when a degraded battery is used to start an engine at low temperatures. In addition, there is a back electromotive force that occurs when an inductive load current is cut off when a long wire harness or motor is used. In addition, compliance and immunity to large power supply voltage fluctuations caused by electromagnetic compatibility (EMC) noise that enters from the power supply line and output line via the wire harness are also important.

[0017] As a method of matching the VDS of the Sense MOS to the VDS of the Main MOS, voltage negative feedback control by an operational amplifier is used as shown in FIG. 1 of Patent Document 1. This is because the size of the circuit becomes large when a high-voltage transistor is used in the operational amplifier. In this case, if the power MOS that senses the current is on the high-voltage side, VDS is generated with the battery voltage (hereinafter, VB) as the reference potential. The low-potential side of the operational amplifier power supply that receives VDS also requires a floating ground (hereinafter, FGND) that is linked to VB. However, in the configuration of FIG. 5, a voltage lower than the FGND voltage is also required to generate FGND. Therefore, in current sensing applications that require operation in a voltage power supply range lower than normal operation, such as protection and monitoring functions, there is a problem that the current sensing circuit cannot operate at a low voltage because the minimum operating voltage at which the system operates is high. In addition, the PSRR (Power Supply Rejection Ratio) performance of the operational amplifier causes power supply voltage fluctuations to leak to the output. In addition, when the negative feedback control cannot keep up with the steep input voltage changes due to the frequency characteristics, a phase difference occurs between the input and output signals. As a result, the VDS of the Sense MOS and the VDS of the Main MOS no longer match, which causes a problem of deterioration in the accuracy of the extracted sense current.

[0018] When using the current negative feedback control shown in Figure 6, it is not necessary to generate the above FGND. In addition, the current negative feedback control shown in Figure 6 is suitable for operation from low voltages because the operating point voltage of the circuit is naturally determined by simply supplying IBIAS. In addition, the current negative feedback control shown in Figure 6 requires a small number of elements, so it does not require phase compensation capacitance in the circuit like a voltage negative feedback op-amp, making it easy to miniaturize and has good frequency characteristics. However, in applications where there is a lot of noise around the usage environment, such as automotive applications, if EMC (Electromagnetic Compatibility) noise including high-frequency components that enter through the wire harness cannot be properly canceled, a transient difference will occur between the VDS of the Sense MOS and the VDS of the Main MOS, deteriorating the accuracy of the sense current. In particular, when measures against deterioration and destruction against reverse connection of the power supply, which is required for automotive applications, are essential, a countermeasure circuit is required in addition to the current sense circuit. In addition, in the case of semiconductor products, countermeasure components such as a reverse current prevention diode and a current limiting resistor are required for the GND of the control circuit.

[0019] As shown in FIG. 1, the current sense circuit according to the first embodiment includes a first NPN bipolar transistor QN1 having an emitter that outputs IBIAS and a collector connected to the base. The current sense circuit also includes a second NPN bipolar transistor QN2 having an emitter connected to the emitter of QN1 and a base connected to the base of QN1. The current sense circuit also includes a first PNP bipolar transistor QP1 having a collector connected to the collector of QN1 and a base connected to the collector. The current sense circuit also includes a second PNP bipolar transistor QP2 having a collector connected to the collector of QN2 and a base connected to the base of QP1. The current sense circuit also includes a third PNP bipolar transistor QP3 having a collector connected to the emitter of QP1 and a base connected to the collector. The current sense circuit also includes a fourth PNP bipolar transistor QP4 having a collector connected to the emitter of QP2 and a base connected to the base of QP3. The current sense circuit also includes a first P-channel transistor MP1 having a gate connected to the collector of QN2 and a source that outputs ISENSE. The current sense circuit also includes a second P-channel transistor MP2, where MP1 has a drain connected to the source of MP2, a gate connected to the collector of QN2, and a source that outputs a sense current, and MP2 has a drain connected to the Sense MOS, a gate connected to the collector of QN2, and a source connected to MP1. The current sense circuit also includes a third P-channel transistor MP3 having a gate connected to the emitter of QN1 and a source connected to the emitter of QP3. The current sense circuit also includes a fourth P-channel transistor MP4 having a gate connected to the emitter of QN1 and a source connected to the emitter of QP4. The current sense circuit also includes a resistor R1 having a first terminal connected to the drain of MP4.The current sense circuit also includes an N-channel Sense MOS (Metal Oxide Semiconductor) transistor (hereinafter also referred to as Sense MOS) having a source connected to the drain of MP3 and the drain of MP2. The current sense circuit also includes an N-channel Main MOS transistor (hereinafter also referred to as Main MOS) having a source connected to the second terminal of R1 and the output. The gate of the Sense MOS transistor is connected to the gate of the Main MOS transistor. The drain of the Sense MOS transistor is connected to the drain of the Main MOS transistor and the battery voltage.

[0020] The current mirror circuits QN1 and QN2, QP1 and QP2 with their bases connected together, and the diode-connected sides of QP3 and QP4 (QN1, QP1, QP3) are stacked side by side, and the emitter of QP2 is connected to the collector of QP4. The gates of MP1 and MP2 are connected to the collectors of QN2 and QP2. The source of MP1 is connected to the drain of MP3 via the source and drain of MP2, and is also connected to the source of the Sense MOS. The emitter of QP4 is connected to the source of MP4 via R1, and the drain of MP4 is connected to the source of the Main MOS (OUT terminal). The gates of MP3 and MP4 are connected to the emitters of QN1 and QN2. In this case, QN1 and QN2, QP1 and QP2, QP3 and QP4, and MP3 and MP4 have the same structure and area. By matching the resistance value of R1 to the ON resistance of the Sense MOS minus the ON resistance of the Main MOS, IBIAS is supplied from the common emitter of QN1 and QN2, and ISENSE is taken from the drain of MP1.

[0021] When the power supply polarity is normal, MP2, MP3, and MP4 function as reverse transistors with the only difference being that their ON resistance increases, and they operate in the same way as in Figure 6. When the power supply is reverse-connected, MP2, MP3, and MP4 turn OFF, cutting off the abnormal current that flows from GND to VB.

[0022] As for the specific operation, when the power supply has the normal polarity, by flowing IBIAS, the gate voltages of MP3 and MP4 become lower than the source voltage by three levels of Vf of QP3, QP1, and QN1, so they turn on as reverse transistors. The same resistors are attached to the emitters of QP3 and QP4. In the steady state, since the voltage drops (caused by 1 / 2×IBIAS×the ON resistance of MP3 and MP4) are the same, the source voltage of the Main MOS (OUT terminal) to be compared and the source voltage of the Sense MOS do not deviate. In this state, a current flows through QN1 and QP1 to the base of QP4, and the base voltages of QP4 and QP3 are determined from the voltage drop of MP4 and R1×IBIAS / 2 from the voltage of the OUT terminal. When the emitter voltage of QP3 = the emitter voltage of QP4, the emitter current of QP4 also becomes the same. Therefore, the collector current of QP2 that receives this is balanced with the collector current of QN2. Similarly, when the emitter voltage of QP3 (= the source of the Sense MOS - the voltage drop of MP3) > the emitter voltage of QP4 (= the source of the Main MOS - R1 + the voltage drop of MP4 = OUT terminal - (the ON resistance of MP4 + R1)×IBIAS / 2), the collector current of QP2 < the collector current of QN2. When the gate voltages of MP1 and MP2 drop and turn on, and draw current from the Sense MOS, the source voltage of the Sense MOS and the source voltage of the Main MOS drop until they match. Conversely, when the emitter voltage of QP3 < the emitter voltage of QP4, the collector current of QP2 > the collector current of QN2. When the gate voltage of MP1 rises and the Ids current decreases, and the current drawn from the Sense MOS decreases, the source voltage of the Sense MOS and the source voltage of the Main MOS rise until they match. Through such a series of negative feedback operations, a sense current can be extracted according to the area ratio of the Sense MOS and the Main MOS.

[0023] On the other hand, when the power supply is reverse-connected, since the gate voltages of MP2, MP3, and MP4 become lower than Vf and turn off, the current path from IBIAS and ISENSE to VB is cut off.

[0024] With the above configuration, while maintaining the performance of the conventional basic configuration, it is possible to protect the circuit from deterioration and destruction by turning off MP2, MP3, and MP4 and cutting off the current when the power supply is reverse-connected, which is particularly required for automotive applications.

[0025] The above explanation was given using an example of a high-side system that turns on / off with VB as the reference voltage, but the same effect can be obtained by replacing the bipolar transistors with MOS transistors.In addition, by switching between N-type and P-type, it can also be applied to a low-side system that operates with the GND potential as the reference.

[0026] (Description of the Current Sense Circuit According to the Second Embodiment) 2 is a circuit diagram of a current sense circuit according to embodiment 2. The current sense circuit according to the embodiment will be described with reference to FIG.

[0027] 2, the current sense circuit according to the second embodiment includes a first capacitance element C1 having a first terminal connected to the base of QP3 and a second terminal connected to the emitter of QP4, and a second capacitance element C2 having a first terminal connected to the gate of MP1 and a second terminal connected to the emitter of QP4.

[0028] That is, a first capacitance element C1 is added between the base and emitter of QP4, and a second capacitance element C2 is added between the source of MP4 and the gates of MP1 and MP2. The current sensing accuracy during transient voltage fluctuations including EMC noise and high frequency components propagating to the VB and OUT terminals when the power MOS is ON is improved. Operation during steady state is the same as in embodiment 1, so a description is omitted.

[0029] In the first embodiment, when the power MOS is in the ON state, the source voltage (OUT terminal) of the Main MOS is received by the emitter of QP4, and the source voltage of the Sense MOS is received by the emitter of QP3, and the gate-source voltage of MP1 is generated from the difference in the collector currents of QN2 and QP2. The current flowing through MP1 is negatively feedback controlled to adjust the source voltage of the Sense MOS to the source voltage of the Main MOS. At this time, if a sudden voltage fluctuation and high-frequency EMC noise enter the source (OUT terminal) of the Main MOS, the generation of the collector difference current between QN2 and QP2 and the generation of the gate-source voltage of MP1 cannot keep up transiently. This causes an error in the extracted ISENSE.

[0030] In the second embodiment, in order to improve this problem, a first capacitance element C1 is added between the base and emitter of QP4, and a second capacitance element C2 is added between the source of MP4 and the gates of MP1 and MP2. By adding the first capacitance element C1, it is possible to suppress the change in the base-emitter voltage of QP4 when the source (OUT terminal) voltage of the Main MOS changes suddenly. Therefore, the difference current between the collector currents of QN2 and QP2 that drive MP1 does not follow high frequency and sudden voltage fluctuations, but rather follows the average value.

[0031] In addition, the second capacitance element C2 is added by taking advantage of the fact that the gate of MP1 has high impedance due to the collector connection of QN2 and QP2, and that VB ≒ VOUT when the power MOS is in the ON state. Therefore, even when a steep voltage fluctuation or high-frequency EMC noise is present at the OUT terminal, the change in the gate voltage of MP1 is linked to the OUT terminal. This makes it possible to prevent MP1 itself from generating abnormal current due to transient VGS fluctuations of MP1.

[0032] However, in this case, the capacitance values ​​of the first capacitance element C1 and the second capacitance element C2 change depending on the transistor structure and size and the BIAS current, so they must be adjusted to values ​​that provide the optimal effect depending on the noise slew rate to be addressed and the response frequency required for basic operation.

[0033] Compared to embodiment 1, the above configuration makes it possible to improve the current sensing accuracy when receiving back electromotive voltage that occurs when cutting off the current of an inductive load caused by the use of a long wire harness and motor, which are problems particularly in automotive applications, and EMC noise that enters from the power supply line and output line via the wire harness.

[0034] (Description of the Current Sense Circuit According to the Third Embodiment) 3 is a circuit diagram of a current sense circuit according to a third embodiment. The current sense circuit according to the third embodiment will be described with reference to FIG.

[0035] 3, the current sense circuit according to the third embodiment differs from that according to the first embodiment in the position of the resistor R1. The resistor R1 has a first terminal connected to the emitter of the fourth PNP bipolar transistor and a second terminal connected to the source of the fourth P-channel transistor. Even though the position of the resistor R1 differs from that according to the first embodiment, the current sense circuit can operate in the same manner.

[0036] (Description of the Current Sense Circuit According to the Fourth Embodiment) 4 is a circuit diagram of a current sense circuit according to a fourth embodiment. The current sense circuit according to the fourth embodiment will be described with reference to FIG.

[0037] 4, the current sense circuit according to the fourth embodiment differs from that according to the second embodiment in the position of the resistor R1. The resistor R1 has a first terminal connected to the emitter of the fourth PNP bipolar transistor and the second terminal of the first capacitance element, and a first terminal connected to the source of the fourth P-channel transistor and the second terminal of the second capacitance element. Thus, even if the position of the resistor R1 differs from that according to the second embodiment, the current sense circuit can operate in the same manner.

[0038] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention.

[0039] For example, a current sense circuit with the polarity of the above current sense circuit reversed includes a first PNP bipolar transistor having an emitter that outputs a BIAS current and a collector connected to the base. The current sense circuit also includes a second PNP bipolar transistor having an emitter connected to the emitter of the first PNP bipolar transistor and a base connected to the base of the first PNP bipolar transistor. The current sense circuit also includes a first NPN bipolar transistor having a collector connected to the collector of the first PNP bipolar transistor and a base connected to the collector. The current sense circuit also includes a second NPN bipolar transistor having a collector connected to the collector of the second PNP bipolar transistor and a base connected to the base of the first NPN bipolar transistor. The current sense circuit also includes a third NPN bipolar transistor having a collector connected to the emitter of the first NPN bipolar transistor and a base connected to the collector. The current sense circuit also includes a fourth NPN bipolar transistor having a collector connected to the emitter of the second NPN bipolar transistor and a base connected to the base of the third NPN bipolar transistor. The current sense circuit also includes a first N-channel transistor having a gate connected to the collector of the second PNP bipolar transistor and a drain for outputting a SENSE current. The current sense circuit also includes a second N-channel transistor having a gate connected to the collector of the second PNP bipolar transistor and a source connected to the source of the first N-channel transistor. The current sense circuit also includes a third N-channel transistor having a gate connected to the emitter of the first PNP bipolar transistor and a source connected to the emitter of the third NPN bipolar transistor. The current sense circuit also includes a fourth N-channel transistor having a gate connected to the emitter of the first PNP bipolar transistor and a source connected to the emitter of the fourth NPN bipolar transistor.The current sense circuit also includes a resistor having a first terminal connected to the drain of the fourth N-channel transistor. The current sense circuit also includes a P-channel Sense MOS transistor having a source connected to the drain of the third N-channel transistor and the drain of the second N-channel transistor. The current sense circuit also includes a P-channel Main MOS transistor having a source connected to the second terminal of the resistor and the output. The gate of the Sense MOS is connected to the gate of the Main MOS. The drain of the Sense MOS is connected to the drain of the Main MOS and to a ground voltage.

[0040] A current sense circuit in which the bipolar transistor of the current sense circuit is replaced with a MOS transistor includes a first N-channel transistor having a drain connected to a gate and a source that outputs a BIAS current. The current sense circuit also includes a second N-channel transistor having a source connected to the source of the first N-channel transistor and a gate connected to the gate of the first N-channel transistor. The current sense circuit also includes a first P-channel transistor having a drain connected to the drain of the first N-channel transistor and a gate connected to the drain. The current sense circuit also includes a second P-channel transistor having a drain connected to the drain of the second N-channel transistor and a gate connected to the gate of the first P-channel transistor. The current sense circuit also includes a third P-channel transistor having a drain connected to the source of the first P-channel transistor and a gate connected to the drain. The current sense circuit also includes a fourth P-channel transistor having a drain connected to the source of the second P-channel transistor and a gate connected to the gate of the third P-channel transistor. The current sense circuit also includes a fifth P-channel transistor having a gate connected to the drain of the second N-channel transistor and a drain that outputs a SENSE current. The current sense circuit also includes a sixth P-channel transistor having a gate connected to the drain of the second N-channel transistor and a source connected to the source of the fifth P-channel transistor. The current sense circuit also includes a seventh P-channel transistor having a gate connected to the source of the first N-channel transistor and a source connected to the source of the third P-channel transistor. The current sense circuit also includes an eighth P-channel transistor having a gate connected to the source of the first N-channel transistor and a source connected to the source of the fourth P-channel transistor. The current sense circuit also includes a resistor having a first terminal connected to the drain of the eighth P-channel transistor.The current sense circuit also includes an N-channel Sense MOS transistor having a source connected to the drain of the seventh P-channel transistor and the drain of the sixth P-channel transistor. The current sense circuit also includes an N-channel Main MOS transistor having a source connected to the second terminal of the resistor and the output. The gate of the Sense MOS is connected to the gate of the Main MOS. The drain of the Sense MOS is connected to the drain of the Main MOS and the battery voltage.

[0041] In the current sense circuit with MOS transistors, the P-channel type can be replaced with the N-channel type, and the N-channel type can be replaced with the P-channel type, and the battery voltage can be replaced with the ground voltage.

Claims

1. a first NPN bipolar transistor having an emitter for outputting a BIAS current and a collector connected to a base; a second NPN bipolar transistor having an emitter connected to the emitter of the first NPN bipolar transistor and a base connected to the base of the first NPN bipolar transistor; a first PNP bipolar transistor having a collector connected to the collector of the first NPN bipolar transistor and a base connected to the collector; a second PNP bipolar transistor having a collector connected to the collector of the second NPN bipolar transistor and a base connected to the base of the first PNP bipolar transistor; a third PNP bipolar transistor having a collector connected to the emitter of the first PNP bipolar transistor and a base connected to the collector; a fourth PNP bipolar transistor having a collector connected to the emitter of the second PNP bipolar transistor and a base connected to the base of the third PNP bipolar transistor; a first P-channel transistor having a gate connected to the collector of the second NPN bipolar transistor and a drain for outputting a SENSE current; a second P-channel transistor having a gate connected to the collector of the second NPN bipolar transistor and a source connected to a source of the first P-channel transistor; a third P-channel transistor having a gate connected to the emitter of the first NPN bipolar transistor and a source connected to the emitter of a third PNP bipolar transistor; a fourth P-channel transistor having a gate connected to the emitter of the first NPN bipolar transistor and a source connected to the emitter of the fourth PNP bipolar transistor; a resistor having a first terminal connected to the drain of the fourth P-channel transistor; an N-channel sense MOS (Metal Oxide Semiconductor) transistor having a source connected to the drain of the third P-channel transistor and the drain of the second P-channel transistor; an N-channel type Main MOS transistor having a source connected to the second terminal of the resistor and an output; The gate of the sense MOS transistor is connected to the gate of the main MOS transistor, A current sense circuit, wherein the drain of the Sense MOS transistor is connected to the drain of the Main MOS transistor and a battery voltage.

2. a first capacitive element having a first terminal connected to the base of the third PNP bipolar transistor and a second terminal connected to the emitter of the fourth PNP bipolar transistor; a second capacitive element having a first terminal connected to the gate of the first P-channel transistor and a second terminal connected to the emitter of the fourth PNP bipolar transistor.

3. a first PNP bipolar transistor having an emitter for outputting a BIAS current and a collector connected to a base; a second PNP bipolar transistor having an emitter connected to the emitter of the first PNP bipolar transistor and a base connected to the base of the first PNP bipolar transistor; a first NPN bipolar transistor having a collector connected to the collector of the first PNP bipolar transistor and a base connected to the collector; a second NPN bipolar transistor having a collector connected to the collector of the second PNP bipolar transistor and a base connected to the base of the first NPN bipolar transistor; a third NPN bipolar transistor having a collector connected to the emitter of the first NPN bipolar transistor and a base connected to the collector; a fourth NPN bipolar transistor having a collector connected to the emitter of the second NPN bipolar transistor and a base connected to the base of the third NPN bipolar transistor; a first N-channel transistor having a gate connected to the collector of the second PNP bipolar transistor and a drain for outputting a SENSE current; a second N-channel transistor having a gate connected to the collector of the second PNP bipolar transistor and a source connected to a source of the first N-channel transistor; a third N-channel transistor having a gate connected to the emitter of the first PNP bipolar transistor and a source connected to the emitter of the third NPN bipolar transistor; a fourth N-channel transistor having a gate connected to the emitter of the first PNP bipolar transistor and a source connected to the emitter of the fourth NPN bipolar transistor; a resistor having a first terminal connected to the drain of the fourth N-channel transistor; a P-channel sense MOS transistor having a source connected to the drain of the third N-channel transistor and the drain of the second N-channel transistor; a P-channel type Main MOS transistor having a source connected to the second terminal of the resistor and an output; The gate of the sense MOS transistor is connected to the gate of the main MOS transistor, a drain of the Sense MOS transistor is connected to the drain of the Main MOS transistor and a ground voltage;

4. a first capacitive element having a first terminal connected to the base of the third NPN bipolar transistor and a second terminal connected to the emitter of the fourth NPN bipolar transistor; 4. The current sense circuit of claim 3, further comprising: a second capacitive element having a first terminal connected to the gate of the first N-channel transistor and the emitter of the fourth NPN bipolar transistor.

5. a first N-channel transistor having a source for outputting a BIAS current and a drain connected to a gate; a second N-channel transistor having a source connected to the source of the first N-channel transistor and a gate connected to the gate of the first N-channel transistor; a first P-channel transistor having a drain connected to the drain of the first N-channel transistor and a gate connected to the drain; a second P-channel transistor having a drain connected to the drain of the second N-channel transistor and a gate connected to the gate of the first P-channel transistor; a third P-channel transistor having a drain connected to the source of the first P-channel transistor and a gate connected to the drain; a fourth P-channel transistor having a drain connected to the source of the second P-channel transistor and a gate connected to the gate of the third P-channel transistor; a fifth P-channel transistor having a gate connected to the drain of the second N-channel transistor and a drain for outputting a SENSE current; a sixth P-channel transistor having a gate connected to the drain of the second N-channel transistor and a source connected to the source of the fifth P-channel transistor; a seventh P-channel transistor having a gate connected to the source of the first N-channel transistor and a source connected to the source of the third P-channel transistor; an eighth P-channel transistor having a gate connected to the source of the first N-channel transistor and a source connected to the source of the fourth P-channel transistor; a resistor having a first terminal connected to the drain of the eighth P-channel transistor; an N-channel sense MOS transistor having a source connected to the drain of the seventh P-channel transistor and the drain of the sixth P-channel transistor; an N-channel type Main MOS transistor having a source connected to the second terminal of the resistor and an output; The gate of the sense MOS transistor is connected to the gate of the main MOS transistor, A current sense circuit, wherein the drain of the Sense MOS transistor is connected to the drain of the Main MOS transistor and a battery voltage.

6. a first capacitive element having a first terminal connected to a gate of the third P-channel transistor and a second terminal connected to a source of the fourth P-channel transistor; a second capacitive element having a first terminal connected to the gate of the fifth P-channel transistor and a second terminal connected to the source of the fourth P-channel transistor.

7. The N-channel type is replaced with a P-channel type, The P-channel type is replaced with an N-channel type, 6. The current sense circuit of claim 5, wherein the battery voltage is replaced by a ground voltage.

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