Semiconductor device

Abstract

To provide a DCDC converter which achieves improvement in power conversion efficiency.SOLUTION: A semiconductor device includes: a transistor which functions as a switching element for controlling output power and comprises a back gate electrode for controlling a threshold voltage in addition to a normal gate electrode; and a back gate control circuit for controlling a level of a voltage applied to the back gate electrode according to a magnitude of an output voltage output from a DCDC converter. By controlling potential applied to the back gate electrode by the back gate control circuit, the threshold voltage can be adjusted in such a manner that on-resistance is decreased when the output power is large and the threshold voltage can be adjusted in such a manner that an off-state current is decreased when the output power is small. in addition, the transistor functioning as the switching element is an insulated gate filed effect transistor having an extremely small off-state current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a DC-DC converter, a power supply circuit, and a semiconductor device using a thin semiconductor film. do. [Background technology]

[0002] In recent years, the high mobility achieved by polysilicon and microcrystalline silicon and the high mobility achieved by amorphous silicon have been Oxide semiconductors are being developed as new semiconductor materials that combine uniform device characteristics obtained by the use of Metal oxides, which are called conductors and exhibit semiconducting properties, are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid It is used as a transparent electrode material in liquid crystal display devices. Examples of the oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Transistors that use metal oxides that exhibit such semiconducting properties in the channel formation region are already known. It has been reported (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0004] By the way, the DC-DC converter is designed to obtain a constant output voltage regardless of the input voltage. It is a constant voltage circuit that can be used in power supply circuits together with rectifier circuits. A power supply circuit using a switching DC / DC converter is a switching power supply or It is called a switching regulator.

[0005] A switching-type DC-DC converter uses a switching element to generate pulses from the input voltage. A voltage having a waveform like this is formed, and the voltage is smoothed or By holding the voltage at the desired level, a desired output voltage is obtained. The current in the DC-DC converter is much lower than that in the linear method, which uses a voltage drop caused by a resistor. Since the internal power loss can be theoretically reduced, the power conversion efficiency is high and there is no power loss. This allows the amount of heat generated by large output devices such as microprocessors to be kept small. In semiconductor devices that require a power supply voltage, a power supply using a switching DC / DC converter is used. Power circuits are used extensively.

[0006] However, switching DC / DC converters offer higher power conversion efficiency than linear converters. However, in order to reduce the power consumption of semiconductor devices, further improvement of the power conversion efficiency is required. In particular, the energy stored in various batteries such as primary batteries and secondary batteries, and in capacitors, etc. In the case of portable electronic devices that use stored power, the voltage output from a battery or capacitor, etc. To convert to the optimal size, a DC / DC converter is required. Improving the power conversion efficiency of the converter reduces the power consumption of the semiconductor device and extends the life of the device. In this case, it is possible to secure a long continuous use time of a portable electronic device using the semiconductor device. do.

[0007] In view of the above problems, the present invention provides a DC-DC converter that realizes improved power conversion efficiency, Another object of the present invention is to provide a power supply circuit using the above DC-DC converter. One object is to reduce power consumption of a semiconductor device using a DC-DC converter. [Means for solving the problem]

[0008] The inventors have found that the power conversion efficiency of a DC-DC converter is improved by using a switch to control the output power. The on-resistance or off-current of the transistor that functions as the switching element is important. When the output power of the DC-DC converter is small, the on-state of the transistor The power loss due to the off-state current of the transistor is greater than the power loss due to the on-resistance of the power converter. This leads to a decrease in efficiency. Also, when the output power of the DC-DC converter is large, Power loss due to the on-resistance of a transistor is greater than power loss due to the off-current of the transistor. would lead to a reduction in power conversion efficiency.

[0009] Therefore, the DC-DC converter according to one aspect of the present invention has a function as a switching element. In addition to a normal gate electrode, a transistor has a channel forming region sandwiched between the gate A back gate electrode is provided facing the electrode to control the threshold voltage. Then, the back gate electrode is turned on according to the magnitude of the output power from the DC-DC converter. The back gate control circuit controls the level of the potential applied to the When the output power is large, the control circuit controls the potential applied to the back gate electrode. When the threshold voltage is adjusted to lower the on-resistance (when the threshold voltage exceeds a certain value), the output power is reduced. If the off-current is small (below a certain value), the threshold voltage can be adjusted to reduce the off-current. can.

[0010] Furthermore, in the DC-DC converter according to one aspect of the present invention, The transistor that is used is an insulated gate field effect transistor (hereinafter referred to as The transistor is characterized in that it is a semiconductor. A semiconductor with a wider band gap than silicon and a lower intrinsic carrier density than silicon. The semiconductor device is characterized in that the semiconductor material is contained in the channel forming region. By including the dielectric material in the channel formation region, the off-current is extremely low and the breakdown voltage is high. A transistor can be realized. Examples of such semiconductor materials include silicon. An example of such an oxide semiconductor is one having a band gap approximately three times larger than that of an oxide semiconductor having the above-mentioned structure. By using a transistor with a high output current as a switching element, This prevents deterioration of the switching element due to the application of a large current, and when the output power is small, the off-state current is The flow can be significantly reduced.

[0011] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid A highly purified oxide semiconductor (purified OS) with reduced electron vacancies is i-type (intrinsic semiconductor) or very close to i-type. The transistor has the characteristic of having a very low off-state current. Physical semiconductors are processed using secondary ion mass spectrometry (SIMS). The hydrogen concentration measured by spectrometry was 5×10 19 / cm 3 below, Preferably 5 x 10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The following is further Preferably 1 x 10 16 / cm 3 The following can also be measured by Hall effect measurement. The carrier density of the oxide semiconductor film is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 In addition, the oxide semiconductor The band gap of the The concentration of impurities such as moisture and hydrogen is sufficiently reduced, and oxygen deficiency is also reduced. By using an oxide semiconductor film that has been highly purified by the above treatment, You can lower the flow.

[0012] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The hydrogen concentration in the conductive film is measured by SIMS. It is known that it is difficult to obtain accurate data on the interface between layers of different materials. Therefore, when analyzing the distribution of hydrogen concentration in the thickness direction of a film by SIMS, Within the range where the target film exists, the value does not fluctuate dramatically and an almost constant value is obtained. The average value in the region is adopted as the hydrogen concentration. In this case, we found a region where the hydrogen concentration in the adjacent film was almost constant. In this case, the maximum or minimum hydrogen concentration in the region where the film exists may not be obtained. The minimum value is adopted as the hydrogen concentration in the film. If there is no mountain-shaped peak having a maximum value or a valley-shaped peak having a minimum value, The value at that point is taken as the hydrogen concentration.

[0013] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer The low value of can be proved by various experiments. For example, when the channel width is 1×10 6 μm Even if the channel length of the device is 10 μm, the voltage between the source and drain electrodes (drain The off-state current (voltage between the gate and source electrodes) is in the range of 1V to 10V. The drain current when the input voltage is set to 0 V or less is below the measurement limit of the semiconductor parameter analyzer. , i.e. 1 × 10 -13 In this case, the off-current can be reduced to less than 1 A. The off-state current density, which corresponds to the value divided by the channel width of the transistor, is 100zA / μm or more. In addition, by connecting the capacitor and the transistor, or a circuit that controls the charge flowing out of a capacitor using the transistor. In the measurement, a highly purified oxide semiconductor film was formed in the transistor. It is used in the channel formation region, and the charge amount per unit time of the capacitance element is used to calculate the capacitance of the transistor. The off-state current density of the transistor was measured. At a voltage of 3 V, even lower off-state current densities of a few tens of yA / μm can be obtained. Therefore, in the semiconductor device according to one embodiment of the present invention, a highly purified oxide semiconductor The off-state current density of a transistor using a conductive film as an active layer was measured by Depending on the voltage between the two terminals, the current may be 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably Therefore, the highly purified oxide semiconductor film can be formed with a high conductivity. The transistor used as the active layer is made of crystalline silicon. This is significantly lower than that of transistors.

[0014] The oxide semiconductor is an In-Sn-Ga-Zn-O oxide semiconductor, which is a quaternary metal oxide. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides Semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, , In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. In the present specification, for example, an In-Sn-Ga-Zn-O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The composition ratio is not particularly limited. The semiconductor may include silicon.

[0015] Alternatively, the oxide semiconductor may be represented by the chemical formula InMO 3 (ZnO) m (m>0, m is a natural number. Here, M is Zn, Ga, Al, Mn, and Co. It represents one or more metal elements selected from the above. For example, M is Ga, Ga and Al, G Examples include Al and Mn, or Ga and Co. Effect of the Invention

[0016] In one embodiment of the present invention, with the above-described structure, when the output power is large, the on-resistance of the transistor is When the output power is small, the off-state current of the transistor can be reduced. Therefore, it is important to determine that the main factors that lead to power loss differ depending on the output power. By taking measures to reduce power loss according to the cause, the DC / DC converter and the above The power conversion efficiency of a power supply circuit using a DC-DC converter can be improved. By improving the power conversion efficiency of the DC-DC converter, The power consumption of the semiconductor device can be reduced. [Brief description of the drawings]

[0017] [Figure 1] A diagram showing the configuration of a DC-DC converter and a diagram showing the cross-sectional structure of a transistor. [Diagram 2] FIG. 1 is a diagram showing an example of the configuration of a DC-DC converter. [Diagram 3] 1 is a timing chart showing the operation of a DC-DC converter. [Figure 4] 1 is a timing chart showing the operation of a DC-DC converter. [Diagram 5] 1A and 1B are a top view and a cross-sectional view of a transistor. [Figure 6] FIG. 1 is an enlarged top view of a portion of a transistor. [Figure 7] Graph showing measured values ​​of drain current Id (A) versus gate voltage Vgs (V). [Figure 8] 1 is a graph showing the relationship between output power Wout (W) and power conversion efficiency (%). [Figure 9] FIG. 2 is a diagram showing an example of the configuration of an output voltage control circuit. [Figure 10] FIG. 2 is a diagram showing an example of the configuration of a backgate control circuit. [Figure 11] FIG. 1 is a diagram showing an example of the configuration of a DC-DC converter. [Figure 12] FIG. 1 is a diagram showing a configuration of a lighting device. [Figure 13] FIG. 1 is a diagram showing the configuration of a solar cell. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 15] FIG. 1 illustrates a structure of a transistor. [Figure 16] Circuit diagram of the characteristic evaluation circuit. [Figure 17] 4 is a timing chart of a characteristic evaluation circuit. [Figure 18] 4 is a diagram showing the relationship between the elapsed time Time and the potential Vout of the output signal in the characteristic evaluation circuit. [Figure 19] FIG. 13 is a graph showing the relationship between the elapsed time Time in the characteristic evaluation circuit and the leakage current calculated by the measurement. [Figure 20] FIG. 13 is a graph showing the relationship between the potential of node A and the leakage current in the characteristic evaluation circuit. [Figure 21] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0019] In addition, integrated circuits such as microprocessors and image processing circuits, RF tags, storage media, solar Batteries, lighting devices using light-emitting elements, semiconductor display devices, DC-DC converters or power supplies Any and all semiconductor devices in which the circuitry can be used are included within the scope of the present invention. The semiconductor display device includes a liquid crystal display device and a light-emitting device such as an organic light-emitting diode (OLED). Light-emitting device, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Fi DC-DC converter or power supply circuit, such as 100V Emission Display The semiconductor display device having the above-mentioned structure is included in the category.

[0020] (Embodiment 1) FIG. 1A shows an example of a configuration of a DC-DC converter according to one embodiment of the present invention. vinegar.

[0021] The DC-DC converter 100 shown in FIG. 1A converts a voltage (input voltage) given to an input terminal IN into This is a power conversion circuit that uses a constant voltage (output voltage) to generate a constant voltage (output terminal OUT). The power conversion circuit 101 includes a transistor that functions as a switching element. The power supply 102 includes a constant voltage generating unit 103.

[0022] When the transistor 102 is on, it supplies an input voltage to the constant voltage generating unit 103. When the transistor 102 is off, it supplies an input voltage to the constant voltage generating unit 103. When the transistor 102 is turned off, the supply of the constant voltage is stopped. A fixed voltage such as ground is applied to 103. Therefore, the switching According to the switching, the input voltage and the fixed voltage appear alternately as a pulse signal, generating a constant voltage. The signal is supplied to the signal generating unit 103.

[0023] The constant voltage generating unit 103 has one or more of a coil, a capacitance element, and a diode. When a pulse signal is supplied to the constant voltage generating unit 103, the constant voltage generating unit 103 smoothes the voltage of the signal. By adjusting or holding the voltage, a constant output voltage is generated.

[0024] Furthermore, in the DC-DC converter 100 shown in FIG. 1A, when the transistor 102 is on, The output voltage control circuit 104 controls the ratio of the on and off times. By controlling the ratio of the on time and the off time of the transistor 102 in the path 104, In the pulse-shaped signal supplied to the constant voltage generating unit 103, the ratio of the period during which the pulse appears is In other words, the duty ratio can be controlled.

[0025] The switching of the transistor 102 is performed by the voltage Vgs between the gate electrode and the source electrode. The output voltage control circuit 104 controls the time change of the gate voltage Vgs. This controls the ratio of the on time and off time of the transistor 102.

[0026] When the duty ratio changes, the output voltage also changes. The greater the percentage of the period during which the pulse occurs, the greater the difference between the output voltage and the fixed voltage. The smaller the ratio of the period during which the input voltage pulse appears, the smaller the difference between the output voltage and the fixed voltage. It becomes smaller.

[0027] In one embodiment of the present invention, the transistor 102 has a threshold in addition to a normal gate electrode. The transistor is characterized by having a back gate electrode for controlling the value voltage. The transistor 102 has a semiconductor film that functions as an active layer, a gate electrode, and a semiconductor film sandwiched therebetween. The transistor has a back gate electrode located at a position overlapping the gate electrode. The transistor 102 is a gate electrode and a semiconductor film, and an insulating film formed between the back gate electrode and the semiconductor film. The semiconductor device has an insulating film formed between the semiconductor film and a source electrode and a drain electrode in contact with the semiconductor film. do.

[0028] In the DC-DC converter shown in FIG. The back gate control circuit 105 controls the potential applied to the transistor. The threshold voltage of 102 is adjusted by adjusting the back gate voltage Vbgs between the back gate electrode and the source electrode. The back gate control circuit 105 can control the DCD The back gate voltage is set according to the magnitude of the power (output power) output from the C converter 100. The back gate voltage Vbgs is adjusted by controlling the potential applied to the electrode of the transistor 10. The threshold voltage of 2 is controlled according to the magnitude of the output power.

[0029] Specifically, when the output power is large (exceeding a predetermined value), the back gate control circuit 105 In this case, the back gate voltage Vbgs is increased to shift the threshold voltage in the negative direction. This reduces the on-resistance of the transistor 102. 05, when the output power is small (less than a specified value), the back gate voltage V By lowering bgs and shifting the threshold voltage in the positive direction, the transistor 102 Reduce the off-state current.

[0030] With the above configuration, when the output power of the DC-DC converter 100 is small, the transistor The power loss due to the off-current of the transistor 102 is greater than the power loss due to the on-resistance of the transistor 102. By prioritizing the reduction of DCD, it is possible to prevent the reduction of power conversion efficiency. When the output power of the C converter 100 is large, the off-current of the transistor 102 The power loss due to the on-resistance of the transistor 102 is suppressed to a low level, rather than the power loss. This makes it possible to prevent a decrease in power conversion efficiency.

[0031] Unless otherwise specified, in this specification, the off-state current is In this case, the drain electrode is set at a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and the gate electrode. When the potential of the gate electrode is set to a reference potential, the potential of the gate electrode is less than 0. This refers to the current that flows between the source and drain electrodes when the potential is above the threshold.

[0032] In addition, in the DC-DC converter 100 according to one embodiment of the present invention, The semiconductor film has a wider band gap than silicon semiconductor and an intrinsic carrier density similar to that of silicon. The wide-gap semiconductor material has a gap smaller than that of the conventional wide-gap semiconductor. Examples of these include compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), and oxide semiconductors. An oxide semiconductor made of a metal oxide such as zinc (ZnO) can be used. However, compound semiconductors such as silicon carbide and gallium nitride must be single crystals. In order to obtain a crystalline material, crystal growth at temperatures significantly higher than the process temperature of oxide semiconductors is required. The manufacturing conditions are strict, such as the length of the crystal and the need for epitaxial growth on a special substrate. However, it is difficult to form a film on silicon wafers or glass substrates, which are easily available, because the heat resistance of these substrates is low. However, oxide semiconductors can be manufactured by sputtering or wet methods (such as printing). In addition, oxide semiconductors can be formed into films at room temperature. Therefore, it is possible to form a film on a glass substrate or on an integrated circuit using a semiconductor element. Therefore, it is possible to accommodate larger substrates. Among them, oxide semiconductors have the advantage of being easily mass-producible. In order to obtain a crystalline oxide semiconductor in order to improve the performance (for example, the field effect mobility), Even in this case, a crystalline oxide semiconductor can be obtained by heat treatment at 200 to 800°C. do.

[0033] In the following description, oxide semiconductors having the above-mentioned advantages are used as semiconductors with a large band gap. The case where a compound semiconductor is used is given as an example.

[0034] By including a semiconductor material having the above-mentioned characteristics in the channel formation region, the off-current is extremely It is possible to realize a transistor 102 having the lowest possible resistance and high breakdown voltage. By using the transistor 102 having the above configuration as a switching element, When the output power is large, deterioration of the switching element due to the application of high voltage can be prevented. When is small, the off-state current can be suppressed significantly.

[0035] FIG. 1B shows the structure of a top-gate transistor 102 having a channel etch structure. is shown in cross section as an example.

[0036] The transistor 102 shown in FIG. 1B has a gate electrode 1 formed on a substrate 120 having an insulating surface. 10, an insulating film 111 on the gate electrode 110, and a gate electrode 1 10, a semiconductor film 112 overlapping the source electrode 113 and the drain electrode 114 on the semiconductor film 112. A source electrode 114, an insulating film on the semiconductor film 112, a source electrode 113 and a drain electrode 114 115, and a back gate electrode 112 overlapping the semiconductor film 112 with the insulating film 115 sandwiched therebetween. Further, the back gate electrode 116 is covered with an insulating film 117. The transistor 102 may have an insulating film 117 added to its components.

[0037] The transistor 102 shown in FIG. 1B is a bottom-gate transistor and has a source electrode A portion of the semiconductor film 112 located between the source electrode 113 and the drain electrode 114, i.e., the source The part of the semiconductor film 112 that does not overlap with the electrode 113 and the drain electrode 114 is etched. 4 shows an example of a channel etch structure.

[0038] Note that FIG. 1B illustrates the case where the transistor 102 has a single-gate structure. However, the transistor 102 has multiple gate electrodes 110 electrically connected to each other. In this way, a multi-gate structure having a plurality of channel formation regions may be used.

[0039] In addition, an inorganic material such as silicon oxide or silicon oxynitride containing oxygen is in contact with the semiconductor film 112. By using the insulating film 115, the semiconductor Even if oxygen vacancies occur in the film 112, oxygen is transferred from the insulating film 115 to the semiconductor film 112. This structure provides oxygen vacancies that act as donors and satisfies the stoichiometric composition ratio of the semiconductor material. In addition, the semiconductor film 112 may contain oxygen in an amount exceeding the stoichiometric composition. Therefore, the semiconductor film 112 can be made closer to an i-type semiconductor film. The variation in the electrical characteristics of the transistor 102 caused by elemental defects is reduced, and the electrical characteristics are improved. It is possible.

[0040] In addition, oxygen is added to the oxide semiconductor by performing heat treatment on the semiconductor film 112 in an oxygen atmosphere. In this case, oxygen vacancies that serve as donors in the semiconductor film 112 may be reduced. The temperature is, for example, 100° C. or higher and lower than 350° C., preferably 150° C. or higher and lower than 250° C. The oxygen gas used in the heat treatment in the oxygen atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas introduced into the heat treatment device is preferably 6N (99.999 9%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration in oxygen It is preferable to set the concentration to 1 ppm or less, and more preferably 0.1 ppm or less.

[0041] Alternatively, oxygen may be introduced into the semiconductor film 112 by ion implantation or ion doping. By adding oxygen, it is possible to reduce the oxygen vacancies that act as donors. Oxygen plasma generated by microwaves may be added to the semiconductor film 112 .

[0042] In this specification, an oxynitride is a material having a composition in which oxygen is more abundant than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means substance.

[0043] Next, an example of a specific configuration of the power conversion circuit 101 will be described.

[0044] In this specification, the term "connection" means electrical connection, and the term "connection" means a state in which a current, a voltage, or a potential is Therefore, the connected state corresponds to a direct connection. It does not necessarily refer to the state in which a current, voltage or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via another means.

[0045] In addition, even if components that are independent on the circuit diagram are connected, In the case where a conductive film is connected to a plurality of components, for example, when a part of the wiring also functions as an electrode, In this specification, the term "connection" refers to such a conductive A membrane that combines the functions of multiple components is also included in this category.

[0046] The source electrode and the drain electrode of the transistor are connected to each other. The name is changed depending on the difference in potential between the electrodes. Generally, n-channel In a transistor with a low potential, the electrode to which a high potential is applied is called the source electrode. The electrode that is connected to the drain electrode is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In the following, either the source electrode or the drain electrode is referred to as the first terminal, and the other is referred to as the second terminal. Then, the configuration of the DC-DC converter will be explained.

[0047] A DC-DC converter according to one embodiment of the present invention provides a large output voltage relative to an input voltage. It may be a step-up type in which a small output voltage is obtained for an input voltage, or a step-down type in which a small output voltage is obtained for an input voltage. Figure 2(A) shows the configuration of a step-down DC-DC converter.

[0048] In the DC-DC converter shown in FIG. 2A, the constant voltage generating unit 103 includes a diode 130 and a coil 140. The DC-DC converter shown in FIG. An input terminal IN1 to which an output voltage is applied, an input terminal IN2 to which a fixed voltage is applied, and an output terminal The input terminal has an output terminal OUT1 and an output terminal OUT2.

[0049] Transistor 102 provides a connection between input terminal IN1 and the cathode of diode 130. Specifically, the transistor 102 has a first terminal connected to the input terminal IN1. The second terminal of the coil is connected to the cathode of the diode 130. One of the pair of terminals is connected to the cathode of the diode 130, and the other is connected to the The input terminal IN2 is connected to the anode of the diode 130 and the output terminal OUT1. The capacitor 132 has a pair of electrodes, one of which is connected to the terminal OUT2. One end is connected to the output terminal OUT1, and the other end is connected to the output terminal OUT2.

[0050] In the DC-DC converter shown in FIG. 2A, when the transistor 102 is turned on, A potential difference occurs between the terminal IN1 and the output terminal OUT1, causing a current to flow through the coil 131. The coil 131 is magnetized by the current flowing therethrough, and the current flow is increased by self-induction. Therefore, the output terminal OUT1 generates an electromotive force in the opposite direction to the electromotive force given to the input terminal IN1. The voltage is obtained by stepping down the input voltage. Between a pair of electrodes of the A voltage corresponding to the difference between the voltage obtained by

[0051] Next, when the transistor 102 is turned off, a voltage Vout is applied between the input terminal IN1 and the output terminal OUT1. The current path that was formed is interrupted. In the coil 131, the change in the current is prevented. When the transistor 102 is turned on, an electromotive force is generated in the opposite direction. Therefore, the current flowing through the coil 131 is caused by the voltage generated by the electromotive force. That is, when the transistor 102 is off, the input terminal IN2 or Between the output terminal OUT2 and the output terminal OUT1, a coil 131 and a diode 130 are connected. A current path is formed. Therefore, the current provided between the pair of electrodes of the capacitor 132 is The voltage applied is maintained to a certain extent.

[0052] The voltage held in the capacitance element 132 is the output voltage output from the output terminal OUT1. In the above operation, the higher the ratio of the period during which the transistor 102 is on, the Thus, the voltage held in the capacitance element 132 becomes close to the difference between the fixed voltage and the input voltage. The voltage can be stepped down to obtain an output voltage closer in magnitude to the input voltage. The higher the ratio of the period during which the transistor 102 is off, the greater the amount of current stored in the capacitor 132. Therefore, the output voltage is closer to the fixed voltage. The voltage can be stepped down so that

[0053] Next, FIG. 2(B) shows the configuration of a boost type DCDC converter.

[0054] In the DC-DC converter shown in FIG. 2B, the constant voltage generating unit 103 includes a diode 130 and a coil 140. The DC-DC converter shown in FIG. An input terminal IN1 to which an output voltage is applied, an input terminal IN2 to which a fixed voltage is applied, and an output terminal The input terminal has an output terminal OUT1 and an output terminal OUT2.

[0055] The coil 131 has a pair of terminals, one of which is connected to the input terminal IN1 and the other of which is connected to a diode. The transistor 102 is connected to the anode of the coil 131 and the diode 130. 130 and the input terminal IN2 or the output terminal OUT2. Specifically, the first terminal of the transistor 102 is connected to the coil 131 and the diode 132. 30, and its second terminal is connected to the input terminal IN2 and the output terminal OUT2 The cathode of the diode 130 is connected to the output terminal OUT1. The capacitor 132 has a pair of electrodes, one of which is connected to the output terminal OUT1 and the other of which is connected to the output terminal OUT2. The input terminal OUT1 is connected to the output terminal OUT2.

[0056] In the DC-DC converter shown in FIG. 2B, when the transistor 102 is turned on, A current flows through the coil 131 due to a potential difference between the input terminal IN1 and the input terminal IN2. The coil 131 is magnetized by the current flowing therethrough. This generates an electromotive force in the opposite direction to the current flow, so the current gradually increases.

[0057] Then, when the transistor 102 is turned off, a voltage is formed between the input terminals IN1 and IN2. The current path that was previously formed is interrupted. In the coil 131, a current is generated in a direction that prevents the change in the current. That is, an electromotive force in the opposite direction to the electromotive force generated when the transistor 102 is on is generated. Therefore, a current flows between a pair of terminals of the coil 131 when the transistor 102 is on. At this time, a voltage is generated that corresponds to the current flowing through coil 131. The current flowing through 31 is maintained by the voltage developed across its terminals. When 102 is off, the coil 131 and diode 132 are connected between the input terminal IN1 and the output terminal OUT1. At this time, a current path is formed through the diode 130. The voltage generated across the terminals of coil 131 is added to the input voltage applied to input terminal IN1. The voltage obtained by the above calculation is given, and this voltage is output from the DC-DC converter as the output voltage. The voltage corresponding to the difference between the voltage of the output terminal OUT1 and the fixed voltage is the voltage of the capacitance element 132. It is held between the poles.

[0058] In the above operation, if the percentage of time that transistor 102 is on is high, then coil 131 Therefore, when transistor 102 is turned off, the current flowing through coil 1 The voltage generated between the terminals of 31 becomes larger, so the difference between the output voltage and the input voltage becomes larger. Conversely, the higher the ratio of the period during which the transistor 102 is off, the higher the Therefore, the current flowing through the coil 131 is low, and the transistor 102 is turned off. When the voltage across the terminals of coil 131 becomes small, the difference between the output voltage and the input voltage becomes The voltage can be boosted to be smaller.

[0059] In addition, in FIG. 1 and FIG. 2, the constant voltage generating unit 103 is a transistor that functions as a switching element. Although a configuration having only one star 102 is shown, the present invention is not limited to this configuration. In one aspect of the invention, a plurality of transistors may function as one switching element. In the case where a plurality of transistors functioning as a single switching element are provided, The transistors may be connected in parallel, in series, or in series. In either case, multiple transformers may be connected in parallel. In one or more of the transistors, the potential applied to the back gate electrode is controlled. The off-current or on-resistance of the switching element is adjusted according to the magnitude of the output power. This makes it possible to improve the power conversion efficiency.

[0060] In this specification, the state in which transistors are connected in series refers to, for example, a first Only one of the first terminal and the second terminal of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the terminals. A state in which transistors are connected in parallel is when the first terminal of a first transistor is connected to the a second terminal of the first transistor connected to a first terminal of the second transistor; It means that it is connected to a child.

[0061] The switching of the transistor 102 is controlled by pulse width modulation (PWM). dth Modulation control) or pulse frequency Control (PFM:Pulse Frequency Modulation control) l) may also be used.

[0062] FIG. 3A shows the gate voltage Vgs of the transistor 102 when the pulse width control is used. The time change is shown as an example. In FIG. 3(A), the gate voltage Vgs is a pulse voltage. 5 shows a case where the pulse width Ton is increased with the passage of time. In the case of pulse width control, the time interval Tp between the appearance of the pulses is kept constant. , the pulse width Ton is variable.

[0063] FIG. 3B shows the change in the gate voltage Vgs of the transistor 102 according to the change in the gate voltage Vgs shown in FIG. The time variation of the output power Wout obtained when switching is shown in FIG. 3(B). As shown in the figure, as the pulse width Ton increases, a larger output power Wout can be obtained. .

[0064] In one embodiment of the present invention, the amount of the power applied to the back gate electrode is determined according to the magnitude of the output power Wout. By controlling the potential at the back gate electrode, the back gate voltage Vbg between the back gate electrode and the source electrode can be As shown in FIG. 3(B), the output power Wout is changed over time. FIG. 3C shows an example of the change in the back gate voltage Vbgs over time. vinegar.

[0065] In FIG. 3C, the back gate voltage Vbgs is increased in stages. When the output power Wout is small, the back gate voltage Vbgs is low and the output power W When out is large, the back gate voltage Vbgs is high. When the output Wout is small, the back gate voltage Vbgs is lowered to reduce the By shifting the threshold voltage in the positive direction, the power due to the off-state current of the transistor 102 is It is possible to suppress losses to a minimum and prevent a decrease in power conversion efficiency. When out is large, the back gate voltage Vbgs is increased to lower the threshold voltage of the transistor 102. By shifting the value voltage in the negative direction, the power This allows the losses to be kept low as a priority, thereby preventing a decrease in power conversion efficiency.

[0066] In FIG. 3(C), the magnitude of the back gate voltage Vbgs is set to seven levels. The present invention is not limited to this configuration. The magnitude of the back gate voltage Vbgs can be set in stages. If this is possible, the above-mentioned effects can be obtained.

[0067] In addition, as shown in FIG. 3(B), when the output power Wout is changed over time, Another example of the change in gate voltage Vbgs over time is shown in FIG. 3(D). The gate voltage Vbgs is changed so as to increase linearly over time.

[0068] Alternatively, the back gate voltage Vbgs is set to the gate voltage Vgs of the transistor 102. In this case, the gate voltage Vgs pulse appears. The back gate voltage Vbgs pulse appears during the period when the back gate voltage Vbgs is applied. It is desirable to control the gate voltage Vbgs.

[0069] FIG. 4A shows the gate voltage of the transistor 102 when pulse frequency control is used. As an example, the change in the gate voltage Vgs over time is shown in FIG. 4(A). The time interval Tp between the timing of the voltage application and the appearance of the pulse is called the time In the case of pulse frequency control, the pulse width T On is kept constant, and the time interval Tp between the timing of pulse appearance is made variable.

[0070] FIG. 4B shows a state in which the transistor 102 is switched according to the gate voltage Vgs shown in FIG. The time change of the output power Wout obtained when switching is shown in FIG. In this way, the time interval Tp between the timings of pulse appearance is made smaller as time passes. Accordingly, a large output power Wout can be obtained.

[0071] In one embodiment of the present invention, pulse width control and pulse frequency control are combined to The output power may be adjusted by switching the resistor 102. For example, If the switching frequency of the transistor 102 is small, it is better to use pulse frequency control. This allows the number of transistors to be kept low, thereby reducing power loss due to switching of the transistor 102. Conversely, when the output power is large, it is better to use pulse width control. The switching frequency of the transistor 102 can be kept low, and the switching Therefore, the power loss due to switching can be reduced according to the output power. In addition, power conversion efficiency is improved by switching between pulse width control and pulse frequency control. It is possible.

[0072] (Embodiment 2) In this embodiment, the configuration and characteristics of the transistors included in the DC-DC converter of the present invention will be described. We will explain the characteristics of the transistor and the measurement of the power conversion efficiency of a DC-DC converter using the transistor. do.

[0073] FIG. 5A illustrates a top view of a transistor included in a DC-DC converter according to one embodiment of the present invention. FIG. 5(B) shows an example of the top view of FIG. 5(A) along the dashed line A1-A2. 4 shows a cross-sectional view of the same.

[0074] The transistor shown in FIG. 5A and FIG. 5B includes an insulating film 501 formed on a glass substrate 500. a back gate electrode 502 on the insulating film 501; and an insulating film 503 on the back gate electrode 502. 03 and a semiconductor film 503 overlapping the back gate electrode 502 with an insulating film 503 sandwiched therebetween. 4, a source electrode 505 and a drain electrode 506 on the semiconductor film 504, and , an insulating film 507 covering the source electrode 505 and the drain electrode 506; A gate electrode 508 overlapping the back gate electrode 502 and the semiconductor film 504 on the top and

[0075] In FIG. 5A, in order to clearly show the structure of the transistor, the insulating film 501 and the insulating film 503 and the insulating film 507 are omitted.

[0076] Specifically, the insulating film 501 contains silicon oxynitride and has a thickness of about 100 nm. The back gate electrode 502 contains tungsten and has a thickness of 150 nm. The insulating film 503 contains silicon oxynitride and has a thickness of 100 nm. 504 contains an In-Ga-Zn-O oxide semiconductor and its thickness is 50 nm. The source electrode 505 and the drain electrode 506 contain titanium and have a thickness of 150 mm. The insulating film 507 contains silicon oxide and has a thickness of 300 nm. The gate electrode 508 includes indium tin oxide with silicon oxide (ITSO). The film thickness is 150 nm.

[0077] As shown in FIG. 5B, the channel forming region is a region of the semiconductor film 504 where the gate electrode 508 and is sandwiched between the source electrode 505 and the drain electrode 506. FIG. 6 shows the channel formation of the transistor shown in FIG. 6 shows an enlarged view of the vicinity of the back gate electrode 502. There are.

[0078] As shown in FIG. 6, in the transistor described in this embodiment, the source electrode The contours of the drain electrode 505 and the drain electrode 506 are comb-shaped and parallel to the surface of the substrate 500. The source electrode 505 and the drain electrode 506 are The comb-like projections are arranged so that they interdigitate with each other and maintain a constant channel length L. The channel width W is the width of the channel in the direction perpendicular to the direction in which the carriers flow. This is the length of the channel forming region, and corresponds to the length of the dashed line W1-W2 in FIG.

[0079] In this embodiment, the channel length L is set to 3 μm, and the channel width W is set to 10 cm.

[0080] FIG. 7 shows the relationship between the gate voltage Vgs (V) of the transistor having the structure shown in FIG. The drain current Id (A) measured by the source electrode 505 and the drain The voltage Vds between the gate electrodes 506 is set to 5 V. In FIG. The back gate voltage Vbgs between the gate electrode and the source electrode is set to -2.5V, 0V, and 5V, respectively. , and 10V.

[0081] As shown in FIG. 7, the lower the back gate voltage Vbgs, the lower the transistor threshold voltage It can be seen that the back gate voltage Vb As gs increases, the transistor threshold voltage shifts to the negative side and the off-current increases. That is, the on-resistance decreases.

[0082] Next, the power of the DC-DC converter using the above transistor as a switching element was The conversion efficiency was measured. The power conversion circuit of the DC-DC converter used for the measurement is shown in Figure 2 ( The power conversion circuit 101 has the same configuration as the power conversion circuit 101 of the DC-DC converter shown in FIG.

[0083] The switching of the transistor 102 is performed by setting the gate voltage Vgs to 0V or 5V. The duty ratio was adjusted using pulse width control, and the timing at which the pulse appears was The timing frequency was set to 97 Hz. The duty ratio was set to the gate of the transistor 102. During the period when the gate voltage Vgs is 5 V, that is, during the period when the transistor 102 is on, The input voltage applied to the input terminal IN1 is 5V, and the output The output voltage given to the output terminal OUT1 was fixed at 10 V. The duty ratio was The relationship between the output power Wout (W) and the power conversion efficiency (%) was measured by changing the ratio from 40% to 68%. It was determined by measurement.

[0084] Figure 8 shows the relationship between the output power Wout (W) and the power conversion efficiency (%) obtained from the measurement. From Figure 8, when the output power Wout is small, the backgate voltage Vbgs is low. As the output power Wout increases, the power conversion efficiency increases. In either case, the power conversion efficiency increases, but when the back gate voltage Vbgs is low, In contrast, the increase in power conversion efficiency saturates and then declines. When the input voltage is high, such as 5 V or 10 V, the saturation of the increase in power conversion efficiency is not observed. In addition, the back gate voltage Vbgs is -2.5V, and the power dissipation is higher than when the back gate voltage Vbgs is low, such as 0V. conversion efficiency was obtained.

[0085] Therefore, in one aspect of the present invention, when the output power is large, the back gate voltage Vbgs When the output power is small, the back gate voltage Vbgs is lowered. As can be seen from the measurement results shown in Figure 8, this configuration allows for a DC A DC converter or a power supply circuit can be obtained.

[0086] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0087] (Embodiment 3) In this embodiment, an example of the configuration of an output voltage control circuit when pulse width control is used will be described. He explains.

[0088] FIG. 9 shows a schematic diagram of an example of the configuration of an output voltage control circuit. 04 includes a resistor 200, a resistor 201, an error amplifier 202, a phase compensation circuit 203, a comparator The converter 204 , a triangular wave oscillator 205 , and a buffer 206 .

[0089] Resistor 200 and resistor 201 are connected in series. One terminal of resistor 200 is connected to The output voltage is applied from the output terminal OUT1 of the converter. A fixed voltage such as ground is applied to one terminal of resistor 200. The node where the terminal of the resistor 201 is connected to the other terminal of the resistor 201 is the inverse terminal of the error amplifier 202. The output voltage given from the output terminal OUT1 is is divided by resistors 200 and 201, and the inverting input terminal ( -) is given.

[0090] A reference voltage Vref1 is applied to the non-inverting input terminal (+) of the error amplifier 202. In the difference amplifier 202, the voltage applied to the inverting input terminal (-) and the reference voltage Vref1 are The error is amplified and output from the output terminal of the error amplifier 202 .

[0091] The voltage output from the error amplifier 202 is provided to a phase compensation circuit 203. The circuit 203 controls the phase of the voltage output from the error amplifier 202. By controlling the voltage phase by the resistor 03, the error amplifier 202 or the comparator 204, etc. It can prevent the amplifier output voltage from oscillating and stabilize the operation of the DCDC converter. can.

[0092] The voltage output from the phase compensation circuit 203 is input to the non-inverting input terminal (+) of the comparator 204. The inverting input terminal (-) of the comparator 204 is supplied with a triangular wave oscillator 20 A triangular wave or sawtooth wave signal is output from the comparator 5. In the case of the inverter 204, the period is constant and the pulse width is given to the non-inverting input terminal (+). The output of the comparator 204 is a square wave signal that changes according to the magnitude of the voltage applied to the The input rectangular wave signal is output from the output voltage control circuit 104 via a buffer 206. , is input to the gate electrode of transistor 102.

[0093] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0094] (Embodiment 4) In this embodiment, an example of the configuration of a backgate control circuit will be described.

[0095] FIG. 10 is a schematic diagram showing an example of the configuration of a backgate control circuit. The output control circuit 105 is a current detection circuit that detects the magnitude of the current output from the output terminal OUT1. The circuit 210, the magnitude of the current detected by the current detection circuit 210, and the output terminal OUT1 and a power voltage conversion circuit 216 for determining the potential of the back gate electrode using the output voltage of the is doing.

[0096] Specifically, in FIG. 10, the current detection circuit 210 is a CT sensor (current transformer sensor). 211, a rectifier 212, and an integrating circuit 213. 211 is installed adjacent to a conductor such as a wiring that supplies current to the output terminal OUT1. When a current flows through the conductor, a magnetic flux is generated around the conductor, which acts as a transformer element. According to the theory, a current having a magnitude corresponding to the magnitude of the above current is generated in the CT sensor 211. For example, the current flowing through the output terminal OUT1 is I 0 , generated in the CT sensor 211 If the current flowing through the resistor is Ict, then I 0 :Ict=N:1(N>>1). That is, C The T sensor 211 detects the current I 0 It is possible to generate a minute current Ict proportional to

[0097] The rectifier 212 rectifies the current generated in the CT sensor 211 and then outputs it to the integrating circuit 21 The integrator circuit 213 is connected between the rectifier 212 and a node to which a fixed voltage is applied. The resistor 214 and the capacitance element 215 are connected in parallel. Therefore, the integrator circuit 213 functions as a filter. The current is converted into a voltage, averaged, and output. The voltage Vct output from the integrating circuit 213 is expressed as follows: The power is provided to a power voltage conversion circuit 216 .

[0098] In FIG. 10, the power voltage conversion circuit 216 includes a comparator 217, an inverter 220, and A power supply 221, a transistor 218 functioning as a switching element, and a transistor 2 19 is an example of a case having the above.

[0099] The non-inverting input terminal (+) of the comparator 217 receives the voltage V ct is applied, and the inverting input terminal (-) is connected to the output voltage of the output terminal OUT1 or A voltage that corresponds to the voltage of the output terminal OUT1 is provided as the reference voltage Vref2. The regulator 217 compares the input voltage Vct with the reference voltage Vref2 and determines whether the voltage Vct is greater than the reference voltage Vref2. When the reference voltage Vref2 is reached, a high-level voltage is output, and the voltage Vct is less than or equal to the reference voltage Vref2. In this case, a low-level voltage is output.

[0100] The voltage output from the comparator 217 is applied to the gate electrode of the transistor 219. Furthermore, the voltage output from the comparator 217 is inverted by an inverter 220. is inverted and applied to the gate electrode of transistor 218. When the voltage output from 217 is at a high level, transistor 218 is off; Since the power supply 221 supplies a potential Vbg1 to the power supply voltage conversion circuit 216, the power supply 221 supplies a potential Vbg2 to the power supply voltage conversion circuit 216. When the voltage output from the comparator 217 is at a low level, the transistor Since the transistor 218 is on and the transistor 219 is off, the ground potential Vbg2 , which is output from the power voltage conversion circuit 216. In this embodiment, the potential Vbg2 is The example shows a case where the potential Vbg2 is round, but the potential Vbg2 may be a potential other than ground. good.

[0101] The potential Vbg1 or the potential Vbg2 output from the power voltage conversion circuit 216 is a back gate. The output from the control circuit 105 is, for example, the buffer of the transistor 102 shown in FIG. That is, the back gate electrode is supplied with the DCDC control signal by the back gate control circuit 105. A potential is applied to the back gate electrode of the transistor 102 according to the output power of the inverter. can be changed.

[0102] In one embodiment of the present invention, a back gate is connected to the output terminal OUT1 in response to the current and the output voltage. By changing the potential applied to the output electrode, the transistor 102 is turned on when the output power is large. When the output power is small, the threshold voltage is adjusted so that the on-resistance of the transistor 102 is reduced. The threshold voltage can be adjusted so that the off-current of the DCDC converter is reduced. In addition, as an embodiment of the present invention, the power conversion efficiency of the DCD The output power of the C converter is monitored, and the potential of the back gate electrode is adjusted according to the output power. By controlling the output voltage of the DC / DC converter, the The potential of the gate electrode can be set to a more appropriate value, resulting in a higher power conversion efficiency. It can be improved.

[0103] In addition, by using the above DC-DC converter, the power conversion efficiency of the power supply circuit can be improved. Alternatively, by improving the power conversion efficiency of the DCDC converter, The power consumption of a semiconductor device using a converter can be reduced.

[0104] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0105] (Embodiment 5) In this embodiment, the DC-DC converter shown in FIG. 2 has a configuration of a power conversion circuit 101. A different type of DC-DC converter will now be described.

[0106] FIG. 11(A) shows the configuration of a flyback type DC-DC converter. The DC-DC converter includes a constant voltage generating unit 103, a diode 130, a capacitance element 132, and a transistor. In addition, the DC-DC converter shown in FIG. The input terminal IN1 is supplied with a fixed voltage, the input terminal IN2 is supplied with a fixed voltage, and the output terminal OUT1 is supplied with a fixed voltage. and an output terminal OUT2.

[0107] The transformer 133 has a primary coil and a secondary coil with a common core at its center. The transistor 102 is connected to the input terminal IN2 and the primary coil of the transformer 133. Specifically, the transistor 102 controls the connection between the first terminal and the second terminal of the The first terminal is connected to the input terminal IN2, and the second terminal is connected to the primary coil of the transformer 133. The other terminal of the primary coil of the transformer 133 is connected to the other terminal of the primary coil of the transformer 133. One terminal is connected to the input terminal IN1.

[0108] The secondary coil of the transformer 133 has a pair of terminals, one of which is connected to a diode 1. The other terminal is connected to the anode of the diode 30 and the other terminal is connected to the output terminal OUT2. The cathode of the node 130 is connected to the output terminal OUT1. One of the electrodes is connected to the output terminal OUT1, and the other is connected to the output terminal OUT2. It is being done.

[0109] FIG. 11(B) shows the configuration of a forward type DC-DC converter. In the DC-DC converter shown in FIG. 4, a coil 131, a capacitance element 132, and a transformer 135. The DC-DC converter has an input terminal IN1 to which the input voltage is applied and a fixed voltage The input terminal IN2 and the output terminals OUT1 and OUT2 are connected to each other.

[0110] The transformer 135 has a common core at its center, similar to the transformer 133 shown in FIG. However, the transformer 133 has a primary coil and a secondary coil. The winding positions of the primary coil and secondary coil are arranged on opposite sides, while the transformer 13 5, the primary coil and secondary coil are arranged so that the winding start position is on the same side.

[0111] The transistor 102 is connected to the input terminal IN2 and one of the terminals of the primary coil of the transformer 135. Specifically, the transistor 102 has a first terminal The second terminal of the input terminal IN2 is connected to the primary coil of the transformer 135. The other terminal of the primary coil of the transformer 135 is connected to the is connected to the input terminal IN1.

[0112] The secondary coil of the transformer 135 has a pair of terminals, one of which is connected to a diode 1. The other terminal is connected to the anode of the diode 30 and the other terminal is connected to the output terminal OUT2. The cathode of the diode 130 is connected to the cathode of the diode 134 and to one terminal of the coil 131. The anode of the diode 134 is connected to the output terminal OUT2. The other terminal of the capacitance element 132 is connected to the output terminal OUT1. One pole is connected to the output terminal OUT1 and the other pole is connected to the output terminal OUT2. There are.

[0113] In this embodiment, a flyback type DC-DC converter and a forward type DC The configuration of the DC converter has been described above. However, the DC-DC converter according to one embodiment of the present invention has the following features: The DC-DC converter according to one embodiment of the present invention is not limited to the above. If it is a switching method that can adjust the output voltage by the duty ratio, Good.

[0114] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0115] (Embodiment 6) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. Fig. 12 shows an example of the configuration of a lighting device.

[0116] The lighting device shown in FIG. 12 includes an AC power source 301, a switch 302, a rectifier circuit 303, and a D The CDC converter 100 and the light emitting element 304 are included. The C converter 100 constitutes a power supply circuit.

[0117] The DC-DC converter 100 shown in FIG. 12 is a step-down type DC-DC converter shown in FIG. The lighting device according to one embodiment of the present invention has the same configuration as the DCDC shown in FIG. The converter 100 does not necessarily have to be used, and other DCDs according to an embodiment of the present invention may be used. It is also possible to use a C converter.

[0118] Specifically, in the lighting device shown in FIG. 12, an AC voltage from an AC power source 301 is applied to a switch 30 2 to the rectifier circuit 303, where it is rectified. is input to the DC-DC converter 100, its magnitude is adjusted, and it is output. For detailed operation of the C converter 100, please refer to the description of FIG. 2(A) in the first embodiment. In this embodiment, the DC-DC converter 100 receives The received voltage is stepped down and output.

[0119] Then, the voltage output from the DC-DC converter 100 is applied to the light emitting element 304. As a result, the light emitting element 304 emits light. The light emitting element 304 may be a light emitting diode (LED), A variety of light sources can be used, including organic light emitting devices (OLEDs).

[0120] In addition, FIG. 12 shows the configuration of a lighting device that uses an AC power supply 301 as a power supply. However, the present invention is not limited to this configuration. However, when a DC power supply is used, the rectifier circuit 303 does not have to be provided.

[0121] FIG. 12 shows the configuration of a lighting device having an AC power supply 301 as a power source. However, the lighting device according to one aspect of the present invention does not necessarily need to include a power source as a component. .

[0122] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0123] (Embodiment 7) In this embodiment, a solar cell, which is one of the semiconductor devices according to one embodiment of the present invention, will be described. An example of the configuration of a solar cell is shown in FIG.

[0124] The solar cell shown in FIG. 13 includes a photodiode 350, a switch 351, and a capacitance element 35 2, a DC-DC converter 100, a pulse width modulation circuit 353, and an inverter 354, and a bandpass filter 355.

[0125] The DC-DC converter 100 shown in FIG. 13 is a step-up type DC-DC converter shown in FIG. The solar cell according to one embodiment of the present invention has the same configuration as the DCDC solar cell shown in FIG. The converter 100 does not necessarily have to be used, and other DCDs according to an embodiment of the present invention may be used. It is also possible to use a C converter.

[0126] Specifically, in the solar cell shown in FIG. 13, when light is irradiated onto the photodiode 350, a voltage The voltage is smoothed by the capacitance element 352 and then passed through the switch 351. The signal is input to the DC-DC converter 100. The pulsed current generated by the switching of the switch 351 passes through the photodiode 350. This can prevent the water from flowing into the

[0127] The voltage input to the DC-DC converter 100 is The magnitude of the signal is adjusted and then output. For this, the description of FIG. 2(B) in the first embodiment can be referred to. In this embodiment, the input voltage is boosted and output in the DC-DC converter 100. .

[0128] The voltage output from the output terminal OUT1 of the DC-DC converter 100 is a DC voltage. The inverter 354 converts the DC voltage output from the DC-DC converter 100 into an AC voltage. In FIG. 13, an inverter 354 includes four transistors 356 to 3 shows an example of a diode 359 and four diodes 360 to 363. There are.

[0129] Specifically, the transistor 356 has a first terminal connected to the output terminal of the DC-DC converter 100. OUT1, the second terminal of which is connected to the first terminal of transistor 357. The second terminal of the transistor 357 is connected to the output terminal OUT2 of the DC-DC converter 100. The first terminal of the transistor 358 is connected to the The second terminal of the output terminal OUT1 is connected to the first terminal of the transistor 359. The second terminal of the transistor 359 is connected to the output terminal of the DC-DC converter 100. OUT2. Diodes 360 to 363 are connected to the transistor 35 6 to 359 are connected in parallel to each other. The anodes of the diodes 360 to 363 are connected to the first terminals of the transistors 356 to 359. The second terminals of the transistors 356 to 359 are connected to the diodes 3 The cathodes of diodes 60 to 363 are connected to each other.

[0130] In addition, the voltage output from the DC-DC converter 100 is applied to the pulse width modulation circuit 353. The pulse width modulation circuit 353 operates when the above voltage is applied, and A signal that controls the switching of the transistor 356 to the transistor 359 is generated.

[0131] In response to the signal from the pulse width modulation circuit 353, the transistors 356 to 35 9 performs switching, the second transistor 356 of the inverter 354 A node where the terminal and the first terminal of the transistor 357 are connected, and A PWM waveform is generated from the node to which the second terminal and the first terminal of the transistor 359 are connected. An AC voltage having the above characteristics is output.

[0132] Then, the AC current output from the inverter 354 is filtered using a bandpass filter 355. By removing the high frequency components of the voltage, an AC voltage having a sine wave can be obtained.

[0133] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0134] (Embodiment 8) In this embodiment, a transistor using silicon and a transistor using an oxide semiconductor are A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described.

[0135] In one embodiment of the present invention, at least a DC-DC converter is provided for controlling the output power. An oxide semiconductor may be used for a transistor functioning as a switching element. The transistors other than the transistors functioning as the switching elements are made of germanium. Conventional CMOs using silicon, silicon germanium, or single crystal silicon carbide. For example, a silicon-based transistor can be formed using the S process. Single crystal semiconductor substrates such as silicon wafers, silicon thin films produced by the SOI method, and gas phase It can be formed by using a silicon thin film produced by a growth method.

[0136] First, as shown in FIG. 14(A), a semiconductor device is formed on an insulating surface of a substrate 700 by a known CMOS manufacturing method. An n-channel transistor 704 and a p-channel transistor 705 are formed by using the method. In this embodiment mode, a single crystal semiconductor film separated from a single crystal semiconductor substrate is used. For example, an n-channel transistor 704 and a p-channel transistor 705 are formed. He lists them as:

[0137] A specific example of a method for manufacturing a single crystal semiconductor film will be briefly described. An ion beam consisting of ions accelerated by an electric field is injected into a semiconductor substrate, and the ions are radiated from the surface of the semiconductor substrate. The crystal structure is disturbed and a brittle layer is formed locally in a region at a certain depth from the surface. The depth of the region where the embrittlement layer is formed depends on the acceleration energy of the ion beam and the The incident angle can be adjusted. Then, the semiconductor substrate and the insulating film 701 are formed. The insulating film 701 is sandwiched between the substrate 700 and the insulating film 701. After the semiconductor substrate and the substrate 700 are superimposed, a 1N / cm 2 More than 500N / cm 2 Less than 11N / cm, preferably 11N / cm 2 More than 20N / cm 2 below When pressure is applied to a certain part, the semiconductor substrate and the insulating film 701 are separated from that part. The bonding process begins, and eventually the bonding spreads over the entire surface. Then, heat treatment is performed. The microvoids in the embrittled layer expand and combine to form voids with a large volume. As a result, the single crystal semiconductor film, which is a part of the semiconductor substrate, is separated from the semiconductor substrate in the embrittlement layer. The temperature of the heat treatment is set to a temperature not exceeding the distortion point of the substrate 700. The single crystal semiconductor film is processed into a desired shape by etching or the like, thereby forming an island-shaped semiconductor film. 702 and an island-shaped semiconductor film 703 can be formed.

[0138] The n-channel transistor 704 is formed using an island-shaped semiconductor film 702 on an insulating film 701. A p-channel transistor 705 is formed on an island-shaped semiconductor film 7 on the insulating film 701. 03. An n-channel transistor 704 is formed using a gate electrode 70 6, and the p-channel transistor 705 has a gate electrode 707. The n-channel transistor 704 is formed by an island-shaped semiconductor film 702 and a gate electrode 706. The p-channel transistor 705 has an island-shaped semiconductor film 70 An insulating film 708 is provided between the first insulating film 703 and the gate electrode 707 .

[0139] There is no particular limitation on the substrate that can be used as the substrate 700, but at least the substrate that can be used in the subsequent processing should be The substrate 700 must have sufficient heat resistance to withstand heat treatment. Glass substrates, quartz substrates, ceramic substrates, etc. manufactured by the fusion method or float method For glass substrates, when the temperature of the subsequent heat treatment is high, the distortion point It is recommended to use a substrate with a temperature of 730°C or higher. A conductive substrate with an insulating film formed on the surface may be used. Generally, the heat resistance of the synthetic resin substrate tends to be lower than that of the above-mentioned substrates. Any material can be used as long as it can withstand the processing temperatures in the manufacturing process.

[0140] In this embodiment mode, a single crystal semiconductor film is used as the n-channel transistor 704. Although an example of forming a p-channel transistor 705 has been described, the present invention does not include this structure. For example, a polycrystalline or microcrystalline film formed on the insulating film 701 by vapor phase growth may be used. A crystalline semiconductor film may be used, or the semiconductor film may be crystalline by converting an amorphous semiconductor into a crystalline semiconductor film by a known technique. Known crystallization methods include laser crystallization using a laser beam, and a method using a catalyst element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method may be combined. In addition, when a substrate having excellent heat resistance such as quartz is used, , thermal crystallization method using electric furnace, lamp annealing crystallization method using infrared light, catalytic element The crystallization method used may be combined with high-temperature annealing at about 950°C. .

[0141] In FIG. 14A, a conductive film is formed over the insulating film 708, and then the conductive film is etched. The gate electrode 706 and the gate electrode 707 are processed into a desired shape by a machining process or the like. , and a wiring 711 is formed.

[0142] Next, as shown in FIG. 14(A), an n-channel transistor 704 and a p-channel transistor An insulating film 712 is formed so as to cover the transistor 705 and the wiring 711. In the embodiment, the case where a single-layer insulating film 712 is used is illustrated. It is not necessary to use a single insulating film, and two or more insulating films may be stacked to be used as the insulating film 712.

[0143] The insulating film 712 is made of a material that can withstand the temperature of a heat treatment in a later manufacturing process. The insulating film 712 may be made of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or aluminum nitride. It is preferable to use aluminum, aluminum oxide, etc.

[0144] The surface of the insulating film 712 may be planarized by a CMP method or the like.

[0145] Next, a gate electrode 713 is formed on the insulating film 712 as shown in FIG.

[0146] The material of the gate electrode 713 is molybdenum, titanium, chromium, tantalum, tungsten, nickel, etc. Conductive materials made of metals such as chromium, chromium, and scandium, and alloys made mainly of these metals. The conductive film or the nitride of these metals can be used in a single layer or a multilayer structure. If it can withstand the temperature of the heat treatment performed in the process, the metal material is aluminum. Aluminum or copper can be used. Aluminum or copper avoids the problems of heat resistance and corrosion. To avoid this, it is recommended to use it in combination with high melting point metal materials. High melting point metal materials include: Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. There can be.

[0147] For example, a gate electrode 713 having a two-layer laminate structure may be formed by depositing molybdenum on an aluminum film. A two-layer structure with a molybdenum film laminated on a copper film, a two-layer structure with a molybdenum film laminated on a copper film, A two-layer structure of a titanium nitride film or a tantalum nitride film, or a titanium nitride film and a molybdenum nitride film It is preferable to use a two-layer structure in which a butyl film and a butyl film are laminated. The electrode 713 is made of aluminum film, aluminum and silicon alloy film, aluminum and A titanium alloy film or an aluminum-neodymium alloy film is used as an intermediate layer, and a tungsten film, The structure is made by laminating a tungsten nitride film, a titanium nitride film, or a titanium film as upper and lower layers. is preferred.

[0148] In addition, the gate electrode 713 may be made of indium oxide, indium oxide tin oxide mixed ... Indium zinc oxide mixed oxide, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride Alternatively, a light-transmitting conductive oxide film such as zinc gallium oxide or zinc oxide can be used.

[0149] The thickness of the gate electrode 713 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm sputtering method using a tungsten target is used. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. The gate electrode 713 is formed by patterning. If the end of the electrode is tapered, the coverage of the gate insulating film to be laminated thereon is improved, which is preferable. The resist mask may be formed by an ink-jet method. When formed using the inkjet method, no photomask is used, reducing manufacturing costs. .

[0150] Next, as shown in FIG. 14(B), a gate insulating film 714 is formed on the gate electrode 713. The gate insulating film 714 is formed by oxidizing the gate insulating film 714 using a plasma CVD method, a sputtering method, or the like. Silicon film, silicon nitride film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride aluminum film, aluminum oxide nitride film, aluminum nitride oxide film, hafnium oxide film or The gate insulating film 714 can be formed of a single layer or a multilayer of tantalum oxide. It is desirable to have as few impurities as possible, such as moisture and hydrogen. When forming a silicon film, a silicon target or a quartz target is used. As the sputtering gas, oxygen or a mixed gas of oxygen and argon is used.

[0151] Oxides that have been made i-type or substantially i-type by removing impurities and reducing oxygen vacancies Semiconductors (highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, the interface between the highly purified oxide semiconductor and the gate insulating film 714 is important. Therefore, high quality gate insulating film (GI) that contacts the highly purified oxide semiconductor is required. .

[0152] For example, high-density plasma CVD using μ-waves (frequency 2.45 GHz) produces dense, high-insulation This is preferable because it allows the formation of a high-quality insulating film with high pressure. By closely contacting the gate insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0153] Of course, if a good insulating film can be formed as the gate insulating film 714, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film may be one whose film quality or interface characteristics with an oxide semiconductor are improved by heat treatment. In any case, the quality of the gate insulating film is of course good, and the gate insulating film Any material that can reduce the interface state density between the film and the oxide semiconductor and form a good interface is acceptable. .

[0154] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 714 having a structure in which an insulating film such as a silicon oxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films have high barrier properties and are oxide semiconductors. As an insulating film with high barrier properties, for example, a silicon nitride film or a silicon oxynitride film is used. , an aluminum nitride film, or an aluminum nitride oxide film. By using a thin insulating film, impurities in the atmosphere such as moisture or hydrogen, or impurities contained in the substrate Impurities such as alkali metals and heavy metals are contained in the oxide semiconductor film, the gate insulating film 714, Alternatively, it is possible to prevent the oxide semiconductor film from penetrating into the interface between the oxide semiconductor film and another insulating film and its vicinity. In addition, a silicon oxide film or a silicon oxynitride film having a low nitrogen content that is in contact with the oxide semiconductor film may be used. By forming an insulating film such as a thin film, the insulating film with high barrier properties is in direct contact with the oxide semiconductor film. This can prevent the following:

[0155] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0) is formed, and a second gate insulating film is formed on the first gate insulating film. The insulating film is a silicon oxide film (SiO x (x>0) The gate insulating film 714 may be formed by layering the gate insulating film 714 with a thickness of 100 nm. can be set appropriately depending on the characteristics required for the transistor, and is within the range of 350 nm to 400 nm. It can be about m.

[0156] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 71 having a structure in which a silicon oxide film having a thickness of 100 nm formed by the above method is laminated. Form 4.

[0157] Note that the gate insulating film 714 is in contact with an oxide semiconductor that will be formed later. Since the presence of hydrogen, hydroxyl groups, and It is preferable that the gate insulating film 714 does not contain hydrogen, hydroxyl groups, and moisture. In order to prevent this from being included, the pre-heating of the sputtering equipment is required as a pretreatment for film formation. The substrate 700 on which the gate electrode 713 is formed is preheated in a chamber, and the moisture adsorbed on the substrate 700 is removed. It is preferable to desorb and exhaust impurities such as hydrogen. The temperature is from 00°C to 400°C, preferably from 150°C to 300°C. The exhaust means provided in the chamber is preferably a cryopump. Note that this preheating process is omitted. It is also possible.

[0158] Next, a film having a thickness of 2 nm to 200 nm, preferably 3 nm, is deposited on the gate insulating film 714. The thickness of the oxide semiconductor film is preferably 3 nm to 20 nm. The oxide semiconductor film is formed by a sputtering method using an oxide semiconductor as a target. The oxide semiconductor film is formed in a rare gas (e.g., argon) atmosphere, an oxygen atmosphere, or Alternatively, it is formed by sputtering in a mixed atmosphere of rare gas (e.g. argon) and oxygen. It is possible.

[0159] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate a mask, and the dust adhering to the surface of the gate insulating film 714 is removed. In reverse sputtering, the target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power source under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an atmosphere in which oxygen, nitrous oxide, etc. are added to an argon atmosphere. Alternatively, the treatment may be carried out in an atmosphere in which chlorine, carbon tetrafluoride, etc. have been added to the argon atmosphere.

[0160] As described above, the oxide semiconductor film is made of a quaternary metal oxide, In-Sn-Ga-Zn -O-based oxide semiconductors, and In-Ga-Zn-O-based oxide semiconductors, which are ternary metal oxides. In-Sn-Zn-O oxide semiconductor, In-Al-Zn-O oxide semiconductor, Sn-G a-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, Sn-Al-Zn -O-based oxide semiconductors, In-Hf-Zn-O-based oxide semiconductors, In-La-Zn-O-based Oxide semiconductor, In-Ce-Zn-O oxide semiconductor, In-Pr-Zn-O oxide semiconductor Conductor, In-Nd-Zn-O oxide semiconductor, In-Pm-Zn-O oxide semiconductor, I n-Sm-Zn-O oxide semiconductor, In-Eu-Zn-O oxide semiconductor, In-Gd -Zn-O oxide semiconductor, In-Tb-Zn-O oxide semiconductor, In-Dy-Zn- O-based oxide semiconductor, In-Ho-Zn-O-based oxide semiconductor, In-Er-Zn-O-based oxide Semiconductors, In-Tm-Zn-O oxide semiconductors, In-Yb-Zn-O oxide semiconductors In-Lu-Zn-O oxide semiconductors and In-Zn-O oxides, which are binary metal oxides, are oxide semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-M ZnO-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors , In-Ga-O-based oxide semiconductors, In-O-based oxide semiconductors, Sn-O-based oxide semiconductors , Zn-O based oxide semiconductors, etc. can be used.

[0161] In this embodiment, a tantalum containing In (indium), Ga (gallium), and Zn (zinc) is used. In-Ga-Zn-O oxide with a thickness of 30 nm obtained by sputtering using a ZnO target A thin film of an oxide semiconductor is used as the target. 2 O 3 :Ga 2 O 3 A target having a composition ratio of ZnO=1:1:1 [molar ratio] Also, In 2 O 3 :Ga 2 O 3 The composition ratio of ZnO is 1:1:2 [molar ratio] Targets with, or In 2 O 3 :Ga 2 O 3 :ZnO=1:1:4[mol ratio] In addition, targets containing In, Ga, and Zn can be used. The filling rate of the filler is 90% or more and 100% or less, preferably 95% or more and less than 100%. By using a target with a high conversion efficiency, the formed oxide semiconductor film becomes a dense film.

[0162] When using an In-Zn-O-based material as the oxide semiconductor, the composition of the target to be used is The composition ratio, in atomic ratio, is In:Zn=50:1 to 1:2 (converted to molar ratio, In 2 O 3 In:ZnO=25:1 to 1:4, preferably In:Zn=20:1 to 1:1 (molar ratio) This translates to In 2 O 3 In:ZnO=10:1 to 1:2), more preferably In:Zn=1 .5:1 to 15:1 (converted to molar ratio: In 2 O 3 :ZnO=3:4~15:2) For example, the target used for forming an In-Zn-O oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn is within the above range. By enclosing the electrons in the electron-doped region, it is possible to improve the mobility.

[0163] In this embodiment, the substrate is held in a processing chamber that is maintained in a reduced pressure state, and residual moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the above target is used. An oxide semiconductor film is formed over a substrate 700. During the film formation, the substrate temperature is set to 100° C. or higher and 600° C. The temperature may be set to 200° C. or higher and 400° C. or lower. This allows the impurity concentration in the formed oxide semiconductor film to be reduced. In addition, damage caused by sputtering is reduced. To remove residual moisture in the processing chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, It is preferable to use a titanium sublimation pump. A cryopump with a cold trap may be used. When the chamber is evacuated, hydrogen atoms, water (H 2 Compounds containing hydrogen atoms such as 0 (preferably The oxide semiconductor film formed in the film formation chamber is The concentration of impurities contained in the body membrane can be reduced.

[0164] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, and the film can be This is preferable since the thickness distribution is also uniform.

[0165] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, the gate insulating film 714 is formed in the pre-heating chamber of the sputtering device. The substrate 700 is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 700. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150° C. or more and 300° C. or less. The pre-heating process may be omitted. The heating is performed before the insulating film 723 is formed on the substrate on which the electrodes 716 to 718 are formed. Plate 700 may be similarly treated.

[0166] Next, as shown in FIG. 14B, the oxide semiconductor film is etched into a desired shape. Then, at a position on the gate insulating film 714 where the gate electrode 713 overlaps, An island-shaped oxide semiconductor film 715 is formed.

[0167] A resist mask for forming the island-shaped oxide semiconductor film 715 is formed by an inkjet method. If the resist mask is formed by the inkjet method, no photomask is required. This reduces manufacturing costs.

[0168] Note that the etching for forming the island-shaped oxide semiconductor film 715 is performed by dry etching. Dry etching may be performed by wet etching or by both. The gas used is a gas containing chlorine (chlorine-based gas, e.g., chlorine (Cl 2 ), boron trichloride ( BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ) is preferred. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CHF 3 ), Hydrogen bromide (HB r), oxygen (O 2 ), and rare gases such as helium (He) and argon (Ar) are added to these gases. A gas containing , etc. can be used.

[0169] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0170] The etching solution used for wet etching was ITO-07N (Kanto Chemical Co., Ltd.). In addition, the etching solution after wet etching may be mixed with the etched material. The removed material is then removed by cleaning. The waste etching solution containing the removed material is purified and The material contained in the oxide semiconductor film may be reused. By recovering and reusing materials such as indium, we aim to make effective use of resources and reduce costs. It is possible.

[0171] Note that reverse sputtering is performed before a conductive film is formed in the next step, and the island-shaped oxide semiconductor film 715 and It is also preferable to remove resist residues adhering to the surface of the gate insulating film 714. .

[0172] Note that moisture or hydrogen as an impurity is contained in the oxide semiconductor film formed by sputtering or the like. Moisture or hydrogen can easily form donor levels, so oxidation In one embodiment of the present invention, water in an oxide semiconductor film is an impurity. In order to reduce impurities such as atoms or hydrogen, the oxide semiconductor film 715 is In an atmosphere of nitrogen, ultra-dry air, or rare gas (argon, helium, etc.), The semiconductor film 715 is subjected to heat treatment. The above gas has a water content of 20 ppm or less, preferably It is desirable that the concentration is 1 ppm or less, and preferably 10 ppb or less.

[0173] By performing heat treatment on the oxide semiconductor film 715, moisture or water in the oxide semiconductor film 715 is removed. Specifically, the temperature is 300° C. or higher and 700° C. or lower, preferably 30 Heat treatment may be performed at 0°C or higher and 500°C or lower. For example, 500°C for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be achieved in a short time. This allows processing at temperatures above the distortion point of the glass substrate.

[0174] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0175] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0176] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain any hydrogen or other elements. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0177] Through the above steps, the hydrogen concentration in the oxide semiconductor film 715 can be reduced and the oxide semiconductor film 715 can be highly purified. This makes it possible to stabilize the oxide semiconductor film. The following heat treatment produces an oxide semiconductor film with extremely low carrier density and a wide band gap. Therefore, a transistor can be manufactured using a large-area substrate. This allows for improved mass production. By using a semiconductor film, it is possible to fabricate transistors with high voltage resistance and high on-off ratio. This can be done.

[0178] In the case where the oxide semiconductor film is heated, depending on the material of the oxide semiconductor film and heating conditions, Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the single crystal has a c-axis oriented substantially vertically. It is preferable that the crystals are polycrystalline with the c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. In addition to the c-axis orientation, the ab planes of the crystals of the polycrystalline body coincide with each other. It is preferable that the a-axis or the b-axis of the oxide semiconductor film coincide with each other. If the surface is uneven, the plate crystals will become polycrystalline. Therefore, the surface of the substrate should be as flat as possible. It is desirable for the information to be clear and unambiguous.

[0179] Next, the insulating film 708, the insulating film 712, and the gate insulating film 714 are partially etched. The island-shaped semiconductor film 702, the island-shaped semiconductor film 703, and the contact hole reaching the wiring 711 are Form a loop.

[0180] Then, a conductive film is formed by a sputtering method or a vacuum evaporation method so as to cover the oxide semiconductor film 715. Then, the conductive film is patterned by etching or the like to obtain a structure as shown in FIG. As shown in FIG. 1, electrodes 716 to 718 functioning as source electrodes, drain electrodes, or wiring are Form.

[0181] The electrode 716 and the electrode 717 are in contact with the island-shaped semiconductor film 702. The electrode 718 is in contact with the island-shaped semiconductor film 703. The electrode 719 is connected to the wiring 711 and the oxide film 702. The electrode 720 is in contact with the oxide semiconductor film 715.

[0182] The conductive film that becomes the electrodes 716 to 718 may be made of aluminum, chromium, copper, or titanium. An element selected from the group consisting of tungsten, titanium, molybdenum, and tungsten, or the above-mentioned elements The above-mentioned elements may be combined to form an alloy film. Chromium, tantalum, titanium, molybdenum, thion, etc. are placed under or on top of a metal film such as aluminum or copper. Alternatively, a film of a high melting point metal such as tin or the like may be laminated. Copper is used in combination with high melting point metal materials to avoid problems of heat resistance and corrosion. High melting point metal materials include molybdenum, titanium, chromium, tantalum, and tungsten. Examples of materials that can be used include lanthanum, neodymium, scandium, yttrium, etc.

[0183] The conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of an aluminum film containing titanium, a two-layer structure of a titanium film laminated on an aluminum film, and a Ti A Ti film is then laminated on top of the Ti film, an aluminum film is then laminated on top of the Ti film, and a Ti film is then formed on top of that. Three-layer structure, etc.

[0184] The conductive films that become the electrodes 716 to 718 may be made of a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium oxide. Indium-tin oxide mixed oxide, indium-zinc oxide mixed oxide or the above metal oxide materials One containing silicon or silicon oxide can be used.

[0185] When a heat treatment is performed after the conductive film is formed, the conductive film is required to have heat resistance to withstand the heat treatment. It is preferable that

[0186] Note that the conductive film is etched so as not to remove the oxide semiconductor film 715 as much as possible. The materials and etching conditions are adjusted appropriately. Depending on the etching conditions, island-shaped The exposed portion of the oxide semiconductor film 715 is partially etched to form a groove (a depression). It may also be achieved.

[0187] In this embodiment mode, a titanium film is used as the conductive film. The conductive film can be selectively wet-etched using a solution containing However, the oxide semiconductor film 715 is also partly etched. Ammonia was mixed with hydrogen peroxide, 28% ammonia water, and water in a volume ratio of 5:2:2. Use monium peroxide or chlorine (Cl 2 ), boron trichloride (BCl 3 ) and other gases The conductive film may be dry-etched using a fluorine-containing ...

[0188] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives multiple levels of intensity to the light is used. The resist mask formed using the multi-tone mask may be a multi-layer mask. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can be used to register at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, making it possible to simplify the process.

[0189] Next, N 2 O, N 2 Alternatively, plasma treatment is performed using a gas such as Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor film. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0190] After the plasma treatment, the electrodes 716 to 718 are An insulating film 723 is formed to cover the oxide semiconductor film 715. It is desirable to minimize the amount of impurities such as hydrogen, oxygen, etc. The insulating film 723 may contain hydrogen, or may be formed of a plurality of insulating films. When the hydrogen is introduced into the oxide semiconductor film, the hydrogen penetrates the oxide semiconductor film, or the hydrogen extracts oxygen from the oxide semiconductor film. When the oxide semiconductor film is turned on, the back channel portion of the oxide semiconductor film becomes low-resistance (n-type), and the parasitic channel Therefore, the insulating film 723 should be a film that contains as little hydrogen as possible. It is important not to use hydrogen in the film formation method. For example, a silicon nitride film or a silicon nitride film is used as an insulating film having a high barrier property. A silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used. When using multiple laminated insulating films, a silicon oxide film with a low nitrogen content and an oxide film with a low nitrogen content are used. The insulating film such as a silicon nitride film is preferably used as the oxide semiconductor film 715 rather than the insulating film having a high barrier property. Then, the electrodes 716 to 717 are formed on the side closer to the substrate 711 with an insulating film having a low nitrogen content sandwiched therebetween. An insulating film with high barrier properties is formed so as to overlap with the electrode 718 and the oxide semiconductor film 715. By using an insulating film with a high barrier property, Moisture, hydrogen, or the like is present in the oxide semiconductor film 715 or in the vicinity of the interface between the oxide semiconductor film 715 and another insulating film. In addition, the oxide semiconductor film 715 can be prevented from being in contact with the insulating film 716. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio on the Therefore, the insulating film using a highly conductive material can be prevented from being in direct contact with the oxide semiconductor film 715. .

[0191] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 723 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. in this embodiment. The temperature is 100°C.

[0192] Note that heat treatment may be performed after the insulating film 723 is formed. In an atmosphere of dry air or rare gas (argon, helium, etc.), preferably for 20 The temperature is between 0°C and 400°C, for example between 250°C and 350°C. The content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less. In this embodiment, for example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. Alternatively, before forming the electrodes 716 to 720, a process for reducing moisture or hydrogen is performed. Similar to the heat treatment performed on the oxide semiconductor film for the above-mentioned purpose, RTA treatment was performed at high temperature for a short time. After the insulating film 723 containing oxygen is provided, heat treatment is performed. In addition, the oxide semiconductor film 715 is formed with oxygen deficiency by the heat treatment performed on the oxide semiconductor film. Even if a loss occurs, oxygen is supplied from the insulating film 723 to the oxide semiconductor film 715. Then, oxygen is supplied to the oxide semiconductor film 715, whereby In this way, it is possible to reduce oxygen vacancies that act as donors and to satisfy the stoichiometric composition ratio. As a result, the oxide semiconductor film 715 can be made closer to an i-type semiconductor, and a transistor due to oxygen vacancies can be formed. This heat treatment reduces the variation in the electrical properties of the capacitors and improves their electrical properties. The timing of the treatment is not particularly limited as long as it is after the formation of the insulating film 723, and may be after other processes, e.g. For example, it can be used for the heat treatment when forming the resin film or for the heat treatment to reduce the resistance of the transparent conductive film. Thus, the oxide semiconductor film 715 can be made closer to i-type without increasing the number of steps.

[0193] In addition, by performing heat treatment on the oxide semiconductor film 715 in an oxygen atmosphere, the oxide semiconductor In this case, oxygen vacancies serving as donors in the oxide semiconductor film 715 may be reduced by adding oxygen. The temperature of the heat treatment is, for example, 100° C. or higher and lower than 350° C., preferably 150° C. or higher and lower than 250° C. The oxygen gas used in the heat treatment in the oxygen atmosphere contains water, hydrogen, etc. It is preferable that the purity of the oxygen gas introduced into the heat treatment device is not more than 6N ( 99.9999%) or more, preferably 7N (99.99999%) or more (i.e., oxygen It is preferable to keep the impurity concentration at 1 ppm or less, and preferably at 0.1 ppm or less.

[0194] Alternatively, the oxide semiconductor film 715 may be formed by ion implantation, ion doping, or the like. By adding oxygen, the donor oxygen vacancies can be reduced. For example, 2.45G Oxygen plasma generated by microwaves at 100 Hz may be added to the oxide semiconductor film 715 .

[0195] Next, as shown in FIG. 14D, a conductive film is formed over the insulating film 723, and then the conductive film is By patterning, a back gate electrode 725 is formed in a position overlapping with the oxide semiconductor film 715. Then, after forming the back gate electrode 725, An insulating film 726 is formed to cover the gate electrode 725. Alternatively, the electrodes 716 to 718 can be formed using the same material and structure.

[0196] The thickness of the back gate electrode 725 is 10 nm to 400 nm, preferably 100 nm to 20 For example, a titanium film, an aluminum film, and a titanium film are laminated. After forming the conductive film, a resist mask is formed by photolithography or the like, and etching is performed. The conductive film is then processed (patterned) into a desired shape by removing unnecessary portions through etching. In this way, the back gate electrode 725 may be formed.

[0197] Through the above steps, a transistor 724 is formed.

[0198] The transistor 724 includes a gate electrode 713 and a gate insulating film 714 on the gate electrode 713. The oxide semiconductor film 71 overlaps with the gate electrode 713 on the gate insulating film 714. 5, a pair of electrodes 719 or 720 formed on the oxide semiconductor film 715, and An insulating film 723 is formed on the oxide semiconductor film 715. The transistor 72 further includes a back gate electrode 725 overlapping the film 715. The transistor 4 may include an insulating film 726 as a component thereof. A portion of the oxide semiconductor film 715 is etched between the electrode 719 and the electrode 720. A channel etch structure is shown in FIG.

[0199] Note that the transistor 724 has a single gate structure. Optionally, a plurality of electrically connected gate electrodes 713 may be provided to form a channel. A transistor having a multi-gate structure having a plurality of regions can also be formed.

[0200] This embodiment mode can be implemented in combination with the above embodiment modes.

[0201] (Embodiment 9) In this embodiment, a transistor using an oxide semiconductor film, which has a structure different from that of Embodiment 8, is described. The following describes the transistor.

[0202] In the semiconductor device shown in FIG. 15A, similarly to the eighth embodiment, an n-channel transistor 15A, the transistor 704 is a p-channel transistor 705. An oxide semiconductor is formed on the n-channel transistor 704 and the p-channel transistor 705. A bottom-gate type transistor 724 having a channel protection structure using a conductor film is formed. There are.

[0203] The transistor 724 includes a gate electrode 730 formed on an insulating film 712 and a gate electrode 7 30, and a gate insulating film 731 overlapping with the gate electrode 730 on the gate insulating film 731. The oxide semiconductor film 732 is formed on the gate electrode 730. The oxide semiconductor film 732 is formed on the gate electrode 730. A channel protective film 733 formed over the semiconductor film 732 and a The electrodes 734 and 735 are formed on the channel protective film 733. the insulating film 736 formed in a position overlapping with the oxide semiconductor film 732 and a back gate electrode 737 formed thereon. The insulating film 738 formed on the back gate electrode 737 may be included in the components.

[0204] By providing the channel protective film 733, the channel formation region of the oxide semiconductor film 732 In the later process, the plasma and etching agent used in the etching process are used to remove the This prevents damage such as thinning of the film, thus improving the reliability of the transistor. This can be done.

[0205] The channel protection film 733 is made of an inorganic material containing oxygen (silicon oxide, silicon nitride oxide, silicon oxynitride, etc.). Aluminum oxide, aluminum oxynitride, etc.) can be used. The protective film 733 is formed by vapor deposition such as plasma CVD or thermal CVD, or sputtering. The channel protection film 733 can be formed by etching after the film formation. Here, a silicon oxide film is formed by sputtering, and then photolithography is used to process the silicon oxide film. A channel protective film 733 is formed by etching using the mask.

[0206] By using an inorganic material containing oxygen for the channel protective film 733, moisture or hydrogen is reduced. Even if oxygen vacancies are generated in the oxide semiconductor film 732 by the heat treatment for the oxidation, Oxygen is supplied to the nitride semiconductor film 732 from the channel protective film 733 to fill the oxygen vacancies that serve as donors. Therefore, it is possible to reduce the channel formation region to satisfy the stoichiometric composition. The region can be made closer to the i-type, and the variation in the electrical characteristics of the transistor 724 due to oxygen vacancies can be reduced. This reduces adhesion and improves electrical properties.

[0207] The semiconductor device shown in FIG. 15B is an n-channel semiconductor device using crystalline silicon, similar to the eighth embodiment. A first channel transistor 704 and a second channel transistor 705. In FIG. 15B, an n-channel transistor 704 and a p-channel transistor 7 A bottom-contact transistor 724 using an oxide semiconductor film is formed on the semiconductor substrate 710. is.

[0208] The transistor 724 includes a gate electrode 741 formed on an insulating film 712 and a gate electrode 7 A gate insulating film 742 on the gate insulating film 742, an electrode 743 and an electrode 744 on the gate insulating film 742, an oxide semiconductor film 745 overlapping the gate electrode 741 with a gate insulating film 742 interposed therebetween; The insulating film 746 formed over the oxide semiconductor film 745 and the insulating film 746 overlap with the oxide semiconductor film 745. A back gate electrode 747 is formed on the insulating film 746 at the position. The transistor 724 includes an insulating film 748 on a back gate electrode 747 as a component thereof. You can also do so.

[0209] This embodiment mode can be implemented in combination with the above embodiment modes.

[0210] (Embodiment 10) In this embodiment, an example of calculating the off-state current of a transistor will be described.

[0211] First, the configuration of the characteristic evaluation circuit used to calculate the off-state current will be described with reference to FIG. In this embodiment, the characteristic evaluation circuit includes a plurality of measurement systems 801 connected in parallel to each other. Specifically, in FIG. 16, eight measurement systems 801 are connected in parallel to form a characteristic evaluation circuit. The following examples illustrate the measurement paths (only two measurement systems are shown in FIG. 16).

[0212] The measurement system 801 includes a transistor 811, a transistor 812, a capacitance element 813, and a It includes a transistor 814 and a transistor 815 .

[0213] The transistor 811 is a charge injection transistor. , its first terminal is connected to a node to which potential V1 is applied, and its second terminal is , is connected to the first terminal of the transistor 812. The gate electrode of the transistor 811 is , is connected to a node to which a potential Vext_a is applied.

[0214] The transistor 812 is a transistor for evaluating leakage current. The leakage current includes the off-state current of the transistor. 2 has a first terminal connected to the second terminal of the transistor 811, and a second terminal The gate voltage of the transistor 812 is connected to a node to which a potential V2 is applied. The pole is connected to a node to which a potential Vext_b is applied.

[0215] The first electrode of the capacitor 813 is connected to the second terminal of the transistor 811 and the second terminal of the transistor 812. A second electrode of the capacitor 813 is connected to a first terminal of the capacitor 813. A potential V2 is applied to the second electrode of the capacitor 813. It is connected to a node that is

[0216] The transistor 814 has a first terminal connected to a node to which a potential V3 is applied. The second terminal of the transistor 815 is connected to the first terminal of the transistor 815. The gate electrode of 814 is connected to the second terminal of the transistor 811 and the first terminal of the transistor 812. The gate of the transistor 814 is connected to the first electrode of the capacitor element 813. The point where the output electrode is connected is referred to as node A.

[0217] The first terminal of the transistor 815 is connected to the second terminal of the transistor 814. The second terminal of the transistor is connected to a node to which a potential V4 is applied. The gate electrode of 815 is connected to a node to which a potential Vext_c is applied.

[0218] The measurement system 801 includes a second terminal of the transistor 814 and a first terminal of the transistor 815. The potential of the node to which the terminal is connected is output as the potential Vout of the output signal.

[0219] In this embodiment, the transistor 811 includes an oxide semiconductor in an active layer. Furthermore, the size of the channel formation region included in the active layer is the channel length L = 10 μm, A transistor with a panel width W=10 μm was used.

[0220] The channel formation region is a region in the semiconductor film between the source electrode and the drain electrode. , which corresponds to a region overlapping with the gate electrode with the gate insulating film sandwiched therebetween.

[0221] The transistors 814 and 815 each include an oxide semiconductor in an active layer. Furthermore, the size of the channel formation region included in the active layer is the channel length L = 3 μm, A transistor with a panel width W=100 μm was used.

[0222] The transistor 812 includes an oxide semiconductor in an active layer and has a source The source electrode and the drain electrode are in contact with each other, and the gate electrode and the source electrode and the drain electrode are overlapped with each other. A bottom-gate transistor with a 1 μm-wide offset region without a burlap region. By providing an offset region, the parasitic capacitance can be reduced. Further, as the transistor 812, a channel formation region included in an active layer is Transistors having different sizes, as shown in Conditions 1 to 6 in Table 1, were used.

[0223] [Table 1]

[0224] In addition, when the charge injection transistor 811 is not provided in the measurement system 801, the capacitance element 81 When injecting charge into the transistor 812, the transistor 812 for evaluating leakage current must be turned on once. In this case, the leakage current evaluation transistor 812 is in a steady state of being turned on and off. If the device requires time to measure, it will take time. The transistor 811 for use and the transistor 812 for leak current evaluation are separately measured in a measuring system 80. 1, the leakage current evaluation transistor 812 is always turned on during charge injection. Therefore, the time required for measurement can be shortened.

[0225] In addition, the charge injection transistor 811 and the leakage current evaluation transistor 812 are measured. By providing both in system 801, it is possible to appropriately size each transistor. In addition, the channel width W of the leakage current evaluation transistor 812 can be set to be equal to the channel width W of the charge injection transistor 812. By making the channel width W of the transistor 811 larger, the leakage current evaluation transistor The leakage current components in the characteristic evaluation circuit other than the leakage current of the stator 812 are relatively small. As a result, the leakage current of the leakage current evaluation transistor 812 can be measured with high accuracy. At the same time, when the charge is injected, the leakage current evaluation transistor 81 Since it is not necessary to turn on 2 once, some of the charge in the channel formation region flows into node A. There is no effect of potential fluctuations at node A due to the

[0226] On the other hand, the channel width W of the charge injection transistor 811 is set to By making the channel width W of the charge injection transistor 811 smaller than that of the charge injection transistor 812, In addition, the peak current in the channel formation region can be reduced. The effect of the potential fluctuation at node A caused by a part of the charge flowing into node A is also small.

[0227] In addition, as shown in FIG. 16, by connecting multiple measurement systems 801 in parallel, This allows for more accurate calculation of the leakage current of the characteristic evaluation circuit.

[0228] Next, a specific method for calculating the off-state current of a transistor using the characteristic evaluation circuit shown in FIG. This article explains:

[0229] First, the method for measuring the leakage current of the characteristic evaluation circuit shown in FIG. 16 will be described with reference to FIG. 17. FIG. 17 is a diagram for explaining a leakage current measuring method using the characteristic evaluation circuit shown in FIG. 2 is a timing chart.

[0230] The leakage current measurement method using the characteristic evaluation circuit shown in FIG. The operation during each period is explained below. During both the pulse width and the hold period, the potentials V2 and V4 are set to 0 V, the potential V3 is set to 5 V, and the potential Vext_c was set to 0.5V.

[0231] First, in the writing period, the potential Vext_b is set to 0 so that the transistor 812 is turned off. After setting the potential V1 to the write potential Vw, The potential Vext_a is set to a potential VH( With the above configuration, charge is stored in node A, and the potential of node A becomes Next, the potential Vext_a is set to a value equivalent to the write potential Vw by the transistor 811. Then, set the potential V1 to the potential VSS (0V). do.

[0232] Next, during the hold period, the charge stored in node A changes. The amount of change in potential is measured. From the amount of change in potential, the first terminal and the second terminal of the transistor 812 are determined. The current flowing between the terminals of the node A can be calculated. and the amount of change in the potential of node A can be measured.

[0233] Accumulating charge at node A and measuring the change in potential at node A (also called the accumulation and measurement operation) First, the first accumulation and measurement operation was repeated 15 times. In the measurement operation, a potential of 5 V is input as the write potential Vw during the write period, and A one hour hold was performed between the two. The second accumulation and measurement operation was then repeated twice. In the accumulation and measurement operation, the write potential Vw is set to 3.5 V during the write period and The retention time was 50 hours. Next, the third accumulation and measurement operation was performed once. In the measurement operation, the write potential Vw was set to 4.5 V during the write period and 10 hours for the hold period. By repeating the accumulation and measurement operations, the measured current value was kept at a steady state. In other words, the current flowing through node A is I A Excluding the transient current (current component that decreases over time after measurement begins) As a result, the leakage current can be measured with higher accuracy.

[0234] In general, the potential of node A, V A is expressed as a function of the output signal potential Vout as follows: It is possible.

[0235]

number

[0236] Also, the charge Q at node A A is the potential V of node A. A , capacitance C connected to node A A , fixed Using a constant, the capacitance C connected to node A is expressed as follows: A teeth, This is the sum of the capacitance of the capacitor 813 and the capacitance of the capacitors other than the capacitor 813 .

[0237]

number

[0238] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I A is expressed as follows:

[0239]

number

[0240] For example, Δt is set to about 54000 sec. The capacitance C connected to node A A and the output signal The current I A Since it is possible to obtain The peak current can be calculated.

[0241] Next, the measurement results of the potential Vout of the output signal by the measurement method using the above-mentioned characteristic evaluation circuit and The leakage current value of the characteristic evaluation circuit calculated from the measurement results is shown.

[0242] FIG. 18 shows an example of the above measurement (first accumulation and measurement) under conditions 1, 2, and 3. FIG. 19 shows the relationship between the elapsed time Time and the potential Vout of the output signal. The relationship between the elapsed time Time in the above measurement and the leakage current calculated by the measurement is The output signal potential Vout fluctuates after the measurement starts, and it takes time for the output signal to reach a steady state. It turns out it takes more than 10 hours.

[0243] FIG. 20 shows the potential of node A under conditions 1 to 6 estimated by the above measurements. The relationship between leakage current and the potential at node A is shown in Figure 20. At 0V, the leakage current is 28yA / μm. The leakage current is Since the off-current is also included, the off-current of the transistor 812 is also considered to be 28 yA / μm or less. It is possible.

[0244] As described above, the present invention can be implemented by using a semiconductor device that includes a highly purified oxide semiconductor layer having a function as a channel formation layer. In the characteristic evaluation circuit using a transistor including It can be seen that the off-state current of the transistor is sufficiently small. EXAMPLES

[0245] By using a semiconductor device according to one embodiment of the present invention, an electronic device with low power consumption can be provided. In particular, in the case of portable electronic devices for which it is difficult to receive a constant supply of power, By adding a low-power semiconductor device according to one embodiment of the present invention to the components, The benefit is that it can be used for a longer period of time.

[0246] The semiconductor device according to one embodiment of the present invention is applicable to a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in a power As child devices, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, Digital still camera, goggle-type display (head-mounted display), navigation systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combination machines, automated teller machines (A TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 21.

[0247] FIG. 21A shows a portable game machine. The portable game machine includes a housing 7031, a housing 7032, a display portion 7033, A display unit 7034, a microphone 7035, a speaker 7036, an operation key 7037, a star The semiconductor device according to one embodiment of the present invention is a driving circuit for a portable game machine. The present invention can be used in an integrated circuit for controlling a portable game machine. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, a portable game device with low power consumption can be realized. The portable game machine shown in FIG. 21(A) can provide two The display unit 7033 and the display unit 7034 are included. is not limited to this.

[0248] FIG. 21B shows a mobile phone. The mobile phone includes a housing 7041, a display unit 7042, an audio input unit 7043, The device has a voice output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using the device, it is possible to provide a mobile phone with low power consumption.

[0249] FIG. 21C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 21C has a modem built in a housing 7051. The semiconductor device according to one embodiment of the present invention may be a semiconductor device for controlling the driving of a portable information terminal. The present invention can be used in an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor device according to one embodiment, a portable information terminal with low power consumption can be provided. can.

[0250] FIG. 21D shows a lighting device including a housing 7081 and a light source 7082. In the semiconductor device according to one embodiment of the present invention, a light emitting element is provided in the light source 7082. The present invention can be used in an integrated circuit for controlling the driving of a lighting device. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit, a lighting device with low power consumption can be provided. can be provided.

[0251] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0252] 100 DC-DC Converters 101 Power Conversion Circuit 102 Transistor 103 Constant voltage generator 104 Output voltage control circuit 105 Backgate control circuit 110 Gate electrode 111 Insulating film 112 Semiconductor film 113 Source Electrode 114 Drain electrode 115 Insulating film 116 Back gate electrode 117 Insulating Film 120 Substrate 130 Diode 131 Coil 132 Capacitive element 133 Trans 134 Diode 135 Trans 200 Resistance 201 Resistance 202 Error amplifier 203 Phase compensation circuit 204 Comparator 205 Triangle Wave Oscillator 206 Buffer 210 Current detection circuit 211 CT sensor 212 Rectifier 213 Integral circuit 214 Resistance 215 Capacitive element 216 Power Voltage Conversion Circuit 217 Comparator 218 Transistor 219 Transistor 220 Inverter 221 Power supply 301 AC power supply 302 Switch 303 Rectifier circuit 304 Light emitting element 350 Photodiode 351 Switch 352 Capacitive element 353 Pulse Width Modulation Circuit 354 Inverter 355 Bandpass Filter 356 Transistor 357 Transistor 358 Transistor 359 Transistor 360 Diode 363 Diode 500 Glass Substrate 501 Insulating film 502 Gate electrode 503 Insulating film 504 Semiconductor film 505 Source Electrode 506 Drain electrode 507 Insulating film 508 Backgate electrode 510 areas 700 Substrates 701 Insulating film 702 Semiconductor film 703 Semiconductor Film 704 n-channel transistor 705 p-channel transistor 706 Gate electrode 707 Gate electrode 708 Insulating film 711 Wiring 712 Insulating film 713 Gate electrode 714 Gate insulating film 715 Oxide Semiconductor Film 716 Electrode 717 Electrode 718 Electrode 719 Electrode 720 electrode 723 Insulating Film 724 Transistor 725 Backgate electrode 726 Insulating Film 730 Gate electrode 731 Gate insulating film 732 Oxide Semiconductor Film 733 Channel protection film 734 Electrode 735 Electrode 736 Insulating Film 737 Backgate electrode 738 Insulating Film 741 Gate electrode 742 Gate insulating film 743 Electrode 744 Electrode 745 Oxide Semiconductor Film 746 Insulating Film 747 Backgate electrode 748 Insulating film 801 Measurement System 811 Transistor 812 Transistor 813 Capacitive element 814 Transistor 815 Transistor 7031 Case 7032 Case 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Case 7042 Display section 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Case 7052 Display section 7053 Operation key 7081 Case 7082 light source

Claims

1. a first conductive film that functions as a gate of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; In a plan view, the second conductive film has a comb-like shape having a plurality of first protrusions, In a plan view, the third conductive film has a comb-like shape having a plurality of second protrusions, the second conductive film has a region sandwiched between the third conductive films in a plan view, the second conductive film and the third conductive film are arranged such that the first convex portions and the second convex portions are interdigitated with each other; in a cross-sectional view in a channel length direction including a channel formation region of the transistor, the second conductive film has a first end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween, and a second end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween and facing the first end portion, When viewed in the cross-section, the third conductive film has a third end portion overlapping the first conductive film with the oxide semiconductor film interposed therebetween, and a fourth end portion overlapping the oxide semiconductor film, not overlapping the first conductive film, and facing the third end portion. Semiconductor device.

2. a first conductive film that functions as a gate of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; In a plan view, the second conductive film has a comb-like shape having a plurality of first protrusions, In a plan view, the third conductive film has a comb-like shape having a plurality of second protrusions, the second conductive film has a region sandwiched between the third conductive films in a plan view, the second conductive film and the third conductive film are arranged such that the first convex portions and the second convex portions are interdigitated with each other; the first conductive film has a region overlapping with the oxide semiconductor film and a region not overlapping with the oxide semiconductor film in a plan view; in a cross-sectional view in a channel length direction including a channel formation region of the transistor, the second conductive film has a first end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween, and a second end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween and facing the first end portion, When viewed in the cross-section, the third conductive film has a third end portion overlapping the first conductive film with the oxide semiconductor film interposed therebetween, and a fourth end portion overlapping the oxide semiconductor film, not overlapping the first conductive film, and facing the third end portion. Semiconductor device.

3. a first conductive film that functions as a gate of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; In a plan view, the second conductive film has a comb-like shape having a plurality of first protrusions, In a plan view, the third conductive film has a comb-like shape having a plurality of second protrusions, the second conductive film has a region sandwiched between the third conductive films in a plan view, the second conductive film and the third conductive film are arranged such that the first convex portions and the second convex portions are interdigitated with each other; the third conductive film overlaps with a periphery of the first conductive film in a plan view; in a cross-sectional view in a channel length direction including a channel formation region of the transistor, the second conductive film has a first end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween, and a second end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween and facing the first end portion, When viewed in the cross-section, the third conductive film has a third end portion overlapping the first conductive film with the oxide semiconductor film interposed therebetween, and a fourth end portion overlapping the oxide semiconductor film, not overlapping the first conductive film, and facing the third end portion. Semiconductor device.

4. a first conductive film that functions as a gate of a transistor; an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the transistor; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; In a plan view, the second conductive film has a comb-like shape having a plurality of first protrusions, In a plan view, the third conductive film has a comb-like shape having a plurality of second protrusions, the second conductive film has a region sandwiched between the third conductive films in a plan view, the second conductive film and the third conductive film are arranged such that the first convex portions and the second convex portions are interdigitated with each other; the first conductive film has a region overlapping with the oxide semiconductor film and a region not overlapping with the oxide semiconductor film in a plan view; the third conductive film overlaps with a periphery of the first conductive film in a plan view; in a cross-sectional view in a channel length direction including a channel formation region of the transistor, the second conductive film has a first end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween, and a second end portion overlapping with the first conductive film with the oxide semiconductor film interposed therebetween and facing the first end portion, When viewed in the cross-section, the third conductive film has a third end portion overlapping the first conductive film with the oxide semiconductor film interposed therebetween, and a fourth end portion overlapping the oxide semiconductor film, not overlapping the first conductive film, and facing the third end portion. Semiconductor device.

5. In any one of claims 1 to 4, In a plan view, the second end portion and the third end portion face each other across a channel formation region of the transistor. Semiconductor device.

Images